i82557.c revision 1.78
1 /* $NetBSD: i82557.c,v 1.78 2003/12/06 11:27:28 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.78 2003/12/06 11:27:28 yamt Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 92 #include <machine/endian.h> 93 94 #include <uvm/uvm_extern.h> 95 96 #if NRND > 0 97 #include <sys/rnd.h> 98 #endif 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <machine/bus.h> 110 #include <machine/intr.h> 111 112 #include <dev/mii/miivar.h> 113 114 #include <dev/ic/i82557reg.h> 115 #include <dev/ic/i82557var.h> 116 117 #include <dev/microcode/i8255x/rcvbundl.h> 118 119 /* 120 * NOTE! On the Alpha, we have an alignment constraint. The 121 * card DMAs the packet immediately following the RFA. However, 122 * the first thing in the packet is a 14-byte Ethernet header. 123 * This means that the packet is misaligned. To compensate, 124 * we actually offset the RFA 2 bytes into the cluster. This 125 * alignes the packet after the Ethernet header at a 32-bit 126 * boundary. HOWEVER! This means that the RFA is misaligned! 127 */ 128 #define RFA_ALIGNMENT_FUDGE 2 129 130 /* 131 * The configuration byte map has several undefined fields which 132 * must be one or must be zero. Set up a template for these bits 133 * only (assuming an i82557 chip), leaving the actual configuration 134 * for fxp_init(). 135 * 136 * See the definition of struct fxp_cb_config for the bit definitions. 137 */ 138 const u_int8_t fxp_cb_config_template[] = { 139 0x0, 0x0, /* cb_status */ 140 0x0, 0x0, /* cb_command */ 141 0x0, 0x0, 0x0, 0x0, /* link_addr */ 142 0x0, /* 0 */ 143 0x0, /* 1 */ 144 0x0, /* 2 */ 145 0x0, /* 3 */ 146 0x0, /* 4 */ 147 0x0, /* 5 */ 148 0x32, /* 6 */ 149 0x0, /* 7 */ 150 0x0, /* 8 */ 151 0x0, /* 9 */ 152 0x6, /* 10 */ 153 0x0, /* 11 */ 154 0x0, /* 12 */ 155 0x0, /* 13 */ 156 0xf2, /* 14 */ 157 0x48, /* 15 */ 158 0x0, /* 16 */ 159 0x40, /* 17 */ 160 0xf0, /* 18 */ 161 0x0, /* 19 */ 162 0x3f, /* 20 */ 163 0x5, /* 21 */ 164 0x0, /* 22 */ 165 0x0, /* 23 */ 166 0x0, /* 24 */ 167 0x0, /* 25 */ 168 0x0, /* 26 */ 169 0x0, /* 27 */ 170 0x0, /* 28 */ 171 0x0, /* 29 */ 172 0x0, /* 30 */ 173 0x0, /* 31 */ 174 }; 175 176 void fxp_mii_initmedia(struct fxp_softc *); 177 int fxp_mii_mediachange(struct ifnet *); 178 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 void fxp_80c24_initmedia(struct fxp_softc *); 181 int fxp_80c24_mediachange(struct ifnet *); 182 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184 void fxp_start(struct ifnet *); 185 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 186 void fxp_watchdog(struct ifnet *); 187 int fxp_init(struct ifnet *); 188 void fxp_stop(struct ifnet *, int); 189 190 void fxp_txintr(struct fxp_softc *); 191 void fxp_rxintr(struct fxp_softc *); 192 193 void fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 194 195 void fxp_rxdrain(struct fxp_softc *); 196 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 197 int fxp_mdi_read(struct device *, int, int); 198 void fxp_statchg(struct device *); 199 void fxp_mdi_write(struct device *, int, int, int); 200 void fxp_autosize_eeprom(struct fxp_softc*); 201 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 202 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_eeprom_update_cksum(struct fxp_softc *); 204 void fxp_get_info(struct fxp_softc *, u_int8_t *); 205 void fxp_tick(void *); 206 void fxp_mc_setup(struct fxp_softc *); 207 void fxp_load_ucode(struct fxp_softc *); 208 209 void fxp_shutdown(void *); 210 void fxp_power(int, void *); 211 212 int fxp_copy_small = 0; 213 214 /* 215 * Variables for interrupt mitigating microcode. 216 */ 217 int fxp_int_delay = 1000; /* usec */ 218 int fxp_bundle_max = 6; /* packets */ 219 220 struct fxp_phytype { 221 int fp_phy; /* type of PHY, -1 for MII at the end. */ 222 void (*fp_init)(struct fxp_softc *); 223 } fxp_phytype_table[] = { 224 { FXP_PHY_80C24, fxp_80c24_initmedia }, 225 { -1, fxp_mii_initmedia }, 226 }; 227 228 /* 229 * Set initial transmit threshold at 64 (512 bytes). This is 230 * increased by 64 (512 bytes) at a time, to maximum of 192 231 * (1536 bytes), if an underrun occurs. 232 */ 233 static int tx_threshold = 64; 234 235 /* 236 * Wait for the previous command to be accepted (but not necessarily 237 * completed). 238 */ 239 static __inline void 240 fxp_scb_wait(struct fxp_softc *sc) 241 { 242 int i = 10000; 243 244 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 245 delay(2); 246 if (i == 0) 247 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 248 } 249 250 /* 251 * Submit a command to the i82557. 252 */ 253 static __inline void 254 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 255 { 256 257 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 258 } 259 260 /* 261 * Finish attaching an i82557 interface. Called by bus-specific front-end. 262 */ 263 void 264 fxp_attach(struct fxp_softc *sc) 265 { 266 u_int8_t enaddr[ETHER_ADDR_LEN]; 267 struct ifnet *ifp; 268 bus_dma_segment_t seg; 269 int rseg, i, error; 270 struct fxp_phytype *fp; 271 272 callout_init(&sc->sc_callout); 273 274 /* 275 * Enable some good stuff on i82558 and later. 276 */ 277 if (sc->sc_rev >= FXP_REV_82558_A4) { 278 /* Enable the extended TxCB. */ 279 sc->sc_flags |= FXPF_EXT_TXCB; 280 } 281 282 /* 283 * Enable use of extended RFDs and TCBs for 82550 284 * and later chips. Note: we need extended TXCB support 285 * too, but that's already enabled by the code above. 286 * Be careful to do this only on the right devices. 287 */ 288 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 289 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 290 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 291 } else { 292 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 293 } 294 295 sc->sc_rfa_size = 296 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 297 298 /* 299 * Allocate the control data structures, and create and load the 300 * DMA map for it. 301 */ 302 if ((error = bus_dmamem_alloc(sc->sc_dmat, 303 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 304 0)) != 0) { 305 aprint_error( 306 "%s: unable to allocate control data, error = %d\n", 307 sc->sc_dev.dv_xname, error); 308 goto fail_0; 309 } 310 311 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 312 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 313 BUS_DMA_COHERENT)) != 0) { 314 aprint_error("%s: unable to map control data, error = %d\n", 315 sc->sc_dev.dv_xname, error); 316 goto fail_1; 317 } 318 sc->sc_cdseg = seg; 319 sc->sc_cdnseg = rseg; 320 321 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 322 323 if ((error = bus_dmamap_create(sc->sc_dmat, 324 sizeof(struct fxp_control_data), 1, 325 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 326 aprint_error("%s: unable to create control data DMA map, " 327 "error = %d\n", sc->sc_dev.dv_xname, error); 328 goto fail_2; 329 } 330 331 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 332 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 333 0)) != 0) { 334 aprint_error( 335 "%s: can't load control data DMA map, error = %d\n", 336 sc->sc_dev.dv_xname, error); 337 goto fail_3; 338 } 339 340 /* 341 * Create the transmit buffer DMA maps. 342 */ 343 for (i = 0; i < FXP_NTXCB; i++) { 344 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 345 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 346 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 347 aprint_error("%s: unable to create tx DMA map %d, " 348 "error = %d\n", sc->sc_dev.dv_xname, i, error); 349 goto fail_4; 350 } 351 } 352 353 /* 354 * Create the receive buffer DMA maps. 355 */ 356 for (i = 0; i < FXP_NRFABUFS; i++) { 357 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 359 aprint_error("%s: unable to create rx DMA map %d, " 360 "error = %d\n", sc->sc_dev.dv_xname, i, error); 361 goto fail_5; 362 } 363 } 364 365 /* Initialize MAC address and media structures. */ 366 fxp_get_info(sc, enaddr); 367 368 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 369 ether_sprintf(enaddr)); 370 371 ifp = &sc->sc_ethercom.ec_if; 372 373 /* 374 * Get info about our media interface, and initialize it. Note 375 * the table terminates itself with a phy of -1, indicating 376 * that we're using MII. 377 */ 378 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 379 if (fp->fp_phy == sc->phy_primary_device) 380 break; 381 (*fp->fp_init)(sc); 382 383 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 384 ifp->if_softc = sc; 385 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 386 ifp->if_ioctl = fxp_ioctl; 387 ifp->if_start = fxp_start; 388 ifp->if_watchdog = fxp_watchdog; 389 ifp->if_init = fxp_init; 390 ifp->if_stop = fxp_stop; 391 IFQ_SET_READY(&ifp->if_snd); 392 393 if (sc->sc_flags & FXPF_IPCB) { 394 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 395 /* 396 * IFCAP_CSUM_IPv4 seems to have a problem, 397 * at least, on i82550 rev.12. 398 * specifically, it doesn't calculate ipv4 checksum correctly 399 * when sending 20 byte ipv4 header + 1 or 2 byte data. 400 * FreeBSD driver has related comments. 401 * 402 * XXX we should have separate IFCAP flags 403 * for transmit and receive. 404 */ 405 ifp->if_capabilities = 406 /*IFCAP_CSUM_IPv4 |*/ IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 407 } 408 409 /* 410 * We can support 802.1Q VLAN-sized frames. 411 */ 412 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 413 414 /* 415 * Attach the interface. 416 */ 417 if_attach(ifp); 418 ether_ifattach(ifp, enaddr); 419 #if NRND > 0 420 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 421 RND_TYPE_NET, 0); 422 #endif 423 424 #ifdef FXP_EVENT_COUNTERS 425 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 426 NULL, sc->sc_dev.dv_xname, "txstall"); 427 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 428 NULL, sc->sc_dev.dv_xname, "txintr"); 429 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 430 NULL, sc->sc_dev.dv_xname, "rxintr"); 431 #endif /* FXP_EVENT_COUNTERS */ 432 433 /* 434 * Add shutdown hook so that DMA is disabled prior to reboot. Not 435 * doing do could allow DMA to corrupt kernel memory during the 436 * reboot before the driver initializes. 437 */ 438 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 439 if (sc->sc_sdhook == NULL) 440 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 441 sc->sc_dev.dv_xname); 442 /* 443 * Add suspend hook, for similar reasons.. 444 */ 445 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 446 if (sc->sc_powerhook == NULL) 447 aprint_error("%s: WARNING: unable to establish power hook\n", 448 sc->sc_dev.dv_xname); 449 450 /* The attach is successful. */ 451 sc->sc_flags |= FXPF_ATTACHED; 452 453 return; 454 455 /* 456 * Free any resources we've allocated during the failed attach 457 * attempt. Do this in reverse order and fall though. 458 */ 459 fail_5: 460 for (i = 0; i < FXP_NRFABUFS; i++) { 461 if (sc->sc_rxmaps[i] != NULL) 462 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 463 } 464 fail_4: 465 for (i = 0; i < FXP_NTXCB; i++) { 466 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 467 bus_dmamap_destroy(sc->sc_dmat, 468 FXP_DSTX(sc, i)->txs_dmamap); 469 } 470 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 471 fail_3: 472 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 473 fail_2: 474 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 475 sizeof(struct fxp_control_data)); 476 fail_1: 477 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 478 fail_0: 479 return; 480 } 481 482 void 483 fxp_mii_initmedia(struct fxp_softc *sc) 484 { 485 int flags; 486 487 sc->sc_flags |= FXPF_MII; 488 489 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 490 sc->sc_mii.mii_readreg = fxp_mdi_read; 491 sc->sc_mii.mii_writereg = fxp_mdi_write; 492 sc->sc_mii.mii_statchg = fxp_statchg; 493 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 494 fxp_mii_mediastatus); 495 496 flags = MIIF_NOISOLATE; 497 if (sc->sc_rev >= FXP_REV_82558_A4) 498 flags |= MIIF_DOPAUSE; 499 /* 500 * The i82557 wedges if all of its PHYs are isolated! 501 */ 502 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 503 MII_OFFSET_ANY, flags); 504 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 505 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 506 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 507 } else 508 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 509 } 510 511 void 512 fxp_80c24_initmedia(struct fxp_softc *sc) 513 { 514 515 /* 516 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 517 * doesn't have a programming interface of any sort. The 518 * media is sensed automatically based on how the link partner 519 * is configured. This is, in essence, manual configuration. 520 */ 521 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 522 sc->sc_dev.dv_xname); 523 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 524 fxp_80c24_mediastatus); 525 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 526 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 527 } 528 529 /* 530 * Device shutdown routine. Called at system shutdown after sync. The 531 * main purpose of this routine is to shut off receiver DMA so that 532 * kernel memory doesn't get clobbered during warmboot. 533 */ 534 void 535 fxp_shutdown(void *arg) 536 { 537 struct fxp_softc *sc = arg; 538 539 /* 540 * Since the system's going to halt shortly, don't bother 541 * freeing mbufs. 542 */ 543 fxp_stop(&sc->sc_ethercom.ec_if, 0); 544 } 545 /* 546 * Power handler routine. Called when the system is transitioning 547 * into/out of power save modes. As with fxp_shutdown, the main 548 * purpose of this routine is to shut off receiver DMA so it doesn't 549 * clobber kernel memory at the wrong time. 550 */ 551 void 552 fxp_power(int why, void *arg) 553 { 554 struct fxp_softc *sc = arg; 555 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 556 int s; 557 558 s = splnet(); 559 switch (why) { 560 case PWR_SUSPEND: 561 case PWR_STANDBY: 562 fxp_stop(ifp, 0); 563 break; 564 case PWR_RESUME: 565 if (ifp->if_flags & IFF_UP) 566 fxp_init(ifp); 567 break; 568 case PWR_SOFTSUSPEND: 569 case PWR_SOFTSTANDBY: 570 case PWR_SOFTRESUME: 571 break; 572 } 573 splx(s); 574 } 575 576 /* 577 * Initialize the interface media. 578 */ 579 void 580 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 581 { 582 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 583 584 /* 585 * Reset to a stable state. 586 */ 587 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 588 DELAY(10); 589 590 sc->sc_eeprom_size = 0; 591 fxp_autosize_eeprom(sc); 592 if (sc->sc_eeprom_size == 0) { 593 aprint_error("%s: failed to detect EEPROM size\n", 594 sc->sc_dev.dv_xname); 595 sc->sc_eeprom_size = 6; /* XXX panic here? */ 596 } 597 #ifdef DEBUG 598 aprint_debug("%s: detected %d word EEPROM\n", 599 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 600 #endif 601 602 /* 603 * Get info about the primary PHY 604 */ 605 fxp_read_eeprom(sc, &data, 6, 1); 606 sc->phy_primary_device = 607 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 608 609 /* 610 * Read MAC address. 611 */ 612 fxp_read_eeprom(sc, myea, 0, 3); 613 enaddr[0] = myea[0] & 0xff; 614 enaddr[1] = myea[0] >> 8; 615 enaddr[2] = myea[1] & 0xff; 616 enaddr[3] = myea[1] >> 8; 617 enaddr[4] = myea[2] & 0xff; 618 enaddr[5] = myea[2] >> 8; 619 620 /* 621 * Systems based on the ICH2/ICH2-M chip from Intel, as well 622 * as some i82559 designs, have a defect where the chip can 623 * cause a PCI protocol violation if it receives a CU_RESUME 624 * command when it is entering the IDLE state. 625 * 626 * The work-around is to disable Dynamic Standby Mode, so that 627 * the chip never deasserts #CLKRUN, and always remains in the 628 * active state. 629 * 630 * Unfortunately, the only way to disable Dynamic Standby is 631 * to frob an EEPROM setting and reboot (the EEPROM setting 632 * is only consulted when the PCI bus comes out of reset). 633 * 634 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 635 */ 636 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 637 fxp_read_eeprom(sc, &data, 10, 1); 638 if (data & 0x02) { /* STB enable */ 639 aprint_error("%s: WARNING: " 640 "Disabling dynamic standby mode in EEPROM " 641 "to work around a\n", 642 sc->sc_dev.dv_xname); 643 aprint_normal( 644 "%s: WARNING: hardware bug. You must reset " 645 "the system before using this\n", 646 sc->sc_dev.dv_xname); 647 aprint_normal("%s: WARNING: interface.\n", 648 sc->sc_dev.dv_xname); 649 data &= ~0x02; 650 fxp_write_eeprom(sc, &data, 10, 1); 651 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 652 sc->sc_dev.dv_xname, data); 653 fxp_eeprom_update_cksum(sc); 654 } 655 } 656 } 657 658 static void 659 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 660 { 661 uint16_t reg; 662 int x; 663 664 for (x = 1 << (len - 1); x != 0; x >>= 1) { 665 if (data & x) 666 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 667 else 668 reg = FXP_EEPROM_EECS; 669 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 670 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 671 reg | FXP_EEPROM_EESK); 672 DELAY(4); 673 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 674 DELAY(4); 675 } 676 } 677 678 /* 679 * Figure out EEPROM size. 680 * 681 * 559's can have either 64-word or 256-word EEPROMs, the 558 682 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 683 * talks about the existence of 16 to 256 word EEPROMs. 684 * 685 * The only known sizes are 64 and 256, where the 256 version is used 686 * by CardBus cards to store CIS information. 687 * 688 * The address is shifted in msb-to-lsb, and after the last 689 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 690 * after which follows the actual data. We try to detect this zero, by 691 * probing the data-out bit in the EEPROM control register just after 692 * having shifted in a bit. If the bit is zero, we assume we've 693 * shifted enough address bits. The data-out should be tri-state, 694 * before this, which should translate to a logical one. 695 * 696 * Other ways to do this would be to try to read a register with known 697 * contents with a varying number of address bits, but no such 698 * register seem to be available. The high bits of register 10 are 01 699 * on the 558 and 559, but apparently not on the 557. 700 * 701 * The Linux driver computes a checksum on the EEPROM data, but the 702 * value of this checksum is not very well documented. 703 */ 704 705 void 706 fxp_autosize_eeprom(struct fxp_softc *sc) 707 { 708 int x; 709 710 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 711 712 /* Shift in read opcode. */ 713 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 714 715 /* 716 * Shift in address, wait for the dummy zero following a correct 717 * address shift. 718 */ 719 for (x = 1; x <= 8; x++) { 720 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 721 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 722 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 723 DELAY(4); 724 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 725 FXP_EEPROM_EEDO) == 0) 726 break; 727 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 728 DELAY(4); 729 } 730 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 731 DELAY(4); 732 if (x != 6 && x != 8) { 733 #ifdef DEBUG 734 printf("%s: strange EEPROM size (%d)\n", 735 sc->sc_dev.dv_xname, 1 << x); 736 #endif 737 } else 738 sc->sc_eeprom_size = x; 739 } 740 741 /* 742 * Read from the serial EEPROM. Basically, you manually shift in 743 * the read opcode (one bit at a time) and then shift in the address, 744 * and then you shift out the data (all of this one bit at a time). 745 * The word size is 16 bits, so you have to provide the address for 746 * every 16 bits of data. 747 */ 748 void 749 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 750 { 751 u_int16_t reg; 752 int i, x; 753 754 for (i = 0; i < words; i++) { 755 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 756 757 /* Shift in read opcode. */ 758 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 759 760 /* Shift in address. */ 761 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 762 763 reg = FXP_EEPROM_EECS; 764 data[i] = 0; 765 766 /* Shift out data. */ 767 for (x = 16; x > 0; x--) { 768 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 769 reg | FXP_EEPROM_EESK); 770 DELAY(4); 771 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 772 FXP_EEPROM_EEDO) 773 data[i] |= (1 << (x - 1)); 774 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 775 DELAY(4); 776 } 777 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 778 DELAY(4); 779 } 780 } 781 782 /* 783 * Write data to the serial EEPROM. 784 */ 785 void 786 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 787 { 788 int i, j; 789 790 for (i = 0; i < words; i++) { 791 /* Erase/write enable. */ 792 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 793 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 794 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 795 sc->sc_eeprom_size); 796 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 797 DELAY(4); 798 799 /* Shift in write opcode, address, data. */ 800 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 801 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 802 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 803 fxp_eeprom_shiftin(sc, data[i], 16); 804 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 805 DELAY(4); 806 807 /* Wait for the EEPROM to finish up. */ 808 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 809 DELAY(4); 810 for (j = 0; j < 1000; j++) { 811 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 812 FXP_EEPROM_EEDO) 813 break; 814 DELAY(50); 815 } 816 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 817 DELAY(4); 818 819 /* Erase/write disable. */ 820 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 821 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 822 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 823 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 824 DELAY(4); 825 } 826 } 827 828 /* 829 * Update the checksum of the EEPROM. 830 */ 831 void 832 fxp_eeprom_update_cksum(struct fxp_softc *sc) 833 { 834 int i; 835 uint16_t data, cksum; 836 837 cksum = 0; 838 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 839 fxp_read_eeprom(sc, &data, i, 1); 840 cksum += data; 841 } 842 i = (1 << sc->sc_eeprom_size) - 1; 843 cksum = 0xbaba - cksum; 844 fxp_read_eeprom(sc, &data, i, 1); 845 fxp_write_eeprom(sc, &cksum, i, 1); 846 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 847 sc->sc_dev.dv_xname, i, data, cksum); 848 } 849 850 /* 851 * Start packet transmission on the interface. 852 */ 853 void 854 fxp_start(struct ifnet *ifp) 855 { 856 struct fxp_softc *sc = ifp->if_softc; 857 struct mbuf *m0, *m; 858 struct fxp_txdesc *txd; 859 struct fxp_txsoft *txs; 860 bus_dmamap_t dmamap; 861 int error, lasttx, nexttx, opending, seg; 862 863 /* 864 * If we want a re-init, bail out now. 865 */ 866 if (sc->sc_flags & FXPF_WANTINIT) { 867 ifp->if_flags |= IFF_OACTIVE; 868 return; 869 } 870 871 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 872 return; 873 874 /* 875 * Remember the previous txpending and the current lasttx. 876 */ 877 opending = sc->sc_txpending; 878 lasttx = sc->sc_txlast; 879 880 /* 881 * Loop through the send queue, setting up transmit descriptors 882 * until we drain the queue, or use up all available transmit 883 * descriptors. 884 */ 885 for (;;) { 886 struct fxp_tbd *tbdp; 887 int csum_flags; 888 889 /* 890 * Grab a packet off the queue. 891 */ 892 IFQ_POLL(&ifp->if_snd, m0); 893 if (m0 == NULL) 894 break; 895 m = NULL; 896 897 if (sc->sc_txpending == FXP_NTXCB) { 898 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 899 break; 900 } 901 902 /* 903 * Get the next available transmit descriptor. 904 */ 905 nexttx = FXP_NEXTTX(sc->sc_txlast); 906 txd = FXP_CDTX(sc, nexttx); 907 txs = FXP_DSTX(sc, nexttx); 908 dmamap = txs->txs_dmamap; 909 910 /* 911 * Load the DMA map. If this fails, the packet either 912 * didn't fit in the allotted number of frags, or we were 913 * short on resources. In this case, we'll copy and try 914 * again. 915 */ 916 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 917 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 918 MGETHDR(m, M_DONTWAIT, MT_DATA); 919 if (m == NULL) { 920 printf("%s: unable to allocate Tx mbuf\n", 921 sc->sc_dev.dv_xname); 922 break; 923 } 924 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 925 if (m0->m_pkthdr.len > MHLEN) { 926 MCLGET(m, M_DONTWAIT); 927 if ((m->m_flags & M_EXT) == 0) { 928 printf("%s: unable to allocate Tx " 929 "cluster\n", sc->sc_dev.dv_xname); 930 m_freem(m); 931 break; 932 } 933 } 934 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 935 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 936 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 937 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 938 if (error) { 939 printf("%s: unable to load Tx buffer, " 940 "error = %d\n", sc->sc_dev.dv_xname, error); 941 break; 942 } 943 } 944 945 IFQ_DEQUEUE(&ifp->if_snd, m0); 946 csum_flags = m0->m_pkthdr.csum_flags; 947 if (m != NULL) { 948 m_freem(m0); 949 m0 = m; 950 } 951 952 /* Initialize the fraglist. */ 953 tbdp = txd->txd_tbd; 954 if (sc->sc_flags & FXPF_IPCB) 955 tbdp++; 956 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 957 tbdp[seg].tb_addr = 958 htole32(dmamap->dm_segs[seg].ds_addr); 959 tbdp[seg].tb_size = 960 htole32(dmamap->dm_segs[seg].ds_len); 961 } 962 963 /* Sync the DMA map. */ 964 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 965 BUS_DMASYNC_PREWRITE); 966 967 /* 968 * Store a pointer to the packet so we can free it later. 969 */ 970 txs->txs_mbuf = m0; 971 972 /* 973 * Initialize the transmit descriptor. 974 */ 975 /* BIG_ENDIAN: no need to swap to store 0 */ 976 txd->txd_txcb.cb_status = 0; 977 txd->txd_txcb.cb_command = 978 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 979 txd->txd_txcb.tx_threshold = tx_threshold; 980 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 981 982 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 983 if (sc->sc_flags & FXPF_IPCB) { 984 struct fxp_ipcb *ipcb; 985 /* 986 * Deal with TCP/IP checksum offload. Note that 987 * in order for TCP checksum offload to work, 988 * the pseudo header checksum must have already 989 * been computed and stored in the checksum field 990 * in the TCP header. The stack should have 991 * already done this for us. 992 */ 993 ipcb = &txd->txd_u.txdu_ipcb; 994 memset(ipcb, 0, sizeof(*ipcb)); 995 /* 996 * always do hardware parsing. 997 */ 998 ipcb->ipcb_ip_activation_high = 999 FXP_IPCB_HARDWAREPARSING_ENABLE; 1000 /* 1001 * ip checksum offloading. 1002 */ 1003 if (csum_flags & M_CSUM_IPv4) { 1004 ipcb->ipcb_ip_schedule |= 1005 FXP_IPCB_IP_CHECKSUM_ENABLE; 1006 } 1007 /* 1008 * TCP/UDP checksum offloading. 1009 */ 1010 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1011 ipcb->ipcb_ip_schedule |= 1012 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1013 } 1014 } else { 1015 KASSERT((csum_flags & 1016 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1017 } 1018 1019 FXP_CDTXSYNC(sc, nexttx, 1020 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1021 1022 /* Advance the tx pointer. */ 1023 sc->sc_txpending++; 1024 sc->sc_txlast = nexttx; 1025 1026 #if NBPFILTER > 0 1027 /* 1028 * Pass packet to bpf if there is a listener. 1029 */ 1030 if (ifp->if_bpf) 1031 bpf_mtap(ifp->if_bpf, m0); 1032 #endif 1033 } 1034 1035 if (sc->sc_txpending == FXP_NTXCB) { 1036 /* No more slots; notify upper layer. */ 1037 ifp->if_flags |= IFF_OACTIVE; 1038 } 1039 1040 if (sc->sc_txpending != opending) { 1041 /* 1042 * We enqueued packets. If the transmitter was idle, 1043 * reset the txdirty pointer. 1044 */ 1045 if (opending == 0) 1046 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1047 1048 /* 1049 * Cause the chip to interrupt and suspend command 1050 * processing once the last packet we've enqueued 1051 * has been transmitted. 1052 */ 1053 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 1054 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1055 FXP_CDTXSYNC(sc, sc->sc_txlast, 1056 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1057 1058 /* 1059 * The entire packet chain is set up. Clear the suspend bit 1060 * on the command prior to the first packet we set up. 1061 */ 1062 FXP_CDTXSYNC(sc, lasttx, 1063 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1064 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1065 htole16(~FXP_CB_COMMAND_S); 1066 FXP_CDTXSYNC(sc, lasttx, 1067 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1068 1069 /* 1070 * Issue a Resume command in case the chip was suspended. 1071 */ 1072 fxp_scb_wait(sc); 1073 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1074 1075 /* Set a watchdog timer in case the chip flakes out. */ 1076 ifp->if_timer = 5; 1077 } 1078 } 1079 1080 /* 1081 * Process interface interrupts. 1082 */ 1083 int 1084 fxp_intr(void *arg) 1085 { 1086 struct fxp_softc *sc = arg; 1087 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1088 bus_dmamap_t rxmap; 1089 int claimed = 0; 1090 u_int8_t statack; 1091 1092 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0 || sc->sc_enabled == 0) 1093 return (0); 1094 /* 1095 * If the interface isn't running, don't try to 1096 * service the interrupt.. just ack it and bail. 1097 */ 1098 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1099 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1100 if (statack) { 1101 claimed = 1; 1102 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1103 } 1104 return (claimed); 1105 } 1106 1107 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1108 claimed = 1; 1109 1110 /* 1111 * First ACK all the interrupts in this pass. 1112 */ 1113 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1114 1115 /* 1116 * Process receiver interrupts. If a no-resource (RNR) 1117 * condition exists, get whatever packets we can and 1118 * re-start the receiver. 1119 */ 1120 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1121 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1122 fxp_rxintr(sc); 1123 } 1124 1125 if (statack & FXP_SCB_STATACK_RNR) { 1126 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1127 fxp_scb_wait(sc); 1128 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1129 rxmap->dm_segs[0].ds_addr + 1130 RFA_ALIGNMENT_FUDGE); 1131 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1132 } 1133 1134 /* 1135 * Free any finished transmit mbuf chains. 1136 */ 1137 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1138 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1139 fxp_txintr(sc); 1140 1141 /* 1142 * Try to get more packets going. 1143 */ 1144 fxp_start(ifp); 1145 1146 if (sc->sc_txpending == 0) { 1147 /* 1148 * If we want a re-init, do that now. 1149 */ 1150 if (sc->sc_flags & FXPF_WANTINIT) 1151 (void) fxp_init(ifp); 1152 } 1153 } 1154 } 1155 1156 #if NRND > 0 1157 if (claimed) 1158 rnd_add_uint32(&sc->rnd_source, statack); 1159 #endif 1160 return (claimed); 1161 } 1162 1163 /* 1164 * Handle transmit completion interrupts. 1165 */ 1166 void 1167 fxp_txintr(struct fxp_softc *sc) 1168 { 1169 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1170 struct fxp_txdesc *txd; 1171 struct fxp_txsoft *txs; 1172 int i; 1173 u_int16_t txstat; 1174 1175 ifp->if_flags &= ~IFF_OACTIVE; 1176 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1177 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1178 txd = FXP_CDTX(sc, i); 1179 txs = FXP_DSTX(sc, i); 1180 1181 FXP_CDTXSYNC(sc, i, 1182 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1183 1184 txstat = le16toh(txd->txd_txcb.cb_status); 1185 1186 if ((txstat & FXP_CB_STATUS_C) == 0) 1187 break; 1188 1189 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1190 0, txs->txs_dmamap->dm_mapsize, 1191 BUS_DMASYNC_POSTWRITE); 1192 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1193 m_freem(txs->txs_mbuf); 1194 txs->txs_mbuf = NULL; 1195 } 1196 1197 /* Update the dirty transmit buffer pointer. */ 1198 sc->sc_txdirty = i; 1199 1200 /* 1201 * Cancel the watchdog timer if there are no pending 1202 * transmissions. 1203 */ 1204 if (sc->sc_txpending == 0) 1205 ifp->if_timer = 0; 1206 } 1207 1208 void 1209 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1210 { 1211 u_int16_t rxparsestat; 1212 u_int16_t csum_stat; 1213 u_int32_t csum_data; 1214 int csum_flags; 1215 1216 rxparsestat = le16toh(rfa->rx_parse_stat); 1217 csum_stat = le16toh(rfa->cksum_stat); 1218 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1219 return; 1220 1221 csum_flags = 0; 1222 csum_data = 0; 1223 1224 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1225 csum_flags = M_CSUM_IPv4; 1226 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1227 csum_flags |= M_CSUM_IPv4_BAD; 1228 } 1229 1230 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1231 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1232 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1233 csum_flags |= M_CSUM_TCP_UDP_BAD; 1234 } 1235 1236 m->m_pkthdr.csum_flags = csum_flags; 1237 m->m_pkthdr.csum_data = csum_data; 1238 } 1239 1240 /* 1241 * Handle receive interrupts. 1242 */ 1243 void 1244 fxp_rxintr(struct fxp_softc *sc) 1245 { 1246 struct ethercom *ec = &sc->sc_ethercom; 1247 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1248 struct mbuf *m, *m0; 1249 bus_dmamap_t rxmap; 1250 struct fxp_rfa *rfa; 1251 u_int16_t len, rxstat; 1252 1253 for (;;) { 1254 m = sc->sc_rxq.ifq_head; 1255 rfa = FXP_MTORFA(m); 1256 rxmap = M_GETCTX(m, bus_dmamap_t); 1257 1258 FXP_RFASYNC(sc, m, 1259 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1260 1261 rxstat = le16toh(rfa->rfa_status); 1262 1263 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1264 /* 1265 * We have processed all of the 1266 * receive buffers. 1267 */ 1268 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1269 return; 1270 } 1271 1272 IF_DEQUEUE(&sc->sc_rxq, m); 1273 1274 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1275 1276 len = le16toh(rfa->actual_size) & 1277 (m->m_ext.ext_size - 1); 1278 1279 if (len < sizeof(struct ether_header)) { 1280 /* 1281 * Runt packet; drop it now. 1282 */ 1283 FXP_INIT_RFABUF(sc, m); 1284 continue; 1285 } 1286 1287 /* 1288 * If support for 802.1Q VLAN sized frames is 1289 * enabled, we need to do some additional error 1290 * checking (as we are saving bad frames, in 1291 * order to receive the larger ones). 1292 */ 1293 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1294 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1295 FXP_RFA_STATUS_RNR| 1296 FXP_RFA_STATUS_ALIGN| 1297 FXP_RFA_STATUS_CRC)) != 0) { 1298 FXP_INIT_RFABUF(sc, m); 1299 continue; 1300 } 1301 1302 /* Do checksum checking. */ 1303 m->m_pkthdr.csum_flags = 0; 1304 if (sc->sc_flags & FXPF_EXT_RFA) 1305 fxp_rx_hwcksum(m, rfa); 1306 1307 /* 1308 * If the packet is small enough to fit in a 1309 * single header mbuf, allocate one and copy 1310 * the data into it. This greatly reduces 1311 * memory consumption when we receive lots 1312 * of small packets. 1313 * 1314 * Otherwise, we add a new buffer to the receive 1315 * chain. If this fails, we drop the packet and 1316 * recycle the old buffer. 1317 */ 1318 if (fxp_copy_small != 0 && len <= MHLEN) { 1319 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1320 if (m0 == NULL) 1321 goto dropit; 1322 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1323 memcpy(mtod(m0, caddr_t), 1324 mtod(m, caddr_t), len); 1325 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1326 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1327 FXP_INIT_RFABUF(sc, m); 1328 m = m0; 1329 } else { 1330 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1331 dropit: 1332 ifp->if_ierrors++; 1333 FXP_INIT_RFABUF(sc, m); 1334 continue; 1335 } 1336 } 1337 1338 m->m_pkthdr.rcvif = ifp; 1339 m->m_pkthdr.len = m->m_len = len; 1340 1341 #if NBPFILTER > 0 1342 /* 1343 * Pass this up to any BPF listeners, but only 1344 * pass it up the stack it its for us. 1345 */ 1346 if (ifp->if_bpf) 1347 bpf_mtap(ifp->if_bpf, m); 1348 #endif 1349 1350 /* Pass it on. */ 1351 (*ifp->if_input)(ifp, m); 1352 } 1353 } 1354 1355 /* 1356 * Update packet in/out/collision statistics. The i82557 doesn't 1357 * allow you to access these counters without doing a fairly 1358 * expensive DMA to get _all_ of the statistics it maintains, so 1359 * we do this operation here only once per second. The statistics 1360 * counters in the kernel are updated from the previous dump-stats 1361 * DMA and then a new dump-stats DMA is started. The on-chip 1362 * counters are zeroed when the DMA completes. If we can't start 1363 * the DMA immediately, we don't wait - we just prepare to read 1364 * them again next time. 1365 */ 1366 void 1367 fxp_tick(void *arg) 1368 { 1369 struct fxp_softc *sc = arg; 1370 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1371 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1372 int s; 1373 1374 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1375 return; 1376 1377 s = splnet(); 1378 1379 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1380 1381 ifp->if_opackets += le32toh(sp->tx_good); 1382 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1383 if (sp->rx_good) { 1384 ifp->if_ipackets += le32toh(sp->rx_good); 1385 sc->sc_rxidle = 0; 1386 } else { 1387 sc->sc_rxidle++; 1388 } 1389 ifp->if_ierrors += 1390 le32toh(sp->rx_crc_errors) + 1391 le32toh(sp->rx_alignment_errors) + 1392 le32toh(sp->rx_rnr_errors) + 1393 le32toh(sp->rx_overrun_errors); 1394 /* 1395 * If any transmit underruns occurred, bump up the transmit 1396 * threshold by another 512 bytes (64 * 8). 1397 */ 1398 if (sp->tx_underruns) { 1399 ifp->if_oerrors += le32toh(sp->tx_underruns); 1400 if (tx_threshold < 192) 1401 tx_threshold += 64; 1402 } 1403 1404 /* 1405 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1406 * then assume the receiver has locked up and attempt to clear 1407 * the condition by reprogramming the multicast filter (actually, 1408 * resetting the interface). This is a work-around for a bug in 1409 * the 82557 where the receiver locks up if it gets certain types 1410 * of garbage in the synchronization bits prior to the packet header. 1411 * This bug is supposed to only occur in 10Mbps mode, but has been 1412 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1413 * speed transition). 1414 */ 1415 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1416 (void) fxp_init(ifp); 1417 splx(s); 1418 return; 1419 } 1420 /* 1421 * If there is no pending command, start another stats 1422 * dump. Otherwise punt for now. 1423 */ 1424 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1425 /* 1426 * Start another stats dump. 1427 */ 1428 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1429 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1430 } else { 1431 /* 1432 * A previous command is still waiting to be accepted. 1433 * Just zero our copy of the stats and wait for the 1434 * next timer event to update them. 1435 */ 1436 /* BIG_ENDIAN: no swap required to store 0 */ 1437 sp->tx_good = 0; 1438 sp->tx_underruns = 0; 1439 sp->tx_total_collisions = 0; 1440 1441 sp->rx_good = 0; 1442 sp->rx_crc_errors = 0; 1443 sp->rx_alignment_errors = 0; 1444 sp->rx_rnr_errors = 0; 1445 sp->rx_overrun_errors = 0; 1446 } 1447 1448 if (sc->sc_flags & FXPF_MII) { 1449 /* Tick the MII clock. */ 1450 mii_tick(&sc->sc_mii); 1451 } 1452 1453 splx(s); 1454 1455 /* 1456 * Schedule another timeout one second from now. 1457 */ 1458 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1459 } 1460 1461 /* 1462 * Drain the receive queue. 1463 */ 1464 void 1465 fxp_rxdrain(struct fxp_softc *sc) 1466 { 1467 bus_dmamap_t rxmap; 1468 struct mbuf *m; 1469 1470 for (;;) { 1471 IF_DEQUEUE(&sc->sc_rxq, m); 1472 if (m == NULL) 1473 break; 1474 rxmap = M_GETCTX(m, bus_dmamap_t); 1475 bus_dmamap_unload(sc->sc_dmat, rxmap); 1476 FXP_RXMAP_PUT(sc, rxmap); 1477 m_freem(m); 1478 } 1479 } 1480 1481 /* 1482 * Stop the interface. Cancels the statistics updater and resets 1483 * the interface. 1484 */ 1485 void 1486 fxp_stop(struct ifnet *ifp, int disable) 1487 { 1488 struct fxp_softc *sc = ifp->if_softc; 1489 struct fxp_txsoft *txs; 1490 int i; 1491 1492 /* 1493 * Turn down interface (done early to avoid bad interactions 1494 * between panics, shutdown hooks, and the watchdog timer) 1495 */ 1496 ifp->if_timer = 0; 1497 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1498 1499 /* 1500 * Cancel stats updater. 1501 */ 1502 callout_stop(&sc->sc_callout); 1503 if (sc->sc_flags & FXPF_MII) { 1504 /* Down the MII. */ 1505 mii_down(&sc->sc_mii); 1506 } 1507 1508 /* 1509 * Issue software reset. This unloads any microcode that 1510 * might already be loaded. 1511 */ 1512 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1513 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1514 DELAY(50); 1515 1516 /* 1517 * Release any xmit buffers. 1518 */ 1519 for (i = 0; i < FXP_NTXCB; i++) { 1520 txs = FXP_DSTX(sc, i); 1521 if (txs->txs_mbuf != NULL) { 1522 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1523 m_freem(txs->txs_mbuf); 1524 txs->txs_mbuf = NULL; 1525 } 1526 } 1527 sc->sc_txpending = 0; 1528 1529 if (disable) { 1530 fxp_rxdrain(sc); 1531 fxp_disable(sc); 1532 } 1533 1534 } 1535 1536 /* 1537 * Watchdog/transmission transmit timeout handler. Called when a 1538 * transmission is started on the interface, but no interrupt is 1539 * received before the timeout. This usually indicates that the 1540 * card has wedged for some reason. 1541 */ 1542 void 1543 fxp_watchdog(struct ifnet *ifp) 1544 { 1545 struct fxp_softc *sc = ifp->if_softc; 1546 1547 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1548 ifp->if_oerrors++; 1549 1550 (void) fxp_init(ifp); 1551 } 1552 1553 /* 1554 * Initialize the interface. Must be called at splnet(). 1555 */ 1556 int 1557 fxp_init(struct ifnet *ifp) 1558 { 1559 struct fxp_softc *sc = ifp->if_softc; 1560 struct fxp_cb_config *cbp; 1561 struct fxp_cb_ias *cb_ias; 1562 struct fxp_txdesc *txd; 1563 bus_dmamap_t rxmap; 1564 int i, prm, save_bf, lrxen, allm, error = 0; 1565 1566 if ((error = fxp_enable(sc)) != 0) 1567 goto out; 1568 1569 /* 1570 * Cancel any pending I/O 1571 */ 1572 fxp_stop(ifp, 0); 1573 1574 /* 1575 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1576 * flag, and this prevents the MII from detaching resulting in 1577 * a panic. The flags field should perhaps be split in runtime 1578 * flags and more static information. For now, just clear the 1579 * only other flag set. 1580 */ 1581 1582 sc->sc_flags &= ~FXPF_WANTINIT; 1583 1584 /* 1585 * Initialize base of CBL and RFA memory. Loading with zero 1586 * sets it up for regular linear addressing. 1587 */ 1588 fxp_scb_wait(sc); 1589 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1590 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1591 1592 fxp_scb_wait(sc); 1593 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1594 1595 /* 1596 * Initialize the multicast filter. Do this now, since we might 1597 * have to setup the config block differently. 1598 */ 1599 fxp_mc_setup(sc); 1600 1601 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1602 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1603 1604 /* 1605 * In order to support receiving 802.1Q VLAN frames, we have to 1606 * enable "save bad frames", since they are 4 bytes larger than 1607 * the normal Ethernet maximum frame length. On i82558 and later, 1608 * we have a better mechanism for this. 1609 */ 1610 save_bf = 0; 1611 lrxen = 0; 1612 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1613 if (sc->sc_rev < FXP_REV_82558_A4) 1614 save_bf = 1; 1615 else 1616 lrxen = 1; 1617 } 1618 1619 /* 1620 * Initialize base of dump-stats buffer. 1621 */ 1622 fxp_scb_wait(sc); 1623 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1624 sc->sc_cddma + FXP_CDSTATSOFF); 1625 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1626 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1627 1628 cbp = &sc->sc_control_data->fcd_configcb; 1629 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1630 1631 /* 1632 * Load microcode for this controller. 1633 */ 1634 fxp_load_ucode(sc); 1635 1636 /* 1637 * This copy is kind of disgusting, but there are a bunch of must be 1638 * zero and must be one bits in this structure and this is the easiest 1639 * way to initialize them all to proper values. 1640 */ 1641 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1642 1643 /* BIG_ENDIAN: no need to swap to store 0 */ 1644 cbp->cb_status = 0; 1645 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1646 FXP_CB_COMMAND_EL); 1647 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1648 cbp->link_addr = 0xffffffff; /* (no) next command */ 1649 /* bytes in config block */ 1650 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1651 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1652 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1653 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1654 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1655 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1656 cbp->type_enable = 0; /* actually reserved */ 1657 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1658 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1659 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1660 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1661 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1662 cbp->late_scb = 0; /* (don't) defer SCB update */ 1663 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1664 cbp->ci_int = 1; /* interrupt on CU idle */ 1665 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1666 cbp->ext_stats_dis = 1; /* disable extended counters */ 1667 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1668 cbp->save_bf = save_bf;/* save bad frames */ 1669 cbp->disc_short_rx = !prm; /* discard short packets */ 1670 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1671 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1672 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1673 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1674 /* interface mode */ 1675 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1676 cbp->csma_dis = 0; /* (don't) disable link */ 1677 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1678 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1679 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1680 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1681 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1682 cbp->nsai = 1; /* (don't) disable source addr insert */ 1683 cbp->preamble_length = 2; /* (7 byte) preamble */ 1684 cbp->loopback = 0; /* (don't) loopback */ 1685 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1686 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1687 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1688 cbp->promiscuous = prm; /* promiscuous mode */ 1689 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1690 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1691 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1692 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1693 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1694 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1695 cbp->padding = 1; /* (do) pad short tx packets */ 1696 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1697 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1698 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1699 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1700 /* must set wake_en in PMCSR also */ 1701 cbp->force_fdx = 0; /* (don't) force full duplex */ 1702 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1703 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1704 cbp->mc_all = allm; /* accept all multicasts */ 1705 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1706 1707 if (sc->sc_rev < FXP_REV_82558_A4) { 1708 /* 1709 * The i82557 has no hardware flow control, the values 1710 * here are the defaults for the chip. 1711 */ 1712 cbp->fc_delay_lsb = 0; 1713 cbp->fc_delay_msb = 0x40; 1714 cbp->pri_fc_thresh = 3; 1715 cbp->tx_fc_dis = 0; 1716 cbp->rx_fc_restop = 0; 1717 cbp->rx_fc_restart = 0; 1718 cbp->fc_filter = 0; 1719 cbp->pri_fc_loc = 1; 1720 } else { 1721 cbp->fc_delay_lsb = 0x1f; 1722 cbp->fc_delay_msb = 0x01; 1723 cbp->pri_fc_thresh = 3; 1724 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1725 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1726 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1727 cbp->fc_filter = !prm; /* drop FC frames to host */ 1728 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1729 } 1730 1731 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1732 1733 /* 1734 * Start the config command/DMA. 1735 */ 1736 fxp_scb_wait(sc); 1737 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1738 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1739 /* ...and wait for it to complete. */ 1740 i = 1000; 1741 do { 1742 FXP_CDCONFIGSYNC(sc, 1743 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1744 DELAY(1); 1745 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1746 if (i == 0) { 1747 printf("%s at line %d: dmasync timeout\n", 1748 sc->sc_dev.dv_xname, __LINE__); 1749 return (ETIMEDOUT); 1750 } 1751 1752 /* 1753 * Initialize the station address. 1754 */ 1755 cb_ias = &sc->sc_control_data->fcd_iascb; 1756 /* BIG_ENDIAN: no need to swap to store 0 */ 1757 cb_ias->cb_status = 0; 1758 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1759 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1760 cb_ias->link_addr = 0xffffffff; 1761 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1762 1763 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1764 1765 /* 1766 * Start the IAS (Individual Address Setup) command/DMA. 1767 */ 1768 fxp_scb_wait(sc); 1769 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1770 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1771 /* ...and wait for it to complete. */ 1772 i = 1000; 1773 do { 1774 FXP_CDIASSYNC(sc, 1775 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1776 DELAY(1); 1777 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1778 if (i == 0) { 1779 printf("%s at line %d: dmasync timeout\n", 1780 sc->sc_dev.dv_xname, __LINE__); 1781 return (ETIMEDOUT); 1782 } 1783 1784 /* 1785 * Initialize the transmit descriptor ring. txlast is initialized 1786 * to the end of the list so that it will wrap around to the first 1787 * descriptor when the first packet is transmitted. 1788 */ 1789 for (i = 0; i < FXP_NTXCB; i++) { 1790 txd = FXP_CDTX(sc, i); 1791 memset(txd, 0, sizeof(*txd)); 1792 txd->txd_txcb.cb_command = 1793 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1794 txd->txd_txcb.link_addr = 1795 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1796 if (sc->sc_flags & FXPF_EXT_TXCB) 1797 txd->txd_txcb.tbd_array_addr = 1798 htole32(FXP_CDTBDADDR(sc, i) + 1799 (2 * sizeof(struct fxp_tbd))); 1800 else 1801 txd->txd_txcb.tbd_array_addr = 1802 htole32(FXP_CDTBDADDR(sc, i)); 1803 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1804 } 1805 sc->sc_txpending = 0; 1806 sc->sc_txdirty = 0; 1807 sc->sc_txlast = FXP_NTXCB - 1; 1808 1809 /* 1810 * Initialize the receive buffer list. 1811 */ 1812 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1813 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1814 rxmap = FXP_RXMAP_GET(sc); 1815 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1816 printf("%s: unable to allocate or map rx " 1817 "buffer %d, error = %d\n", 1818 sc->sc_dev.dv_xname, 1819 sc->sc_rxq.ifq_len, error); 1820 /* 1821 * XXX Should attempt to run with fewer receive 1822 * XXX buffers instead of just failing. 1823 */ 1824 FXP_RXMAP_PUT(sc, rxmap); 1825 fxp_rxdrain(sc); 1826 goto out; 1827 } 1828 } 1829 sc->sc_rxidle = 0; 1830 1831 /* 1832 * Give the transmit ring to the chip. We do this by pointing 1833 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1834 * issuing a start command. It will execute the NOP and then 1835 * suspend, pointing at the first descriptor. 1836 */ 1837 fxp_scb_wait(sc); 1838 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1839 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1840 1841 /* 1842 * Initialize receiver buffer area - RFA. 1843 */ 1844 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1845 fxp_scb_wait(sc); 1846 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1847 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1848 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1849 1850 if (sc->sc_flags & FXPF_MII) { 1851 /* 1852 * Set current media. 1853 */ 1854 mii_mediachg(&sc->sc_mii); 1855 } 1856 1857 /* 1858 * ...all done! 1859 */ 1860 ifp->if_flags |= IFF_RUNNING; 1861 ifp->if_flags &= ~IFF_OACTIVE; 1862 1863 /* 1864 * Start the one second timer. 1865 */ 1866 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1867 1868 /* 1869 * Attempt to start output on the interface. 1870 */ 1871 fxp_start(ifp); 1872 1873 out: 1874 if (error) { 1875 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1876 ifp->if_timer = 0; 1877 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1878 } 1879 return (error); 1880 } 1881 1882 /* 1883 * Change media according to request. 1884 */ 1885 int 1886 fxp_mii_mediachange(struct ifnet *ifp) 1887 { 1888 struct fxp_softc *sc = ifp->if_softc; 1889 1890 if (ifp->if_flags & IFF_UP) 1891 mii_mediachg(&sc->sc_mii); 1892 return (0); 1893 } 1894 1895 /* 1896 * Notify the world which media we're using. 1897 */ 1898 void 1899 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1900 { 1901 struct fxp_softc *sc = ifp->if_softc; 1902 1903 if (sc->sc_enabled == 0) { 1904 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1905 ifmr->ifm_status = 0; 1906 return; 1907 } 1908 1909 mii_pollstat(&sc->sc_mii); 1910 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1911 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1912 } 1913 1914 int 1915 fxp_80c24_mediachange(struct ifnet *ifp) 1916 { 1917 1918 /* Nothing to do here. */ 1919 return (0); 1920 } 1921 1922 void 1923 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1924 { 1925 struct fxp_softc *sc = ifp->if_softc; 1926 1927 /* 1928 * Media is currently-selected media. We cannot determine 1929 * the link status. 1930 */ 1931 ifmr->ifm_status = 0; 1932 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1933 } 1934 1935 /* 1936 * Add a buffer to the end of the RFA buffer list. 1937 * Return 0 if successful, error code on failure. 1938 * 1939 * The RFA struct is stuck at the beginning of mbuf cluster and the 1940 * data pointer is fixed up to point just past it. 1941 */ 1942 int 1943 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1944 { 1945 struct mbuf *m; 1946 int error; 1947 1948 MGETHDR(m, M_DONTWAIT, MT_DATA); 1949 if (m == NULL) 1950 return (ENOBUFS); 1951 1952 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1953 MCLGET(m, M_DONTWAIT); 1954 if ((m->m_flags & M_EXT) == 0) { 1955 m_freem(m); 1956 return (ENOBUFS); 1957 } 1958 1959 if (unload) 1960 bus_dmamap_unload(sc->sc_dmat, rxmap); 1961 1962 M_SETCTX(m, rxmap); 1963 1964 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1965 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 1966 BUS_DMA_READ|BUS_DMA_NOWAIT); 1967 if (error) { 1968 printf("%s: can't load rx DMA map %d, error = %d\n", 1969 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1970 panic("fxp_add_rfabuf"); /* XXX */ 1971 } 1972 1973 FXP_INIT_RFABUF(sc, m); 1974 1975 return (0); 1976 } 1977 1978 int 1979 fxp_mdi_read(struct device *self, int phy, int reg) 1980 { 1981 struct fxp_softc *sc = (struct fxp_softc *)self; 1982 int count = 10000; 1983 int value; 1984 1985 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1986 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1987 1988 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 1989 0x10000000) == 0 && count--) 1990 DELAY(10); 1991 1992 if (count <= 0) 1993 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1994 1995 return (value & 0xffff); 1996 } 1997 1998 void 1999 fxp_statchg(struct device *self) 2000 { 2001 2002 /* Nothing to do. */ 2003 } 2004 2005 void 2006 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2007 { 2008 struct fxp_softc *sc = (struct fxp_softc *)self; 2009 int count = 10000; 2010 2011 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2012 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2013 (value & 0xffff)); 2014 2015 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2016 count--) 2017 DELAY(10); 2018 2019 if (count <= 0) 2020 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2021 } 2022 2023 int 2024 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2025 { 2026 struct fxp_softc *sc = ifp->if_softc; 2027 struct ifreq *ifr = (struct ifreq *)data; 2028 int s, error; 2029 2030 s = splnet(); 2031 2032 switch (cmd) { 2033 case SIOCSIFMEDIA: 2034 case SIOCGIFMEDIA: 2035 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2036 break; 2037 2038 default: 2039 error = ether_ioctl(ifp, cmd, data); 2040 if (error == ENETRESET) { 2041 if (sc->sc_enabled) { 2042 /* 2043 * Multicast list has changed; set the 2044 * hardware filter accordingly. 2045 */ 2046 if (sc->sc_txpending) { 2047 sc->sc_flags |= FXPF_WANTINIT; 2048 error = 0; 2049 } else 2050 error = fxp_init(ifp); 2051 } else 2052 error = 0; 2053 } 2054 break; 2055 } 2056 2057 /* Try to get more packets going. */ 2058 if (sc->sc_enabled) 2059 fxp_start(ifp); 2060 2061 splx(s); 2062 return (error); 2063 } 2064 2065 /* 2066 * Program the multicast filter. 2067 * 2068 * This function must be called at splnet(). 2069 */ 2070 void 2071 fxp_mc_setup(struct fxp_softc *sc) 2072 { 2073 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2074 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2075 struct ethercom *ec = &sc->sc_ethercom; 2076 struct ether_multi *enm; 2077 struct ether_multistep step; 2078 int count, nmcasts; 2079 2080 #ifdef DIAGNOSTIC 2081 if (sc->sc_txpending) 2082 panic("fxp_mc_setup: pending transmissions"); 2083 #endif 2084 2085 ifp->if_flags &= ~IFF_ALLMULTI; 2086 2087 /* 2088 * Initialize multicast setup descriptor. 2089 */ 2090 nmcasts = 0; 2091 ETHER_FIRST_MULTI(step, ec, enm); 2092 while (enm != NULL) { 2093 /* 2094 * Check for too many multicast addresses or if we're 2095 * listening to a range. Either way, we simply have 2096 * to accept all multicasts. 2097 */ 2098 if (nmcasts >= MAXMCADDR || 2099 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2100 ETHER_ADDR_LEN) != 0) { 2101 /* 2102 * Callers of this function must do the 2103 * right thing with this. If we're called 2104 * from outside fxp_init(), the caller must 2105 * detect if the state if IFF_ALLMULTI changes. 2106 * If it does, the caller must then call 2107 * fxp_init(), since allmulti is handled by 2108 * the config block. 2109 */ 2110 ifp->if_flags |= IFF_ALLMULTI; 2111 return; 2112 } 2113 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2114 ETHER_ADDR_LEN); 2115 nmcasts++; 2116 ETHER_NEXT_MULTI(step, enm); 2117 } 2118 2119 /* BIG_ENDIAN: no need to swap to store 0 */ 2120 mcsp->cb_status = 0; 2121 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2122 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2123 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2124 2125 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2126 2127 /* 2128 * Wait until the command unit is not active. This should never 2129 * happen since nothing is queued, but make sure anyway. 2130 */ 2131 count = 100; 2132 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2133 FXP_SCB_CUS_ACTIVE && --count) 2134 DELAY(1); 2135 if (count == 0) { 2136 printf("%s at line %d: command queue timeout\n", 2137 sc->sc_dev.dv_xname, __LINE__); 2138 return; 2139 } 2140 2141 /* 2142 * Start the multicast setup command/DMA. 2143 */ 2144 fxp_scb_wait(sc); 2145 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2146 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2147 2148 /* ...and wait for it to complete. */ 2149 count = 1000; 2150 do { 2151 FXP_CDMCSSYNC(sc, 2152 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2153 DELAY(1); 2154 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2155 if (count == 0) { 2156 printf("%s at line %d: dmasync timeout\n", 2157 sc->sc_dev.dv_xname, __LINE__); 2158 return; 2159 } 2160 } 2161 2162 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2163 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2164 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2165 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2166 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2167 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2168 2169 #define UCODE(x) x, sizeof(x) 2170 2171 static const struct ucode { 2172 int32_t revision; 2173 const uint32_t *ucode; 2174 size_t length; 2175 uint16_t int_delay_offset; 2176 uint16_t bundle_max_offset; 2177 } ucode_table[] = { 2178 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2179 D101_CPUSAVER_DWORD, 0 }, 2180 2181 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2182 D101_CPUSAVER_DWORD, 0 }, 2183 2184 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2185 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2186 2187 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2188 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2189 2190 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2191 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2192 2193 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2194 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2195 2196 { 0, NULL, 0, 0, 0 } 2197 }; 2198 2199 void 2200 fxp_load_ucode(struct fxp_softc *sc) 2201 { 2202 const struct ucode *uc; 2203 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2204 int count; 2205 2206 if (sc->sc_flags & FXPF_UCODE_LOADED) 2207 return; 2208 2209 /* 2210 * Only load the uCode if the user has requested that 2211 * we do so. 2212 */ 2213 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2214 sc->sc_int_delay = 0; 2215 sc->sc_bundle_max = 0; 2216 return; 2217 } 2218 2219 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2220 if (sc->sc_rev == uc->revision) 2221 break; 2222 } 2223 if (uc->ucode == NULL) 2224 return; 2225 2226 /* BIG ENDIAN: no need to swap to store 0 */ 2227 cbp->cb_status = 0; 2228 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2229 cbp->link_addr = 0xffffffff; /* (no) next command */ 2230 memcpy((void *) cbp->ucode, uc->ucode, uc->length); 2231 2232 if (uc->int_delay_offset) 2233 *(uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2234 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2235 2236 if (uc->bundle_max_offset) 2237 *(uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2238 htole16(fxp_bundle_max); 2239 2240 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2241 2242 /* 2243 * Download the uCode to the chip. 2244 */ 2245 fxp_scb_wait(sc); 2246 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2247 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2248 2249 /* ...and wait for it to complete. */ 2250 count = 10000; 2251 do { 2252 FXP_CDUCODESYNC(sc, 2253 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2254 DELAY(2); 2255 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2256 if (count == 0) { 2257 sc->sc_int_delay = 0; 2258 sc->sc_bundle_max = 0; 2259 printf("%s: timeout loading microcode\n", 2260 sc->sc_dev.dv_xname); 2261 return; 2262 } 2263 2264 if (sc->sc_int_delay != fxp_int_delay || 2265 sc->sc_bundle_max != fxp_bundle_max) { 2266 sc->sc_int_delay = fxp_int_delay; 2267 sc->sc_bundle_max = fxp_bundle_max; 2268 printf("%s: Microcode loaded: int delay: %d usec, " 2269 "max bundle: %d\n", sc->sc_dev.dv_xname, 2270 sc->sc_int_delay, 2271 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2272 } 2273 2274 sc->sc_flags |= FXPF_UCODE_LOADED; 2275 } 2276 2277 int 2278 fxp_enable(struct fxp_softc *sc) 2279 { 2280 2281 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2282 if ((*sc->sc_enable)(sc) != 0) { 2283 printf("%s: device enable failed\n", 2284 sc->sc_dev.dv_xname); 2285 return (EIO); 2286 } 2287 } 2288 2289 sc->sc_enabled = 1; 2290 return (0); 2291 } 2292 2293 void 2294 fxp_disable(struct fxp_softc *sc) 2295 { 2296 2297 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2298 (*sc->sc_disable)(sc); 2299 sc->sc_enabled = 0; 2300 } 2301 } 2302 2303 /* 2304 * fxp_activate: 2305 * 2306 * Handle device activation/deactivation requests. 2307 */ 2308 int 2309 fxp_activate(struct device *self, enum devact act) 2310 { 2311 struct fxp_softc *sc = (void *) self; 2312 int s, error = 0; 2313 2314 s = splnet(); 2315 switch (act) { 2316 case DVACT_ACTIVATE: 2317 error = EOPNOTSUPP; 2318 break; 2319 2320 case DVACT_DEACTIVATE: 2321 if (sc->sc_flags & FXPF_MII) 2322 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2323 MII_OFFSET_ANY); 2324 if_deactivate(&sc->sc_ethercom.ec_if); 2325 break; 2326 } 2327 splx(s); 2328 2329 return (error); 2330 } 2331 2332 /* 2333 * fxp_detach: 2334 * 2335 * Detach an i82557 interface. 2336 */ 2337 int 2338 fxp_detach(struct fxp_softc *sc) 2339 { 2340 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2341 int i; 2342 2343 /* Succeed now if there's no work to do. */ 2344 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2345 return (0); 2346 2347 /* Unhook our tick handler. */ 2348 callout_stop(&sc->sc_callout); 2349 2350 if (sc->sc_flags & FXPF_MII) { 2351 /* Detach all PHYs */ 2352 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2353 } 2354 2355 /* Delete all remaining media. */ 2356 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2357 2358 #if NRND > 0 2359 rnd_detach_source(&sc->rnd_source); 2360 #endif 2361 ether_ifdetach(ifp); 2362 if_detach(ifp); 2363 2364 for (i = 0; i < FXP_NRFABUFS; i++) { 2365 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2366 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2367 } 2368 2369 for (i = 0; i < FXP_NTXCB; i++) { 2370 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2371 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2372 } 2373 2374 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2375 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2376 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2377 sizeof(struct fxp_control_data)); 2378 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2379 2380 shutdownhook_disestablish(sc->sc_sdhook); 2381 powerhook_disestablish(sc->sc_powerhook); 2382 2383 return (0); 2384 } 2385
Indexes created Sun Sep 28 12:09:53 GMT 2025