i82557.c revision 1.80
1 /* $NetBSD: i82557.c,v 1.80 2004/02/19 13:34:51 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.80 2004/02/19 13:34:51 yamt Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 92 #include <machine/endian.h> 93 94 #include <uvm/uvm_extern.h> 95 96 #if NRND > 0 97 #include <sys/rnd.h> 98 #endif 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <machine/bus.h> 110 #include <machine/intr.h> 111 112 #include <dev/mii/miivar.h> 113 114 #include <dev/ic/i82557reg.h> 115 #include <dev/ic/i82557var.h> 116 117 #include <dev/microcode/i8255x/rcvbundl.h> 118 119 /* 120 * NOTE! On the Alpha, we have an alignment constraint. The 121 * card DMAs the packet immediately following the RFA. However, 122 * the first thing in the packet is a 14-byte Ethernet header. 123 * This means that the packet is misaligned. To compensate, 124 * we actually offset the RFA 2 bytes into the cluster. This 125 * alignes the packet after the Ethernet header at a 32-bit 126 * boundary. HOWEVER! This means that the RFA is misaligned! 127 */ 128 #define RFA_ALIGNMENT_FUDGE 2 129 130 /* 131 * The configuration byte map has several undefined fields which 132 * must be one or must be zero. Set up a template for these bits 133 * only (assuming an i82557 chip), leaving the actual configuration 134 * for fxp_init(). 135 * 136 * See the definition of struct fxp_cb_config for the bit definitions. 137 */ 138 const u_int8_t fxp_cb_config_template[] = { 139 0x0, 0x0, /* cb_status */ 140 0x0, 0x0, /* cb_command */ 141 0x0, 0x0, 0x0, 0x0, /* link_addr */ 142 0x0, /* 0 */ 143 0x0, /* 1 */ 144 0x0, /* 2 */ 145 0x0, /* 3 */ 146 0x0, /* 4 */ 147 0x0, /* 5 */ 148 0x32, /* 6 */ 149 0x0, /* 7 */ 150 0x0, /* 8 */ 151 0x0, /* 9 */ 152 0x6, /* 10 */ 153 0x0, /* 11 */ 154 0x0, /* 12 */ 155 0x0, /* 13 */ 156 0xf2, /* 14 */ 157 0x48, /* 15 */ 158 0x0, /* 16 */ 159 0x40, /* 17 */ 160 0xf0, /* 18 */ 161 0x0, /* 19 */ 162 0x3f, /* 20 */ 163 0x5, /* 21 */ 164 0x0, /* 22 */ 165 0x0, /* 23 */ 166 0x0, /* 24 */ 167 0x0, /* 25 */ 168 0x0, /* 26 */ 169 0x0, /* 27 */ 170 0x0, /* 28 */ 171 0x0, /* 29 */ 172 0x0, /* 30 */ 173 0x0, /* 31 */ 174 }; 175 176 void fxp_mii_initmedia(struct fxp_softc *); 177 int fxp_mii_mediachange(struct ifnet *); 178 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 void fxp_80c24_initmedia(struct fxp_softc *); 181 int fxp_80c24_mediachange(struct ifnet *); 182 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184 void fxp_start(struct ifnet *); 185 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 186 void fxp_watchdog(struct ifnet *); 187 int fxp_init(struct ifnet *); 188 void fxp_stop(struct ifnet *, int); 189 190 void fxp_txintr(struct fxp_softc *); 191 void fxp_rxintr(struct fxp_softc *); 192 193 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 194 195 void fxp_rxdrain(struct fxp_softc *); 196 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 197 int fxp_mdi_read(struct device *, int, int); 198 void fxp_statchg(struct device *); 199 void fxp_mdi_write(struct device *, int, int, int); 200 void fxp_autosize_eeprom(struct fxp_softc*); 201 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 202 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_eeprom_update_cksum(struct fxp_softc *); 204 void fxp_get_info(struct fxp_softc *, u_int8_t *); 205 void fxp_tick(void *); 206 void fxp_mc_setup(struct fxp_softc *); 207 void fxp_load_ucode(struct fxp_softc *); 208 209 void fxp_shutdown(void *); 210 void fxp_power(int, void *); 211 212 int fxp_copy_small = 0; 213 214 /* 215 * Variables for interrupt mitigating microcode. 216 */ 217 int fxp_int_delay = 1000; /* usec */ 218 int fxp_bundle_max = 6; /* packets */ 219 220 struct fxp_phytype { 221 int fp_phy; /* type of PHY, -1 for MII at the end. */ 222 void (*fp_init)(struct fxp_softc *); 223 } fxp_phytype_table[] = { 224 { FXP_PHY_80C24, fxp_80c24_initmedia }, 225 { -1, fxp_mii_initmedia }, 226 }; 227 228 /* 229 * Set initial transmit threshold at 64 (512 bytes). This is 230 * increased by 64 (512 bytes) at a time, to maximum of 192 231 * (1536 bytes), if an underrun occurs. 232 */ 233 static int tx_threshold = 64; 234 235 /* 236 * Wait for the previous command to be accepted (but not necessarily 237 * completed). 238 */ 239 static __inline void 240 fxp_scb_wait(struct fxp_softc *sc) 241 { 242 int i = 10000; 243 244 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 245 delay(2); 246 if (i == 0) 247 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 248 } 249 250 /* 251 * Submit a command to the i82557. 252 */ 253 static __inline void 254 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 255 { 256 257 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 258 } 259 260 /* 261 * Finish attaching an i82557 interface. Called by bus-specific front-end. 262 */ 263 void 264 fxp_attach(struct fxp_softc *sc) 265 { 266 u_int8_t enaddr[ETHER_ADDR_LEN]; 267 struct ifnet *ifp; 268 bus_dma_segment_t seg; 269 int rseg, i, error; 270 struct fxp_phytype *fp; 271 272 callout_init(&sc->sc_callout); 273 274 /* 275 * Enable some good stuff on i82558 and later. 276 */ 277 if (sc->sc_rev >= FXP_REV_82558_A4) { 278 /* Enable the extended TxCB. */ 279 sc->sc_flags |= FXPF_EXT_TXCB; 280 } 281 282 /* 283 * Enable use of extended RFDs and TCBs for 82550 284 * and later chips. Note: we need extended TXCB support 285 * too, but that's already enabled by the code above. 286 * Be careful to do this only on the right devices. 287 */ 288 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 289 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 290 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 291 } else { 292 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 293 } 294 295 sc->sc_rfa_size = 296 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 297 298 /* 299 * Allocate the control data structures, and create and load the 300 * DMA map for it. 301 */ 302 if ((error = bus_dmamem_alloc(sc->sc_dmat, 303 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 304 0)) != 0) { 305 aprint_error( 306 "%s: unable to allocate control data, error = %d\n", 307 sc->sc_dev.dv_xname, error); 308 goto fail_0; 309 } 310 311 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 312 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 313 BUS_DMA_COHERENT)) != 0) { 314 aprint_error("%s: unable to map control data, error = %d\n", 315 sc->sc_dev.dv_xname, error); 316 goto fail_1; 317 } 318 sc->sc_cdseg = seg; 319 sc->sc_cdnseg = rseg; 320 321 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 322 323 if ((error = bus_dmamap_create(sc->sc_dmat, 324 sizeof(struct fxp_control_data), 1, 325 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 326 aprint_error("%s: unable to create control data DMA map, " 327 "error = %d\n", sc->sc_dev.dv_xname, error); 328 goto fail_2; 329 } 330 331 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 332 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 333 0)) != 0) { 334 aprint_error( 335 "%s: can't load control data DMA map, error = %d\n", 336 sc->sc_dev.dv_xname, error); 337 goto fail_3; 338 } 339 340 /* 341 * Create the transmit buffer DMA maps. 342 */ 343 for (i = 0; i < FXP_NTXCB; i++) { 344 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 345 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 346 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 347 aprint_error("%s: unable to create tx DMA map %d, " 348 "error = %d\n", sc->sc_dev.dv_xname, i, error); 349 goto fail_4; 350 } 351 } 352 353 /* 354 * Create the receive buffer DMA maps. 355 */ 356 for (i = 0; i < FXP_NRFABUFS; i++) { 357 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 359 aprint_error("%s: unable to create rx DMA map %d, " 360 "error = %d\n", sc->sc_dev.dv_xname, i, error); 361 goto fail_5; 362 } 363 } 364 365 /* Initialize MAC address and media structures. */ 366 fxp_get_info(sc, enaddr); 367 368 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 369 ether_sprintf(enaddr)); 370 371 ifp = &sc->sc_ethercom.ec_if; 372 373 /* 374 * Get info about our media interface, and initialize it. Note 375 * the table terminates itself with a phy of -1, indicating 376 * that we're using MII. 377 */ 378 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 379 if (fp->fp_phy == sc->phy_primary_device) 380 break; 381 (*fp->fp_init)(sc); 382 383 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 384 ifp->if_softc = sc; 385 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 386 ifp->if_ioctl = fxp_ioctl; 387 ifp->if_start = fxp_start; 388 ifp->if_watchdog = fxp_watchdog; 389 ifp->if_init = fxp_init; 390 ifp->if_stop = fxp_stop; 391 IFQ_SET_READY(&ifp->if_snd); 392 393 if (sc->sc_flags & FXPF_IPCB) { 394 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 395 /* 396 * IFCAP_CSUM_IPv4 seems to have a problem, 397 * at least, on i82550 rev.12. 398 * specifically, it doesn't calculate ipv4 checksum correctly 399 * when sending 20 byte ipv4 header + 1 or 2 byte data. 400 * FreeBSD driver has related comments. 401 * 402 * XXX we should have separate IFCAP flags 403 * for transmit and receive. 404 */ 405 ifp->if_capabilities = 406 /*IFCAP_CSUM_IPv4 |*/ IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 407 } 408 409 /* 410 * We can support 802.1Q VLAN-sized frames. 411 */ 412 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 413 414 /* 415 * Attach the interface. 416 */ 417 if_attach(ifp); 418 ether_ifattach(ifp, enaddr); 419 #if NRND > 0 420 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 421 RND_TYPE_NET, 0); 422 #endif 423 424 #ifdef FXP_EVENT_COUNTERS 425 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 426 NULL, sc->sc_dev.dv_xname, "txstall"); 427 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 428 NULL, sc->sc_dev.dv_xname, "txintr"); 429 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 430 NULL, sc->sc_dev.dv_xname, "rxintr"); 431 #endif /* FXP_EVENT_COUNTERS */ 432 433 /* 434 * Add shutdown hook so that DMA is disabled prior to reboot. Not 435 * doing do could allow DMA to corrupt kernel memory during the 436 * reboot before the driver initializes. 437 */ 438 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 439 if (sc->sc_sdhook == NULL) 440 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 441 sc->sc_dev.dv_xname); 442 /* 443 * Add suspend hook, for similar reasons.. 444 */ 445 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 446 if (sc->sc_powerhook == NULL) 447 aprint_error("%s: WARNING: unable to establish power hook\n", 448 sc->sc_dev.dv_xname); 449 450 /* The attach is successful. */ 451 sc->sc_flags |= FXPF_ATTACHED; 452 453 return; 454 455 /* 456 * Free any resources we've allocated during the failed attach 457 * attempt. Do this in reverse order and fall though. 458 */ 459 fail_5: 460 for (i = 0; i < FXP_NRFABUFS; i++) { 461 if (sc->sc_rxmaps[i] != NULL) 462 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 463 } 464 fail_4: 465 for (i = 0; i < FXP_NTXCB; i++) { 466 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 467 bus_dmamap_destroy(sc->sc_dmat, 468 FXP_DSTX(sc, i)->txs_dmamap); 469 } 470 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 471 fail_3: 472 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 473 fail_2: 474 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 475 sizeof(struct fxp_control_data)); 476 fail_1: 477 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 478 fail_0: 479 return; 480 } 481 482 void 483 fxp_mii_initmedia(struct fxp_softc *sc) 484 { 485 int flags; 486 487 sc->sc_flags |= FXPF_MII; 488 489 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 490 sc->sc_mii.mii_readreg = fxp_mdi_read; 491 sc->sc_mii.mii_writereg = fxp_mdi_write; 492 sc->sc_mii.mii_statchg = fxp_statchg; 493 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 494 fxp_mii_mediastatus); 495 496 flags = MIIF_NOISOLATE; 497 if (sc->sc_rev >= FXP_REV_82558_A4) 498 flags |= MIIF_DOPAUSE; 499 /* 500 * The i82557 wedges if all of its PHYs are isolated! 501 */ 502 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 503 MII_OFFSET_ANY, flags); 504 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 505 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 506 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 507 } else 508 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 509 } 510 511 void 512 fxp_80c24_initmedia(struct fxp_softc *sc) 513 { 514 515 /* 516 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 517 * doesn't have a programming interface of any sort. The 518 * media is sensed automatically based on how the link partner 519 * is configured. This is, in essence, manual configuration. 520 */ 521 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 522 sc->sc_dev.dv_xname); 523 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 524 fxp_80c24_mediastatus); 525 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 526 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 527 } 528 529 /* 530 * Device shutdown routine. Called at system shutdown after sync. The 531 * main purpose of this routine is to shut off receiver DMA so that 532 * kernel memory doesn't get clobbered during warmboot. 533 */ 534 void 535 fxp_shutdown(void *arg) 536 { 537 struct fxp_softc *sc = arg; 538 539 /* 540 * Since the system's going to halt shortly, don't bother 541 * freeing mbufs. 542 */ 543 fxp_stop(&sc->sc_ethercom.ec_if, 0); 544 } 545 /* 546 * Power handler routine. Called when the system is transitioning 547 * into/out of power save modes. As with fxp_shutdown, the main 548 * purpose of this routine is to shut off receiver DMA so it doesn't 549 * clobber kernel memory at the wrong time. 550 */ 551 void 552 fxp_power(int why, void *arg) 553 { 554 struct fxp_softc *sc = arg; 555 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 556 int s; 557 558 s = splnet(); 559 switch (why) { 560 case PWR_SUSPEND: 561 case PWR_STANDBY: 562 fxp_stop(ifp, 0); 563 break; 564 case PWR_RESUME: 565 if (ifp->if_flags & IFF_UP) 566 fxp_init(ifp); 567 break; 568 case PWR_SOFTSUSPEND: 569 case PWR_SOFTSTANDBY: 570 case PWR_SOFTRESUME: 571 break; 572 } 573 splx(s); 574 } 575 576 /* 577 * Initialize the interface media. 578 */ 579 void 580 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 581 { 582 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 583 584 /* 585 * Reset to a stable state. 586 */ 587 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 588 DELAY(100); 589 590 sc->sc_eeprom_size = 0; 591 fxp_autosize_eeprom(sc); 592 if (sc->sc_eeprom_size == 0) { 593 aprint_error("%s: failed to detect EEPROM size\n", 594 sc->sc_dev.dv_xname); 595 sc->sc_eeprom_size = 6; /* XXX panic here? */ 596 } 597 #ifdef DEBUG 598 aprint_debug("%s: detected %d word EEPROM\n", 599 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 600 #endif 601 602 /* 603 * Get info about the primary PHY 604 */ 605 fxp_read_eeprom(sc, &data, 6, 1); 606 sc->phy_primary_device = 607 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 608 609 /* 610 * Read MAC address. 611 */ 612 fxp_read_eeprom(sc, myea, 0, 3); 613 enaddr[0] = myea[0] & 0xff; 614 enaddr[1] = myea[0] >> 8; 615 enaddr[2] = myea[1] & 0xff; 616 enaddr[3] = myea[1] >> 8; 617 enaddr[4] = myea[2] & 0xff; 618 enaddr[5] = myea[2] >> 8; 619 620 /* 621 * Systems based on the ICH2/ICH2-M chip from Intel, as well 622 * as some i82559 designs, have a defect where the chip can 623 * cause a PCI protocol violation if it receives a CU_RESUME 624 * command when it is entering the IDLE state. 625 * 626 * The work-around is to disable Dynamic Standby Mode, so that 627 * the chip never deasserts #CLKRUN, and always remains in the 628 * active state. 629 * 630 * Unfortunately, the only way to disable Dynamic Standby is 631 * to frob an EEPROM setting and reboot (the EEPROM setting 632 * is only consulted when the PCI bus comes out of reset). 633 * 634 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 635 */ 636 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 637 fxp_read_eeprom(sc, &data, 10, 1); 638 if (data & 0x02) { /* STB enable */ 639 aprint_error("%s: WARNING: " 640 "Disabling dynamic standby mode in EEPROM " 641 "to work around a\n", 642 sc->sc_dev.dv_xname); 643 aprint_normal( 644 "%s: WARNING: hardware bug. You must reset " 645 "the system before using this\n", 646 sc->sc_dev.dv_xname); 647 aprint_normal("%s: WARNING: interface.\n", 648 sc->sc_dev.dv_xname); 649 data &= ~0x02; 650 fxp_write_eeprom(sc, &data, 10, 1); 651 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 652 sc->sc_dev.dv_xname, data); 653 fxp_eeprom_update_cksum(sc); 654 } 655 } 656 } 657 658 static void 659 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 660 { 661 uint16_t reg; 662 int x; 663 664 for (x = 1 << (len - 1); x != 0; x >>= 1) { 665 DELAY(40); 666 if (data & x) 667 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 668 else 669 reg = FXP_EEPROM_EECS; 670 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 671 DELAY(40); 672 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 673 reg | FXP_EEPROM_EESK); 674 DELAY(40); 675 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 676 } 677 DELAY(40); 678 } 679 680 /* 681 * Figure out EEPROM size. 682 * 683 * 559's can have either 64-word or 256-word EEPROMs, the 558 684 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 685 * talks about the existence of 16 to 256 word EEPROMs. 686 * 687 * The only known sizes are 64 and 256, where the 256 version is used 688 * by CardBus cards to store CIS information. 689 * 690 * The address is shifted in msb-to-lsb, and after the last 691 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 692 * after which follows the actual data. We try to detect this zero, by 693 * probing the data-out bit in the EEPROM control register just after 694 * having shifted in a bit. If the bit is zero, we assume we've 695 * shifted enough address bits. The data-out should be tri-state, 696 * before this, which should translate to a logical one. 697 * 698 * Other ways to do this would be to try to read a register with known 699 * contents with a varying number of address bits, but no such 700 * register seem to be available. The high bits of register 10 are 01 701 * on the 558 and 559, but apparently not on the 557. 702 * 703 * The Linux driver computes a checksum on the EEPROM data, but the 704 * value of this checksum is not very well documented. 705 */ 706 707 void 708 fxp_autosize_eeprom(struct fxp_softc *sc) 709 { 710 int x; 711 712 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 713 DELAY(40); 714 715 /* Shift in read opcode. */ 716 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 717 718 /* 719 * Shift in address, wait for the dummy zero following a correct 720 * address shift. 721 */ 722 for (x = 1; x <= 8; x++) { 723 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 724 DELAY(40); 725 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 726 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 727 DELAY(40); 728 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 729 FXP_EEPROM_EEDO) == 0) 730 break; 731 DELAY(40); 732 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 733 DELAY(40); 734 } 735 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 736 DELAY(40); 737 if (x != 6 && x != 8) { 738 #ifdef DEBUG 739 printf("%s: strange EEPROM size (%d)\n", 740 sc->sc_dev.dv_xname, 1 << x); 741 #endif 742 } else 743 sc->sc_eeprom_size = x; 744 } 745 746 /* 747 * Read from the serial EEPROM. Basically, you manually shift in 748 * the read opcode (one bit at a time) and then shift in the address, 749 * and then you shift out the data (all of this one bit at a time). 750 * The word size is 16 bits, so you have to provide the address for 751 * every 16 bits of data. 752 */ 753 void 754 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 755 { 756 u_int16_t reg; 757 int i, x; 758 759 for (i = 0; i < words; i++) { 760 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 761 762 /* Shift in read opcode. */ 763 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 764 765 /* Shift in address. */ 766 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 767 768 reg = FXP_EEPROM_EECS; 769 data[i] = 0; 770 771 /* Shift out data. */ 772 for (x = 16; x > 0; x--) { 773 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 774 reg | FXP_EEPROM_EESK); 775 DELAY(40); 776 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 777 FXP_EEPROM_EEDO) 778 data[i] |= (1 << (x - 1)); 779 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 780 DELAY(40); 781 } 782 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 783 DELAY(40); 784 } 785 } 786 787 /* 788 * Write data to the serial EEPROM. 789 */ 790 void 791 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 792 { 793 int i, j; 794 795 for (i = 0; i < words; i++) { 796 /* Erase/write enable. */ 797 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 798 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 799 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 800 sc->sc_eeprom_size); 801 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 802 DELAY(4); 803 804 /* Shift in write opcode, address, data. */ 805 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 806 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 807 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 808 fxp_eeprom_shiftin(sc, data[i], 16); 809 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 810 DELAY(4); 811 812 /* Wait for the EEPROM to finish up. */ 813 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 814 DELAY(4); 815 for (j = 0; j < 1000; j++) { 816 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 817 FXP_EEPROM_EEDO) 818 break; 819 DELAY(50); 820 } 821 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 822 DELAY(4); 823 824 /* Erase/write disable. */ 825 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 826 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 827 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 828 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 829 DELAY(4); 830 } 831 } 832 833 /* 834 * Update the checksum of the EEPROM. 835 */ 836 void 837 fxp_eeprom_update_cksum(struct fxp_softc *sc) 838 { 839 int i; 840 uint16_t data, cksum; 841 842 cksum = 0; 843 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 844 fxp_read_eeprom(sc, &data, i, 1); 845 cksum += data; 846 } 847 i = (1 << sc->sc_eeprom_size) - 1; 848 cksum = 0xbaba - cksum; 849 fxp_read_eeprom(sc, &data, i, 1); 850 fxp_write_eeprom(sc, &cksum, i, 1); 851 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 852 sc->sc_dev.dv_xname, i, data, cksum); 853 } 854 855 /* 856 * Start packet transmission on the interface. 857 */ 858 void 859 fxp_start(struct ifnet *ifp) 860 { 861 struct fxp_softc *sc = ifp->if_softc; 862 struct mbuf *m0, *m; 863 struct fxp_txdesc *txd; 864 struct fxp_txsoft *txs; 865 bus_dmamap_t dmamap; 866 int error, lasttx, nexttx, opending, seg; 867 868 /* 869 * If we want a re-init, bail out now. 870 */ 871 if (sc->sc_flags & FXPF_WANTINIT) { 872 ifp->if_flags |= IFF_OACTIVE; 873 return; 874 } 875 876 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 877 return; 878 879 /* 880 * Remember the previous txpending and the current lasttx. 881 */ 882 opending = sc->sc_txpending; 883 lasttx = sc->sc_txlast; 884 885 /* 886 * Loop through the send queue, setting up transmit descriptors 887 * until we drain the queue, or use up all available transmit 888 * descriptors. 889 */ 890 for (;;) { 891 struct fxp_tbd *tbdp; 892 int csum_flags; 893 894 /* 895 * Grab a packet off the queue. 896 */ 897 IFQ_POLL(&ifp->if_snd, m0); 898 if (m0 == NULL) 899 break; 900 m = NULL; 901 902 if (sc->sc_txpending == FXP_NTXCB) { 903 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 904 break; 905 } 906 907 /* 908 * Get the next available transmit descriptor. 909 */ 910 nexttx = FXP_NEXTTX(sc->sc_txlast); 911 txd = FXP_CDTX(sc, nexttx); 912 txs = FXP_DSTX(sc, nexttx); 913 dmamap = txs->txs_dmamap; 914 915 /* 916 * Load the DMA map. If this fails, the packet either 917 * didn't fit in the allotted number of frags, or we were 918 * short on resources. In this case, we'll copy and try 919 * again. 920 */ 921 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 922 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 923 MGETHDR(m, M_DONTWAIT, MT_DATA); 924 if (m == NULL) { 925 printf("%s: unable to allocate Tx mbuf\n", 926 sc->sc_dev.dv_xname); 927 break; 928 } 929 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 930 if (m0->m_pkthdr.len > MHLEN) { 931 MCLGET(m, M_DONTWAIT); 932 if ((m->m_flags & M_EXT) == 0) { 933 printf("%s: unable to allocate Tx " 934 "cluster\n", sc->sc_dev.dv_xname); 935 m_freem(m); 936 break; 937 } 938 } 939 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 940 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 941 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 942 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 943 if (error) { 944 printf("%s: unable to load Tx buffer, " 945 "error = %d\n", sc->sc_dev.dv_xname, error); 946 break; 947 } 948 } 949 950 IFQ_DEQUEUE(&ifp->if_snd, m0); 951 csum_flags = m0->m_pkthdr.csum_flags; 952 if (m != NULL) { 953 m_freem(m0); 954 m0 = m; 955 } 956 957 /* Initialize the fraglist. */ 958 tbdp = txd->txd_tbd; 959 if (sc->sc_flags & FXPF_IPCB) 960 tbdp++; 961 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 962 tbdp[seg].tb_addr = 963 htole32(dmamap->dm_segs[seg].ds_addr); 964 tbdp[seg].tb_size = 965 htole32(dmamap->dm_segs[seg].ds_len); 966 } 967 968 /* Sync the DMA map. */ 969 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 970 BUS_DMASYNC_PREWRITE); 971 972 /* 973 * Store a pointer to the packet so we can free it later. 974 */ 975 txs->txs_mbuf = m0; 976 977 /* 978 * Initialize the transmit descriptor. 979 */ 980 /* BIG_ENDIAN: no need to swap to store 0 */ 981 txd->txd_txcb.cb_status = 0; 982 txd->txd_txcb.cb_command = 983 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 984 txd->txd_txcb.tx_threshold = tx_threshold; 985 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 986 987 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 988 if (sc->sc_flags & FXPF_IPCB) { 989 struct fxp_ipcb *ipcb; 990 /* 991 * Deal with TCP/IP checksum offload. Note that 992 * in order for TCP checksum offload to work, 993 * the pseudo header checksum must have already 994 * been computed and stored in the checksum field 995 * in the TCP header. The stack should have 996 * already done this for us. 997 */ 998 ipcb = &txd->txd_u.txdu_ipcb; 999 memset(ipcb, 0, sizeof(*ipcb)); 1000 /* 1001 * always do hardware parsing. 1002 */ 1003 ipcb->ipcb_ip_activation_high = 1004 FXP_IPCB_HARDWAREPARSING_ENABLE; 1005 /* 1006 * ip checksum offloading. 1007 */ 1008 if (csum_flags & M_CSUM_IPv4) { 1009 ipcb->ipcb_ip_schedule |= 1010 FXP_IPCB_IP_CHECKSUM_ENABLE; 1011 } 1012 /* 1013 * TCP/UDP checksum offloading. 1014 */ 1015 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1016 ipcb->ipcb_ip_schedule |= 1017 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1018 } 1019 } else { 1020 KASSERT((csum_flags & 1021 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1022 } 1023 1024 FXP_CDTXSYNC(sc, nexttx, 1025 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1026 1027 /* Advance the tx pointer. */ 1028 sc->sc_txpending++; 1029 sc->sc_txlast = nexttx; 1030 1031 #if NBPFILTER > 0 1032 /* 1033 * Pass packet to bpf if there is a listener. 1034 */ 1035 if (ifp->if_bpf) 1036 bpf_mtap(ifp->if_bpf, m0); 1037 #endif 1038 } 1039 1040 if (sc->sc_txpending == FXP_NTXCB) { 1041 /* No more slots; notify upper layer. */ 1042 ifp->if_flags |= IFF_OACTIVE; 1043 } 1044 1045 if (sc->sc_txpending != opending) { 1046 /* 1047 * We enqueued packets. If the transmitter was idle, 1048 * reset the txdirty pointer. 1049 */ 1050 if (opending == 0) 1051 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1052 1053 /* 1054 * Cause the chip to interrupt and suspend command 1055 * processing once the last packet we've enqueued 1056 * has been transmitted. 1057 */ 1058 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 1059 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1060 FXP_CDTXSYNC(sc, sc->sc_txlast, 1061 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1062 1063 /* 1064 * The entire packet chain is set up. Clear the suspend bit 1065 * on the command prior to the first packet we set up. 1066 */ 1067 FXP_CDTXSYNC(sc, lasttx, 1068 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1069 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1070 htole16(~FXP_CB_COMMAND_S); 1071 FXP_CDTXSYNC(sc, lasttx, 1072 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1073 1074 /* 1075 * Issue a Resume command in case the chip was suspended. 1076 */ 1077 fxp_scb_wait(sc); 1078 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1079 1080 /* Set a watchdog timer in case the chip flakes out. */ 1081 ifp->if_timer = 5; 1082 } 1083 } 1084 1085 /* 1086 * Process interface interrupts. 1087 */ 1088 int 1089 fxp_intr(void *arg) 1090 { 1091 struct fxp_softc *sc = arg; 1092 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1093 bus_dmamap_t rxmap; 1094 int claimed = 0; 1095 u_int8_t statack; 1096 1097 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0 || sc->sc_enabled == 0) 1098 return (0); 1099 /* 1100 * If the interface isn't running, don't try to 1101 * service the interrupt.. just ack it and bail. 1102 */ 1103 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1104 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1105 if (statack) { 1106 claimed = 1; 1107 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1108 } 1109 return (claimed); 1110 } 1111 1112 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1113 claimed = 1; 1114 1115 /* 1116 * First ACK all the interrupts in this pass. 1117 */ 1118 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1119 1120 /* 1121 * Process receiver interrupts. If a no-resource (RNR) 1122 * condition exists, get whatever packets we can and 1123 * re-start the receiver. 1124 */ 1125 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1126 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1127 fxp_rxintr(sc); 1128 } 1129 1130 if (statack & FXP_SCB_STATACK_RNR) { 1131 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1132 fxp_scb_wait(sc); 1133 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1134 rxmap->dm_segs[0].ds_addr + 1135 RFA_ALIGNMENT_FUDGE); 1136 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1137 } 1138 1139 /* 1140 * Free any finished transmit mbuf chains. 1141 */ 1142 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1143 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1144 fxp_txintr(sc); 1145 1146 /* 1147 * Try to get more packets going. 1148 */ 1149 fxp_start(ifp); 1150 1151 if (sc->sc_txpending == 0) { 1152 /* 1153 * If we want a re-init, do that now. 1154 */ 1155 if (sc->sc_flags & FXPF_WANTINIT) 1156 (void) fxp_init(ifp); 1157 } 1158 } 1159 } 1160 1161 #if NRND > 0 1162 if (claimed) 1163 rnd_add_uint32(&sc->rnd_source, statack); 1164 #endif 1165 return (claimed); 1166 } 1167 1168 /* 1169 * Handle transmit completion interrupts. 1170 */ 1171 void 1172 fxp_txintr(struct fxp_softc *sc) 1173 { 1174 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1175 struct fxp_txdesc *txd; 1176 struct fxp_txsoft *txs; 1177 int i; 1178 u_int16_t txstat; 1179 1180 ifp->if_flags &= ~IFF_OACTIVE; 1181 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1182 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1183 txd = FXP_CDTX(sc, i); 1184 txs = FXP_DSTX(sc, i); 1185 1186 FXP_CDTXSYNC(sc, i, 1187 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1188 1189 txstat = le16toh(txd->txd_txcb.cb_status); 1190 1191 if ((txstat & FXP_CB_STATUS_C) == 0) 1192 break; 1193 1194 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1195 0, txs->txs_dmamap->dm_mapsize, 1196 BUS_DMASYNC_POSTWRITE); 1197 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1198 m_freem(txs->txs_mbuf); 1199 txs->txs_mbuf = NULL; 1200 } 1201 1202 /* Update the dirty transmit buffer pointer. */ 1203 sc->sc_txdirty = i; 1204 1205 /* 1206 * Cancel the watchdog timer if there are no pending 1207 * transmissions. 1208 */ 1209 if (sc->sc_txpending == 0) 1210 ifp->if_timer = 0; 1211 } 1212 1213 /* 1214 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1215 */ 1216 1217 int 1218 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1219 { 1220 u_int16_t rxparsestat; 1221 u_int16_t csum_stat; 1222 u_int32_t csum_data; 1223 int csum_flags; 1224 1225 /* 1226 * check VLAN tag stripping. 1227 */ 1228 1229 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1230 struct m_tag *vtag; 1231 1232 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1233 if (vtag == NULL) 1234 return ENOMEM; 1235 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1236 m_tag_prepend(m, vtag); 1237 } 1238 1239 /* 1240 * check H/W Checksumming. 1241 */ 1242 1243 csum_stat = le16toh(rfa->cksum_stat); 1244 rxparsestat = le16toh(rfa->rx_parse_stat); 1245 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1246 return 0; 1247 1248 csum_flags = 0; 1249 csum_data = 0; 1250 1251 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1252 csum_flags = M_CSUM_IPv4; 1253 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1254 csum_flags |= M_CSUM_IPv4_BAD; 1255 } 1256 1257 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1258 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1259 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1260 csum_flags |= M_CSUM_TCP_UDP_BAD; 1261 } 1262 1263 m->m_pkthdr.csum_flags = csum_flags; 1264 m->m_pkthdr.csum_data = csum_data; 1265 1266 return 0; 1267 } 1268 1269 /* 1270 * Handle receive interrupts. 1271 */ 1272 void 1273 fxp_rxintr(struct fxp_softc *sc) 1274 { 1275 struct ethercom *ec = &sc->sc_ethercom; 1276 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1277 struct mbuf *m, *m0; 1278 bus_dmamap_t rxmap; 1279 struct fxp_rfa *rfa; 1280 u_int16_t len, rxstat; 1281 1282 for (;;) { 1283 m = sc->sc_rxq.ifq_head; 1284 rfa = FXP_MTORFA(m); 1285 rxmap = M_GETCTX(m, bus_dmamap_t); 1286 1287 FXP_RFASYNC(sc, m, 1288 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1289 1290 rxstat = le16toh(rfa->rfa_status); 1291 1292 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1293 /* 1294 * We have processed all of the 1295 * receive buffers. 1296 */ 1297 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1298 return; 1299 } 1300 1301 IF_DEQUEUE(&sc->sc_rxq, m); 1302 1303 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1304 1305 len = le16toh(rfa->actual_size) & 1306 (m->m_ext.ext_size - 1); 1307 1308 if (len < sizeof(struct ether_header)) { 1309 /* 1310 * Runt packet; drop it now. 1311 */ 1312 FXP_INIT_RFABUF(sc, m); 1313 continue; 1314 } 1315 1316 /* 1317 * If support for 802.1Q VLAN sized frames is 1318 * enabled, we need to do some additional error 1319 * checking (as we are saving bad frames, in 1320 * order to receive the larger ones). 1321 */ 1322 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1323 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1324 FXP_RFA_STATUS_RNR| 1325 FXP_RFA_STATUS_ALIGN| 1326 FXP_RFA_STATUS_CRC)) != 0) { 1327 FXP_INIT_RFABUF(sc, m); 1328 continue; 1329 } 1330 1331 /* Do checksum checking. */ 1332 m->m_pkthdr.csum_flags = 0; 1333 if (sc->sc_flags & FXPF_EXT_RFA) 1334 if (fxp_rx_hwcksum(m, rfa)) 1335 goto dropit; 1336 1337 /* 1338 * If the packet is small enough to fit in a 1339 * single header mbuf, allocate one and copy 1340 * the data into it. This greatly reduces 1341 * memory consumption when we receive lots 1342 * of small packets. 1343 * 1344 * Otherwise, we add a new buffer to the receive 1345 * chain. If this fails, we drop the packet and 1346 * recycle the old buffer. 1347 */ 1348 if (fxp_copy_small != 0 && len <= MHLEN) { 1349 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1350 if (m0 == NULL) 1351 goto dropit; 1352 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1353 memcpy(mtod(m0, caddr_t), 1354 mtod(m, caddr_t), len); 1355 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1356 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1357 FXP_INIT_RFABUF(sc, m); 1358 m = m0; 1359 } else { 1360 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1361 dropit: 1362 ifp->if_ierrors++; 1363 FXP_INIT_RFABUF(sc, m); 1364 continue; 1365 } 1366 } 1367 1368 m->m_pkthdr.rcvif = ifp; 1369 m->m_pkthdr.len = m->m_len = len; 1370 1371 #if NBPFILTER > 0 1372 /* 1373 * Pass this up to any BPF listeners, but only 1374 * pass it up the stack it its for us. 1375 */ 1376 if (ifp->if_bpf) 1377 bpf_mtap(ifp->if_bpf, m); 1378 #endif 1379 1380 /* Pass it on. */ 1381 (*ifp->if_input)(ifp, m); 1382 } 1383 } 1384 1385 /* 1386 * Update packet in/out/collision statistics. The i82557 doesn't 1387 * allow you to access these counters without doing a fairly 1388 * expensive DMA to get _all_ of the statistics it maintains, so 1389 * we do this operation here only once per second. The statistics 1390 * counters in the kernel are updated from the previous dump-stats 1391 * DMA and then a new dump-stats DMA is started. The on-chip 1392 * counters are zeroed when the DMA completes. If we can't start 1393 * the DMA immediately, we don't wait - we just prepare to read 1394 * them again next time. 1395 */ 1396 void 1397 fxp_tick(void *arg) 1398 { 1399 struct fxp_softc *sc = arg; 1400 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1401 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1402 int s; 1403 1404 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1405 return; 1406 1407 s = splnet(); 1408 1409 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1410 1411 ifp->if_opackets += le32toh(sp->tx_good); 1412 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1413 if (sp->rx_good) { 1414 ifp->if_ipackets += le32toh(sp->rx_good); 1415 sc->sc_rxidle = 0; 1416 } else { 1417 sc->sc_rxidle++; 1418 } 1419 ifp->if_ierrors += 1420 le32toh(sp->rx_crc_errors) + 1421 le32toh(sp->rx_alignment_errors) + 1422 le32toh(sp->rx_rnr_errors) + 1423 le32toh(sp->rx_overrun_errors); 1424 /* 1425 * If any transmit underruns occurred, bump up the transmit 1426 * threshold by another 512 bytes (64 * 8). 1427 */ 1428 if (sp->tx_underruns) { 1429 ifp->if_oerrors += le32toh(sp->tx_underruns); 1430 if (tx_threshold < 192) 1431 tx_threshold += 64; 1432 } 1433 1434 /* 1435 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1436 * then assume the receiver has locked up and attempt to clear 1437 * the condition by reprogramming the multicast filter (actually, 1438 * resetting the interface). This is a work-around for a bug in 1439 * the 82557 where the receiver locks up if it gets certain types 1440 * of garbage in the synchronization bits prior to the packet header. 1441 * This bug is supposed to only occur in 10Mbps mode, but has been 1442 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1443 * speed transition). 1444 */ 1445 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1446 (void) fxp_init(ifp); 1447 splx(s); 1448 return; 1449 } 1450 /* 1451 * If there is no pending command, start another stats 1452 * dump. Otherwise punt for now. 1453 */ 1454 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1455 /* 1456 * Start another stats dump. 1457 */ 1458 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1459 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1460 } else { 1461 /* 1462 * A previous command is still waiting to be accepted. 1463 * Just zero our copy of the stats and wait for the 1464 * next timer event to update them. 1465 */ 1466 /* BIG_ENDIAN: no swap required to store 0 */ 1467 sp->tx_good = 0; 1468 sp->tx_underruns = 0; 1469 sp->tx_total_collisions = 0; 1470 1471 sp->rx_good = 0; 1472 sp->rx_crc_errors = 0; 1473 sp->rx_alignment_errors = 0; 1474 sp->rx_rnr_errors = 0; 1475 sp->rx_overrun_errors = 0; 1476 } 1477 1478 if (sc->sc_flags & FXPF_MII) { 1479 /* Tick the MII clock. */ 1480 mii_tick(&sc->sc_mii); 1481 } 1482 1483 splx(s); 1484 1485 /* 1486 * Schedule another timeout one second from now. 1487 */ 1488 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1489 } 1490 1491 /* 1492 * Drain the receive queue. 1493 */ 1494 void 1495 fxp_rxdrain(struct fxp_softc *sc) 1496 { 1497 bus_dmamap_t rxmap; 1498 struct mbuf *m; 1499 1500 for (;;) { 1501 IF_DEQUEUE(&sc->sc_rxq, m); 1502 if (m == NULL) 1503 break; 1504 rxmap = M_GETCTX(m, bus_dmamap_t); 1505 bus_dmamap_unload(sc->sc_dmat, rxmap); 1506 FXP_RXMAP_PUT(sc, rxmap); 1507 m_freem(m); 1508 } 1509 } 1510 1511 /* 1512 * Stop the interface. Cancels the statistics updater and resets 1513 * the interface. 1514 */ 1515 void 1516 fxp_stop(struct ifnet *ifp, int disable) 1517 { 1518 struct fxp_softc *sc = ifp->if_softc; 1519 struct fxp_txsoft *txs; 1520 int i; 1521 1522 /* 1523 * Turn down interface (done early to avoid bad interactions 1524 * between panics, shutdown hooks, and the watchdog timer) 1525 */ 1526 ifp->if_timer = 0; 1527 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1528 1529 /* 1530 * Cancel stats updater. 1531 */ 1532 callout_stop(&sc->sc_callout); 1533 if (sc->sc_flags & FXPF_MII) { 1534 /* Down the MII. */ 1535 mii_down(&sc->sc_mii); 1536 } 1537 1538 /* 1539 * Issue software reset. This unloads any microcode that 1540 * might already be loaded. 1541 */ 1542 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1543 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1544 DELAY(50); 1545 1546 /* 1547 * Release any xmit buffers. 1548 */ 1549 for (i = 0; i < FXP_NTXCB; i++) { 1550 txs = FXP_DSTX(sc, i); 1551 if (txs->txs_mbuf != NULL) { 1552 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1553 m_freem(txs->txs_mbuf); 1554 txs->txs_mbuf = NULL; 1555 } 1556 } 1557 sc->sc_txpending = 0; 1558 1559 if (disable) { 1560 fxp_rxdrain(sc); 1561 fxp_disable(sc); 1562 } 1563 1564 } 1565 1566 /* 1567 * Watchdog/transmission transmit timeout handler. Called when a 1568 * transmission is started on the interface, but no interrupt is 1569 * received before the timeout. This usually indicates that the 1570 * card has wedged for some reason. 1571 */ 1572 void 1573 fxp_watchdog(struct ifnet *ifp) 1574 { 1575 struct fxp_softc *sc = ifp->if_softc; 1576 1577 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1578 ifp->if_oerrors++; 1579 1580 (void) fxp_init(ifp); 1581 } 1582 1583 /* 1584 * Initialize the interface. Must be called at splnet(). 1585 */ 1586 int 1587 fxp_init(struct ifnet *ifp) 1588 { 1589 struct fxp_softc *sc = ifp->if_softc; 1590 struct fxp_cb_config *cbp; 1591 struct fxp_cb_ias *cb_ias; 1592 struct fxp_txdesc *txd; 1593 bus_dmamap_t rxmap; 1594 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1595 1596 if ((error = fxp_enable(sc)) != 0) 1597 goto out; 1598 1599 /* 1600 * Cancel any pending I/O 1601 */ 1602 fxp_stop(ifp, 0); 1603 1604 /* 1605 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1606 * flag, and this prevents the MII from detaching resulting in 1607 * a panic. The flags field should perhaps be split in runtime 1608 * flags and more static information. For now, just clear the 1609 * only other flag set. 1610 */ 1611 1612 sc->sc_flags &= ~FXPF_WANTINIT; 1613 1614 /* 1615 * Initialize base of CBL and RFA memory. Loading with zero 1616 * sets it up for regular linear addressing. 1617 */ 1618 fxp_scb_wait(sc); 1619 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1620 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1621 1622 fxp_scb_wait(sc); 1623 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1624 1625 /* 1626 * Initialize the multicast filter. Do this now, since we might 1627 * have to setup the config block differently. 1628 */ 1629 fxp_mc_setup(sc); 1630 1631 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1632 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1633 1634 /* 1635 * In order to support receiving 802.1Q VLAN frames, we have to 1636 * enable "save bad frames", since they are 4 bytes larger than 1637 * the normal Ethernet maximum frame length. On i82558 and later, 1638 * we have a better mechanism for this. 1639 */ 1640 save_bf = 0; 1641 lrxen = 0; 1642 vlan_drop = 0; 1643 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1644 if (sc->sc_rev < FXP_REV_82558_A4) 1645 save_bf = 1; 1646 else 1647 lrxen = 1; 1648 if (sc->sc_rev >= FXP_REV_82550) 1649 vlan_drop = 1; 1650 } 1651 1652 /* 1653 * Initialize base of dump-stats buffer. 1654 */ 1655 fxp_scb_wait(sc); 1656 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1657 sc->sc_cddma + FXP_CDSTATSOFF); 1658 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1659 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1660 1661 cbp = &sc->sc_control_data->fcd_configcb; 1662 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1663 1664 /* 1665 * Load microcode for this controller. 1666 */ 1667 fxp_load_ucode(sc); 1668 1669 /* 1670 * This copy is kind of disgusting, but there are a bunch of must be 1671 * zero and must be one bits in this structure and this is the easiest 1672 * way to initialize them all to proper values. 1673 */ 1674 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1675 1676 /* BIG_ENDIAN: no need to swap to store 0 */ 1677 cbp->cb_status = 0; 1678 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1679 FXP_CB_COMMAND_EL); 1680 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1681 cbp->link_addr = 0xffffffff; /* (no) next command */ 1682 /* bytes in config block */ 1683 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1684 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1685 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1686 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1687 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1688 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1689 cbp->type_enable = 0; /* actually reserved */ 1690 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1691 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1692 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1693 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1694 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1695 cbp->late_scb = 0; /* (don't) defer SCB update */ 1696 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1697 cbp->ci_int = 1; /* interrupt on CU idle */ 1698 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1699 cbp->ext_stats_dis = 1; /* disable extended counters */ 1700 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1701 cbp->save_bf = save_bf;/* save bad frames */ 1702 cbp->disc_short_rx = !prm; /* discard short packets */ 1703 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1704 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1705 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1706 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1707 /* interface mode */ 1708 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1709 cbp->csma_dis = 0; /* (don't) disable link */ 1710 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1711 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1712 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1713 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1714 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1715 cbp->nsai = 1; /* (don't) disable source addr insert */ 1716 cbp->preamble_length = 2; /* (7 byte) preamble */ 1717 cbp->loopback = 0; /* (don't) loopback */ 1718 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1719 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1720 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1721 cbp->promiscuous = prm; /* promiscuous mode */ 1722 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1723 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1724 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1725 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1726 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1727 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1728 cbp->padding = 1; /* (do) pad short tx packets */ 1729 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1730 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1731 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1732 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1733 /* must set wake_en in PMCSR also */ 1734 cbp->force_fdx = 0; /* (don't) force full duplex */ 1735 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1736 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1737 cbp->mc_all = allm; /* accept all multicasts */ 1738 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1739 cbp->vlan_drop_en = vlan_drop; 1740 1741 if (sc->sc_rev < FXP_REV_82558_A4) { 1742 /* 1743 * The i82557 has no hardware flow control, the values 1744 * here are the defaults for the chip. 1745 */ 1746 cbp->fc_delay_lsb = 0; 1747 cbp->fc_delay_msb = 0x40; 1748 cbp->pri_fc_thresh = 3; 1749 cbp->tx_fc_dis = 0; 1750 cbp->rx_fc_restop = 0; 1751 cbp->rx_fc_restart = 0; 1752 cbp->fc_filter = 0; 1753 cbp->pri_fc_loc = 1; 1754 } else { 1755 cbp->fc_delay_lsb = 0x1f; 1756 cbp->fc_delay_msb = 0x01; 1757 cbp->pri_fc_thresh = 3; 1758 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1759 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1760 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1761 cbp->fc_filter = !prm; /* drop FC frames to host */ 1762 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1763 } 1764 1765 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1766 1767 /* 1768 * Start the config command/DMA. 1769 */ 1770 fxp_scb_wait(sc); 1771 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1772 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1773 /* ...and wait for it to complete. */ 1774 i = 1000; 1775 do { 1776 FXP_CDCONFIGSYNC(sc, 1777 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1778 DELAY(1); 1779 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1780 if (i == 0) { 1781 printf("%s at line %d: dmasync timeout\n", 1782 sc->sc_dev.dv_xname, __LINE__); 1783 return (ETIMEDOUT); 1784 } 1785 1786 /* 1787 * Initialize the station address. 1788 */ 1789 cb_ias = &sc->sc_control_data->fcd_iascb; 1790 /* BIG_ENDIAN: no need to swap to store 0 */ 1791 cb_ias->cb_status = 0; 1792 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1793 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1794 cb_ias->link_addr = 0xffffffff; 1795 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1796 1797 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1798 1799 /* 1800 * Start the IAS (Individual Address Setup) command/DMA. 1801 */ 1802 fxp_scb_wait(sc); 1803 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1804 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1805 /* ...and wait for it to complete. */ 1806 i = 1000; 1807 do { 1808 FXP_CDIASSYNC(sc, 1809 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1810 DELAY(1); 1811 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1812 if (i == 0) { 1813 printf("%s at line %d: dmasync timeout\n", 1814 sc->sc_dev.dv_xname, __LINE__); 1815 return (ETIMEDOUT); 1816 } 1817 1818 /* 1819 * Initialize the transmit descriptor ring. txlast is initialized 1820 * to the end of the list so that it will wrap around to the first 1821 * descriptor when the first packet is transmitted. 1822 */ 1823 for (i = 0; i < FXP_NTXCB; i++) { 1824 txd = FXP_CDTX(sc, i); 1825 memset(txd, 0, sizeof(*txd)); 1826 txd->txd_txcb.cb_command = 1827 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1828 txd->txd_txcb.link_addr = 1829 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1830 if (sc->sc_flags & FXPF_EXT_TXCB) 1831 txd->txd_txcb.tbd_array_addr = 1832 htole32(FXP_CDTBDADDR(sc, i) + 1833 (2 * sizeof(struct fxp_tbd))); 1834 else 1835 txd->txd_txcb.tbd_array_addr = 1836 htole32(FXP_CDTBDADDR(sc, i)); 1837 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1838 } 1839 sc->sc_txpending = 0; 1840 sc->sc_txdirty = 0; 1841 sc->sc_txlast = FXP_NTXCB - 1; 1842 1843 /* 1844 * Initialize the receive buffer list. 1845 */ 1846 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1847 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1848 rxmap = FXP_RXMAP_GET(sc); 1849 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1850 printf("%s: unable to allocate or map rx " 1851 "buffer %d, error = %d\n", 1852 sc->sc_dev.dv_xname, 1853 sc->sc_rxq.ifq_len, error); 1854 /* 1855 * XXX Should attempt to run with fewer receive 1856 * XXX buffers instead of just failing. 1857 */ 1858 FXP_RXMAP_PUT(sc, rxmap); 1859 fxp_rxdrain(sc); 1860 goto out; 1861 } 1862 } 1863 sc->sc_rxidle = 0; 1864 1865 /* 1866 * Give the transmit ring to the chip. We do this by pointing 1867 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1868 * issuing a start command. It will execute the NOP and then 1869 * suspend, pointing at the first descriptor. 1870 */ 1871 fxp_scb_wait(sc); 1872 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1873 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1874 1875 /* 1876 * Initialize receiver buffer area - RFA. 1877 */ 1878 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1879 fxp_scb_wait(sc); 1880 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1881 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1882 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1883 1884 if (sc->sc_flags & FXPF_MII) { 1885 /* 1886 * Set current media. 1887 */ 1888 mii_mediachg(&sc->sc_mii); 1889 } 1890 1891 /* 1892 * ...all done! 1893 */ 1894 ifp->if_flags |= IFF_RUNNING; 1895 ifp->if_flags &= ~IFF_OACTIVE; 1896 1897 /* 1898 * Start the one second timer. 1899 */ 1900 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1901 1902 /* 1903 * Attempt to start output on the interface. 1904 */ 1905 fxp_start(ifp); 1906 1907 out: 1908 if (error) { 1909 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1910 ifp->if_timer = 0; 1911 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1912 } 1913 return (error); 1914 } 1915 1916 /* 1917 * Change media according to request. 1918 */ 1919 int 1920 fxp_mii_mediachange(struct ifnet *ifp) 1921 { 1922 struct fxp_softc *sc = ifp->if_softc; 1923 1924 if (ifp->if_flags & IFF_UP) 1925 mii_mediachg(&sc->sc_mii); 1926 return (0); 1927 } 1928 1929 /* 1930 * Notify the world which media we're using. 1931 */ 1932 void 1933 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1934 { 1935 struct fxp_softc *sc = ifp->if_softc; 1936 1937 if (sc->sc_enabled == 0) { 1938 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1939 ifmr->ifm_status = 0; 1940 return; 1941 } 1942 1943 mii_pollstat(&sc->sc_mii); 1944 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1945 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1946 } 1947 1948 int 1949 fxp_80c24_mediachange(struct ifnet *ifp) 1950 { 1951 1952 /* Nothing to do here. */ 1953 return (0); 1954 } 1955 1956 void 1957 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1958 { 1959 struct fxp_softc *sc = ifp->if_softc; 1960 1961 /* 1962 * Media is currently-selected media. We cannot determine 1963 * the link status. 1964 */ 1965 ifmr->ifm_status = 0; 1966 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1967 } 1968 1969 /* 1970 * Add a buffer to the end of the RFA buffer list. 1971 * Return 0 if successful, error code on failure. 1972 * 1973 * The RFA struct is stuck at the beginning of mbuf cluster and the 1974 * data pointer is fixed up to point just past it. 1975 */ 1976 int 1977 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1978 { 1979 struct mbuf *m; 1980 int error; 1981 1982 MGETHDR(m, M_DONTWAIT, MT_DATA); 1983 if (m == NULL) 1984 return (ENOBUFS); 1985 1986 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1987 MCLGET(m, M_DONTWAIT); 1988 if ((m->m_flags & M_EXT) == 0) { 1989 m_freem(m); 1990 return (ENOBUFS); 1991 } 1992 1993 if (unload) 1994 bus_dmamap_unload(sc->sc_dmat, rxmap); 1995 1996 M_SETCTX(m, rxmap); 1997 1998 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1999 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2000 BUS_DMA_READ|BUS_DMA_NOWAIT); 2001 if (error) { 2002 printf("%s: can't load rx DMA map %d, error = %d\n", 2003 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 2004 panic("fxp_add_rfabuf"); /* XXX */ 2005 } 2006 2007 FXP_INIT_RFABUF(sc, m); 2008 2009 return (0); 2010 } 2011 2012 int 2013 fxp_mdi_read(struct device *self, int phy, int reg) 2014 { 2015 struct fxp_softc *sc = (struct fxp_softc *)self; 2016 int count = 10000; 2017 int value; 2018 2019 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2020 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2021 2022 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2023 0x10000000) == 0 && count--) 2024 DELAY(10); 2025 2026 if (count <= 0) 2027 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 2028 2029 return (value & 0xffff); 2030 } 2031 2032 void 2033 fxp_statchg(struct device *self) 2034 { 2035 2036 /* Nothing to do. */ 2037 } 2038 2039 void 2040 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2041 { 2042 struct fxp_softc *sc = (struct fxp_softc *)self; 2043 int count = 10000; 2044 2045 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2046 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2047 (value & 0xffff)); 2048 2049 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2050 count--) 2051 DELAY(10); 2052 2053 if (count <= 0) 2054 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2055 } 2056 2057 int 2058 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2059 { 2060 struct fxp_softc *sc = ifp->if_softc; 2061 struct ifreq *ifr = (struct ifreq *)data; 2062 int s, error; 2063 2064 s = splnet(); 2065 2066 switch (cmd) { 2067 case SIOCSIFMEDIA: 2068 case SIOCGIFMEDIA: 2069 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2070 break; 2071 2072 default: 2073 error = ether_ioctl(ifp, cmd, data); 2074 if (error == ENETRESET) { 2075 if (sc->sc_enabled) { 2076 /* 2077 * Multicast list has changed; set the 2078 * hardware filter accordingly. 2079 */ 2080 if (sc->sc_txpending) { 2081 sc->sc_flags |= FXPF_WANTINIT; 2082 error = 0; 2083 } else 2084 error = fxp_init(ifp); 2085 } else 2086 error = 0; 2087 } 2088 break; 2089 } 2090 2091 /* Try to get more packets going. */ 2092 if (sc->sc_enabled) 2093 fxp_start(ifp); 2094 2095 splx(s); 2096 return (error); 2097 } 2098 2099 /* 2100 * Program the multicast filter. 2101 * 2102 * This function must be called at splnet(). 2103 */ 2104 void 2105 fxp_mc_setup(struct fxp_softc *sc) 2106 { 2107 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2108 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2109 struct ethercom *ec = &sc->sc_ethercom; 2110 struct ether_multi *enm; 2111 struct ether_multistep step; 2112 int count, nmcasts; 2113 2114 #ifdef DIAGNOSTIC 2115 if (sc->sc_txpending) 2116 panic("fxp_mc_setup: pending transmissions"); 2117 #endif 2118 2119 ifp->if_flags &= ~IFF_ALLMULTI; 2120 2121 /* 2122 * Initialize multicast setup descriptor. 2123 */ 2124 nmcasts = 0; 2125 ETHER_FIRST_MULTI(step, ec, enm); 2126 while (enm != NULL) { 2127 /* 2128 * Check for too many multicast addresses or if we're 2129 * listening to a range. Either way, we simply have 2130 * to accept all multicasts. 2131 */ 2132 if (nmcasts >= MAXMCADDR || 2133 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2134 ETHER_ADDR_LEN) != 0) { 2135 /* 2136 * Callers of this function must do the 2137 * right thing with this. If we're called 2138 * from outside fxp_init(), the caller must 2139 * detect if the state if IFF_ALLMULTI changes. 2140 * If it does, the caller must then call 2141 * fxp_init(), since allmulti is handled by 2142 * the config block. 2143 */ 2144 ifp->if_flags |= IFF_ALLMULTI; 2145 return; 2146 } 2147 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2148 ETHER_ADDR_LEN); 2149 nmcasts++; 2150 ETHER_NEXT_MULTI(step, enm); 2151 } 2152 2153 /* BIG_ENDIAN: no need to swap to store 0 */ 2154 mcsp->cb_status = 0; 2155 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2156 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2157 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2158 2159 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2160 2161 /* 2162 * Wait until the command unit is not active. This should never 2163 * happen since nothing is queued, but make sure anyway. 2164 */ 2165 count = 100; 2166 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2167 FXP_SCB_CUS_ACTIVE && --count) 2168 DELAY(1); 2169 if (count == 0) { 2170 printf("%s at line %d: command queue timeout\n", 2171 sc->sc_dev.dv_xname, __LINE__); 2172 return; 2173 } 2174 2175 /* 2176 * Start the multicast setup command/DMA. 2177 */ 2178 fxp_scb_wait(sc); 2179 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2180 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2181 2182 /* ...and wait for it to complete. */ 2183 count = 1000; 2184 do { 2185 FXP_CDMCSSYNC(sc, 2186 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2187 DELAY(1); 2188 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2189 if (count == 0) { 2190 printf("%s at line %d: dmasync timeout\n", 2191 sc->sc_dev.dv_xname, __LINE__); 2192 return; 2193 } 2194 } 2195 2196 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2197 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2198 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2199 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2200 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2201 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2202 2203 #define UCODE(x) x, sizeof(x) 2204 2205 static const struct ucode { 2206 int32_t revision; 2207 const uint32_t *ucode; 2208 size_t length; 2209 uint16_t int_delay_offset; 2210 uint16_t bundle_max_offset; 2211 } ucode_table[] = { 2212 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2213 D101_CPUSAVER_DWORD, 0 }, 2214 2215 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2216 D101_CPUSAVER_DWORD, 0 }, 2217 2218 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2219 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2220 2221 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2222 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2223 2224 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2225 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2226 2227 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2228 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2229 2230 { 0, NULL, 0, 0, 0 } 2231 }; 2232 2233 void 2234 fxp_load_ucode(struct fxp_softc *sc) 2235 { 2236 const struct ucode *uc; 2237 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2238 int count; 2239 2240 if (sc->sc_flags & FXPF_UCODE_LOADED) 2241 return; 2242 2243 /* 2244 * Only load the uCode if the user has requested that 2245 * we do so. 2246 */ 2247 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2248 sc->sc_int_delay = 0; 2249 sc->sc_bundle_max = 0; 2250 return; 2251 } 2252 2253 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2254 if (sc->sc_rev == uc->revision) 2255 break; 2256 } 2257 if (uc->ucode == NULL) 2258 return; 2259 2260 /* BIG ENDIAN: no need to swap to store 0 */ 2261 cbp->cb_status = 0; 2262 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2263 cbp->link_addr = 0xffffffff; /* (no) next command */ 2264 memcpy((void *) cbp->ucode, uc->ucode, uc->length); 2265 2266 if (uc->int_delay_offset) 2267 *(uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2268 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2269 2270 if (uc->bundle_max_offset) 2271 *(uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2272 htole16(fxp_bundle_max); 2273 2274 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2275 2276 /* 2277 * Download the uCode to the chip. 2278 */ 2279 fxp_scb_wait(sc); 2280 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2281 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2282 2283 /* ...and wait for it to complete. */ 2284 count = 10000; 2285 do { 2286 FXP_CDUCODESYNC(sc, 2287 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2288 DELAY(2); 2289 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2290 if (count == 0) { 2291 sc->sc_int_delay = 0; 2292 sc->sc_bundle_max = 0; 2293 printf("%s: timeout loading microcode\n", 2294 sc->sc_dev.dv_xname); 2295 return; 2296 } 2297 2298 if (sc->sc_int_delay != fxp_int_delay || 2299 sc->sc_bundle_max != fxp_bundle_max) { 2300 sc->sc_int_delay = fxp_int_delay; 2301 sc->sc_bundle_max = fxp_bundle_max; 2302 printf("%s: Microcode loaded: int delay: %d usec, " 2303 "max bundle: %d\n", sc->sc_dev.dv_xname, 2304 sc->sc_int_delay, 2305 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2306 } 2307 2308 sc->sc_flags |= FXPF_UCODE_LOADED; 2309 } 2310 2311 int 2312 fxp_enable(struct fxp_softc *sc) 2313 { 2314 2315 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2316 if ((*sc->sc_enable)(sc) != 0) { 2317 printf("%s: device enable failed\n", 2318 sc->sc_dev.dv_xname); 2319 return (EIO); 2320 } 2321 } 2322 2323 sc->sc_enabled = 1; 2324 return (0); 2325 } 2326 2327 void 2328 fxp_disable(struct fxp_softc *sc) 2329 { 2330 2331 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2332 (*sc->sc_disable)(sc); 2333 sc->sc_enabled = 0; 2334 } 2335 } 2336 2337 /* 2338 * fxp_activate: 2339 * 2340 * Handle device activation/deactivation requests. 2341 */ 2342 int 2343 fxp_activate(struct device *self, enum devact act) 2344 { 2345 struct fxp_softc *sc = (void *) self; 2346 int s, error = 0; 2347 2348 s = splnet(); 2349 switch (act) { 2350 case DVACT_ACTIVATE: 2351 error = EOPNOTSUPP; 2352 break; 2353 2354 case DVACT_DEACTIVATE: 2355 if (sc->sc_flags & FXPF_MII) 2356 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2357 MII_OFFSET_ANY); 2358 if_deactivate(&sc->sc_ethercom.ec_if); 2359 break; 2360 } 2361 splx(s); 2362 2363 return (error); 2364 } 2365 2366 /* 2367 * fxp_detach: 2368 * 2369 * Detach an i82557 interface. 2370 */ 2371 int 2372 fxp_detach(struct fxp_softc *sc) 2373 { 2374 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2375 int i; 2376 2377 /* Succeed now if there's no work to do. */ 2378 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2379 return (0); 2380 2381 /* Unhook our tick handler. */ 2382 callout_stop(&sc->sc_callout); 2383 2384 if (sc->sc_flags & FXPF_MII) { 2385 /* Detach all PHYs */ 2386 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2387 } 2388 2389 /* Delete all remaining media. */ 2390 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2391 2392 #if NRND > 0 2393 rnd_detach_source(&sc->rnd_source); 2394 #endif 2395 ether_ifdetach(ifp); 2396 if_detach(ifp); 2397 2398 for (i = 0; i < FXP_NRFABUFS; i++) { 2399 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2400 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2401 } 2402 2403 for (i = 0; i < FXP_NTXCB; i++) { 2404 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2405 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2406 } 2407 2408 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2409 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2410 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2411 sizeof(struct fxp_control_data)); 2412 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2413 2414 shutdownhook_disestablish(sc->sc_sdhook); 2415 powerhook_disestablish(sc->sc_powerhook); 2416 2417 return (0); 2418 } 2419
Indexes created Mon Sep 29 21:09:56 GMT 2025