i82557.c revision 1.85
1 /* $NetBSD: i82557.c,v 1.85 2004/05/16 02:41:46 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.85 2004/05/16 02:41:46 thorpej Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 92 #include <machine/endian.h> 93 94 #include <uvm/uvm_extern.h> 95 96 #if NRND > 0 97 #include <sys/rnd.h> 98 #endif 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <machine/bus.h> 110 #include <machine/intr.h> 111 112 #include <dev/mii/miivar.h> 113 114 #include <dev/ic/i82557reg.h> 115 #include <dev/ic/i82557var.h> 116 117 #include <dev/microcode/i8255x/rcvbundl.h> 118 119 /* 120 * NOTE! On the Alpha, we have an alignment constraint. The 121 * card DMAs the packet immediately following the RFA. However, 122 * the first thing in the packet is a 14-byte Ethernet header. 123 * This means that the packet is misaligned. To compensate, 124 * we actually offset the RFA 2 bytes into the cluster. This 125 * alignes the packet after the Ethernet header at a 32-bit 126 * boundary. HOWEVER! This means that the RFA is misaligned! 127 */ 128 #define RFA_ALIGNMENT_FUDGE 2 129 130 /* 131 * The configuration byte map has several undefined fields which 132 * must be one or must be zero. Set up a template for these bits 133 * only (assuming an i82557 chip), leaving the actual configuration 134 * for fxp_init(). 135 * 136 * See the definition of struct fxp_cb_config for the bit definitions. 137 */ 138 const u_int8_t fxp_cb_config_template[] = { 139 0x0, 0x0, /* cb_status */ 140 0x0, 0x0, /* cb_command */ 141 0x0, 0x0, 0x0, 0x0, /* link_addr */ 142 0x0, /* 0 */ 143 0x0, /* 1 */ 144 0x0, /* 2 */ 145 0x0, /* 3 */ 146 0x0, /* 4 */ 147 0x0, /* 5 */ 148 0x32, /* 6 */ 149 0x0, /* 7 */ 150 0x0, /* 8 */ 151 0x0, /* 9 */ 152 0x6, /* 10 */ 153 0x0, /* 11 */ 154 0x0, /* 12 */ 155 0x0, /* 13 */ 156 0xf2, /* 14 */ 157 0x48, /* 15 */ 158 0x0, /* 16 */ 159 0x40, /* 17 */ 160 0xf0, /* 18 */ 161 0x0, /* 19 */ 162 0x3f, /* 20 */ 163 0x5, /* 21 */ 164 0x0, /* 22 */ 165 0x0, /* 23 */ 166 0x0, /* 24 */ 167 0x0, /* 25 */ 168 0x0, /* 26 */ 169 0x0, /* 27 */ 170 0x0, /* 28 */ 171 0x0, /* 29 */ 172 0x0, /* 30 */ 173 0x0, /* 31 */ 174 }; 175 176 void fxp_mii_initmedia(struct fxp_softc *); 177 int fxp_mii_mediachange(struct ifnet *); 178 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 void fxp_80c24_initmedia(struct fxp_softc *); 181 int fxp_80c24_mediachange(struct ifnet *); 182 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184 void fxp_start(struct ifnet *); 185 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 186 void fxp_watchdog(struct ifnet *); 187 int fxp_init(struct ifnet *); 188 void fxp_stop(struct ifnet *, int); 189 190 void fxp_txintr(struct fxp_softc *); 191 void fxp_rxintr(struct fxp_softc *); 192 193 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 194 195 void fxp_rxdrain(struct fxp_softc *); 196 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 197 int fxp_mdi_read(struct device *, int, int); 198 void fxp_statchg(struct device *); 199 void fxp_mdi_write(struct device *, int, int, int); 200 void fxp_autosize_eeprom(struct fxp_softc*); 201 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 202 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_eeprom_update_cksum(struct fxp_softc *); 204 void fxp_get_info(struct fxp_softc *, u_int8_t *); 205 void fxp_tick(void *); 206 void fxp_mc_setup(struct fxp_softc *); 207 void fxp_load_ucode(struct fxp_softc *); 208 209 void fxp_shutdown(void *); 210 void fxp_power(int, void *); 211 212 int fxp_copy_small = 0; 213 214 /* 215 * Variables for interrupt mitigating microcode. 216 */ 217 int fxp_int_delay = 1000; /* usec */ 218 int fxp_bundle_max = 6; /* packets */ 219 220 struct fxp_phytype { 221 int fp_phy; /* type of PHY, -1 for MII at the end. */ 222 void (*fp_init)(struct fxp_softc *); 223 } fxp_phytype_table[] = { 224 { FXP_PHY_80C24, fxp_80c24_initmedia }, 225 { -1, fxp_mii_initmedia }, 226 }; 227 228 /* 229 * Set initial transmit threshold at 64 (512 bytes). This is 230 * increased by 64 (512 bytes) at a time, to maximum of 192 231 * (1536 bytes), if an underrun occurs. 232 */ 233 static int tx_threshold = 64; 234 235 /* 236 * Wait for the previous command to be accepted (but not necessarily 237 * completed). 238 */ 239 static __inline void 240 fxp_scb_wait(struct fxp_softc *sc) 241 { 242 int i = 10000; 243 244 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 245 delay(2); 246 if (i == 0) 247 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 248 } 249 250 /* 251 * Submit a command to the i82557. 252 */ 253 static __inline void 254 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 255 { 256 257 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 258 } 259 260 /* 261 * Finish attaching an i82557 interface. Called by bus-specific front-end. 262 */ 263 void 264 fxp_attach(struct fxp_softc *sc) 265 { 266 u_int8_t enaddr[ETHER_ADDR_LEN]; 267 struct ifnet *ifp; 268 bus_dma_segment_t seg; 269 int rseg, i, error; 270 struct fxp_phytype *fp; 271 272 callout_init(&sc->sc_callout); 273 274 /* 275 * Enable some good stuff on i82558 and later. 276 */ 277 if (sc->sc_rev >= FXP_REV_82558_A4) { 278 /* Enable the extended TxCB. */ 279 sc->sc_flags |= FXPF_EXT_TXCB; 280 } 281 282 /* 283 * Enable use of extended RFDs and TCBs for 82550 284 * and later chips. Note: we need extended TXCB support 285 * too, but that's already enabled by the code above. 286 * Be careful to do this only on the right devices. 287 */ 288 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 289 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 290 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 291 } else { 292 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 293 } 294 295 sc->sc_rfa_size = 296 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 297 298 /* 299 * Allocate the control data structures, and create and load the 300 * DMA map for it. 301 */ 302 if ((error = bus_dmamem_alloc(sc->sc_dmat, 303 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 304 0)) != 0) { 305 aprint_error( 306 "%s: unable to allocate control data, error = %d\n", 307 sc->sc_dev.dv_xname, error); 308 goto fail_0; 309 } 310 311 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 312 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 313 BUS_DMA_COHERENT)) != 0) { 314 aprint_error("%s: unable to map control data, error = %d\n", 315 sc->sc_dev.dv_xname, error); 316 goto fail_1; 317 } 318 sc->sc_cdseg = seg; 319 sc->sc_cdnseg = rseg; 320 321 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 322 323 if ((error = bus_dmamap_create(sc->sc_dmat, 324 sizeof(struct fxp_control_data), 1, 325 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 326 aprint_error("%s: unable to create control data DMA map, " 327 "error = %d\n", sc->sc_dev.dv_xname, error); 328 goto fail_2; 329 } 330 331 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 332 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 333 0)) != 0) { 334 aprint_error( 335 "%s: can't load control data DMA map, error = %d\n", 336 sc->sc_dev.dv_xname, error); 337 goto fail_3; 338 } 339 340 /* 341 * Create the transmit buffer DMA maps. 342 */ 343 for (i = 0; i < FXP_NTXCB; i++) { 344 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 345 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 346 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 347 aprint_error("%s: unable to create tx DMA map %d, " 348 "error = %d\n", sc->sc_dev.dv_xname, i, error); 349 goto fail_4; 350 } 351 } 352 353 /* 354 * Create the receive buffer DMA maps. 355 */ 356 for (i = 0; i < FXP_NRFABUFS; i++) { 357 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 359 aprint_error("%s: unable to create rx DMA map %d, " 360 "error = %d\n", sc->sc_dev.dv_xname, i, error); 361 goto fail_5; 362 } 363 } 364 365 /* Initialize MAC address and media structures. */ 366 fxp_get_info(sc, enaddr); 367 368 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 369 ether_sprintf(enaddr)); 370 371 ifp = &sc->sc_ethercom.ec_if; 372 373 /* 374 * Get info about our media interface, and initialize it. Note 375 * the table terminates itself with a phy of -1, indicating 376 * that we're using MII. 377 */ 378 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 379 if (fp->fp_phy == sc->phy_primary_device) 380 break; 381 (*fp->fp_init)(sc); 382 383 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 384 ifp->if_softc = sc; 385 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 386 ifp->if_ioctl = fxp_ioctl; 387 ifp->if_start = fxp_start; 388 ifp->if_watchdog = fxp_watchdog; 389 ifp->if_init = fxp_init; 390 ifp->if_stop = fxp_stop; 391 IFQ_SET_READY(&ifp->if_snd); 392 393 if (sc->sc_flags & FXPF_IPCB) { 394 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 395 /* 396 * IFCAP_CSUM_IPv4 seems to have a problem, 397 * at least, on i82550 rev.12. 398 * specifically, it doesn't calculate ipv4 checksum correctly 399 * when sending 20 byte ipv4 header + 1 or 2 byte data. 400 * FreeBSD driver has related comments. 401 * 402 * XXX we should have separate IFCAP flags 403 * for transmit and receive. 404 */ 405 ifp->if_capabilities = 406 /*IFCAP_CSUM_IPv4 |*/ IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 407 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 408 } 409 410 /* 411 * We can support 802.1Q VLAN-sized frames. 412 */ 413 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 414 415 /* 416 * Attach the interface. 417 */ 418 if_attach(ifp); 419 ether_ifattach(ifp, enaddr); 420 #if NRND > 0 421 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 422 RND_TYPE_NET, 0); 423 #endif 424 425 #ifdef FXP_EVENT_COUNTERS 426 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 427 NULL, sc->sc_dev.dv_xname, "txstall"); 428 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 429 NULL, sc->sc_dev.dv_xname, "txintr"); 430 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 431 NULL, sc->sc_dev.dv_xname, "rxintr"); 432 #endif /* FXP_EVENT_COUNTERS */ 433 434 /* 435 * Add shutdown hook so that DMA is disabled prior to reboot. Not 436 * doing do could allow DMA to corrupt kernel memory during the 437 * reboot before the driver initializes. 438 */ 439 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 440 if (sc->sc_sdhook == NULL) 441 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 442 sc->sc_dev.dv_xname); 443 /* 444 * Add suspend hook, for similar reasons.. 445 */ 446 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 447 if (sc->sc_powerhook == NULL) 448 aprint_error("%s: WARNING: unable to establish power hook\n", 449 sc->sc_dev.dv_xname); 450 451 /* The attach is successful. */ 452 sc->sc_flags |= FXPF_ATTACHED; 453 454 return; 455 456 /* 457 * Free any resources we've allocated during the failed attach 458 * attempt. Do this in reverse order and fall though. 459 */ 460 fail_5: 461 for (i = 0; i < FXP_NRFABUFS; i++) { 462 if (sc->sc_rxmaps[i] != NULL) 463 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 464 } 465 fail_4: 466 for (i = 0; i < FXP_NTXCB; i++) { 467 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 468 bus_dmamap_destroy(sc->sc_dmat, 469 FXP_DSTX(sc, i)->txs_dmamap); 470 } 471 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 472 fail_3: 473 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 474 fail_2: 475 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 476 sizeof(struct fxp_control_data)); 477 fail_1: 478 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 479 fail_0: 480 return; 481 } 482 483 void 484 fxp_mii_initmedia(struct fxp_softc *sc) 485 { 486 int flags; 487 488 sc->sc_flags |= FXPF_MII; 489 490 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 491 sc->sc_mii.mii_readreg = fxp_mdi_read; 492 sc->sc_mii.mii_writereg = fxp_mdi_write; 493 sc->sc_mii.mii_statchg = fxp_statchg; 494 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 495 fxp_mii_mediastatus); 496 497 flags = MIIF_NOISOLATE; 498 if (sc->sc_rev >= FXP_REV_82558_A4) 499 flags |= MIIF_DOPAUSE; 500 /* 501 * The i82557 wedges if all of its PHYs are isolated! 502 */ 503 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 504 MII_OFFSET_ANY, flags); 505 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 506 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 507 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 508 } else 509 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 510 } 511 512 void 513 fxp_80c24_initmedia(struct fxp_softc *sc) 514 { 515 516 /* 517 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 518 * doesn't have a programming interface of any sort. The 519 * media is sensed automatically based on how the link partner 520 * is configured. This is, in essence, manual configuration. 521 */ 522 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 523 sc->sc_dev.dv_xname); 524 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 525 fxp_80c24_mediastatus); 526 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 527 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 528 } 529 530 /* 531 * Device shutdown routine. Called at system shutdown after sync. The 532 * main purpose of this routine is to shut off receiver DMA so that 533 * kernel memory doesn't get clobbered during warmboot. 534 */ 535 void 536 fxp_shutdown(void *arg) 537 { 538 struct fxp_softc *sc = arg; 539 540 /* 541 * Since the system's going to halt shortly, don't bother 542 * freeing mbufs. 543 */ 544 fxp_stop(&sc->sc_ethercom.ec_if, 0); 545 } 546 /* 547 * Power handler routine. Called when the system is transitioning 548 * into/out of power save modes. As with fxp_shutdown, the main 549 * purpose of this routine is to shut off receiver DMA so it doesn't 550 * clobber kernel memory at the wrong time. 551 */ 552 void 553 fxp_power(int why, void *arg) 554 { 555 struct fxp_softc *sc = arg; 556 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 557 int s; 558 559 s = splnet(); 560 switch (why) { 561 case PWR_SUSPEND: 562 case PWR_STANDBY: 563 fxp_stop(ifp, 0); 564 break; 565 case PWR_RESUME: 566 if (ifp->if_flags & IFF_UP) 567 fxp_init(ifp); 568 break; 569 case PWR_SOFTSUSPEND: 570 case PWR_SOFTSTANDBY: 571 case PWR_SOFTRESUME: 572 break; 573 } 574 splx(s); 575 } 576 577 /* 578 * Initialize the interface media. 579 */ 580 void 581 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 582 { 583 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 584 585 /* 586 * Reset to a stable state. 587 */ 588 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 589 DELAY(100); 590 591 sc->sc_eeprom_size = 0; 592 fxp_autosize_eeprom(sc); 593 if (sc->sc_eeprom_size == 0) { 594 aprint_error("%s: failed to detect EEPROM size\n", 595 sc->sc_dev.dv_xname); 596 sc->sc_eeprom_size = 6; /* XXX panic here? */ 597 } 598 #ifdef DEBUG 599 aprint_debug("%s: detected %d word EEPROM\n", 600 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 601 #endif 602 603 /* 604 * Get info about the primary PHY 605 */ 606 fxp_read_eeprom(sc, &data, 6, 1); 607 sc->phy_primary_device = 608 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 609 610 /* 611 * Read MAC address. 612 */ 613 fxp_read_eeprom(sc, myea, 0, 3); 614 enaddr[0] = myea[0] & 0xff; 615 enaddr[1] = myea[0] >> 8; 616 enaddr[2] = myea[1] & 0xff; 617 enaddr[3] = myea[1] >> 8; 618 enaddr[4] = myea[2] & 0xff; 619 enaddr[5] = myea[2] >> 8; 620 621 /* 622 * Systems based on the ICH2/ICH2-M chip from Intel, as well 623 * as some i82559 designs, have a defect where the chip can 624 * cause a PCI protocol violation if it receives a CU_RESUME 625 * command when it is entering the IDLE state. 626 * 627 * The work-around is to disable Dynamic Standby Mode, so that 628 * the chip never deasserts #CLKRUN, and always remains in the 629 * active state. 630 * 631 * Unfortunately, the only way to disable Dynamic Standby is 632 * to frob an EEPROM setting and reboot (the EEPROM setting 633 * is only consulted when the PCI bus comes out of reset). 634 * 635 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 636 */ 637 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 638 fxp_read_eeprom(sc, &data, 10, 1); 639 if (data & 0x02) { /* STB enable */ 640 aprint_error("%s: WARNING: " 641 "Disabling dynamic standby mode in EEPROM " 642 "to work around a\n", 643 sc->sc_dev.dv_xname); 644 aprint_normal( 645 "%s: WARNING: hardware bug. You must reset " 646 "the system before using this\n", 647 sc->sc_dev.dv_xname); 648 aprint_normal("%s: WARNING: interface.\n", 649 sc->sc_dev.dv_xname); 650 data &= ~0x02; 651 fxp_write_eeprom(sc, &data, 10, 1); 652 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 653 sc->sc_dev.dv_xname, data); 654 fxp_eeprom_update_cksum(sc); 655 } 656 } 657 658 /* Receiver lock-up workaround detection. */ 659 fxp_read_eeprom(sc, &data, 3, 1); 660 if ((data & 0x03) != 0x03) { 661 aprint_verbose("%s: Enabling receiver lock-up workaround\n", 662 sc->sc_dev.dv_xname); 663 sc->sc_flags |= FXPF_RECV_WORKAROUND; 664 } 665 } 666 667 static void 668 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 669 { 670 uint16_t reg; 671 int x; 672 673 for (x = 1 << (len - 1); x != 0; x >>= 1) { 674 DELAY(40); 675 if (data & x) 676 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 677 else 678 reg = FXP_EEPROM_EECS; 679 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 680 DELAY(40); 681 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 682 reg | FXP_EEPROM_EESK); 683 DELAY(40); 684 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 685 } 686 DELAY(40); 687 } 688 689 /* 690 * Figure out EEPROM size. 691 * 692 * 559's can have either 64-word or 256-word EEPROMs, the 558 693 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 694 * talks about the existence of 16 to 256 word EEPROMs. 695 * 696 * The only known sizes are 64 and 256, where the 256 version is used 697 * by CardBus cards to store CIS information. 698 * 699 * The address is shifted in msb-to-lsb, and after the last 700 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 701 * after which follows the actual data. We try to detect this zero, by 702 * probing the data-out bit in the EEPROM control register just after 703 * having shifted in a bit. If the bit is zero, we assume we've 704 * shifted enough address bits. The data-out should be tri-state, 705 * before this, which should translate to a logical one. 706 * 707 * Other ways to do this would be to try to read a register with known 708 * contents with a varying number of address bits, but no such 709 * register seem to be available. The high bits of register 10 are 01 710 * on the 558 and 559, but apparently not on the 557. 711 * 712 * The Linux driver computes a checksum on the EEPROM data, but the 713 * value of this checksum is not very well documented. 714 */ 715 716 void 717 fxp_autosize_eeprom(struct fxp_softc *sc) 718 { 719 int x; 720 721 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 722 DELAY(40); 723 724 /* Shift in read opcode. */ 725 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 726 727 /* 728 * Shift in address, wait for the dummy zero following a correct 729 * address shift. 730 */ 731 for (x = 1; x <= 8; x++) { 732 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 733 DELAY(40); 734 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 735 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 736 DELAY(40); 737 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 738 FXP_EEPROM_EEDO) == 0) 739 break; 740 DELAY(40); 741 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 742 DELAY(40); 743 } 744 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 745 DELAY(40); 746 if (x != 6 && x != 8) { 747 #ifdef DEBUG 748 printf("%s: strange EEPROM size (%d)\n", 749 sc->sc_dev.dv_xname, 1 << x); 750 #endif 751 } else 752 sc->sc_eeprom_size = x; 753 } 754 755 /* 756 * Read from the serial EEPROM. Basically, you manually shift in 757 * the read opcode (one bit at a time) and then shift in the address, 758 * and then you shift out the data (all of this one bit at a time). 759 * The word size is 16 bits, so you have to provide the address for 760 * every 16 bits of data. 761 */ 762 void 763 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 764 { 765 u_int16_t reg; 766 int i, x; 767 768 for (i = 0; i < words; i++) { 769 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 770 771 /* Shift in read opcode. */ 772 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 773 774 /* Shift in address. */ 775 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 776 777 reg = FXP_EEPROM_EECS; 778 data[i] = 0; 779 780 /* Shift out data. */ 781 for (x = 16; x > 0; x--) { 782 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 783 reg | FXP_EEPROM_EESK); 784 DELAY(40); 785 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 786 FXP_EEPROM_EEDO) 787 data[i] |= (1 << (x - 1)); 788 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 789 DELAY(40); 790 } 791 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 792 DELAY(40); 793 } 794 } 795 796 /* 797 * Write data to the serial EEPROM. 798 */ 799 void 800 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 801 { 802 int i, j; 803 804 for (i = 0; i < words; i++) { 805 /* Erase/write enable. */ 806 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 807 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 808 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 809 sc->sc_eeprom_size); 810 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 811 DELAY(4); 812 813 /* Shift in write opcode, address, data. */ 814 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 815 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 816 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 817 fxp_eeprom_shiftin(sc, data[i], 16); 818 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 819 DELAY(4); 820 821 /* Wait for the EEPROM to finish up. */ 822 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 823 DELAY(4); 824 for (j = 0; j < 1000; j++) { 825 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 826 FXP_EEPROM_EEDO) 827 break; 828 DELAY(50); 829 } 830 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 831 DELAY(4); 832 833 /* Erase/write disable. */ 834 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 835 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 836 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 837 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 838 DELAY(4); 839 } 840 } 841 842 /* 843 * Update the checksum of the EEPROM. 844 */ 845 void 846 fxp_eeprom_update_cksum(struct fxp_softc *sc) 847 { 848 int i; 849 uint16_t data, cksum; 850 851 cksum = 0; 852 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 853 fxp_read_eeprom(sc, &data, i, 1); 854 cksum += data; 855 } 856 i = (1 << sc->sc_eeprom_size) - 1; 857 cksum = 0xbaba - cksum; 858 fxp_read_eeprom(sc, &data, i, 1); 859 fxp_write_eeprom(sc, &cksum, i, 1); 860 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 861 sc->sc_dev.dv_xname, i, data, cksum); 862 } 863 864 /* 865 * Start packet transmission on the interface. 866 */ 867 void 868 fxp_start(struct ifnet *ifp) 869 { 870 struct fxp_softc *sc = ifp->if_softc; 871 struct mbuf *m0, *m; 872 struct fxp_txdesc *txd; 873 struct fxp_txsoft *txs; 874 bus_dmamap_t dmamap; 875 int error, lasttx, nexttx, opending, seg; 876 877 /* 878 * If we want a re-init, bail out now. 879 */ 880 if (sc->sc_flags & FXPF_WANTINIT) { 881 ifp->if_flags |= IFF_OACTIVE; 882 return; 883 } 884 885 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 886 return; 887 888 /* 889 * Remember the previous txpending and the current lasttx. 890 */ 891 opending = sc->sc_txpending; 892 lasttx = sc->sc_txlast; 893 894 /* 895 * Loop through the send queue, setting up transmit descriptors 896 * until we drain the queue, or use up all available transmit 897 * descriptors. 898 */ 899 for (;;) { 900 struct fxp_tbd *tbdp; 901 int csum_flags; 902 903 /* 904 * Grab a packet off the queue. 905 */ 906 IFQ_POLL(&ifp->if_snd, m0); 907 if (m0 == NULL) 908 break; 909 m = NULL; 910 911 if (sc->sc_txpending == FXP_NTXCB) { 912 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 913 break; 914 } 915 916 /* 917 * Get the next available transmit descriptor. 918 */ 919 nexttx = FXP_NEXTTX(sc->sc_txlast); 920 txd = FXP_CDTX(sc, nexttx); 921 txs = FXP_DSTX(sc, nexttx); 922 dmamap = txs->txs_dmamap; 923 924 /* 925 * Load the DMA map. If this fails, the packet either 926 * didn't fit in the allotted number of frags, or we were 927 * short on resources. In this case, we'll copy and try 928 * again. 929 */ 930 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 931 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 932 MGETHDR(m, M_DONTWAIT, MT_DATA); 933 if (m == NULL) { 934 printf("%s: unable to allocate Tx mbuf\n", 935 sc->sc_dev.dv_xname); 936 break; 937 } 938 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 939 if (m0->m_pkthdr.len > MHLEN) { 940 MCLGET(m, M_DONTWAIT); 941 if ((m->m_flags & M_EXT) == 0) { 942 printf("%s: unable to allocate Tx " 943 "cluster\n", sc->sc_dev.dv_xname); 944 m_freem(m); 945 break; 946 } 947 } 948 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 949 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 950 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 951 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 952 if (error) { 953 printf("%s: unable to load Tx buffer, " 954 "error = %d\n", sc->sc_dev.dv_xname, error); 955 break; 956 } 957 } 958 959 IFQ_DEQUEUE(&ifp->if_snd, m0); 960 csum_flags = m0->m_pkthdr.csum_flags; 961 if (m != NULL) { 962 m_freem(m0); 963 m0 = m; 964 } 965 966 /* Initialize the fraglist. */ 967 tbdp = txd->txd_tbd; 968 if (sc->sc_flags & FXPF_IPCB) 969 tbdp++; 970 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 971 tbdp[seg].tb_addr = 972 htole32(dmamap->dm_segs[seg].ds_addr); 973 tbdp[seg].tb_size = 974 htole32(dmamap->dm_segs[seg].ds_len); 975 } 976 977 /* Sync the DMA map. */ 978 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 979 BUS_DMASYNC_PREWRITE); 980 981 /* 982 * Store a pointer to the packet so we can free it later. 983 */ 984 txs->txs_mbuf = m0; 985 986 /* 987 * Initialize the transmit descriptor. 988 */ 989 /* BIG_ENDIAN: no need to swap to store 0 */ 990 txd->txd_txcb.cb_status = 0; 991 txd->txd_txcb.cb_command = 992 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 993 txd->txd_txcb.tx_threshold = tx_threshold; 994 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 995 996 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 997 if (sc->sc_flags & FXPF_IPCB) { 998 struct fxp_ipcb *ipcb; 999 /* 1000 * Deal with TCP/IP checksum offload. Note that 1001 * in order for TCP checksum offload to work, 1002 * the pseudo header checksum must have already 1003 * been computed and stored in the checksum field 1004 * in the TCP header. The stack should have 1005 * already done this for us. 1006 */ 1007 ipcb = &txd->txd_u.txdu_ipcb; 1008 memset(ipcb, 0, sizeof(*ipcb)); 1009 /* 1010 * always do hardware parsing. 1011 */ 1012 ipcb->ipcb_ip_activation_high = 1013 FXP_IPCB_HARDWAREPARSING_ENABLE; 1014 /* 1015 * ip checksum offloading. 1016 */ 1017 if (csum_flags & M_CSUM_IPv4) { 1018 ipcb->ipcb_ip_schedule |= 1019 FXP_IPCB_IP_CHECKSUM_ENABLE; 1020 } 1021 /* 1022 * TCP/UDP checksum offloading. 1023 */ 1024 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1025 ipcb->ipcb_ip_schedule |= 1026 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1027 } 1028 1029 /* 1030 * request VLAN tag insertion if needed. 1031 */ 1032 if (sc->sc_ethercom.ec_nvlans != 0) { 1033 struct m_tag *vtag; 1034 1035 vtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL); 1036 if (vtag) { 1037 ipcb->ipcb_vlan_id = 1038 htobe16(*(u_int *)(vtag + 1)); 1039 ipcb->ipcb_ip_activation_high |= 1040 FXP_IPCB_INSERTVLAN_ENABLE; 1041 } 1042 } 1043 } else { 1044 KASSERT((csum_flags & 1045 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1046 } 1047 1048 FXP_CDTXSYNC(sc, nexttx, 1049 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1050 1051 /* Advance the tx pointer. */ 1052 sc->sc_txpending++; 1053 sc->sc_txlast = nexttx; 1054 1055 #if NBPFILTER > 0 1056 /* 1057 * Pass packet to bpf if there is a listener. 1058 */ 1059 if (ifp->if_bpf) 1060 bpf_mtap(ifp->if_bpf, m0); 1061 #endif 1062 } 1063 1064 if (sc->sc_txpending == FXP_NTXCB) { 1065 /* No more slots; notify upper layer. */ 1066 ifp->if_flags |= IFF_OACTIVE; 1067 } 1068 1069 if (sc->sc_txpending != opending) { 1070 /* 1071 * We enqueued packets. If the transmitter was idle, 1072 * reset the txdirty pointer. 1073 */ 1074 if (opending == 0) 1075 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1076 1077 /* 1078 * Cause the chip to interrupt and suspend command 1079 * processing once the last packet we've enqueued 1080 * has been transmitted. 1081 */ 1082 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 1083 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1084 FXP_CDTXSYNC(sc, sc->sc_txlast, 1085 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1086 1087 /* 1088 * The entire packet chain is set up. Clear the suspend bit 1089 * on the command prior to the first packet we set up. 1090 */ 1091 FXP_CDTXSYNC(sc, lasttx, 1092 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1093 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1094 htole16(~FXP_CB_COMMAND_S); 1095 FXP_CDTXSYNC(sc, lasttx, 1096 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1097 1098 /* 1099 * Issue a Resume command in case the chip was suspended. 1100 */ 1101 fxp_scb_wait(sc); 1102 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1103 1104 /* Set a watchdog timer in case the chip flakes out. */ 1105 ifp->if_timer = 5; 1106 } 1107 } 1108 1109 /* 1110 * Process interface interrupts. 1111 */ 1112 int 1113 fxp_intr(void *arg) 1114 { 1115 struct fxp_softc *sc = arg; 1116 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1117 bus_dmamap_t rxmap; 1118 int claimed = 0; 1119 u_int8_t statack; 1120 1121 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0 || sc->sc_enabled == 0) 1122 return (0); 1123 /* 1124 * If the interface isn't running, don't try to 1125 * service the interrupt.. just ack it and bail. 1126 */ 1127 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1128 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1129 if (statack) { 1130 claimed = 1; 1131 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1132 } 1133 return (claimed); 1134 } 1135 1136 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1137 claimed = 1; 1138 1139 /* 1140 * First ACK all the interrupts in this pass. 1141 */ 1142 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1143 1144 /* 1145 * Process receiver interrupts. If a no-resource (RNR) 1146 * condition exists, get whatever packets we can and 1147 * re-start the receiver. 1148 */ 1149 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1150 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1151 fxp_rxintr(sc); 1152 } 1153 1154 if (statack & FXP_SCB_STATACK_RNR) { 1155 fxp_scb_wait(sc); 1156 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1157 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1158 fxp_scb_wait(sc); 1159 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1160 rxmap->dm_segs[0].ds_addr + 1161 RFA_ALIGNMENT_FUDGE); 1162 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1163 } 1164 1165 /* 1166 * Free any finished transmit mbuf chains. 1167 */ 1168 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1169 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1170 fxp_txintr(sc); 1171 1172 /* 1173 * Try to get more packets going. 1174 */ 1175 fxp_start(ifp); 1176 1177 if (sc->sc_txpending == 0) { 1178 /* 1179 * If we want a re-init, do that now. 1180 */ 1181 if (sc->sc_flags & FXPF_WANTINIT) 1182 (void) fxp_init(ifp); 1183 } 1184 } 1185 } 1186 1187 #if NRND > 0 1188 if (claimed) 1189 rnd_add_uint32(&sc->rnd_source, statack); 1190 #endif 1191 return (claimed); 1192 } 1193 1194 /* 1195 * Handle transmit completion interrupts. 1196 */ 1197 void 1198 fxp_txintr(struct fxp_softc *sc) 1199 { 1200 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1201 struct fxp_txdesc *txd; 1202 struct fxp_txsoft *txs; 1203 int i; 1204 u_int16_t txstat; 1205 1206 ifp->if_flags &= ~IFF_OACTIVE; 1207 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1208 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1209 txd = FXP_CDTX(sc, i); 1210 txs = FXP_DSTX(sc, i); 1211 1212 FXP_CDTXSYNC(sc, i, 1213 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1214 1215 txstat = le16toh(txd->txd_txcb.cb_status); 1216 1217 if ((txstat & FXP_CB_STATUS_C) == 0) 1218 break; 1219 1220 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1221 0, txs->txs_dmamap->dm_mapsize, 1222 BUS_DMASYNC_POSTWRITE); 1223 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1224 m_freem(txs->txs_mbuf); 1225 txs->txs_mbuf = NULL; 1226 } 1227 1228 /* Update the dirty transmit buffer pointer. */ 1229 sc->sc_txdirty = i; 1230 1231 /* 1232 * Cancel the watchdog timer if there are no pending 1233 * transmissions. 1234 */ 1235 if (sc->sc_txpending == 0) 1236 ifp->if_timer = 0; 1237 } 1238 1239 /* 1240 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1241 */ 1242 1243 int 1244 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1245 { 1246 u_int16_t rxparsestat; 1247 u_int16_t csum_stat; 1248 u_int32_t csum_data; 1249 int csum_flags; 1250 1251 /* 1252 * check VLAN tag stripping. 1253 */ 1254 1255 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1256 struct m_tag *vtag; 1257 1258 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1259 if (vtag == NULL) 1260 return ENOMEM; 1261 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1262 m_tag_prepend(m, vtag); 1263 } 1264 1265 /* 1266 * check H/W Checksumming. 1267 */ 1268 1269 csum_stat = le16toh(rfa->cksum_stat); 1270 rxparsestat = le16toh(rfa->rx_parse_stat); 1271 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1272 return 0; 1273 1274 csum_flags = 0; 1275 csum_data = 0; 1276 1277 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1278 csum_flags = M_CSUM_IPv4; 1279 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1280 csum_flags |= M_CSUM_IPv4_BAD; 1281 } 1282 1283 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1284 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1285 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1286 csum_flags |= M_CSUM_TCP_UDP_BAD; 1287 } 1288 1289 m->m_pkthdr.csum_flags = csum_flags; 1290 m->m_pkthdr.csum_data = csum_data; 1291 1292 return 0; 1293 } 1294 1295 /* 1296 * Handle receive interrupts. 1297 */ 1298 void 1299 fxp_rxintr(struct fxp_softc *sc) 1300 { 1301 struct ethercom *ec = &sc->sc_ethercom; 1302 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1303 struct mbuf *m, *m0; 1304 bus_dmamap_t rxmap; 1305 struct fxp_rfa *rfa; 1306 u_int16_t len, rxstat; 1307 1308 for (;;) { 1309 m = sc->sc_rxq.ifq_head; 1310 rfa = FXP_MTORFA(m); 1311 rxmap = M_GETCTX(m, bus_dmamap_t); 1312 1313 FXP_RFASYNC(sc, m, 1314 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1315 1316 rxstat = le16toh(rfa->rfa_status); 1317 1318 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1319 /* 1320 * We have processed all of the 1321 * receive buffers. 1322 */ 1323 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1324 return; 1325 } 1326 1327 IF_DEQUEUE(&sc->sc_rxq, m); 1328 1329 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1330 1331 len = le16toh(rfa->actual_size) & 1332 (m->m_ext.ext_size - 1); 1333 1334 if (len < sizeof(struct ether_header)) { 1335 /* 1336 * Runt packet; drop it now. 1337 */ 1338 FXP_INIT_RFABUF(sc, m); 1339 continue; 1340 } 1341 1342 /* 1343 * If support for 802.1Q VLAN sized frames is 1344 * enabled, we need to do some additional error 1345 * checking (as we are saving bad frames, in 1346 * order to receive the larger ones). 1347 */ 1348 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1349 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1350 FXP_RFA_STATUS_RNR| 1351 FXP_RFA_STATUS_ALIGN| 1352 FXP_RFA_STATUS_CRC)) != 0) { 1353 FXP_INIT_RFABUF(sc, m); 1354 continue; 1355 } 1356 1357 /* Do checksum checking. */ 1358 m->m_pkthdr.csum_flags = 0; 1359 if (sc->sc_flags & FXPF_EXT_RFA) 1360 if (fxp_rx_hwcksum(m, rfa)) 1361 goto dropit; 1362 1363 /* 1364 * If the packet is small enough to fit in a 1365 * single header mbuf, allocate one and copy 1366 * the data into it. This greatly reduces 1367 * memory consumption when we receive lots 1368 * of small packets. 1369 * 1370 * Otherwise, we add a new buffer to the receive 1371 * chain. If this fails, we drop the packet and 1372 * recycle the old buffer. 1373 */ 1374 if (fxp_copy_small != 0 && len <= MHLEN) { 1375 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1376 if (m0 == NULL) 1377 goto dropit; 1378 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1379 memcpy(mtod(m0, caddr_t), 1380 mtod(m, caddr_t), len); 1381 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1382 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1383 FXP_INIT_RFABUF(sc, m); 1384 m = m0; 1385 } else { 1386 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1387 dropit: 1388 ifp->if_ierrors++; 1389 FXP_INIT_RFABUF(sc, m); 1390 continue; 1391 } 1392 } 1393 1394 m->m_pkthdr.rcvif = ifp; 1395 m->m_pkthdr.len = m->m_len = len; 1396 1397 #if NBPFILTER > 0 1398 /* 1399 * Pass this up to any BPF listeners, but only 1400 * pass it up the stack it its for us. 1401 */ 1402 if (ifp->if_bpf) 1403 bpf_mtap(ifp->if_bpf, m); 1404 #endif 1405 1406 /* Pass it on. */ 1407 (*ifp->if_input)(ifp, m); 1408 } 1409 } 1410 1411 /* 1412 * Update packet in/out/collision statistics. The i82557 doesn't 1413 * allow you to access these counters without doing a fairly 1414 * expensive DMA to get _all_ of the statistics it maintains, so 1415 * we do this operation here only once per second. The statistics 1416 * counters in the kernel are updated from the previous dump-stats 1417 * DMA and then a new dump-stats DMA is started. The on-chip 1418 * counters are zeroed when the DMA completes. If we can't start 1419 * the DMA immediately, we don't wait - we just prepare to read 1420 * them again next time. 1421 */ 1422 void 1423 fxp_tick(void *arg) 1424 { 1425 struct fxp_softc *sc = arg; 1426 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1427 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1428 int s; 1429 1430 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1431 return; 1432 1433 s = splnet(); 1434 1435 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1436 1437 ifp->if_opackets += le32toh(sp->tx_good); 1438 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1439 if (sp->rx_good) { 1440 ifp->if_ipackets += le32toh(sp->rx_good); 1441 sc->sc_rxidle = 0; 1442 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1443 sc->sc_rxidle++; 1444 } 1445 ifp->if_ierrors += 1446 le32toh(sp->rx_crc_errors) + 1447 le32toh(sp->rx_alignment_errors) + 1448 le32toh(sp->rx_rnr_errors) + 1449 le32toh(sp->rx_overrun_errors); 1450 /* 1451 * If any transmit underruns occurred, bump up the transmit 1452 * threshold by another 512 bytes (64 * 8). 1453 */ 1454 if (sp->tx_underruns) { 1455 ifp->if_oerrors += le32toh(sp->tx_underruns); 1456 if (tx_threshold < 192) 1457 tx_threshold += 64; 1458 } 1459 1460 /* 1461 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1462 * then assume the receiver has locked up and attempt to clear 1463 * the condition by reprogramming the multicast filter (actually, 1464 * resetting the interface). This is a work-around for a bug in 1465 * the 82557 where the receiver locks up if it gets certain types 1466 * of garbage in the synchronization bits prior to the packet header. 1467 * This bug is supposed to only occur in 10Mbps mode, but has been 1468 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1469 * speed transition). 1470 */ 1471 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1472 (void) fxp_init(ifp); 1473 splx(s); 1474 return; 1475 } 1476 /* 1477 * If there is no pending command, start another stats 1478 * dump. Otherwise punt for now. 1479 */ 1480 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1481 /* 1482 * Start another stats dump. 1483 */ 1484 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1485 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1486 } else { 1487 /* 1488 * A previous command is still waiting to be accepted. 1489 * Just zero our copy of the stats and wait for the 1490 * next timer event to update them. 1491 */ 1492 /* BIG_ENDIAN: no swap required to store 0 */ 1493 sp->tx_good = 0; 1494 sp->tx_underruns = 0; 1495 sp->tx_total_collisions = 0; 1496 1497 sp->rx_good = 0; 1498 sp->rx_crc_errors = 0; 1499 sp->rx_alignment_errors = 0; 1500 sp->rx_rnr_errors = 0; 1501 sp->rx_overrun_errors = 0; 1502 } 1503 1504 if (sc->sc_flags & FXPF_MII) { 1505 /* Tick the MII clock. */ 1506 mii_tick(&sc->sc_mii); 1507 } 1508 1509 splx(s); 1510 1511 /* 1512 * Schedule another timeout one second from now. 1513 */ 1514 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1515 } 1516 1517 /* 1518 * Drain the receive queue. 1519 */ 1520 void 1521 fxp_rxdrain(struct fxp_softc *sc) 1522 { 1523 bus_dmamap_t rxmap; 1524 struct mbuf *m; 1525 1526 for (;;) { 1527 IF_DEQUEUE(&sc->sc_rxq, m); 1528 if (m == NULL) 1529 break; 1530 rxmap = M_GETCTX(m, bus_dmamap_t); 1531 bus_dmamap_unload(sc->sc_dmat, rxmap); 1532 FXP_RXMAP_PUT(sc, rxmap); 1533 m_freem(m); 1534 } 1535 } 1536 1537 /* 1538 * Stop the interface. Cancels the statistics updater and resets 1539 * the interface. 1540 */ 1541 void 1542 fxp_stop(struct ifnet *ifp, int disable) 1543 { 1544 struct fxp_softc *sc = ifp->if_softc; 1545 struct fxp_txsoft *txs; 1546 int i; 1547 1548 /* 1549 * Turn down interface (done early to avoid bad interactions 1550 * between panics, shutdown hooks, and the watchdog timer) 1551 */ 1552 ifp->if_timer = 0; 1553 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1554 1555 /* 1556 * Cancel stats updater. 1557 */ 1558 callout_stop(&sc->sc_callout); 1559 if (sc->sc_flags & FXPF_MII) { 1560 /* Down the MII. */ 1561 mii_down(&sc->sc_mii); 1562 } 1563 1564 /* 1565 * Issue software reset. This unloads any microcode that 1566 * might already be loaded. 1567 */ 1568 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1569 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1570 DELAY(50); 1571 1572 /* 1573 * Release any xmit buffers. 1574 */ 1575 for (i = 0; i < FXP_NTXCB; i++) { 1576 txs = FXP_DSTX(sc, i); 1577 if (txs->txs_mbuf != NULL) { 1578 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1579 m_freem(txs->txs_mbuf); 1580 txs->txs_mbuf = NULL; 1581 } 1582 } 1583 sc->sc_txpending = 0; 1584 1585 if (disable) { 1586 fxp_rxdrain(sc); 1587 fxp_disable(sc); 1588 } 1589 1590 } 1591 1592 /* 1593 * Watchdog/transmission transmit timeout handler. Called when a 1594 * transmission is started on the interface, but no interrupt is 1595 * received before the timeout. This usually indicates that the 1596 * card has wedged for some reason. 1597 */ 1598 void 1599 fxp_watchdog(struct ifnet *ifp) 1600 { 1601 struct fxp_softc *sc = ifp->if_softc; 1602 1603 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1604 ifp->if_oerrors++; 1605 1606 (void) fxp_init(ifp); 1607 } 1608 1609 /* 1610 * Initialize the interface. Must be called at splnet(). 1611 */ 1612 int 1613 fxp_init(struct ifnet *ifp) 1614 { 1615 struct fxp_softc *sc = ifp->if_softc; 1616 struct fxp_cb_config *cbp; 1617 struct fxp_cb_ias *cb_ias; 1618 struct fxp_txdesc *txd; 1619 bus_dmamap_t rxmap; 1620 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1621 1622 if ((error = fxp_enable(sc)) != 0) 1623 goto out; 1624 1625 /* 1626 * Cancel any pending I/O 1627 */ 1628 fxp_stop(ifp, 0); 1629 1630 /* 1631 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1632 * flag, and this prevents the MII from detaching resulting in 1633 * a panic. The flags field should perhaps be split in runtime 1634 * flags and more static information. For now, just clear the 1635 * only other flag set. 1636 */ 1637 1638 sc->sc_flags &= ~FXPF_WANTINIT; 1639 1640 /* 1641 * Initialize base of CBL and RFA memory. Loading with zero 1642 * sets it up for regular linear addressing. 1643 */ 1644 fxp_scb_wait(sc); 1645 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1646 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1647 1648 fxp_scb_wait(sc); 1649 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1650 1651 /* 1652 * Initialize the multicast filter. Do this now, since we might 1653 * have to setup the config block differently. 1654 */ 1655 fxp_mc_setup(sc); 1656 1657 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1658 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1659 1660 /* 1661 * In order to support receiving 802.1Q VLAN frames, we have to 1662 * enable "save bad frames", since they are 4 bytes larger than 1663 * the normal Ethernet maximum frame length. On i82558 and later, 1664 * we have a better mechanism for this. 1665 */ 1666 save_bf = 0; 1667 lrxen = 0; 1668 vlan_drop = 0; 1669 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1670 if (sc->sc_rev < FXP_REV_82558_A4) 1671 save_bf = 1; 1672 else 1673 lrxen = 1; 1674 if (sc->sc_rev >= FXP_REV_82550) 1675 vlan_drop = 1; 1676 } 1677 1678 /* 1679 * Initialize base of dump-stats buffer. 1680 */ 1681 fxp_scb_wait(sc); 1682 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1683 sc->sc_cddma + FXP_CDSTATSOFF); 1684 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1685 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1686 1687 cbp = &sc->sc_control_data->fcd_configcb; 1688 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1689 1690 /* 1691 * Load microcode for this controller. 1692 */ 1693 fxp_load_ucode(sc); 1694 1695 /* 1696 * This copy is kind of disgusting, but there are a bunch of must be 1697 * zero and must be one bits in this structure and this is the easiest 1698 * way to initialize them all to proper values. 1699 */ 1700 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1701 1702 /* BIG_ENDIAN: no need to swap to store 0 */ 1703 cbp->cb_status = 0; 1704 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1705 FXP_CB_COMMAND_EL); 1706 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1707 cbp->link_addr = 0xffffffff; /* (no) next command */ 1708 /* bytes in config block */ 1709 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1710 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1711 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1712 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1713 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1714 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1715 cbp->type_enable = 0; /* actually reserved */ 1716 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1717 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1718 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1719 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1720 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1721 cbp->late_scb = 0; /* (don't) defer SCB update */ 1722 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1723 cbp->ci_int = 1; /* interrupt on CU idle */ 1724 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1725 cbp->ext_stats_dis = 1; /* disable extended counters */ 1726 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1727 cbp->save_bf = save_bf;/* save bad frames */ 1728 cbp->disc_short_rx = !prm; /* discard short packets */ 1729 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1730 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1731 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1732 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1733 /* interface mode */ 1734 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1735 cbp->csma_dis = 0; /* (don't) disable link */ 1736 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1737 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1738 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1739 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1740 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1741 cbp->nsai = 1; /* (don't) disable source addr insert */ 1742 cbp->preamble_length = 2; /* (7 byte) preamble */ 1743 cbp->loopback = 0; /* (don't) loopback */ 1744 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1745 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1746 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1747 cbp->promiscuous = prm; /* promiscuous mode */ 1748 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1749 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1750 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1751 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1752 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1753 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1754 cbp->padding = 1; /* (do) pad short tx packets */ 1755 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1756 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1757 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1758 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1759 /* must set wake_en in PMCSR also */ 1760 cbp->force_fdx = 0; /* (don't) force full duplex */ 1761 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1762 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1763 cbp->mc_all = allm; /* accept all multicasts */ 1764 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1765 cbp->vlan_drop_en = vlan_drop; 1766 1767 if (sc->sc_rev < FXP_REV_82558_A4) { 1768 /* 1769 * The i82557 has no hardware flow control, the values 1770 * here are the defaults for the chip. 1771 */ 1772 cbp->fc_delay_lsb = 0; 1773 cbp->fc_delay_msb = 0x40; 1774 cbp->pri_fc_thresh = 3; 1775 cbp->tx_fc_dis = 0; 1776 cbp->rx_fc_restop = 0; 1777 cbp->rx_fc_restart = 0; 1778 cbp->fc_filter = 0; 1779 cbp->pri_fc_loc = 1; 1780 } else { 1781 cbp->fc_delay_lsb = 0x1f; 1782 cbp->fc_delay_msb = 0x01; 1783 cbp->pri_fc_thresh = 3; 1784 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1785 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1786 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1787 cbp->fc_filter = !prm; /* drop FC frames to host */ 1788 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1789 } 1790 1791 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1792 1793 /* 1794 * Start the config command/DMA. 1795 */ 1796 fxp_scb_wait(sc); 1797 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1798 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1799 /* ...and wait for it to complete. */ 1800 i = 1000; 1801 do { 1802 FXP_CDCONFIGSYNC(sc, 1803 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1804 DELAY(1); 1805 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1806 if (i == 0) { 1807 printf("%s at line %d: dmasync timeout\n", 1808 sc->sc_dev.dv_xname, __LINE__); 1809 return (ETIMEDOUT); 1810 } 1811 1812 /* 1813 * Initialize the station address. 1814 */ 1815 cb_ias = &sc->sc_control_data->fcd_iascb; 1816 /* BIG_ENDIAN: no need to swap to store 0 */ 1817 cb_ias->cb_status = 0; 1818 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1819 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1820 cb_ias->link_addr = 0xffffffff; 1821 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1822 1823 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1824 1825 /* 1826 * Start the IAS (Individual Address Setup) command/DMA. 1827 */ 1828 fxp_scb_wait(sc); 1829 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1830 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1831 /* ...and wait for it to complete. */ 1832 i = 1000; 1833 do { 1834 FXP_CDIASSYNC(sc, 1835 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1836 DELAY(1); 1837 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1838 if (i == 0) { 1839 printf("%s at line %d: dmasync timeout\n", 1840 sc->sc_dev.dv_xname, __LINE__); 1841 return (ETIMEDOUT); 1842 } 1843 1844 /* 1845 * Initialize the transmit descriptor ring. txlast is initialized 1846 * to the end of the list so that it will wrap around to the first 1847 * descriptor when the first packet is transmitted. 1848 */ 1849 for (i = 0; i < FXP_NTXCB; i++) { 1850 txd = FXP_CDTX(sc, i); 1851 memset(txd, 0, sizeof(*txd)); 1852 txd->txd_txcb.cb_command = 1853 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1854 txd->txd_txcb.link_addr = 1855 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1856 if (sc->sc_flags & FXPF_EXT_TXCB) 1857 txd->txd_txcb.tbd_array_addr = 1858 htole32(FXP_CDTBDADDR(sc, i) + 1859 (2 * sizeof(struct fxp_tbd))); 1860 else 1861 txd->txd_txcb.tbd_array_addr = 1862 htole32(FXP_CDTBDADDR(sc, i)); 1863 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1864 } 1865 sc->sc_txpending = 0; 1866 sc->sc_txdirty = 0; 1867 sc->sc_txlast = FXP_NTXCB - 1; 1868 1869 /* 1870 * Initialize the receive buffer list. 1871 */ 1872 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1873 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1874 rxmap = FXP_RXMAP_GET(sc); 1875 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1876 printf("%s: unable to allocate or map rx " 1877 "buffer %d, error = %d\n", 1878 sc->sc_dev.dv_xname, 1879 sc->sc_rxq.ifq_len, error); 1880 /* 1881 * XXX Should attempt to run with fewer receive 1882 * XXX buffers instead of just failing. 1883 */ 1884 FXP_RXMAP_PUT(sc, rxmap); 1885 fxp_rxdrain(sc); 1886 goto out; 1887 } 1888 } 1889 sc->sc_rxidle = 0; 1890 1891 /* 1892 * Give the transmit ring to the chip. We do this by pointing 1893 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1894 * issuing a start command. It will execute the NOP and then 1895 * suspend, pointing at the first descriptor. 1896 */ 1897 fxp_scb_wait(sc); 1898 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1899 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1900 1901 /* 1902 * Initialize receiver buffer area - RFA. 1903 */ 1904 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1905 fxp_scb_wait(sc); 1906 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1907 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1908 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1909 1910 if (sc->sc_flags & FXPF_MII) { 1911 /* 1912 * Set current media. 1913 */ 1914 mii_mediachg(&sc->sc_mii); 1915 } 1916 1917 /* 1918 * ...all done! 1919 */ 1920 ifp->if_flags |= IFF_RUNNING; 1921 ifp->if_flags &= ~IFF_OACTIVE; 1922 1923 /* 1924 * Start the one second timer. 1925 */ 1926 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1927 1928 /* 1929 * Attempt to start output on the interface. 1930 */ 1931 fxp_start(ifp); 1932 1933 out: 1934 if (error) { 1935 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1936 ifp->if_timer = 0; 1937 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1938 } 1939 return (error); 1940 } 1941 1942 /* 1943 * Change media according to request. 1944 */ 1945 int 1946 fxp_mii_mediachange(struct ifnet *ifp) 1947 { 1948 struct fxp_softc *sc = ifp->if_softc; 1949 1950 if (ifp->if_flags & IFF_UP) 1951 mii_mediachg(&sc->sc_mii); 1952 return (0); 1953 } 1954 1955 /* 1956 * Notify the world which media we're using. 1957 */ 1958 void 1959 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1960 { 1961 struct fxp_softc *sc = ifp->if_softc; 1962 1963 if (sc->sc_enabled == 0) { 1964 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1965 ifmr->ifm_status = 0; 1966 return; 1967 } 1968 1969 mii_pollstat(&sc->sc_mii); 1970 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1971 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1972 } 1973 1974 int 1975 fxp_80c24_mediachange(struct ifnet *ifp) 1976 { 1977 1978 /* Nothing to do here. */ 1979 return (0); 1980 } 1981 1982 void 1983 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1984 { 1985 struct fxp_softc *sc = ifp->if_softc; 1986 1987 /* 1988 * Media is currently-selected media. We cannot determine 1989 * the link status. 1990 */ 1991 ifmr->ifm_status = 0; 1992 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1993 } 1994 1995 /* 1996 * Add a buffer to the end of the RFA buffer list. 1997 * Return 0 if successful, error code on failure. 1998 * 1999 * The RFA struct is stuck at the beginning of mbuf cluster and the 2000 * data pointer is fixed up to point just past it. 2001 */ 2002 int 2003 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2004 { 2005 struct mbuf *m; 2006 int error; 2007 2008 MGETHDR(m, M_DONTWAIT, MT_DATA); 2009 if (m == NULL) 2010 return (ENOBUFS); 2011 2012 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2013 MCLGET(m, M_DONTWAIT); 2014 if ((m->m_flags & M_EXT) == 0) { 2015 m_freem(m); 2016 return (ENOBUFS); 2017 } 2018 2019 if (unload) 2020 bus_dmamap_unload(sc->sc_dmat, rxmap); 2021 2022 M_SETCTX(m, rxmap); 2023 2024 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2025 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2026 BUS_DMA_READ|BUS_DMA_NOWAIT); 2027 if (error) { 2028 printf("%s: can't load rx DMA map %d, error = %d\n", 2029 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 2030 panic("fxp_add_rfabuf"); /* XXX */ 2031 } 2032 2033 FXP_INIT_RFABUF(sc, m); 2034 2035 return (0); 2036 } 2037 2038 int 2039 fxp_mdi_read(struct device *self, int phy, int reg) 2040 { 2041 struct fxp_softc *sc = (struct fxp_softc *)self; 2042 int count = 10000; 2043 int value; 2044 2045 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2046 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2047 2048 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2049 0x10000000) == 0 && count--) 2050 DELAY(10); 2051 2052 if (count <= 0) 2053 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 2054 2055 return (value & 0xffff); 2056 } 2057 2058 void 2059 fxp_statchg(struct device *self) 2060 { 2061 2062 /* Nothing to do. */ 2063 } 2064 2065 void 2066 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2067 { 2068 struct fxp_softc *sc = (struct fxp_softc *)self; 2069 int count = 10000; 2070 2071 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2072 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2073 (value & 0xffff)); 2074 2075 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2076 count--) 2077 DELAY(10); 2078 2079 if (count <= 0) 2080 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2081 } 2082 2083 int 2084 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2085 { 2086 struct fxp_softc *sc = ifp->if_softc; 2087 struct ifreq *ifr = (struct ifreq *)data; 2088 int s, error; 2089 2090 s = splnet(); 2091 2092 switch (cmd) { 2093 case SIOCSIFMEDIA: 2094 case SIOCGIFMEDIA: 2095 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2096 break; 2097 2098 default: 2099 error = ether_ioctl(ifp, cmd, data); 2100 if (error == ENETRESET) { 2101 if (sc->sc_enabled) { 2102 /* 2103 * Multicast list has changed; set the 2104 * hardware filter accordingly. 2105 */ 2106 if (sc->sc_txpending) { 2107 sc->sc_flags |= FXPF_WANTINIT; 2108 error = 0; 2109 } else 2110 error = fxp_init(ifp); 2111 } else 2112 error = 0; 2113 } 2114 break; 2115 } 2116 2117 /* Try to get more packets going. */ 2118 if (sc->sc_enabled) 2119 fxp_start(ifp); 2120 2121 splx(s); 2122 return (error); 2123 } 2124 2125 /* 2126 * Program the multicast filter. 2127 * 2128 * This function must be called at splnet(). 2129 */ 2130 void 2131 fxp_mc_setup(struct fxp_softc *sc) 2132 { 2133 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2134 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2135 struct ethercom *ec = &sc->sc_ethercom; 2136 struct ether_multi *enm; 2137 struct ether_multistep step; 2138 int count, nmcasts; 2139 2140 #ifdef DIAGNOSTIC 2141 if (sc->sc_txpending) 2142 panic("fxp_mc_setup: pending transmissions"); 2143 #endif 2144 2145 ifp->if_flags &= ~IFF_ALLMULTI; 2146 2147 /* 2148 * Initialize multicast setup descriptor. 2149 */ 2150 nmcasts = 0; 2151 ETHER_FIRST_MULTI(step, ec, enm); 2152 while (enm != NULL) { 2153 /* 2154 * Check for too many multicast addresses or if we're 2155 * listening to a range. Either way, we simply have 2156 * to accept all multicasts. 2157 */ 2158 if (nmcasts >= MAXMCADDR || 2159 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2160 ETHER_ADDR_LEN) != 0) { 2161 /* 2162 * Callers of this function must do the 2163 * right thing with this. If we're called 2164 * from outside fxp_init(), the caller must 2165 * detect if the state if IFF_ALLMULTI changes. 2166 * If it does, the caller must then call 2167 * fxp_init(), since allmulti is handled by 2168 * the config block. 2169 */ 2170 ifp->if_flags |= IFF_ALLMULTI; 2171 return; 2172 } 2173 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2174 ETHER_ADDR_LEN); 2175 nmcasts++; 2176 ETHER_NEXT_MULTI(step, enm); 2177 } 2178 2179 /* BIG_ENDIAN: no need to swap to store 0 */ 2180 mcsp->cb_status = 0; 2181 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2182 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2183 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2184 2185 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2186 2187 /* 2188 * Wait until the command unit is not active. This should never 2189 * happen since nothing is queued, but make sure anyway. 2190 */ 2191 count = 100; 2192 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2193 FXP_SCB_CUS_ACTIVE && --count) 2194 DELAY(1); 2195 if (count == 0) { 2196 printf("%s at line %d: command queue timeout\n", 2197 sc->sc_dev.dv_xname, __LINE__); 2198 return; 2199 } 2200 2201 /* 2202 * Start the multicast setup command/DMA. 2203 */ 2204 fxp_scb_wait(sc); 2205 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2206 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2207 2208 /* ...and wait for it to complete. */ 2209 count = 1000; 2210 do { 2211 FXP_CDMCSSYNC(sc, 2212 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2213 DELAY(1); 2214 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2215 if (count == 0) { 2216 printf("%s at line %d: dmasync timeout\n", 2217 sc->sc_dev.dv_xname, __LINE__); 2218 return; 2219 } 2220 } 2221 2222 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2223 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2224 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2225 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2226 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2227 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2228 2229 #define UCODE(x) x, sizeof(x) 2230 2231 static const struct ucode { 2232 int32_t revision; 2233 const uint32_t *ucode; 2234 size_t length; 2235 uint16_t int_delay_offset; 2236 uint16_t bundle_max_offset; 2237 } ucode_table[] = { 2238 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2239 D101_CPUSAVER_DWORD, 0 }, 2240 2241 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2242 D101_CPUSAVER_DWORD, 0 }, 2243 2244 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2245 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2246 2247 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2248 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2249 2250 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2251 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2252 2253 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2254 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2255 2256 { 0, NULL, 0, 0, 0 } 2257 }; 2258 2259 void 2260 fxp_load_ucode(struct fxp_softc *sc) 2261 { 2262 const struct ucode *uc; 2263 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2264 int count; 2265 2266 if (sc->sc_flags & FXPF_UCODE_LOADED) 2267 return; 2268 2269 /* 2270 * Only load the uCode if the user has requested that 2271 * we do so. 2272 */ 2273 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2274 sc->sc_int_delay = 0; 2275 sc->sc_bundle_max = 0; 2276 return; 2277 } 2278 2279 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2280 if (sc->sc_rev == uc->revision) 2281 break; 2282 } 2283 if (uc->ucode == NULL) 2284 return; 2285 2286 /* BIG ENDIAN: no need to swap to store 0 */ 2287 cbp->cb_status = 0; 2288 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2289 cbp->link_addr = 0xffffffff; /* (no) next command */ 2290 memcpy((void *) cbp->ucode, uc->ucode, uc->length); 2291 2292 if (uc->int_delay_offset) 2293 *(uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2294 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2295 2296 if (uc->bundle_max_offset) 2297 *(uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2298 htole16(fxp_bundle_max); 2299 2300 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2301 2302 /* 2303 * Download the uCode to the chip. 2304 */ 2305 fxp_scb_wait(sc); 2306 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2307 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2308 2309 /* ...and wait for it to complete. */ 2310 count = 10000; 2311 do { 2312 FXP_CDUCODESYNC(sc, 2313 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2314 DELAY(2); 2315 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2316 if (count == 0) { 2317 sc->sc_int_delay = 0; 2318 sc->sc_bundle_max = 0; 2319 printf("%s: timeout loading microcode\n", 2320 sc->sc_dev.dv_xname); 2321 return; 2322 } 2323 2324 if (sc->sc_int_delay != fxp_int_delay || 2325 sc->sc_bundle_max != fxp_bundle_max) { 2326 sc->sc_int_delay = fxp_int_delay; 2327 sc->sc_bundle_max = fxp_bundle_max; 2328 printf("%s: Microcode loaded: int delay: %d usec, " 2329 "max bundle: %d\n", sc->sc_dev.dv_xname, 2330 sc->sc_int_delay, 2331 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2332 } 2333 2334 sc->sc_flags |= FXPF_UCODE_LOADED; 2335 } 2336 2337 int 2338 fxp_enable(struct fxp_softc *sc) 2339 { 2340 2341 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2342 if ((*sc->sc_enable)(sc) != 0) { 2343 printf("%s: device enable failed\n", 2344 sc->sc_dev.dv_xname); 2345 return (EIO); 2346 } 2347 } 2348 2349 sc->sc_enabled = 1; 2350 return (0); 2351 } 2352 2353 void 2354 fxp_disable(struct fxp_softc *sc) 2355 { 2356 2357 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2358 (*sc->sc_disable)(sc); 2359 sc->sc_enabled = 0; 2360 } 2361 } 2362 2363 /* 2364 * fxp_activate: 2365 * 2366 * Handle device activation/deactivation requests. 2367 */ 2368 int 2369 fxp_activate(struct device *self, enum devact act) 2370 { 2371 struct fxp_softc *sc = (void *) self; 2372 int s, error = 0; 2373 2374 s = splnet(); 2375 switch (act) { 2376 case DVACT_ACTIVATE: 2377 error = EOPNOTSUPP; 2378 break; 2379 2380 case DVACT_DEACTIVATE: 2381 if (sc->sc_flags & FXPF_MII) 2382 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2383 MII_OFFSET_ANY); 2384 if_deactivate(&sc->sc_ethercom.ec_if); 2385 break; 2386 } 2387 splx(s); 2388 2389 return (error); 2390 } 2391 2392 /* 2393 * fxp_detach: 2394 * 2395 * Detach an i82557 interface. 2396 */ 2397 int 2398 fxp_detach(struct fxp_softc *sc) 2399 { 2400 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2401 int i; 2402 2403 /* Succeed now if there's no work to do. */ 2404 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2405 return (0); 2406 2407 /* Unhook our tick handler. */ 2408 callout_stop(&sc->sc_callout); 2409 2410 if (sc->sc_flags & FXPF_MII) { 2411 /* Detach all PHYs */ 2412 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2413 } 2414 2415 /* Delete all remaining media. */ 2416 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2417 2418 #if NRND > 0 2419 rnd_detach_source(&sc->rnd_source); 2420 #endif 2421 ether_ifdetach(ifp); 2422 if_detach(ifp); 2423 2424 for (i = 0; i < FXP_NRFABUFS; i++) { 2425 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2426 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2427 } 2428 2429 for (i = 0; i < FXP_NTXCB; i++) { 2430 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2431 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2432 } 2433 2434 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2435 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2436 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2437 sizeof(struct fxp_control_data)); 2438 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2439 2440 shutdownhook_disestablish(sc->sc_sdhook); 2441 powerhook_disestablish(sc->sc_powerhook); 2442 2443 return (0); 2444 } 2445
Indexes created Tue Sep 30 11:09:46 GMT 2025