i82557.c revision 1.87
1 /* $NetBSD: i82557.c,v 1.87 2004/09/20 07:32:02 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.87 2004/09/20 07:32:02 simonb Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 92 #include <machine/endian.h> 93 94 #include <uvm/uvm_extern.h> 95 96 #if NRND > 0 97 #include <sys/rnd.h> 98 #endif 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <machine/bus.h> 110 #include <machine/intr.h> 111 112 #include <dev/mii/miivar.h> 113 114 #include <dev/ic/i82557reg.h> 115 #include <dev/ic/i82557var.h> 116 117 #include <dev/microcode/i8255x/rcvbundl.h> 118 119 /* 120 * NOTE! On the Alpha, we have an alignment constraint. The 121 * card DMAs the packet immediately following the RFA. However, 122 * the first thing in the packet is a 14-byte Ethernet header. 123 * This means that the packet is misaligned. To compensate, 124 * we actually offset the RFA 2 bytes into the cluster. This 125 * alignes the packet after the Ethernet header at a 32-bit 126 * boundary. HOWEVER! This means that the RFA is misaligned! 127 */ 128 #define RFA_ALIGNMENT_FUDGE 2 129 130 /* 131 * The configuration byte map has several undefined fields which 132 * must be one or must be zero. Set up a template for these bits 133 * only (assuming an i82557 chip), leaving the actual configuration 134 * for fxp_init(). 135 * 136 * See the definition of struct fxp_cb_config for the bit definitions. 137 */ 138 const u_int8_t fxp_cb_config_template[] = { 139 0x0, 0x0, /* cb_status */ 140 0x0, 0x0, /* cb_command */ 141 0x0, 0x0, 0x0, 0x0, /* link_addr */ 142 0x0, /* 0 */ 143 0x0, /* 1 */ 144 0x0, /* 2 */ 145 0x0, /* 3 */ 146 0x0, /* 4 */ 147 0x0, /* 5 */ 148 0x32, /* 6 */ 149 0x0, /* 7 */ 150 0x0, /* 8 */ 151 0x0, /* 9 */ 152 0x6, /* 10 */ 153 0x0, /* 11 */ 154 0x0, /* 12 */ 155 0x0, /* 13 */ 156 0xf2, /* 14 */ 157 0x48, /* 15 */ 158 0x0, /* 16 */ 159 0x40, /* 17 */ 160 0xf0, /* 18 */ 161 0x0, /* 19 */ 162 0x3f, /* 20 */ 163 0x5, /* 21 */ 164 0x0, /* 22 */ 165 0x0, /* 23 */ 166 0x0, /* 24 */ 167 0x0, /* 25 */ 168 0x0, /* 26 */ 169 0x0, /* 27 */ 170 0x0, /* 28 */ 171 0x0, /* 29 */ 172 0x0, /* 30 */ 173 0x0, /* 31 */ 174 }; 175 176 void fxp_mii_initmedia(struct fxp_softc *); 177 int fxp_mii_mediachange(struct ifnet *); 178 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 void fxp_80c24_initmedia(struct fxp_softc *); 181 int fxp_80c24_mediachange(struct ifnet *); 182 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184 void fxp_start(struct ifnet *); 185 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 186 void fxp_watchdog(struct ifnet *); 187 int fxp_init(struct ifnet *); 188 void fxp_stop(struct ifnet *, int); 189 190 void fxp_txintr(struct fxp_softc *); 191 void fxp_rxintr(struct fxp_softc *); 192 193 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 194 195 void fxp_rxdrain(struct fxp_softc *); 196 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 197 int fxp_mdi_read(struct device *, int, int); 198 void fxp_statchg(struct device *); 199 void fxp_mdi_write(struct device *, int, int, int); 200 void fxp_autosize_eeprom(struct fxp_softc*); 201 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 202 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_eeprom_update_cksum(struct fxp_softc *); 204 void fxp_get_info(struct fxp_softc *, u_int8_t *); 205 void fxp_tick(void *); 206 void fxp_mc_setup(struct fxp_softc *); 207 void fxp_load_ucode(struct fxp_softc *); 208 209 void fxp_shutdown(void *); 210 void fxp_power(int, void *); 211 212 int fxp_copy_small = 0; 213 214 /* 215 * Variables for interrupt mitigating microcode. 216 */ 217 int fxp_int_delay = 1000; /* usec */ 218 int fxp_bundle_max = 6; /* packets */ 219 220 struct fxp_phytype { 221 int fp_phy; /* type of PHY, -1 for MII at the end. */ 222 void (*fp_init)(struct fxp_softc *); 223 } fxp_phytype_table[] = { 224 { FXP_PHY_80C24, fxp_80c24_initmedia }, 225 { -1, fxp_mii_initmedia }, 226 }; 227 228 /* 229 * Set initial transmit threshold at 64 (512 bytes). This is 230 * increased by 64 (512 bytes) at a time, to maximum of 192 231 * (1536 bytes), if an underrun occurs. 232 */ 233 static int tx_threshold = 64; 234 235 /* 236 * Wait for the previous command to be accepted (but not necessarily 237 * completed). 238 */ 239 static __inline void 240 fxp_scb_wait(struct fxp_softc *sc) 241 { 242 int i = 10000; 243 244 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 245 delay(2); 246 if (i == 0) 247 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 248 } 249 250 /* 251 * Submit a command to the i82557. 252 */ 253 static __inline void 254 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 255 { 256 257 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 258 } 259 260 /* 261 * Finish attaching an i82557 interface. Called by bus-specific front-end. 262 */ 263 void 264 fxp_attach(struct fxp_softc *sc) 265 { 266 u_int8_t enaddr[ETHER_ADDR_LEN]; 267 struct ifnet *ifp; 268 bus_dma_segment_t seg; 269 int rseg, i, error; 270 struct fxp_phytype *fp; 271 272 callout_init(&sc->sc_callout); 273 274 /* 275 * Enable some good stuff on i82558 and later. 276 */ 277 if (sc->sc_rev >= FXP_REV_82558_A4) { 278 /* Enable the extended TxCB. */ 279 sc->sc_flags |= FXPF_EXT_TXCB; 280 } 281 282 /* 283 * Enable use of extended RFDs and TCBs for 82550 284 * and later chips. Note: we need extended TXCB support 285 * too, but that's already enabled by the code above. 286 * Be careful to do this only on the right devices. 287 */ 288 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 289 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 290 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 291 } else { 292 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 293 } 294 295 sc->sc_rfa_size = 296 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 297 298 /* 299 * Allocate the control data structures, and create and load the 300 * DMA map for it. 301 */ 302 if ((error = bus_dmamem_alloc(sc->sc_dmat, 303 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 304 0)) != 0) { 305 aprint_error( 306 "%s: unable to allocate control data, error = %d\n", 307 sc->sc_dev.dv_xname, error); 308 goto fail_0; 309 } 310 311 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 312 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 313 BUS_DMA_COHERENT)) != 0) { 314 aprint_error("%s: unable to map control data, error = %d\n", 315 sc->sc_dev.dv_xname, error); 316 goto fail_1; 317 } 318 sc->sc_cdseg = seg; 319 sc->sc_cdnseg = rseg; 320 321 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 322 323 if ((error = bus_dmamap_create(sc->sc_dmat, 324 sizeof(struct fxp_control_data), 1, 325 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 326 aprint_error("%s: unable to create control data DMA map, " 327 "error = %d\n", sc->sc_dev.dv_xname, error); 328 goto fail_2; 329 } 330 331 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 332 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 333 0)) != 0) { 334 aprint_error( 335 "%s: can't load control data DMA map, error = %d\n", 336 sc->sc_dev.dv_xname, error); 337 goto fail_3; 338 } 339 340 /* 341 * Create the transmit buffer DMA maps. 342 */ 343 for (i = 0; i < FXP_NTXCB; i++) { 344 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 345 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 346 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 347 aprint_error("%s: unable to create tx DMA map %d, " 348 "error = %d\n", sc->sc_dev.dv_xname, i, error); 349 goto fail_4; 350 } 351 } 352 353 /* 354 * Create the receive buffer DMA maps. 355 */ 356 for (i = 0; i < FXP_NRFABUFS; i++) { 357 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 359 aprint_error("%s: unable to create rx DMA map %d, " 360 "error = %d\n", sc->sc_dev.dv_xname, i, error); 361 goto fail_5; 362 } 363 } 364 365 /* Initialize MAC address and media structures. */ 366 fxp_get_info(sc, enaddr); 367 368 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 369 ether_sprintf(enaddr)); 370 371 ifp = &sc->sc_ethercom.ec_if; 372 373 /* 374 * Get info about our media interface, and initialize it. Note 375 * the table terminates itself with a phy of -1, indicating 376 * that we're using MII. 377 */ 378 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 379 if (fp->fp_phy == sc->phy_primary_device) 380 break; 381 (*fp->fp_init)(sc); 382 383 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 384 ifp->if_softc = sc; 385 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 386 ifp->if_ioctl = fxp_ioctl; 387 ifp->if_start = fxp_start; 388 ifp->if_watchdog = fxp_watchdog; 389 ifp->if_init = fxp_init; 390 ifp->if_stop = fxp_stop; 391 IFQ_SET_READY(&ifp->if_snd); 392 393 if (sc->sc_flags & FXPF_IPCB) { 394 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 395 /* 396 * IFCAP_CSUM_IPv4 seems to have a problem, 397 * at least, on i82550 rev.12. 398 * specifically, it doesn't calculate ipv4 checksum correctly 399 * when sending 20 byte ipv4 header + 1 or 2 byte data. 400 * FreeBSD driver has related comments. 401 * 402 * XXX we should have separate IFCAP flags 403 * for transmit and receive. 404 */ 405 ifp->if_capabilities = 406 /*IFCAP_CSUM_IPv4 |*/ IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 407 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 408 } 409 410 /* 411 * We can support 802.1Q VLAN-sized frames. 412 */ 413 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 414 415 /* 416 * Attach the interface. 417 */ 418 if_attach(ifp); 419 ether_ifattach(ifp, enaddr); 420 #if NRND > 0 421 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 422 RND_TYPE_NET, 0); 423 #endif 424 425 #ifdef FXP_EVENT_COUNTERS 426 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 427 NULL, sc->sc_dev.dv_xname, "txstall"); 428 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 429 NULL, sc->sc_dev.dv_xname, "txintr"); 430 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 431 NULL, sc->sc_dev.dv_xname, "rxintr"); 432 if (sc->sc_rev >= FXP_REV_82558_A4) { 433 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 434 NULL, sc->sc_dev.dv_xname, "txpause"); 435 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 436 NULL, sc->sc_dev.dv_xname, "rxpause"); 437 } 438 #endif /* FXP_EVENT_COUNTERS */ 439 440 /* 441 * Add shutdown hook so that DMA is disabled prior to reboot. Not 442 * doing do could allow DMA to corrupt kernel memory during the 443 * reboot before the driver initializes. 444 */ 445 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 446 if (sc->sc_sdhook == NULL) 447 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 448 sc->sc_dev.dv_xname); 449 /* 450 * Add suspend hook, for similar reasons.. 451 */ 452 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 453 if (sc->sc_powerhook == NULL) 454 aprint_error("%s: WARNING: unable to establish power hook\n", 455 sc->sc_dev.dv_xname); 456 457 /* The attach is successful. */ 458 sc->sc_flags |= FXPF_ATTACHED; 459 460 return; 461 462 /* 463 * Free any resources we've allocated during the failed attach 464 * attempt. Do this in reverse order and fall though. 465 */ 466 fail_5: 467 for (i = 0; i < FXP_NRFABUFS; i++) { 468 if (sc->sc_rxmaps[i] != NULL) 469 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 470 } 471 fail_4: 472 for (i = 0; i < FXP_NTXCB; i++) { 473 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 474 bus_dmamap_destroy(sc->sc_dmat, 475 FXP_DSTX(sc, i)->txs_dmamap); 476 } 477 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 478 fail_3: 479 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 480 fail_2: 481 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 482 sizeof(struct fxp_control_data)); 483 fail_1: 484 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 485 fail_0: 486 return; 487 } 488 489 void 490 fxp_mii_initmedia(struct fxp_softc *sc) 491 { 492 int flags; 493 494 sc->sc_flags |= FXPF_MII; 495 496 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 497 sc->sc_mii.mii_readreg = fxp_mdi_read; 498 sc->sc_mii.mii_writereg = fxp_mdi_write; 499 sc->sc_mii.mii_statchg = fxp_statchg; 500 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 501 fxp_mii_mediastatus); 502 503 flags = MIIF_NOISOLATE; 504 if (sc->sc_rev >= FXP_REV_82558_A4) 505 flags |= MIIF_DOPAUSE; 506 /* 507 * The i82557 wedges if all of its PHYs are isolated! 508 */ 509 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 510 MII_OFFSET_ANY, flags); 511 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 512 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 513 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 514 } else 515 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 516 } 517 518 void 519 fxp_80c24_initmedia(struct fxp_softc *sc) 520 { 521 522 /* 523 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 524 * doesn't have a programming interface of any sort. The 525 * media is sensed automatically based on how the link partner 526 * is configured. This is, in essence, manual configuration. 527 */ 528 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 529 sc->sc_dev.dv_xname); 530 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 531 fxp_80c24_mediastatus); 532 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 533 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 534 } 535 536 /* 537 * Device shutdown routine. Called at system shutdown after sync. The 538 * main purpose of this routine is to shut off receiver DMA so that 539 * kernel memory doesn't get clobbered during warmboot. 540 */ 541 void 542 fxp_shutdown(void *arg) 543 { 544 struct fxp_softc *sc = arg; 545 546 /* 547 * Since the system's going to halt shortly, don't bother 548 * freeing mbufs. 549 */ 550 fxp_stop(&sc->sc_ethercom.ec_if, 0); 551 } 552 /* 553 * Power handler routine. Called when the system is transitioning 554 * into/out of power save modes. As with fxp_shutdown, the main 555 * purpose of this routine is to shut off receiver DMA so it doesn't 556 * clobber kernel memory at the wrong time. 557 */ 558 void 559 fxp_power(int why, void *arg) 560 { 561 struct fxp_softc *sc = arg; 562 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 563 int s; 564 565 s = splnet(); 566 switch (why) { 567 case PWR_SUSPEND: 568 case PWR_STANDBY: 569 fxp_stop(ifp, 0); 570 break; 571 case PWR_RESUME: 572 if (ifp->if_flags & IFF_UP) 573 fxp_init(ifp); 574 break; 575 case PWR_SOFTSUSPEND: 576 case PWR_SOFTSTANDBY: 577 case PWR_SOFTRESUME: 578 break; 579 } 580 splx(s); 581 } 582 583 /* 584 * Initialize the interface media. 585 */ 586 void 587 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 588 { 589 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 590 591 /* 592 * Reset to a stable state. 593 */ 594 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 595 DELAY(100); 596 597 sc->sc_eeprom_size = 0; 598 fxp_autosize_eeprom(sc); 599 if (sc->sc_eeprom_size == 0) { 600 aprint_error("%s: failed to detect EEPROM size\n", 601 sc->sc_dev.dv_xname); 602 sc->sc_eeprom_size = 6; /* XXX panic here? */ 603 } 604 #ifdef DEBUG 605 aprint_debug("%s: detected %d word EEPROM\n", 606 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 607 #endif 608 609 /* 610 * Get info about the primary PHY 611 */ 612 fxp_read_eeprom(sc, &data, 6, 1); 613 sc->phy_primary_device = 614 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 615 616 /* 617 * Read MAC address. 618 */ 619 fxp_read_eeprom(sc, myea, 0, 3); 620 enaddr[0] = myea[0] & 0xff; 621 enaddr[1] = myea[0] >> 8; 622 enaddr[2] = myea[1] & 0xff; 623 enaddr[3] = myea[1] >> 8; 624 enaddr[4] = myea[2] & 0xff; 625 enaddr[5] = myea[2] >> 8; 626 627 /* 628 * Systems based on the ICH2/ICH2-M chip from Intel, as well 629 * as some i82559 designs, have a defect where the chip can 630 * cause a PCI protocol violation if it receives a CU_RESUME 631 * command when it is entering the IDLE state. 632 * 633 * The work-around is to disable Dynamic Standby Mode, so that 634 * the chip never deasserts #CLKRUN, and always remains in the 635 * active state. 636 * 637 * Unfortunately, the only way to disable Dynamic Standby is 638 * to frob an EEPROM setting and reboot (the EEPROM setting 639 * is only consulted when the PCI bus comes out of reset). 640 * 641 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 642 */ 643 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 644 fxp_read_eeprom(sc, &data, 10, 1); 645 if (data & 0x02) { /* STB enable */ 646 aprint_error("%s: WARNING: " 647 "Disabling dynamic standby mode in EEPROM " 648 "to work around a\n", 649 sc->sc_dev.dv_xname); 650 aprint_normal( 651 "%s: WARNING: hardware bug. You must reset " 652 "the system before using this\n", 653 sc->sc_dev.dv_xname); 654 aprint_normal("%s: WARNING: interface.\n", 655 sc->sc_dev.dv_xname); 656 data &= ~0x02; 657 fxp_write_eeprom(sc, &data, 10, 1); 658 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 659 sc->sc_dev.dv_xname, data); 660 fxp_eeprom_update_cksum(sc); 661 } 662 } 663 664 /* Receiver lock-up workaround detection. */ 665 fxp_read_eeprom(sc, &data, 3, 1); 666 if ((data & 0x03) != 0x03) { 667 aprint_verbose("%s: Enabling receiver lock-up workaround\n", 668 sc->sc_dev.dv_xname); 669 sc->sc_flags |= FXPF_RECV_WORKAROUND; 670 } 671 } 672 673 static void 674 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 675 { 676 uint16_t reg; 677 int x; 678 679 for (x = 1 << (len - 1); x != 0; x >>= 1) { 680 DELAY(40); 681 if (data & x) 682 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 683 else 684 reg = FXP_EEPROM_EECS; 685 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 686 DELAY(40); 687 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 688 reg | FXP_EEPROM_EESK); 689 DELAY(40); 690 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 691 } 692 DELAY(40); 693 } 694 695 /* 696 * Figure out EEPROM size. 697 * 698 * 559's can have either 64-word or 256-word EEPROMs, the 558 699 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 700 * talks about the existence of 16 to 256 word EEPROMs. 701 * 702 * The only known sizes are 64 and 256, where the 256 version is used 703 * by CardBus cards to store CIS information. 704 * 705 * The address is shifted in msb-to-lsb, and after the last 706 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 707 * after which follows the actual data. We try to detect this zero, by 708 * probing the data-out bit in the EEPROM control register just after 709 * having shifted in a bit. If the bit is zero, we assume we've 710 * shifted enough address bits. The data-out should be tri-state, 711 * before this, which should translate to a logical one. 712 * 713 * Other ways to do this would be to try to read a register with known 714 * contents with a varying number of address bits, but no such 715 * register seem to be available. The high bits of register 10 are 01 716 * on the 558 and 559, but apparently not on the 557. 717 * 718 * The Linux driver computes a checksum on the EEPROM data, but the 719 * value of this checksum is not very well documented. 720 */ 721 722 void 723 fxp_autosize_eeprom(struct fxp_softc *sc) 724 { 725 int x; 726 727 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 728 DELAY(40); 729 730 /* Shift in read opcode. */ 731 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 732 733 /* 734 * Shift in address, wait for the dummy zero following a correct 735 * address shift. 736 */ 737 for (x = 1; x <= 8; x++) { 738 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 739 DELAY(40); 740 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 741 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 742 DELAY(40); 743 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 744 FXP_EEPROM_EEDO) == 0) 745 break; 746 DELAY(40); 747 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 748 DELAY(40); 749 } 750 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 751 DELAY(40); 752 if (x != 6 && x != 8) { 753 #ifdef DEBUG 754 printf("%s: strange EEPROM size (%d)\n", 755 sc->sc_dev.dv_xname, 1 << x); 756 #endif 757 } else 758 sc->sc_eeprom_size = x; 759 } 760 761 /* 762 * Read from the serial EEPROM. Basically, you manually shift in 763 * the read opcode (one bit at a time) and then shift in the address, 764 * and then you shift out the data (all of this one bit at a time). 765 * The word size is 16 bits, so you have to provide the address for 766 * every 16 bits of data. 767 */ 768 void 769 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 770 { 771 u_int16_t reg; 772 int i, x; 773 774 for (i = 0; i < words; i++) { 775 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 776 777 /* Shift in read opcode. */ 778 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 779 780 /* Shift in address. */ 781 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 782 783 reg = FXP_EEPROM_EECS; 784 data[i] = 0; 785 786 /* Shift out data. */ 787 for (x = 16; x > 0; x--) { 788 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 789 reg | FXP_EEPROM_EESK); 790 DELAY(40); 791 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 792 FXP_EEPROM_EEDO) 793 data[i] |= (1 << (x - 1)); 794 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 795 DELAY(40); 796 } 797 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 798 DELAY(40); 799 } 800 } 801 802 /* 803 * Write data to the serial EEPROM. 804 */ 805 void 806 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 807 { 808 int i, j; 809 810 for (i = 0; i < words; i++) { 811 /* Erase/write enable. */ 812 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 813 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 814 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 815 sc->sc_eeprom_size); 816 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 817 DELAY(4); 818 819 /* Shift in write opcode, address, data. */ 820 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 821 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 822 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 823 fxp_eeprom_shiftin(sc, data[i], 16); 824 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 825 DELAY(4); 826 827 /* Wait for the EEPROM to finish up. */ 828 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 829 DELAY(4); 830 for (j = 0; j < 1000; j++) { 831 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 832 FXP_EEPROM_EEDO) 833 break; 834 DELAY(50); 835 } 836 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 837 DELAY(4); 838 839 /* Erase/write disable. */ 840 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 841 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 842 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 843 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 844 DELAY(4); 845 } 846 } 847 848 /* 849 * Update the checksum of the EEPROM. 850 */ 851 void 852 fxp_eeprom_update_cksum(struct fxp_softc *sc) 853 { 854 int i; 855 uint16_t data, cksum; 856 857 cksum = 0; 858 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 859 fxp_read_eeprom(sc, &data, i, 1); 860 cksum += data; 861 } 862 i = (1 << sc->sc_eeprom_size) - 1; 863 cksum = 0xbaba - cksum; 864 fxp_read_eeprom(sc, &data, i, 1); 865 fxp_write_eeprom(sc, &cksum, i, 1); 866 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 867 sc->sc_dev.dv_xname, i, data, cksum); 868 } 869 870 /* 871 * Start packet transmission on the interface. 872 */ 873 void 874 fxp_start(struct ifnet *ifp) 875 { 876 struct fxp_softc *sc = ifp->if_softc; 877 struct mbuf *m0, *m; 878 struct fxp_txdesc *txd; 879 struct fxp_txsoft *txs; 880 bus_dmamap_t dmamap; 881 int error, lasttx, nexttx, opending, seg; 882 883 /* 884 * If we want a re-init, bail out now. 885 */ 886 if (sc->sc_flags & FXPF_WANTINIT) { 887 ifp->if_flags |= IFF_OACTIVE; 888 return; 889 } 890 891 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 892 return; 893 894 /* 895 * Remember the previous txpending and the current lasttx. 896 */ 897 opending = sc->sc_txpending; 898 lasttx = sc->sc_txlast; 899 900 /* 901 * Loop through the send queue, setting up transmit descriptors 902 * until we drain the queue, or use up all available transmit 903 * descriptors. 904 */ 905 for (;;) { 906 struct fxp_tbd *tbdp; 907 int csum_flags; 908 909 /* 910 * Grab a packet off the queue. 911 */ 912 IFQ_POLL(&ifp->if_snd, m0); 913 if (m0 == NULL) 914 break; 915 m = NULL; 916 917 if (sc->sc_txpending == FXP_NTXCB) { 918 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 919 break; 920 } 921 922 /* 923 * Get the next available transmit descriptor. 924 */ 925 nexttx = FXP_NEXTTX(sc->sc_txlast); 926 txd = FXP_CDTX(sc, nexttx); 927 txs = FXP_DSTX(sc, nexttx); 928 dmamap = txs->txs_dmamap; 929 930 /* 931 * Load the DMA map. If this fails, the packet either 932 * didn't fit in the allotted number of frags, or we were 933 * short on resources. In this case, we'll copy and try 934 * again. 935 */ 936 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 937 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 938 MGETHDR(m, M_DONTWAIT, MT_DATA); 939 if (m == NULL) { 940 printf("%s: unable to allocate Tx mbuf\n", 941 sc->sc_dev.dv_xname); 942 break; 943 } 944 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 945 if (m0->m_pkthdr.len > MHLEN) { 946 MCLGET(m, M_DONTWAIT); 947 if ((m->m_flags & M_EXT) == 0) { 948 printf("%s: unable to allocate Tx " 949 "cluster\n", sc->sc_dev.dv_xname); 950 m_freem(m); 951 break; 952 } 953 } 954 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 955 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 956 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 957 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 958 if (error) { 959 printf("%s: unable to load Tx buffer, " 960 "error = %d\n", sc->sc_dev.dv_xname, error); 961 break; 962 } 963 } 964 965 IFQ_DEQUEUE(&ifp->if_snd, m0); 966 csum_flags = m0->m_pkthdr.csum_flags; 967 if (m != NULL) { 968 m_freem(m0); 969 m0 = m; 970 } 971 972 /* Initialize the fraglist. */ 973 tbdp = txd->txd_tbd; 974 if (sc->sc_flags & FXPF_IPCB) 975 tbdp++; 976 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 977 tbdp[seg].tb_addr = 978 htole32(dmamap->dm_segs[seg].ds_addr); 979 tbdp[seg].tb_size = 980 htole32(dmamap->dm_segs[seg].ds_len); 981 } 982 983 /* Sync the DMA map. */ 984 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 985 BUS_DMASYNC_PREWRITE); 986 987 /* 988 * Store a pointer to the packet so we can free it later. 989 */ 990 txs->txs_mbuf = m0; 991 992 /* 993 * Initialize the transmit descriptor. 994 */ 995 /* BIG_ENDIAN: no need to swap to store 0 */ 996 txd->txd_txcb.cb_status = 0; 997 txd->txd_txcb.cb_command = 998 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 999 txd->txd_txcb.tx_threshold = tx_threshold; 1000 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 1001 1002 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 1003 if (sc->sc_flags & FXPF_IPCB) { 1004 struct fxp_ipcb *ipcb; 1005 /* 1006 * Deal with TCP/IP checksum offload. Note that 1007 * in order for TCP checksum offload to work, 1008 * the pseudo header checksum must have already 1009 * been computed and stored in the checksum field 1010 * in the TCP header. The stack should have 1011 * already done this for us. 1012 */ 1013 ipcb = &txd->txd_u.txdu_ipcb; 1014 memset(ipcb, 0, sizeof(*ipcb)); 1015 /* 1016 * always do hardware parsing. 1017 */ 1018 ipcb->ipcb_ip_activation_high = 1019 FXP_IPCB_HARDWAREPARSING_ENABLE; 1020 /* 1021 * ip checksum offloading. 1022 */ 1023 if (csum_flags & M_CSUM_IPv4) { 1024 ipcb->ipcb_ip_schedule |= 1025 FXP_IPCB_IP_CHECKSUM_ENABLE; 1026 } 1027 /* 1028 * TCP/UDP checksum offloading. 1029 */ 1030 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1031 ipcb->ipcb_ip_schedule |= 1032 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1033 } 1034 1035 /* 1036 * request VLAN tag insertion if needed. 1037 */ 1038 if (sc->sc_ethercom.ec_nvlans != 0) { 1039 struct m_tag *vtag; 1040 1041 vtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL); 1042 if (vtag) { 1043 ipcb->ipcb_vlan_id = 1044 htobe16(*(u_int *)(vtag + 1)); 1045 ipcb->ipcb_ip_activation_high |= 1046 FXP_IPCB_INSERTVLAN_ENABLE; 1047 } 1048 } 1049 } else { 1050 KASSERT((csum_flags & 1051 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1052 } 1053 1054 FXP_CDTXSYNC(sc, nexttx, 1055 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1056 1057 /* Advance the tx pointer. */ 1058 sc->sc_txpending++; 1059 sc->sc_txlast = nexttx; 1060 1061 #if NBPFILTER > 0 1062 /* 1063 * Pass packet to bpf if there is a listener. 1064 */ 1065 if (ifp->if_bpf) 1066 bpf_mtap(ifp->if_bpf, m0); 1067 #endif 1068 } 1069 1070 if (sc->sc_txpending == FXP_NTXCB) { 1071 /* No more slots; notify upper layer. */ 1072 ifp->if_flags |= IFF_OACTIVE; 1073 } 1074 1075 if (sc->sc_txpending != opending) { 1076 /* 1077 * We enqueued packets. If the transmitter was idle, 1078 * reset the txdirty pointer. 1079 */ 1080 if (opending == 0) 1081 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1082 1083 /* 1084 * Cause the chip to interrupt and suspend command 1085 * processing once the last packet we've enqueued 1086 * has been transmitted. 1087 */ 1088 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 1089 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1090 FXP_CDTXSYNC(sc, sc->sc_txlast, 1091 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1092 1093 /* 1094 * The entire packet chain is set up. Clear the suspend bit 1095 * on the command prior to the first packet we set up. 1096 */ 1097 FXP_CDTXSYNC(sc, lasttx, 1098 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1099 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1100 htole16(~FXP_CB_COMMAND_S); 1101 FXP_CDTXSYNC(sc, lasttx, 1102 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1103 1104 /* 1105 * Issue a Resume command in case the chip was suspended. 1106 */ 1107 fxp_scb_wait(sc); 1108 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1109 1110 /* Set a watchdog timer in case the chip flakes out. */ 1111 ifp->if_timer = 5; 1112 } 1113 } 1114 1115 /* 1116 * Process interface interrupts. 1117 */ 1118 int 1119 fxp_intr(void *arg) 1120 { 1121 struct fxp_softc *sc = arg; 1122 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1123 bus_dmamap_t rxmap; 1124 int claimed = 0; 1125 u_int8_t statack; 1126 1127 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0 || sc->sc_enabled == 0) 1128 return (0); 1129 /* 1130 * If the interface isn't running, don't try to 1131 * service the interrupt.. just ack it and bail. 1132 */ 1133 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1134 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1135 if (statack) { 1136 claimed = 1; 1137 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1138 } 1139 return (claimed); 1140 } 1141 1142 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1143 claimed = 1; 1144 1145 /* 1146 * First ACK all the interrupts in this pass. 1147 */ 1148 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1149 1150 /* 1151 * Process receiver interrupts. If a no-resource (RNR) 1152 * condition exists, get whatever packets we can and 1153 * re-start the receiver. 1154 */ 1155 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1156 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1157 fxp_rxintr(sc); 1158 } 1159 1160 if (statack & FXP_SCB_STATACK_RNR) { 1161 fxp_scb_wait(sc); 1162 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1163 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1164 fxp_scb_wait(sc); 1165 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1166 rxmap->dm_segs[0].ds_addr + 1167 RFA_ALIGNMENT_FUDGE); 1168 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1169 } 1170 1171 /* 1172 * Free any finished transmit mbuf chains. 1173 */ 1174 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1175 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1176 fxp_txintr(sc); 1177 1178 /* 1179 * Try to get more packets going. 1180 */ 1181 fxp_start(ifp); 1182 1183 if (sc->sc_txpending == 0) { 1184 /* 1185 * If we want a re-init, do that now. 1186 */ 1187 if (sc->sc_flags & FXPF_WANTINIT) 1188 (void) fxp_init(ifp); 1189 } 1190 } 1191 } 1192 1193 #if NRND > 0 1194 if (claimed) 1195 rnd_add_uint32(&sc->rnd_source, statack); 1196 #endif 1197 return (claimed); 1198 } 1199 1200 /* 1201 * Handle transmit completion interrupts. 1202 */ 1203 void 1204 fxp_txintr(struct fxp_softc *sc) 1205 { 1206 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1207 struct fxp_txdesc *txd; 1208 struct fxp_txsoft *txs; 1209 int i; 1210 u_int16_t txstat; 1211 1212 ifp->if_flags &= ~IFF_OACTIVE; 1213 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1214 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1215 txd = FXP_CDTX(sc, i); 1216 txs = FXP_DSTX(sc, i); 1217 1218 FXP_CDTXSYNC(sc, i, 1219 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1220 1221 txstat = le16toh(txd->txd_txcb.cb_status); 1222 1223 if ((txstat & FXP_CB_STATUS_C) == 0) 1224 break; 1225 1226 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1227 0, txs->txs_dmamap->dm_mapsize, 1228 BUS_DMASYNC_POSTWRITE); 1229 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1230 m_freem(txs->txs_mbuf); 1231 txs->txs_mbuf = NULL; 1232 } 1233 1234 /* Update the dirty transmit buffer pointer. */ 1235 sc->sc_txdirty = i; 1236 1237 /* 1238 * Cancel the watchdog timer if there are no pending 1239 * transmissions. 1240 */ 1241 if (sc->sc_txpending == 0) 1242 ifp->if_timer = 0; 1243 } 1244 1245 /* 1246 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1247 */ 1248 1249 int 1250 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1251 { 1252 u_int16_t rxparsestat; 1253 u_int16_t csum_stat; 1254 u_int32_t csum_data; 1255 int csum_flags; 1256 1257 /* 1258 * check VLAN tag stripping. 1259 */ 1260 1261 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1262 struct m_tag *vtag; 1263 1264 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1265 if (vtag == NULL) 1266 return ENOMEM; 1267 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1268 m_tag_prepend(m, vtag); 1269 } 1270 1271 /* 1272 * check H/W Checksumming. 1273 */ 1274 1275 csum_stat = le16toh(rfa->cksum_stat); 1276 rxparsestat = le16toh(rfa->rx_parse_stat); 1277 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1278 return 0; 1279 1280 csum_flags = 0; 1281 csum_data = 0; 1282 1283 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1284 csum_flags = M_CSUM_IPv4; 1285 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1286 csum_flags |= M_CSUM_IPv4_BAD; 1287 } 1288 1289 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1290 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1291 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1292 csum_flags |= M_CSUM_TCP_UDP_BAD; 1293 } 1294 1295 m->m_pkthdr.csum_flags = csum_flags; 1296 m->m_pkthdr.csum_data = csum_data; 1297 1298 return 0; 1299 } 1300 1301 /* 1302 * Handle receive interrupts. 1303 */ 1304 void 1305 fxp_rxintr(struct fxp_softc *sc) 1306 { 1307 struct ethercom *ec = &sc->sc_ethercom; 1308 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1309 struct mbuf *m, *m0; 1310 bus_dmamap_t rxmap; 1311 struct fxp_rfa *rfa; 1312 u_int16_t len, rxstat; 1313 1314 for (;;) { 1315 m = sc->sc_rxq.ifq_head; 1316 rfa = FXP_MTORFA(m); 1317 rxmap = M_GETCTX(m, bus_dmamap_t); 1318 1319 FXP_RFASYNC(sc, m, 1320 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1321 1322 rxstat = le16toh(rfa->rfa_status); 1323 1324 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1325 /* 1326 * We have processed all of the 1327 * receive buffers. 1328 */ 1329 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1330 return; 1331 } 1332 1333 IF_DEQUEUE(&sc->sc_rxq, m); 1334 1335 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1336 1337 len = le16toh(rfa->actual_size) & 1338 (m->m_ext.ext_size - 1); 1339 1340 if (len < sizeof(struct ether_header)) { 1341 /* 1342 * Runt packet; drop it now. 1343 */ 1344 FXP_INIT_RFABUF(sc, m); 1345 continue; 1346 } 1347 1348 /* 1349 * If support for 802.1Q VLAN sized frames is 1350 * enabled, we need to do some additional error 1351 * checking (as we are saving bad frames, in 1352 * order to receive the larger ones). 1353 */ 1354 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1355 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1356 FXP_RFA_STATUS_RNR| 1357 FXP_RFA_STATUS_ALIGN| 1358 FXP_RFA_STATUS_CRC)) != 0) { 1359 FXP_INIT_RFABUF(sc, m); 1360 continue; 1361 } 1362 1363 /* Do checksum checking. */ 1364 m->m_pkthdr.csum_flags = 0; 1365 if (sc->sc_flags & FXPF_EXT_RFA) 1366 if (fxp_rx_hwcksum(m, rfa)) 1367 goto dropit; 1368 1369 /* 1370 * If the packet is small enough to fit in a 1371 * single header mbuf, allocate one and copy 1372 * the data into it. This greatly reduces 1373 * memory consumption when we receive lots 1374 * of small packets. 1375 * 1376 * Otherwise, we add a new buffer to the receive 1377 * chain. If this fails, we drop the packet and 1378 * recycle the old buffer. 1379 */ 1380 if (fxp_copy_small != 0 && len <= MHLEN) { 1381 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1382 if (m0 == NULL) 1383 goto dropit; 1384 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1385 memcpy(mtod(m0, caddr_t), 1386 mtod(m, caddr_t), len); 1387 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1388 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1389 FXP_INIT_RFABUF(sc, m); 1390 m = m0; 1391 } else { 1392 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1393 dropit: 1394 ifp->if_ierrors++; 1395 FXP_INIT_RFABUF(sc, m); 1396 continue; 1397 } 1398 } 1399 1400 m->m_pkthdr.rcvif = ifp; 1401 m->m_pkthdr.len = m->m_len = len; 1402 1403 #if NBPFILTER > 0 1404 /* 1405 * Pass this up to any BPF listeners, but only 1406 * pass it up the stack it its for us. 1407 */ 1408 if (ifp->if_bpf) 1409 bpf_mtap(ifp->if_bpf, m); 1410 #endif 1411 1412 /* Pass it on. */ 1413 (*ifp->if_input)(ifp, m); 1414 } 1415 } 1416 1417 /* 1418 * Update packet in/out/collision statistics. The i82557 doesn't 1419 * allow you to access these counters without doing a fairly 1420 * expensive DMA to get _all_ of the statistics it maintains, so 1421 * we do this operation here only once per second. The statistics 1422 * counters in the kernel are updated from the previous dump-stats 1423 * DMA and then a new dump-stats DMA is started. The on-chip 1424 * counters are zeroed when the DMA completes. If we can't start 1425 * the DMA immediately, we don't wait - we just prepare to read 1426 * them again next time. 1427 */ 1428 void 1429 fxp_tick(void *arg) 1430 { 1431 struct fxp_softc *sc = arg; 1432 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1433 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1434 int s; 1435 1436 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1437 return; 1438 1439 s = splnet(); 1440 1441 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1442 1443 ifp->if_opackets += le32toh(sp->tx_good); 1444 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1445 if (sp->rx_good) { 1446 ifp->if_ipackets += le32toh(sp->rx_good); 1447 sc->sc_rxidle = 0; 1448 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1449 sc->sc_rxidle++; 1450 } 1451 ifp->if_ierrors += 1452 le32toh(sp->rx_crc_errors) + 1453 le32toh(sp->rx_alignment_errors) + 1454 le32toh(sp->rx_rnr_errors) + 1455 le32toh(sp->rx_overrun_errors); 1456 /* 1457 * If any transmit underruns occurred, bump up the transmit 1458 * threshold by another 512 bytes (64 * 8). 1459 */ 1460 if (sp->tx_underruns) { 1461 ifp->if_oerrors += le32toh(sp->tx_underruns); 1462 if (tx_threshold < 192) 1463 tx_threshold += 64; 1464 } 1465 #ifdef FXP_EVENT_COUNTERS 1466 if (sc->sc_rev >= FXP_REV_82558_A4) { 1467 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1468 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1469 } 1470 #endif 1471 1472 /* 1473 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1474 * then assume the receiver has locked up and attempt to clear 1475 * the condition by reprogramming the multicast filter (actually, 1476 * resetting the interface). This is a work-around for a bug in 1477 * the 82557 where the receiver locks up if it gets certain types 1478 * of garbage in the synchronization bits prior to the packet header. 1479 * This bug is supposed to only occur in 10Mbps mode, but has been 1480 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1481 * speed transition). 1482 */ 1483 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1484 (void) fxp_init(ifp); 1485 splx(s); 1486 return; 1487 } 1488 /* 1489 * If there is no pending command, start another stats 1490 * dump. Otherwise punt for now. 1491 */ 1492 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1493 /* 1494 * Start another stats dump. 1495 */ 1496 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1497 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1498 } else { 1499 /* 1500 * A previous command is still waiting to be accepted. 1501 * Just zero our copy of the stats and wait for the 1502 * next timer event to update them. 1503 */ 1504 /* BIG_ENDIAN: no swap required to store 0 */ 1505 sp->tx_good = 0; 1506 sp->tx_underruns = 0; 1507 sp->tx_total_collisions = 0; 1508 1509 sp->rx_good = 0; 1510 sp->rx_crc_errors = 0; 1511 sp->rx_alignment_errors = 0; 1512 sp->rx_rnr_errors = 0; 1513 sp->rx_overrun_errors = 0; 1514 if (sc->sc_rev >= FXP_REV_82558_A4) { 1515 sp->tx_pauseframes = 0; 1516 sp->rx_pauseframes = 0; 1517 } 1518 } 1519 1520 if (sc->sc_flags & FXPF_MII) { 1521 /* Tick the MII clock. */ 1522 mii_tick(&sc->sc_mii); 1523 } 1524 1525 splx(s); 1526 1527 /* 1528 * Schedule another timeout one second from now. 1529 */ 1530 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1531 } 1532 1533 /* 1534 * Drain the receive queue. 1535 */ 1536 void 1537 fxp_rxdrain(struct fxp_softc *sc) 1538 { 1539 bus_dmamap_t rxmap; 1540 struct mbuf *m; 1541 1542 for (;;) { 1543 IF_DEQUEUE(&sc->sc_rxq, m); 1544 if (m == NULL) 1545 break; 1546 rxmap = M_GETCTX(m, bus_dmamap_t); 1547 bus_dmamap_unload(sc->sc_dmat, rxmap); 1548 FXP_RXMAP_PUT(sc, rxmap); 1549 m_freem(m); 1550 } 1551 } 1552 1553 /* 1554 * Stop the interface. Cancels the statistics updater and resets 1555 * the interface. 1556 */ 1557 void 1558 fxp_stop(struct ifnet *ifp, int disable) 1559 { 1560 struct fxp_softc *sc = ifp->if_softc; 1561 struct fxp_txsoft *txs; 1562 int i; 1563 1564 /* 1565 * Turn down interface (done early to avoid bad interactions 1566 * between panics, shutdown hooks, and the watchdog timer) 1567 */ 1568 ifp->if_timer = 0; 1569 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1570 1571 /* 1572 * Cancel stats updater. 1573 */ 1574 callout_stop(&sc->sc_callout); 1575 if (sc->sc_flags & FXPF_MII) { 1576 /* Down the MII. */ 1577 mii_down(&sc->sc_mii); 1578 } 1579 1580 /* 1581 * Issue software reset. This unloads any microcode that 1582 * might already be loaded. 1583 */ 1584 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1585 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1586 DELAY(50); 1587 1588 /* 1589 * Release any xmit buffers. 1590 */ 1591 for (i = 0; i < FXP_NTXCB; i++) { 1592 txs = FXP_DSTX(sc, i); 1593 if (txs->txs_mbuf != NULL) { 1594 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1595 m_freem(txs->txs_mbuf); 1596 txs->txs_mbuf = NULL; 1597 } 1598 } 1599 sc->sc_txpending = 0; 1600 1601 if (disable) { 1602 fxp_rxdrain(sc); 1603 fxp_disable(sc); 1604 } 1605 1606 } 1607 1608 /* 1609 * Watchdog/transmission transmit timeout handler. Called when a 1610 * transmission is started on the interface, but no interrupt is 1611 * received before the timeout. This usually indicates that the 1612 * card has wedged for some reason. 1613 */ 1614 void 1615 fxp_watchdog(struct ifnet *ifp) 1616 { 1617 struct fxp_softc *sc = ifp->if_softc; 1618 1619 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1620 ifp->if_oerrors++; 1621 1622 (void) fxp_init(ifp); 1623 } 1624 1625 /* 1626 * Initialize the interface. Must be called at splnet(). 1627 */ 1628 int 1629 fxp_init(struct ifnet *ifp) 1630 { 1631 struct fxp_softc *sc = ifp->if_softc; 1632 struct fxp_cb_config *cbp; 1633 struct fxp_cb_ias *cb_ias; 1634 struct fxp_txdesc *txd; 1635 bus_dmamap_t rxmap; 1636 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1637 1638 if ((error = fxp_enable(sc)) != 0) 1639 goto out; 1640 1641 /* 1642 * Cancel any pending I/O 1643 */ 1644 fxp_stop(ifp, 0); 1645 1646 /* 1647 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1648 * flag, and this prevents the MII from detaching resulting in 1649 * a panic. The flags field should perhaps be split in runtime 1650 * flags and more static information. For now, just clear the 1651 * only other flag set. 1652 */ 1653 1654 sc->sc_flags &= ~FXPF_WANTINIT; 1655 1656 /* 1657 * Initialize base of CBL and RFA memory. Loading with zero 1658 * sets it up for regular linear addressing. 1659 */ 1660 fxp_scb_wait(sc); 1661 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1662 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1663 1664 fxp_scb_wait(sc); 1665 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1666 1667 /* 1668 * Initialize the multicast filter. Do this now, since we might 1669 * have to setup the config block differently. 1670 */ 1671 fxp_mc_setup(sc); 1672 1673 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1674 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1675 1676 /* 1677 * In order to support receiving 802.1Q VLAN frames, we have to 1678 * enable "save bad frames", since they are 4 bytes larger than 1679 * the normal Ethernet maximum frame length. On i82558 and later, 1680 * we have a better mechanism for this. 1681 */ 1682 save_bf = 0; 1683 lrxen = 0; 1684 vlan_drop = 0; 1685 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1686 if (sc->sc_rev < FXP_REV_82558_A4) 1687 save_bf = 1; 1688 else 1689 lrxen = 1; 1690 if (sc->sc_rev >= FXP_REV_82550) 1691 vlan_drop = 1; 1692 } 1693 1694 /* 1695 * Initialize base of dump-stats buffer. 1696 */ 1697 fxp_scb_wait(sc); 1698 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1699 sc->sc_cddma + FXP_CDSTATSOFF); 1700 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1701 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1702 1703 cbp = &sc->sc_control_data->fcd_configcb; 1704 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1705 1706 /* 1707 * Load microcode for this controller. 1708 */ 1709 fxp_load_ucode(sc); 1710 1711 /* 1712 * This copy is kind of disgusting, but there are a bunch of must be 1713 * zero and must be one bits in this structure and this is the easiest 1714 * way to initialize them all to proper values. 1715 */ 1716 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1717 1718 /* BIG_ENDIAN: no need to swap to store 0 */ 1719 cbp->cb_status = 0; 1720 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1721 FXP_CB_COMMAND_EL); 1722 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1723 cbp->link_addr = 0xffffffff; /* (no) next command */ 1724 /* bytes in config block */ 1725 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1726 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1727 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1728 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1729 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1730 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1731 cbp->type_enable = 0; /* actually reserved */ 1732 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1733 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1734 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1735 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1736 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1737 cbp->late_scb = 0; /* (don't) defer SCB update */ 1738 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1739 cbp->ci_int = 1; /* interrupt on CU idle */ 1740 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1741 cbp->ext_stats_dis = 1; /* disable extended counters */ 1742 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1743 cbp->save_bf = save_bf;/* save bad frames */ 1744 cbp->disc_short_rx = !prm; /* discard short packets */ 1745 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1746 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1747 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1748 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1749 /* interface mode */ 1750 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1751 cbp->csma_dis = 0; /* (don't) disable link */ 1752 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1753 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1754 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1755 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1756 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1757 cbp->nsai = 1; /* (don't) disable source addr insert */ 1758 cbp->preamble_length = 2; /* (7 byte) preamble */ 1759 cbp->loopback = 0; /* (don't) loopback */ 1760 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1761 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1762 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1763 cbp->promiscuous = prm; /* promiscuous mode */ 1764 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1765 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1766 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1767 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1768 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1769 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1770 cbp->padding = 1; /* (do) pad short tx packets */ 1771 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1772 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1773 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1774 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1775 /* must set wake_en in PMCSR also */ 1776 cbp->force_fdx = 0; /* (don't) force full duplex */ 1777 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1778 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1779 cbp->mc_all = allm; /* accept all multicasts */ 1780 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1781 cbp->vlan_drop_en = vlan_drop; 1782 1783 if (sc->sc_rev < FXP_REV_82558_A4) { 1784 /* 1785 * The i82557 has no hardware flow control, the values 1786 * here are the defaults for the chip. 1787 */ 1788 cbp->fc_delay_lsb = 0; 1789 cbp->fc_delay_msb = 0x40; 1790 cbp->pri_fc_thresh = 3; 1791 cbp->tx_fc_dis = 0; 1792 cbp->rx_fc_restop = 0; 1793 cbp->rx_fc_restart = 0; 1794 cbp->fc_filter = 0; 1795 cbp->pri_fc_loc = 1; 1796 } else { 1797 cbp->fc_delay_lsb = 0x1f; 1798 cbp->fc_delay_msb = 0x01; 1799 cbp->pri_fc_thresh = 3; 1800 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1801 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1802 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1803 cbp->fc_filter = !prm; /* drop FC frames to host */ 1804 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1805 cbp->ext_stats_dis = 0; /* enable extended stats */ 1806 } 1807 1808 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1809 1810 /* 1811 * Start the config command/DMA. 1812 */ 1813 fxp_scb_wait(sc); 1814 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1815 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1816 /* ...and wait for it to complete. */ 1817 i = 1000; 1818 do { 1819 FXP_CDCONFIGSYNC(sc, 1820 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1821 DELAY(1); 1822 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1823 if (i == 0) { 1824 printf("%s at line %d: dmasync timeout\n", 1825 sc->sc_dev.dv_xname, __LINE__); 1826 return (ETIMEDOUT); 1827 } 1828 1829 /* 1830 * Initialize the station address. 1831 */ 1832 cb_ias = &sc->sc_control_data->fcd_iascb; 1833 /* BIG_ENDIAN: no need to swap to store 0 */ 1834 cb_ias->cb_status = 0; 1835 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1836 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1837 cb_ias->link_addr = 0xffffffff; 1838 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1839 1840 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1841 1842 /* 1843 * Start the IAS (Individual Address Setup) command/DMA. 1844 */ 1845 fxp_scb_wait(sc); 1846 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1847 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1848 /* ...and wait for it to complete. */ 1849 i = 1000; 1850 do { 1851 FXP_CDIASSYNC(sc, 1852 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1853 DELAY(1); 1854 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1855 if (i == 0) { 1856 printf("%s at line %d: dmasync timeout\n", 1857 sc->sc_dev.dv_xname, __LINE__); 1858 return (ETIMEDOUT); 1859 } 1860 1861 /* 1862 * Initialize the transmit descriptor ring. txlast is initialized 1863 * to the end of the list so that it will wrap around to the first 1864 * descriptor when the first packet is transmitted. 1865 */ 1866 for (i = 0; i < FXP_NTXCB; i++) { 1867 txd = FXP_CDTX(sc, i); 1868 memset(txd, 0, sizeof(*txd)); 1869 txd->txd_txcb.cb_command = 1870 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1871 txd->txd_txcb.link_addr = 1872 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1873 if (sc->sc_flags & FXPF_EXT_TXCB) 1874 txd->txd_txcb.tbd_array_addr = 1875 htole32(FXP_CDTBDADDR(sc, i) + 1876 (2 * sizeof(struct fxp_tbd))); 1877 else 1878 txd->txd_txcb.tbd_array_addr = 1879 htole32(FXP_CDTBDADDR(sc, i)); 1880 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1881 } 1882 sc->sc_txpending = 0; 1883 sc->sc_txdirty = 0; 1884 sc->sc_txlast = FXP_NTXCB - 1; 1885 1886 /* 1887 * Initialize the receive buffer list. 1888 */ 1889 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1890 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1891 rxmap = FXP_RXMAP_GET(sc); 1892 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1893 printf("%s: unable to allocate or map rx " 1894 "buffer %d, error = %d\n", 1895 sc->sc_dev.dv_xname, 1896 sc->sc_rxq.ifq_len, error); 1897 /* 1898 * XXX Should attempt to run with fewer receive 1899 * XXX buffers instead of just failing. 1900 */ 1901 FXP_RXMAP_PUT(sc, rxmap); 1902 fxp_rxdrain(sc); 1903 goto out; 1904 } 1905 } 1906 sc->sc_rxidle = 0; 1907 1908 /* 1909 * Give the transmit ring to the chip. We do this by pointing 1910 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1911 * issuing a start command. It will execute the NOP and then 1912 * suspend, pointing at the first descriptor. 1913 */ 1914 fxp_scb_wait(sc); 1915 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1916 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1917 1918 /* 1919 * Initialize receiver buffer area - RFA. 1920 */ 1921 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1922 fxp_scb_wait(sc); 1923 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1924 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1925 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1926 1927 if (sc->sc_flags & FXPF_MII) { 1928 /* 1929 * Set current media. 1930 */ 1931 mii_mediachg(&sc->sc_mii); 1932 } 1933 1934 /* 1935 * ...all done! 1936 */ 1937 ifp->if_flags |= IFF_RUNNING; 1938 ifp->if_flags &= ~IFF_OACTIVE; 1939 1940 /* 1941 * Start the one second timer. 1942 */ 1943 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1944 1945 /* 1946 * Attempt to start output on the interface. 1947 */ 1948 fxp_start(ifp); 1949 1950 out: 1951 if (error) { 1952 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1953 ifp->if_timer = 0; 1954 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1955 } 1956 return (error); 1957 } 1958 1959 /* 1960 * Change media according to request. 1961 */ 1962 int 1963 fxp_mii_mediachange(struct ifnet *ifp) 1964 { 1965 struct fxp_softc *sc = ifp->if_softc; 1966 1967 if (ifp->if_flags & IFF_UP) 1968 mii_mediachg(&sc->sc_mii); 1969 return (0); 1970 } 1971 1972 /* 1973 * Notify the world which media we're using. 1974 */ 1975 void 1976 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1977 { 1978 struct fxp_softc *sc = ifp->if_softc; 1979 1980 if (sc->sc_enabled == 0) { 1981 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1982 ifmr->ifm_status = 0; 1983 return; 1984 } 1985 1986 mii_pollstat(&sc->sc_mii); 1987 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1988 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1989 1990 /* 1991 * XXX Flow control is always turned on if the chip supports 1992 * XXX it; we can't easily control it dynamically, since it 1993 * XXX requires sending a setup packet. 1994 */ 1995 if (sc->sc_rev >= FXP_REV_82558_A4) 1996 ifmr->ifm_active |= IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE; 1997 } 1998 1999 int 2000 fxp_80c24_mediachange(struct ifnet *ifp) 2001 { 2002 2003 /* Nothing to do here. */ 2004 return (0); 2005 } 2006 2007 void 2008 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2009 { 2010 struct fxp_softc *sc = ifp->if_softc; 2011 2012 /* 2013 * Media is currently-selected media. We cannot determine 2014 * the link status. 2015 */ 2016 ifmr->ifm_status = 0; 2017 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2018 } 2019 2020 /* 2021 * Add a buffer to the end of the RFA buffer list. 2022 * Return 0 if successful, error code on failure. 2023 * 2024 * The RFA struct is stuck at the beginning of mbuf cluster and the 2025 * data pointer is fixed up to point just past it. 2026 */ 2027 int 2028 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2029 { 2030 struct mbuf *m; 2031 int error; 2032 2033 MGETHDR(m, M_DONTWAIT, MT_DATA); 2034 if (m == NULL) 2035 return (ENOBUFS); 2036 2037 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2038 MCLGET(m, M_DONTWAIT); 2039 if ((m->m_flags & M_EXT) == 0) { 2040 m_freem(m); 2041 return (ENOBUFS); 2042 } 2043 2044 if (unload) 2045 bus_dmamap_unload(sc->sc_dmat, rxmap); 2046 2047 M_SETCTX(m, rxmap); 2048 2049 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2050 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2051 BUS_DMA_READ|BUS_DMA_NOWAIT); 2052 if (error) { 2053 printf("%s: can't load rx DMA map %d, error = %d\n", 2054 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 2055 panic("fxp_add_rfabuf"); /* XXX */ 2056 } 2057 2058 FXP_INIT_RFABUF(sc, m); 2059 2060 return (0); 2061 } 2062 2063 int 2064 fxp_mdi_read(struct device *self, int phy, int reg) 2065 { 2066 struct fxp_softc *sc = (struct fxp_softc *)self; 2067 int count = 10000; 2068 int value; 2069 2070 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2071 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2072 2073 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2074 0x10000000) == 0 && count--) 2075 DELAY(10); 2076 2077 if (count <= 0) 2078 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 2079 2080 return (value & 0xffff); 2081 } 2082 2083 void 2084 fxp_statchg(struct device *self) 2085 { 2086 2087 /* Nothing to do. */ 2088 } 2089 2090 void 2091 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2092 { 2093 struct fxp_softc *sc = (struct fxp_softc *)self; 2094 int count = 10000; 2095 2096 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2097 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2098 (value & 0xffff)); 2099 2100 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2101 count--) 2102 DELAY(10); 2103 2104 if (count <= 0) 2105 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2106 } 2107 2108 int 2109 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2110 { 2111 struct fxp_softc *sc = ifp->if_softc; 2112 struct ifreq *ifr = (struct ifreq *)data; 2113 int s, error; 2114 2115 s = splnet(); 2116 2117 switch (cmd) { 2118 case SIOCSIFMEDIA: 2119 case SIOCGIFMEDIA: 2120 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2121 break; 2122 2123 default: 2124 error = ether_ioctl(ifp, cmd, data); 2125 if (error == ENETRESET) { 2126 if (sc->sc_enabled) { 2127 /* 2128 * Multicast list has changed; set the 2129 * hardware filter accordingly. 2130 */ 2131 if (sc->sc_txpending) { 2132 sc->sc_flags |= FXPF_WANTINIT; 2133 error = 0; 2134 } else 2135 error = fxp_init(ifp); 2136 } else 2137 error = 0; 2138 } 2139 break; 2140 } 2141 2142 /* Try to get more packets going. */ 2143 if (sc->sc_enabled) 2144 fxp_start(ifp); 2145 2146 splx(s); 2147 return (error); 2148 } 2149 2150 /* 2151 * Program the multicast filter. 2152 * 2153 * This function must be called at splnet(). 2154 */ 2155 void 2156 fxp_mc_setup(struct fxp_softc *sc) 2157 { 2158 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2159 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2160 struct ethercom *ec = &sc->sc_ethercom; 2161 struct ether_multi *enm; 2162 struct ether_multistep step; 2163 int count, nmcasts; 2164 2165 #ifdef DIAGNOSTIC 2166 if (sc->sc_txpending) 2167 panic("fxp_mc_setup: pending transmissions"); 2168 #endif 2169 2170 ifp->if_flags &= ~IFF_ALLMULTI; 2171 2172 /* 2173 * Initialize multicast setup descriptor. 2174 */ 2175 nmcasts = 0; 2176 ETHER_FIRST_MULTI(step, ec, enm); 2177 while (enm != NULL) { 2178 /* 2179 * Check for too many multicast addresses or if we're 2180 * listening to a range. Either way, we simply have 2181 * to accept all multicasts. 2182 */ 2183 if (nmcasts >= MAXMCADDR || 2184 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2185 ETHER_ADDR_LEN) != 0) { 2186 /* 2187 * Callers of this function must do the 2188 * right thing with this. If we're called 2189 * from outside fxp_init(), the caller must 2190 * detect if the state if IFF_ALLMULTI changes. 2191 * If it does, the caller must then call 2192 * fxp_init(), since allmulti is handled by 2193 * the config block. 2194 */ 2195 ifp->if_flags |= IFF_ALLMULTI; 2196 return; 2197 } 2198 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2199 ETHER_ADDR_LEN); 2200 nmcasts++; 2201 ETHER_NEXT_MULTI(step, enm); 2202 } 2203 2204 /* BIG_ENDIAN: no need to swap to store 0 */ 2205 mcsp->cb_status = 0; 2206 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2207 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2208 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2209 2210 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2211 2212 /* 2213 * Wait until the command unit is not active. This should never 2214 * happen since nothing is queued, but make sure anyway. 2215 */ 2216 count = 100; 2217 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2218 FXP_SCB_CUS_ACTIVE && --count) 2219 DELAY(1); 2220 if (count == 0) { 2221 printf("%s at line %d: command queue timeout\n", 2222 sc->sc_dev.dv_xname, __LINE__); 2223 return; 2224 } 2225 2226 /* 2227 * Start the multicast setup command/DMA. 2228 */ 2229 fxp_scb_wait(sc); 2230 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2231 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2232 2233 /* ...and wait for it to complete. */ 2234 count = 1000; 2235 do { 2236 FXP_CDMCSSYNC(sc, 2237 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2238 DELAY(1); 2239 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2240 if (count == 0) { 2241 printf("%s at line %d: dmasync timeout\n", 2242 sc->sc_dev.dv_xname, __LINE__); 2243 return; 2244 } 2245 } 2246 2247 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2248 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2249 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2250 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2251 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2252 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2253 2254 #define UCODE(x) x, sizeof(x) 2255 2256 static const struct ucode { 2257 int32_t revision; 2258 const uint32_t *ucode; 2259 size_t length; 2260 uint16_t int_delay_offset; 2261 uint16_t bundle_max_offset; 2262 } ucode_table[] = { 2263 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2264 D101_CPUSAVER_DWORD, 0 }, 2265 2266 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2267 D101_CPUSAVER_DWORD, 0 }, 2268 2269 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2270 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2271 2272 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2273 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2274 2275 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2276 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2277 2278 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2279 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2280 2281 { 0, NULL, 0, 0, 0 } 2282 }; 2283 2284 void 2285 fxp_load_ucode(struct fxp_softc *sc) 2286 { 2287 const struct ucode *uc; 2288 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2289 int count; 2290 2291 if (sc->sc_flags & FXPF_UCODE_LOADED) 2292 return; 2293 2294 /* 2295 * Only load the uCode if the user has requested that 2296 * we do so. 2297 */ 2298 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2299 sc->sc_int_delay = 0; 2300 sc->sc_bundle_max = 0; 2301 return; 2302 } 2303 2304 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2305 if (sc->sc_rev == uc->revision) 2306 break; 2307 } 2308 if (uc->ucode == NULL) 2309 return; 2310 2311 /* BIG ENDIAN: no need to swap to store 0 */ 2312 cbp->cb_status = 0; 2313 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2314 cbp->link_addr = 0xffffffff; /* (no) next command */ 2315 memcpy((void *) cbp->ucode, uc->ucode, uc->length); 2316 2317 if (uc->int_delay_offset) 2318 *(uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2319 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2320 2321 if (uc->bundle_max_offset) 2322 *(uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2323 htole16(fxp_bundle_max); 2324 2325 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2326 2327 /* 2328 * Download the uCode to the chip. 2329 */ 2330 fxp_scb_wait(sc); 2331 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2332 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2333 2334 /* ...and wait for it to complete. */ 2335 count = 10000; 2336 do { 2337 FXP_CDUCODESYNC(sc, 2338 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2339 DELAY(2); 2340 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2341 if (count == 0) { 2342 sc->sc_int_delay = 0; 2343 sc->sc_bundle_max = 0; 2344 printf("%s: timeout loading microcode\n", 2345 sc->sc_dev.dv_xname); 2346 return; 2347 } 2348 2349 if (sc->sc_int_delay != fxp_int_delay || 2350 sc->sc_bundle_max != fxp_bundle_max) { 2351 sc->sc_int_delay = fxp_int_delay; 2352 sc->sc_bundle_max = fxp_bundle_max; 2353 printf("%s: Microcode loaded: int delay: %d usec, " 2354 "max bundle: %d\n", sc->sc_dev.dv_xname, 2355 sc->sc_int_delay, 2356 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2357 } 2358 2359 sc->sc_flags |= FXPF_UCODE_LOADED; 2360 } 2361 2362 int 2363 fxp_enable(struct fxp_softc *sc) 2364 { 2365 2366 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2367 if ((*sc->sc_enable)(sc) != 0) { 2368 printf("%s: device enable failed\n", 2369 sc->sc_dev.dv_xname); 2370 return (EIO); 2371 } 2372 } 2373 2374 sc->sc_enabled = 1; 2375 return (0); 2376 } 2377 2378 void 2379 fxp_disable(struct fxp_softc *sc) 2380 { 2381 2382 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2383 (*sc->sc_disable)(sc); 2384 sc->sc_enabled = 0; 2385 } 2386 } 2387 2388 /* 2389 * fxp_activate: 2390 * 2391 * Handle device activation/deactivation requests. 2392 */ 2393 int 2394 fxp_activate(struct device *self, enum devact act) 2395 { 2396 struct fxp_softc *sc = (void *) self; 2397 int s, error = 0; 2398 2399 s = splnet(); 2400 switch (act) { 2401 case DVACT_ACTIVATE: 2402 error = EOPNOTSUPP; 2403 break; 2404 2405 case DVACT_DEACTIVATE: 2406 if (sc->sc_flags & FXPF_MII) 2407 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2408 MII_OFFSET_ANY); 2409 if_deactivate(&sc->sc_ethercom.ec_if); 2410 break; 2411 } 2412 splx(s); 2413 2414 return (error); 2415 } 2416 2417 /* 2418 * fxp_detach: 2419 * 2420 * Detach an i82557 interface. 2421 */ 2422 int 2423 fxp_detach(struct fxp_softc *sc) 2424 { 2425 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2426 int i; 2427 2428 /* Succeed now if there's no work to do. */ 2429 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2430 return (0); 2431 2432 /* Unhook our tick handler. */ 2433 callout_stop(&sc->sc_callout); 2434 2435 if (sc->sc_flags & FXPF_MII) { 2436 /* Detach all PHYs */ 2437 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2438 } 2439 2440 /* Delete all remaining media. */ 2441 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2442 2443 #if NRND > 0 2444 rnd_detach_source(&sc->rnd_source); 2445 #endif 2446 ether_ifdetach(ifp); 2447 if_detach(ifp); 2448 2449 for (i = 0; i < FXP_NRFABUFS; i++) { 2450 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2451 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2452 } 2453 2454 for (i = 0; i < FXP_NTXCB; i++) { 2455 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2456 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2457 } 2458 2459 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2460 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2461 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2462 sizeof(struct fxp_control_data)); 2463 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2464 2465 shutdownhook_disestablish(sc->sc_sdhook); 2466 powerhook_disestablish(sc->sc_powerhook); 2467 2468 return (0); 2469 } 2470
Indexes created Mon Sep 29 21:09:56 GMT 2025