i82557.c revision 1.93
1 /* $NetBSD: i82557.c,v 1.93 2005/10/12 19:26:10 abs Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.93 2005/10/12 19:26:10 abs Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/syslog.h> 92 93 #include <machine/endian.h> 94 95 #include <uvm/uvm_extern.h> 96 97 #if NRND > 0 98 #include <sys/rnd.h> 99 #endif 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #if NBPFILTER > 0 107 #include <net/bpf.h> 108 #endif 109 110 #include <machine/bus.h> 111 #include <machine/intr.h> 112 113 #include <dev/mii/miivar.h> 114 115 #include <dev/ic/i82557reg.h> 116 #include <dev/ic/i82557var.h> 117 118 #include <dev/microcode/i8255x/rcvbundl.h> 119 120 /* 121 * NOTE! On the Alpha, we have an alignment constraint. The 122 * card DMAs the packet immediately following the RFA. However, 123 * the first thing in the packet is a 14-byte Ethernet header. 124 * This means that the packet is misaligned. To compensate, 125 * we actually offset the RFA 2 bytes into the cluster. This 126 * alignes the packet after the Ethernet header at a 32-bit 127 * boundary. HOWEVER! This means that the RFA is misaligned! 128 */ 129 #define RFA_ALIGNMENT_FUDGE 2 130 131 /* 132 * The configuration byte map has several undefined fields which 133 * must be one or must be zero. Set up a template for these bits 134 * only (assuming an i82557 chip), leaving the actual configuration 135 * for fxp_init(). 136 * 137 * See the definition of struct fxp_cb_config for the bit definitions. 138 */ 139 const u_int8_t fxp_cb_config_template[] = { 140 0x0, 0x0, /* cb_status */ 141 0x0, 0x0, /* cb_command */ 142 0x0, 0x0, 0x0, 0x0, /* link_addr */ 143 0x0, /* 0 */ 144 0x0, /* 1 */ 145 0x0, /* 2 */ 146 0x0, /* 3 */ 147 0x0, /* 4 */ 148 0x0, /* 5 */ 149 0x32, /* 6 */ 150 0x0, /* 7 */ 151 0x0, /* 8 */ 152 0x0, /* 9 */ 153 0x6, /* 10 */ 154 0x0, /* 11 */ 155 0x0, /* 12 */ 156 0x0, /* 13 */ 157 0xf2, /* 14 */ 158 0x48, /* 15 */ 159 0x0, /* 16 */ 160 0x40, /* 17 */ 161 0xf0, /* 18 */ 162 0x0, /* 19 */ 163 0x3f, /* 20 */ 164 0x5, /* 21 */ 165 0x0, /* 22 */ 166 0x0, /* 23 */ 167 0x0, /* 24 */ 168 0x0, /* 25 */ 169 0x0, /* 26 */ 170 0x0, /* 27 */ 171 0x0, /* 28 */ 172 0x0, /* 29 */ 173 0x0, /* 30 */ 174 0x0, /* 31 */ 175 }; 176 177 void fxp_mii_initmedia(struct fxp_softc *); 178 int fxp_mii_mediachange(struct ifnet *); 179 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 180 181 void fxp_80c24_initmedia(struct fxp_softc *); 182 int fxp_80c24_mediachange(struct ifnet *); 183 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 184 185 void fxp_start(struct ifnet *); 186 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 187 void fxp_watchdog(struct ifnet *); 188 int fxp_init(struct ifnet *); 189 void fxp_stop(struct ifnet *, int); 190 191 void fxp_txintr(struct fxp_softc *); 192 void fxp_rxintr(struct fxp_softc *); 193 194 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 195 196 void fxp_rxdrain(struct fxp_softc *); 197 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 198 int fxp_mdi_read(struct device *, int, int); 199 void fxp_statchg(struct device *); 200 void fxp_mdi_write(struct device *, int, int, int); 201 void fxp_autosize_eeprom(struct fxp_softc*); 202 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 204 void fxp_eeprom_update_cksum(struct fxp_softc *); 205 void fxp_get_info(struct fxp_softc *, u_int8_t *); 206 void fxp_tick(void *); 207 void fxp_mc_setup(struct fxp_softc *); 208 void fxp_load_ucode(struct fxp_softc *); 209 210 void fxp_shutdown(void *); 211 void fxp_power(int, void *); 212 213 int fxp_copy_small = 0; 214 215 /* 216 * Variables for interrupt mitigating microcode. 217 */ 218 int fxp_int_delay = 1000; /* usec */ 219 int fxp_bundle_max = 6; /* packets */ 220 221 struct fxp_phytype { 222 int fp_phy; /* type of PHY, -1 for MII at the end. */ 223 void (*fp_init)(struct fxp_softc *); 224 } fxp_phytype_table[] = { 225 { FXP_PHY_80C24, fxp_80c24_initmedia }, 226 { -1, fxp_mii_initmedia }, 227 }; 228 229 /* 230 * Set initial transmit threshold at 64 (512 bytes). This is 231 * increased by 64 (512 bytes) at a time, to maximum of 192 232 * (1536 bytes), if an underrun occurs. 233 */ 234 static int tx_threshold = 64; 235 236 /* 237 * Wait for the previous command to be accepted (but not necessarily 238 * completed). 239 */ 240 static __inline void 241 fxp_scb_wait(struct fxp_softc *sc) 242 { 243 int i = 10000; 244 245 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 246 delay(2); 247 if (i == 0) 248 log(LOG_WARNING, 249 "%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 250 } 251 252 /* 253 * Submit a command to the i82557. 254 */ 255 static __inline void 256 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 257 { 258 259 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 260 } 261 262 /* 263 * Finish attaching an i82557 interface. Called by bus-specific front-end. 264 */ 265 void 266 fxp_attach(struct fxp_softc *sc) 267 { 268 u_int8_t enaddr[ETHER_ADDR_LEN]; 269 struct ifnet *ifp; 270 bus_dma_segment_t seg; 271 int rseg, i, error; 272 struct fxp_phytype *fp; 273 274 callout_init(&sc->sc_callout); 275 276 /* 277 * Enable some good stuff on i82558 and later. 278 */ 279 if (sc->sc_rev >= FXP_REV_82558_A4) { 280 /* Enable the extended TxCB. */ 281 sc->sc_flags |= FXPF_EXT_TXCB; 282 } 283 284 /* 285 * Enable use of extended RFDs and TCBs for 82550 286 * and later chips. Note: we need extended TXCB support 287 * too, but that's already enabled by the code above. 288 * Be careful to do this only on the right devices. 289 */ 290 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 291 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 292 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 293 } else { 294 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 295 } 296 297 sc->sc_rfa_size = 298 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 299 300 /* 301 * Allocate the control data structures, and create and load the 302 * DMA map for it. 303 */ 304 if ((error = bus_dmamem_alloc(sc->sc_dmat, 305 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 306 0)) != 0) { 307 aprint_error( 308 "%s: unable to allocate control data, error = %d\n", 309 sc->sc_dev.dv_xname, error); 310 goto fail_0; 311 } 312 313 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 314 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 315 BUS_DMA_COHERENT)) != 0) { 316 aprint_error("%s: unable to map control data, error = %d\n", 317 sc->sc_dev.dv_xname, error); 318 goto fail_1; 319 } 320 sc->sc_cdseg = seg; 321 sc->sc_cdnseg = rseg; 322 323 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 324 325 if ((error = bus_dmamap_create(sc->sc_dmat, 326 sizeof(struct fxp_control_data), 1, 327 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 328 aprint_error("%s: unable to create control data DMA map, " 329 "error = %d\n", sc->sc_dev.dv_xname, error); 330 goto fail_2; 331 } 332 333 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 334 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 335 0)) != 0) { 336 aprint_error( 337 "%s: can't load control data DMA map, error = %d\n", 338 sc->sc_dev.dv_xname, error); 339 goto fail_3; 340 } 341 342 /* 343 * Create the transmit buffer DMA maps. 344 */ 345 for (i = 0; i < FXP_NTXCB; i++) { 346 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 347 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 348 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 349 aprint_error("%s: unable to create tx DMA map %d, " 350 "error = %d\n", sc->sc_dev.dv_xname, i, error); 351 goto fail_4; 352 } 353 } 354 355 /* 356 * Create the receive buffer DMA maps. 357 */ 358 for (i = 0; i < FXP_NRFABUFS; i++) { 359 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 360 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 361 aprint_error("%s: unable to create rx DMA map %d, " 362 "error = %d\n", sc->sc_dev.dv_xname, i, error); 363 goto fail_5; 364 } 365 } 366 367 /* Initialize MAC address and media structures. */ 368 fxp_get_info(sc, enaddr); 369 370 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 371 ether_sprintf(enaddr)); 372 373 ifp = &sc->sc_ethercom.ec_if; 374 375 /* 376 * Get info about our media interface, and initialize it. Note 377 * the table terminates itself with a phy of -1, indicating 378 * that we're using MII. 379 */ 380 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 381 if (fp->fp_phy == sc->phy_primary_device) 382 break; 383 (*fp->fp_init)(sc); 384 385 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 386 ifp->if_softc = sc; 387 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 388 ifp->if_ioctl = fxp_ioctl; 389 ifp->if_start = fxp_start; 390 ifp->if_watchdog = fxp_watchdog; 391 ifp->if_init = fxp_init; 392 ifp->if_stop = fxp_stop; 393 IFQ_SET_READY(&ifp->if_snd); 394 395 if (sc->sc_flags & FXPF_IPCB) { 396 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 397 /* 398 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 399 * at least, on i82550 rev.12. 400 * specifically, it doesn't calculate ipv4 checksum correctly 401 * when sending 20 byte ipv4 header + 1 or 2 byte data. 402 * FreeBSD driver has related comments. 403 */ 404 ifp->if_capabilities = 405 IFCAP_CSUM_IPv4_Rx | 406 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 407 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 408 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 409 } 410 411 /* 412 * We can support 802.1Q VLAN-sized frames. 413 */ 414 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 415 416 /* 417 * Attach the interface. 418 */ 419 if_attach(ifp); 420 ether_ifattach(ifp, enaddr); 421 #if NRND > 0 422 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 423 RND_TYPE_NET, 0); 424 #endif 425 426 #ifdef FXP_EVENT_COUNTERS 427 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 428 NULL, sc->sc_dev.dv_xname, "txstall"); 429 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 430 NULL, sc->sc_dev.dv_xname, "txintr"); 431 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 432 NULL, sc->sc_dev.dv_xname, "rxintr"); 433 if (sc->sc_rev >= FXP_REV_82558_A4) { 434 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 435 NULL, sc->sc_dev.dv_xname, "txpause"); 436 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 437 NULL, sc->sc_dev.dv_xname, "rxpause"); 438 } 439 #endif /* FXP_EVENT_COUNTERS */ 440 441 /* 442 * Add shutdown hook so that DMA is disabled prior to reboot. Not 443 * doing do could allow DMA to corrupt kernel memory during the 444 * reboot before the driver initializes. 445 */ 446 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 447 if (sc->sc_sdhook == NULL) 448 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 449 sc->sc_dev.dv_xname); 450 /* 451 * Add suspend hook, for similar reasons.. 452 */ 453 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 454 if (sc->sc_powerhook == NULL) 455 aprint_error("%s: WARNING: unable to establish power hook\n", 456 sc->sc_dev.dv_xname); 457 458 /* The attach is successful. */ 459 sc->sc_flags |= FXPF_ATTACHED; 460 461 return; 462 463 /* 464 * Free any resources we've allocated during the failed attach 465 * attempt. Do this in reverse order and fall though. 466 */ 467 fail_5: 468 for (i = 0; i < FXP_NRFABUFS; i++) { 469 if (sc->sc_rxmaps[i] != NULL) 470 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 471 } 472 fail_4: 473 for (i = 0; i < FXP_NTXCB; i++) { 474 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 475 bus_dmamap_destroy(sc->sc_dmat, 476 FXP_DSTX(sc, i)->txs_dmamap); 477 } 478 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 479 fail_3: 480 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 481 fail_2: 482 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 483 sizeof(struct fxp_control_data)); 484 fail_1: 485 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 486 fail_0: 487 return; 488 } 489 490 void 491 fxp_mii_initmedia(struct fxp_softc *sc) 492 { 493 int flags; 494 495 sc->sc_flags |= FXPF_MII; 496 497 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 498 sc->sc_mii.mii_readreg = fxp_mdi_read; 499 sc->sc_mii.mii_writereg = fxp_mdi_write; 500 sc->sc_mii.mii_statchg = fxp_statchg; 501 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 502 fxp_mii_mediastatus); 503 504 flags = MIIF_NOISOLATE; 505 if (sc->sc_rev >= FXP_REV_82558_A4) 506 flags |= MIIF_DOPAUSE; 507 /* 508 * The i82557 wedges if all of its PHYs are isolated! 509 */ 510 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 511 MII_OFFSET_ANY, flags); 512 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 513 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 514 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 515 } else 516 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 517 } 518 519 void 520 fxp_80c24_initmedia(struct fxp_softc *sc) 521 { 522 523 /* 524 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 525 * doesn't have a programming interface of any sort. The 526 * media is sensed automatically based on how the link partner 527 * is configured. This is, in essence, manual configuration. 528 */ 529 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 530 sc->sc_dev.dv_xname); 531 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 532 fxp_80c24_mediastatus); 533 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 534 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 535 } 536 537 /* 538 * Device shutdown routine. Called at system shutdown after sync. The 539 * main purpose of this routine is to shut off receiver DMA so that 540 * kernel memory doesn't get clobbered during warmboot. 541 */ 542 void 543 fxp_shutdown(void *arg) 544 { 545 struct fxp_softc *sc = arg; 546 547 /* 548 * Since the system's going to halt shortly, don't bother 549 * freeing mbufs. 550 */ 551 fxp_stop(&sc->sc_ethercom.ec_if, 0); 552 } 553 /* 554 * Power handler routine. Called when the system is transitioning 555 * into/out of power save modes. As with fxp_shutdown, the main 556 * purpose of this routine is to shut off receiver DMA so it doesn't 557 * clobber kernel memory at the wrong time. 558 */ 559 void 560 fxp_power(int why, void *arg) 561 { 562 struct fxp_softc *sc = arg; 563 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 564 int s; 565 566 s = splnet(); 567 switch (why) { 568 case PWR_SUSPEND: 569 case PWR_STANDBY: 570 fxp_stop(ifp, 0); 571 break; 572 case PWR_RESUME: 573 if (ifp->if_flags & IFF_UP) 574 fxp_init(ifp); 575 break; 576 case PWR_SOFTSUSPEND: 577 case PWR_SOFTSTANDBY: 578 case PWR_SOFTRESUME: 579 break; 580 } 581 splx(s); 582 } 583 584 /* 585 * Initialize the interface media. 586 */ 587 void 588 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 589 { 590 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 591 592 /* 593 * Reset to a stable state. 594 */ 595 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 596 DELAY(100); 597 598 sc->sc_eeprom_size = 0; 599 fxp_autosize_eeprom(sc); 600 if (sc->sc_eeprom_size == 0) { 601 aprint_error("%s: failed to detect EEPROM size\n", 602 sc->sc_dev.dv_xname); 603 sc->sc_eeprom_size = 6; /* XXX panic here? */ 604 } 605 #ifdef DEBUG 606 aprint_debug("%s: detected %d word EEPROM\n", 607 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 608 #endif 609 610 /* 611 * Get info about the primary PHY 612 */ 613 fxp_read_eeprom(sc, &data, 6, 1); 614 sc->phy_primary_device = 615 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 616 617 /* 618 * Read MAC address. 619 */ 620 fxp_read_eeprom(sc, myea, 0, 3); 621 enaddr[0] = myea[0] & 0xff; 622 enaddr[1] = myea[0] >> 8; 623 enaddr[2] = myea[1] & 0xff; 624 enaddr[3] = myea[1] >> 8; 625 enaddr[4] = myea[2] & 0xff; 626 enaddr[5] = myea[2] >> 8; 627 628 /* 629 * Systems based on the ICH2/ICH2-M chip from Intel, as well 630 * as some i82559 designs, have a defect where the chip can 631 * cause a PCI protocol violation if it receives a CU_RESUME 632 * command when it is entering the IDLE state. 633 * 634 * The work-around is to disable Dynamic Standby Mode, so that 635 * the chip never deasserts #CLKRUN, and always remains in the 636 * active state. 637 * 638 * Unfortunately, the only way to disable Dynamic Standby is 639 * to frob an EEPROM setting and reboot (the EEPROM setting 640 * is only consulted when the PCI bus comes out of reset). 641 * 642 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 643 */ 644 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 645 fxp_read_eeprom(sc, &data, 10, 1); 646 if (data & 0x02) { /* STB enable */ 647 aprint_error("%s: WARNING: " 648 "Disabling dynamic standby mode in EEPROM " 649 "to work around a\n", 650 sc->sc_dev.dv_xname); 651 aprint_normal( 652 "%s: WARNING: hardware bug. You must reset " 653 "the system before using this\n", 654 sc->sc_dev.dv_xname); 655 aprint_normal("%s: WARNING: interface.\n", 656 sc->sc_dev.dv_xname); 657 data &= ~0x02; 658 fxp_write_eeprom(sc, &data, 10, 1); 659 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 660 sc->sc_dev.dv_xname, data); 661 fxp_eeprom_update_cksum(sc); 662 } 663 } 664 665 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 666 /* Due to false positives we make it conditional on setting link1 */ 667 fxp_read_eeprom(sc, &data, 3, 1); 668 if ((data & 0x03) != 0x03) { 669 aprint_verbose("%s: May need receiver lock-up workaround\n", 670 sc->sc_dev.dv_xname); 671 } 672 } 673 674 static void 675 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 676 { 677 uint16_t reg; 678 int x; 679 680 for (x = 1 << (len - 1); x != 0; x >>= 1) { 681 DELAY(40); 682 if (data & x) 683 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 684 else 685 reg = FXP_EEPROM_EECS; 686 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 687 DELAY(40); 688 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 689 reg | FXP_EEPROM_EESK); 690 DELAY(40); 691 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 692 } 693 DELAY(40); 694 } 695 696 /* 697 * Figure out EEPROM size. 698 * 699 * 559's can have either 64-word or 256-word EEPROMs, the 558 700 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 701 * talks about the existence of 16 to 256 word EEPROMs. 702 * 703 * The only known sizes are 64 and 256, where the 256 version is used 704 * by CardBus cards to store CIS information. 705 * 706 * The address is shifted in msb-to-lsb, and after the last 707 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 708 * after which follows the actual data. We try to detect this zero, by 709 * probing the data-out bit in the EEPROM control register just after 710 * having shifted in a bit. If the bit is zero, we assume we've 711 * shifted enough address bits. The data-out should be tri-state, 712 * before this, which should translate to a logical one. 713 * 714 * Other ways to do this would be to try to read a register with known 715 * contents with a varying number of address bits, but no such 716 * register seem to be available. The high bits of register 10 are 01 717 * on the 558 and 559, but apparently not on the 557. 718 * 719 * The Linux driver computes a checksum on the EEPROM data, but the 720 * value of this checksum is not very well documented. 721 */ 722 723 void 724 fxp_autosize_eeprom(struct fxp_softc *sc) 725 { 726 int x; 727 728 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 729 DELAY(40); 730 731 /* Shift in read opcode. */ 732 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 733 734 /* 735 * Shift in address, wait for the dummy zero following a correct 736 * address shift. 737 */ 738 for (x = 1; x <= 8; x++) { 739 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 740 DELAY(40); 741 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 742 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 743 DELAY(40); 744 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 745 FXP_EEPROM_EEDO) == 0) 746 break; 747 DELAY(40); 748 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 749 DELAY(40); 750 } 751 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 752 DELAY(40); 753 if (x != 6 && x != 8) { 754 #ifdef DEBUG 755 printf("%s: strange EEPROM size (%d)\n", 756 sc->sc_dev.dv_xname, 1 << x); 757 #endif 758 } else 759 sc->sc_eeprom_size = x; 760 } 761 762 /* 763 * Read from the serial EEPROM. Basically, you manually shift in 764 * the read opcode (one bit at a time) and then shift in the address, 765 * and then you shift out the data (all of this one bit at a time). 766 * The word size is 16 bits, so you have to provide the address for 767 * every 16 bits of data. 768 */ 769 void 770 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 771 { 772 u_int16_t reg; 773 int i, x; 774 775 for (i = 0; i < words; i++) { 776 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 777 778 /* Shift in read opcode. */ 779 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 780 781 /* Shift in address. */ 782 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 783 784 reg = FXP_EEPROM_EECS; 785 data[i] = 0; 786 787 /* Shift out data. */ 788 for (x = 16; x > 0; x--) { 789 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 790 reg | FXP_EEPROM_EESK); 791 DELAY(40); 792 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 793 FXP_EEPROM_EEDO) 794 data[i] |= (1 << (x - 1)); 795 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 796 DELAY(40); 797 } 798 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 799 DELAY(40); 800 } 801 } 802 803 /* 804 * Write data to the serial EEPROM. 805 */ 806 void 807 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 808 { 809 int i, j; 810 811 for (i = 0; i < words; i++) { 812 /* Erase/write enable. */ 813 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 814 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 815 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 816 sc->sc_eeprom_size); 817 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 818 DELAY(4); 819 820 /* Shift in write opcode, address, data. */ 821 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 822 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 823 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 824 fxp_eeprom_shiftin(sc, data[i], 16); 825 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 826 DELAY(4); 827 828 /* Wait for the EEPROM to finish up. */ 829 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 830 DELAY(4); 831 for (j = 0; j < 1000; j++) { 832 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 833 FXP_EEPROM_EEDO) 834 break; 835 DELAY(50); 836 } 837 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 838 DELAY(4); 839 840 /* Erase/write disable. */ 841 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 842 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 843 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 844 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 845 DELAY(4); 846 } 847 } 848 849 /* 850 * Update the checksum of the EEPROM. 851 */ 852 void 853 fxp_eeprom_update_cksum(struct fxp_softc *sc) 854 { 855 int i; 856 uint16_t data, cksum; 857 858 cksum = 0; 859 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 860 fxp_read_eeprom(sc, &data, i, 1); 861 cksum += data; 862 } 863 i = (1 << sc->sc_eeprom_size) - 1; 864 cksum = 0xbaba - cksum; 865 fxp_read_eeprom(sc, &data, i, 1); 866 fxp_write_eeprom(sc, &cksum, i, 1); 867 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 868 sc->sc_dev.dv_xname, i, data, cksum); 869 } 870 871 /* 872 * Start packet transmission on the interface. 873 */ 874 void 875 fxp_start(struct ifnet *ifp) 876 { 877 struct fxp_softc *sc = ifp->if_softc; 878 struct mbuf *m0, *m; 879 struct fxp_txdesc *txd; 880 struct fxp_txsoft *txs; 881 bus_dmamap_t dmamap; 882 int error, lasttx, nexttx, opending, seg; 883 884 /* 885 * If we want a re-init, bail out now. 886 */ 887 if (sc->sc_flags & FXPF_WANTINIT) { 888 ifp->if_flags |= IFF_OACTIVE; 889 return; 890 } 891 892 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 893 return; 894 895 /* 896 * Remember the previous txpending and the current lasttx. 897 */ 898 opending = sc->sc_txpending; 899 lasttx = sc->sc_txlast; 900 901 /* 902 * Loop through the send queue, setting up transmit descriptors 903 * until we drain the queue, or use up all available transmit 904 * descriptors. 905 */ 906 for (;;) { 907 struct fxp_tbd *tbdp; 908 int csum_flags; 909 910 /* 911 * Grab a packet off the queue. 912 */ 913 IFQ_POLL(&ifp->if_snd, m0); 914 if (m0 == NULL) 915 break; 916 m = NULL; 917 918 if (sc->sc_txpending == FXP_NTXCB) { 919 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 920 break; 921 } 922 923 /* 924 * Get the next available transmit descriptor. 925 */ 926 nexttx = FXP_NEXTTX(sc->sc_txlast); 927 txd = FXP_CDTX(sc, nexttx); 928 txs = FXP_DSTX(sc, nexttx); 929 dmamap = txs->txs_dmamap; 930 931 /* 932 * Load the DMA map. If this fails, the packet either 933 * didn't fit in the allotted number of frags, or we were 934 * short on resources. In this case, we'll copy and try 935 * again. 936 */ 937 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 938 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 939 MGETHDR(m, M_DONTWAIT, MT_DATA); 940 if (m == NULL) { 941 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 942 sc->sc_dev.dv_xname); 943 break; 944 } 945 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 946 if (m0->m_pkthdr.len > MHLEN) { 947 MCLGET(m, M_DONTWAIT); 948 if ((m->m_flags & M_EXT) == 0) { 949 log(LOG_ERR, 950 "%s: unable to allocate Tx " 951 "cluster\n", sc->sc_dev.dv_xname); 952 m_freem(m); 953 break; 954 } 955 } 956 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 957 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 958 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 959 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 960 if (error) { 961 log(LOG_ERR, "%s: unable to load Tx buffer, " 962 "error = %d\n", sc->sc_dev.dv_xname, error); 963 break; 964 } 965 } 966 967 IFQ_DEQUEUE(&ifp->if_snd, m0); 968 csum_flags = m0->m_pkthdr.csum_flags; 969 if (m != NULL) { 970 m_freem(m0); 971 m0 = m; 972 } 973 974 /* Initialize the fraglist. */ 975 tbdp = txd->txd_tbd; 976 if (sc->sc_flags & FXPF_IPCB) 977 tbdp++; 978 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 979 tbdp[seg].tb_addr = 980 htole32(dmamap->dm_segs[seg].ds_addr); 981 tbdp[seg].tb_size = 982 htole32(dmamap->dm_segs[seg].ds_len); 983 } 984 985 /* Sync the DMA map. */ 986 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 987 BUS_DMASYNC_PREWRITE); 988 989 /* 990 * Store a pointer to the packet so we can free it later. 991 */ 992 txs->txs_mbuf = m0; 993 994 /* 995 * Initialize the transmit descriptor. 996 */ 997 /* BIG_ENDIAN: no need to swap to store 0 */ 998 txd->txd_txcb.cb_status = 0; 999 txd->txd_txcb.cb_command = 1000 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 1001 txd->txd_txcb.tx_threshold = tx_threshold; 1002 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 1003 1004 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 1005 if (sc->sc_flags & FXPF_IPCB) { 1006 struct fxp_ipcb *ipcb; 1007 /* 1008 * Deal with TCP/IP checksum offload. Note that 1009 * in order for TCP checksum offload to work, 1010 * the pseudo header checksum must have already 1011 * been computed and stored in the checksum field 1012 * in the TCP header. The stack should have 1013 * already done this for us. 1014 */ 1015 ipcb = &txd->txd_u.txdu_ipcb; 1016 memset(ipcb, 0, sizeof(*ipcb)); 1017 /* 1018 * always do hardware parsing. 1019 */ 1020 ipcb->ipcb_ip_activation_high = 1021 FXP_IPCB_HARDWAREPARSING_ENABLE; 1022 /* 1023 * ip checksum offloading. 1024 */ 1025 if (csum_flags & M_CSUM_IPv4) { 1026 ipcb->ipcb_ip_schedule |= 1027 FXP_IPCB_IP_CHECKSUM_ENABLE; 1028 } 1029 /* 1030 * TCP/UDP checksum offloading. 1031 */ 1032 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1033 ipcb->ipcb_ip_schedule |= 1034 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1035 } 1036 1037 /* 1038 * request VLAN tag insertion if needed. 1039 */ 1040 if (sc->sc_ethercom.ec_nvlans != 0) { 1041 struct m_tag *vtag; 1042 1043 vtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL); 1044 if (vtag) { 1045 ipcb->ipcb_vlan_id = 1046 htobe16(*(u_int *)(vtag + 1)); 1047 ipcb->ipcb_ip_activation_high |= 1048 FXP_IPCB_INSERTVLAN_ENABLE; 1049 } 1050 } 1051 } else { 1052 KASSERT((csum_flags & 1053 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1054 } 1055 1056 FXP_CDTXSYNC(sc, nexttx, 1057 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1058 1059 /* Advance the tx pointer. */ 1060 sc->sc_txpending++; 1061 sc->sc_txlast = nexttx; 1062 1063 #if NBPFILTER > 0 1064 /* 1065 * Pass packet to bpf if there is a listener. 1066 */ 1067 if (ifp->if_bpf) 1068 bpf_mtap(ifp->if_bpf, m0); 1069 #endif 1070 } 1071 1072 if (sc->sc_txpending == FXP_NTXCB) { 1073 /* No more slots; notify upper layer. */ 1074 ifp->if_flags |= IFF_OACTIVE; 1075 } 1076 1077 if (sc->sc_txpending != opending) { 1078 /* 1079 * We enqueued packets. If the transmitter was idle, 1080 * reset the txdirty pointer. 1081 */ 1082 if (opending == 0) 1083 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1084 1085 /* 1086 * Cause the chip to interrupt and suspend command 1087 * processing once the last packet we've enqueued 1088 * has been transmitted. 1089 */ 1090 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 1091 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1092 FXP_CDTXSYNC(sc, sc->sc_txlast, 1093 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1094 1095 /* 1096 * The entire packet chain is set up. Clear the suspend bit 1097 * on the command prior to the first packet we set up. 1098 */ 1099 FXP_CDTXSYNC(sc, lasttx, 1100 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1101 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1102 htole16(~FXP_CB_COMMAND_S); 1103 FXP_CDTXSYNC(sc, lasttx, 1104 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1105 1106 /* 1107 * Issue a Resume command in case the chip was suspended. 1108 */ 1109 fxp_scb_wait(sc); 1110 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1111 1112 /* Set a watchdog timer in case the chip flakes out. */ 1113 ifp->if_timer = 5; 1114 } 1115 } 1116 1117 /* 1118 * Process interface interrupts. 1119 */ 1120 int 1121 fxp_intr(void *arg) 1122 { 1123 struct fxp_softc *sc = arg; 1124 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1125 bus_dmamap_t rxmap; 1126 int claimed = 0; 1127 u_int8_t statack; 1128 1129 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0 || sc->sc_enabled == 0) 1130 return (0); 1131 /* 1132 * If the interface isn't running, don't try to 1133 * service the interrupt.. just ack it and bail. 1134 */ 1135 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1136 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1137 if (statack) { 1138 claimed = 1; 1139 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1140 } 1141 return (claimed); 1142 } 1143 1144 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1145 claimed = 1; 1146 1147 /* 1148 * First ACK all the interrupts in this pass. 1149 */ 1150 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1151 1152 /* 1153 * Process receiver interrupts. If a no-resource (RNR) 1154 * condition exists, get whatever packets we can and 1155 * re-start the receiver. 1156 */ 1157 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1158 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1159 fxp_rxintr(sc); 1160 } 1161 1162 if (statack & FXP_SCB_STATACK_RNR) { 1163 fxp_scb_wait(sc); 1164 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1165 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1166 fxp_scb_wait(sc); 1167 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1168 rxmap->dm_segs[0].ds_addr + 1169 RFA_ALIGNMENT_FUDGE); 1170 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1171 } 1172 1173 /* 1174 * Free any finished transmit mbuf chains. 1175 */ 1176 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1177 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1178 fxp_txintr(sc); 1179 1180 /* 1181 * Try to get more packets going. 1182 */ 1183 fxp_start(ifp); 1184 1185 if (sc->sc_txpending == 0) { 1186 /* 1187 * If we want a re-init, do that now. 1188 */ 1189 if (sc->sc_flags & FXPF_WANTINIT) 1190 (void) fxp_init(ifp); 1191 } 1192 } 1193 } 1194 1195 #if NRND > 0 1196 if (claimed) 1197 rnd_add_uint32(&sc->rnd_source, statack); 1198 #endif 1199 return (claimed); 1200 } 1201 1202 /* 1203 * Handle transmit completion interrupts. 1204 */ 1205 void 1206 fxp_txintr(struct fxp_softc *sc) 1207 { 1208 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1209 struct fxp_txdesc *txd; 1210 struct fxp_txsoft *txs; 1211 int i; 1212 u_int16_t txstat; 1213 1214 ifp->if_flags &= ~IFF_OACTIVE; 1215 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1216 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1217 txd = FXP_CDTX(sc, i); 1218 txs = FXP_DSTX(sc, i); 1219 1220 FXP_CDTXSYNC(sc, i, 1221 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1222 1223 txstat = le16toh(txd->txd_txcb.cb_status); 1224 1225 if ((txstat & FXP_CB_STATUS_C) == 0) 1226 break; 1227 1228 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1229 0, txs->txs_dmamap->dm_mapsize, 1230 BUS_DMASYNC_POSTWRITE); 1231 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1232 m_freem(txs->txs_mbuf); 1233 txs->txs_mbuf = NULL; 1234 } 1235 1236 /* Update the dirty transmit buffer pointer. */ 1237 sc->sc_txdirty = i; 1238 1239 /* 1240 * Cancel the watchdog timer if there are no pending 1241 * transmissions. 1242 */ 1243 if (sc->sc_txpending == 0) 1244 ifp->if_timer = 0; 1245 } 1246 1247 /* 1248 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1249 */ 1250 1251 int 1252 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1253 { 1254 u_int16_t rxparsestat; 1255 u_int16_t csum_stat; 1256 u_int32_t csum_data; 1257 int csum_flags; 1258 1259 /* 1260 * check VLAN tag stripping. 1261 */ 1262 1263 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1264 struct m_tag *vtag; 1265 1266 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1267 if (vtag == NULL) 1268 return ENOMEM; 1269 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1270 m_tag_prepend(m, vtag); 1271 } 1272 1273 /* 1274 * check H/W Checksumming. 1275 */ 1276 1277 csum_stat = le16toh(rfa->cksum_stat); 1278 rxparsestat = le16toh(rfa->rx_parse_stat); 1279 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1280 return 0; 1281 1282 csum_flags = 0; 1283 csum_data = 0; 1284 1285 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1286 csum_flags = M_CSUM_IPv4; 1287 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1288 csum_flags |= M_CSUM_IPv4_BAD; 1289 } 1290 1291 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1292 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1293 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1294 csum_flags |= M_CSUM_TCP_UDP_BAD; 1295 } 1296 1297 m->m_pkthdr.csum_flags = csum_flags; 1298 m->m_pkthdr.csum_data = csum_data; 1299 1300 return 0; 1301 } 1302 1303 /* 1304 * Handle receive interrupts. 1305 */ 1306 void 1307 fxp_rxintr(struct fxp_softc *sc) 1308 { 1309 struct ethercom *ec = &sc->sc_ethercom; 1310 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1311 struct mbuf *m, *m0; 1312 bus_dmamap_t rxmap; 1313 struct fxp_rfa *rfa; 1314 u_int16_t len, rxstat; 1315 1316 for (;;) { 1317 m = sc->sc_rxq.ifq_head; 1318 rfa = FXP_MTORFA(m); 1319 rxmap = M_GETCTX(m, bus_dmamap_t); 1320 1321 FXP_RFASYNC(sc, m, 1322 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1323 1324 rxstat = le16toh(rfa->rfa_status); 1325 1326 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1327 /* 1328 * We have processed all of the 1329 * receive buffers. 1330 */ 1331 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1332 return; 1333 } 1334 1335 IF_DEQUEUE(&sc->sc_rxq, m); 1336 1337 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1338 1339 len = le16toh(rfa->actual_size) & 1340 (m->m_ext.ext_size - 1); 1341 1342 if (len < sizeof(struct ether_header)) { 1343 /* 1344 * Runt packet; drop it now. 1345 */ 1346 FXP_INIT_RFABUF(sc, m); 1347 continue; 1348 } 1349 1350 /* 1351 * If support for 802.1Q VLAN sized frames is 1352 * enabled, we need to do some additional error 1353 * checking (as we are saving bad frames, in 1354 * order to receive the larger ones). 1355 */ 1356 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1357 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1358 FXP_RFA_STATUS_RNR| 1359 FXP_RFA_STATUS_ALIGN| 1360 FXP_RFA_STATUS_CRC)) != 0) { 1361 FXP_INIT_RFABUF(sc, m); 1362 continue; 1363 } 1364 1365 /* Do checksum checking. */ 1366 m->m_pkthdr.csum_flags = 0; 1367 if (sc->sc_flags & FXPF_EXT_RFA) 1368 if (fxp_rx_hwcksum(m, rfa)) 1369 goto dropit; 1370 1371 /* 1372 * If the packet is small enough to fit in a 1373 * single header mbuf, allocate one and copy 1374 * the data into it. This greatly reduces 1375 * memory consumption when we receive lots 1376 * of small packets. 1377 * 1378 * Otherwise, we add a new buffer to the receive 1379 * chain. If this fails, we drop the packet and 1380 * recycle the old buffer. 1381 */ 1382 if (fxp_copy_small != 0 && len <= MHLEN) { 1383 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1384 if (m0 == NULL) 1385 goto dropit; 1386 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1387 memcpy(mtod(m0, caddr_t), 1388 mtod(m, caddr_t), len); 1389 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1390 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1391 FXP_INIT_RFABUF(sc, m); 1392 m = m0; 1393 } else { 1394 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1395 dropit: 1396 ifp->if_ierrors++; 1397 FXP_INIT_RFABUF(sc, m); 1398 continue; 1399 } 1400 } 1401 1402 m->m_pkthdr.rcvif = ifp; 1403 m->m_pkthdr.len = m->m_len = len; 1404 1405 #if NBPFILTER > 0 1406 /* 1407 * Pass this up to any BPF listeners, but only 1408 * pass it up the stack it its for us. 1409 */ 1410 if (ifp->if_bpf) 1411 bpf_mtap(ifp->if_bpf, m); 1412 #endif 1413 1414 /* Pass it on. */ 1415 (*ifp->if_input)(ifp, m); 1416 } 1417 } 1418 1419 /* 1420 * Update packet in/out/collision statistics. The i82557 doesn't 1421 * allow you to access these counters without doing a fairly 1422 * expensive DMA to get _all_ of the statistics it maintains, so 1423 * we do this operation here only once per second. The statistics 1424 * counters in the kernel are updated from the previous dump-stats 1425 * DMA and then a new dump-stats DMA is started. The on-chip 1426 * counters are zeroed when the DMA completes. If we can't start 1427 * the DMA immediately, we don't wait - we just prepare to read 1428 * them again next time. 1429 */ 1430 void 1431 fxp_tick(void *arg) 1432 { 1433 struct fxp_softc *sc = arg; 1434 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1435 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1436 int s; 1437 1438 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1439 return; 1440 1441 s = splnet(); 1442 1443 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1444 1445 ifp->if_opackets += le32toh(sp->tx_good); 1446 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1447 if (sp->rx_good) { 1448 ifp->if_ipackets += le32toh(sp->rx_good); 1449 sc->sc_rxidle = 0; 1450 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1451 sc->sc_rxidle++; 1452 } 1453 ifp->if_ierrors += 1454 le32toh(sp->rx_crc_errors) + 1455 le32toh(sp->rx_alignment_errors) + 1456 le32toh(sp->rx_rnr_errors) + 1457 le32toh(sp->rx_overrun_errors); 1458 /* 1459 * If any transmit underruns occurred, bump up the transmit 1460 * threshold by another 512 bytes (64 * 8). 1461 */ 1462 if (sp->tx_underruns) { 1463 ifp->if_oerrors += le32toh(sp->tx_underruns); 1464 if (tx_threshold < 192) 1465 tx_threshold += 64; 1466 } 1467 #ifdef FXP_EVENT_COUNTERS 1468 if (sc->sc_rev >= FXP_REV_82558_A4) { 1469 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1470 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1471 } 1472 #endif 1473 1474 /* 1475 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1476 * then assume the receiver has locked up and attempt to clear 1477 * the condition by reprogramming the multicast filter (actually, 1478 * resetting the interface). This is a work-around for a bug in 1479 * the 82557 where the receiver locks up if it gets certain types 1480 * of garbage in the synchronization bits prior to the packet header. 1481 * This bug is supposed to only occur in 10Mbps mode, but has been 1482 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1483 * speed transition). 1484 */ 1485 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1486 (void) fxp_init(ifp); 1487 splx(s); 1488 return; 1489 } 1490 /* 1491 * If there is no pending command, start another stats 1492 * dump. Otherwise punt for now. 1493 */ 1494 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1495 /* 1496 * Start another stats dump. 1497 */ 1498 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1499 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1500 } else { 1501 /* 1502 * A previous command is still waiting to be accepted. 1503 * Just zero our copy of the stats and wait for the 1504 * next timer event to update them. 1505 */ 1506 /* BIG_ENDIAN: no swap required to store 0 */ 1507 sp->tx_good = 0; 1508 sp->tx_underruns = 0; 1509 sp->tx_total_collisions = 0; 1510 1511 sp->rx_good = 0; 1512 sp->rx_crc_errors = 0; 1513 sp->rx_alignment_errors = 0; 1514 sp->rx_rnr_errors = 0; 1515 sp->rx_overrun_errors = 0; 1516 if (sc->sc_rev >= FXP_REV_82558_A4) { 1517 sp->tx_pauseframes = 0; 1518 sp->rx_pauseframes = 0; 1519 } 1520 } 1521 1522 if (sc->sc_flags & FXPF_MII) { 1523 /* Tick the MII clock. */ 1524 mii_tick(&sc->sc_mii); 1525 } 1526 1527 splx(s); 1528 1529 /* 1530 * Schedule another timeout one second from now. 1531 */ 1532 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1533 } 1534 1535 /* 1536 * Drain the receive queue. 1537 */ 1538 void 1539 fxp_rxdrain(struct fxp_softc *sc) 1540 { 1541 bus_dmamap_t rxmap; 1542 struct mbuf *m; 1543 1544 for (;;) { 1545 IF_DEQUEUE(&sc->sc_rxq, m); 1546 if (m == NULL) 1547 break; 1548 rxmap = M_GETCTX(m, bus_dmamap_t); 1549 bus_dmamap_unload(sc->sc_dmat, rxmap); 1550 FXP_RXMAP_PUT(sc, rxmap); 1551 m_freem(m); 1552 } 1553 } 1554 1555 /* 1556 * Stop the interface. Cancels the statistics updater and resets 1557 * the interface. 1558 */ 1559 void 1560 fxp_stop(struct ifnet *ifp, int disable) 1561 { 1562 struct fxp_softc *sc = ifp->if_softc; 1563 struct fxp_txsoft *txs; 1564 int i; 1565 1566 /* 1567 * Turn down interface (done early to avoid bad interactions 1568 * between panics, shutdown hooks, and the watchdog timer) 1569 */ 1570 ifp->if_timer = 0; 1571 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1572 1573 /* 1574 * Cancel stats updater. 1575 */ 1576 callout_stop(&sc->sc_callout); 1577 if (sc->sc_flags & FXPF_MII) { 1578 /* Down the MII. */ 1579 mii_down(&sc->sc_mii); 1580 } 1581 1582 /* 1583 * Issue software reset. This unloads any microcode that 1584 * might already be loaded. 1585 */ 1586 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1587 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1588 DELAY(50); 1589 1590 /* 1591 * Release any xmit buffers. 1592 */ 1593 for (i = 0; i < FXP_NTXCB; i++) { 1594 txs = FXP_DSTX(sc, i); 1595 if (txs->txs_mbuf != NULL) { 1596 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1597 m_freem(txs->txs_mbuf); 1598 txs->txs_mbuf = NULL; 1599 } 1600 } 1601 sc->sc_txpending = 0; 1602 1603 if (disable) { 1604 fxp_rxdrain(sc); 1605 fxp_disable(sc); 1606 } 1607 1608 } 1609 1610 /* 1611 * Watchdog/transmission transmit timeout handler. Called when a 1612 * transmission is started on the interface, but no interrupt is 1613 * received before the timeout. This usually indicates that the 1614 * card has wedged for some reason. 1615 */ 1616 void 1617 fxp_watchdog(struct ifnet *ifp) 1618 { 1619 struct fxp_softc *sc = ifp->if_softc; 1620 1621 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1622 ifp->if_oerrors++; 1623 1624 (void) fxp_init(ifp); 1625 } 1626 1627 /* 1628 * Initialize the interface. Must be called at splnet(). 1629 */ 1630 int 1631 fxp_init(struct ifnet *ifp) 1632 { 1633 struct fxp_softc *sc = ifp->if_softc; 1634 struct fxp_cb_config *cbp; 1635 struct fxp_cb_ias *cb_ias; 1636 struct fxp_txdesc *txd; 1637 bus_dmamap_t rxmap; 1638 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1639 1640 if ((error = fxp_enable(sc)) != 0) 1641 goto out; 1642 1643 /* 1644 * Cancel any pending I/O 1645 */ 1646 fxp_stop(ifp, 0); 1647 1648 /* 1649 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1650 * flag, and this prevents the MII from detaching resulting in 1651 * a panic. The flags field should perhaps be split in runtime 1652 * flags and more static information. For now, just clear the 1653 * only other flag set. 1654 */ 1655 1656 sc->sc_flags &= ~FXPF_WANTINIT; 1657 1658 /* 1659 * Initialize base of CBL and RFA memory. Loading with zero 1660 * sets it up for regular linear addressing. 1661 */ 1662 fxp_scb_wait(sc); 1663 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1664 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1665 1666 fxp_scb_wait(sc); 1667 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1668 1669 /* 1670 * Initialize the multicast filter. Do this now, since we might 1671 * have to setup the config block differently. 1672 */ 1673 fxp_mc_setup(sc); 1674 1675 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1676 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1677 1678 /* 1679 * In order to support receiving 802.1Q VLAN frames, we have to 1680 * enable "save bad frames", since they are 4 bytes larger than 1681 * the normal Ethernet maximum frame length. On i82558 and later, 1682 * we have a better mechanism for this. 1683 */ 1684 save_bf = 0; 1685 lrxen = 0; 1686 vlan_drop = 0; 1687 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1688 if (sc->sc_rev < FXP_REV_82558_A4) 1689 save_bf = 1; 1690 else 1691 lrxen = 1; 1692 if (sc->sc_rev >= FXP_REV_82550) 1693 vlan_drop = 1; 1694 } 1695 1696 /* 1697 * Initialize base of dump-stats buffer. 1698 */ 1699 fxp_scb_wait(sc); 1700 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1701 sc->sc_cddma + FXP_CDSTATSOFF); 1702 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1703 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1704 1705 cbp = &sc->sc_control_data->fcd_configcb; 1706 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1707 1708 /* 1709 * Load microcode for this controller. 1710 */ 1711 fxp_load_ucode(sc); 1712 1713 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1714 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1715 else 1716 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1717 1718 /* 1719 * This copy is kind of disgusting, but there are a bunch of must be 1720 * zero and must be one bits in this structure and this is the easiest 1721 * way to initialize them all to proper values. 1722 */ 1723 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1724 1725 /* BIG_ENDIAN: no need to swap to store 0 */ 1726 cbp->cb_status = 0; 1727 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1728 FXP_CB_COMMAND_EL); 1729 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1730 cbp->link_addr = 0xffffffff; /* (no) next command */ 1731 /* bytes in config block */ 1732 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1733 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1734 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1735 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1736 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1737 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1738 cbp->type_enable = 0; /* actually reserved */ 1739 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1740 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1741 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1742 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1743 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1744 cbp->late_scb = 0; /* (don't) defer SCB update */ 1745 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1746 cbp->ci_int = 1; /* interrupt on CU idle */ 1747 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1748 cbp->ext_stats_dis = 1; /* disable extended counters */ 1749 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1750 cbp->save_bf = save_bf;/* save bad frames */ 1751 cbp->disc_short_rx = !prm; /* discard short packets */ 1752 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1753 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1754 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1755 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1756 /* interface mode */ 1757 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1758 cbp->csma_dis = 0; /* (don't) disable link */ 1759 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1760 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1761 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1762 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1763 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1764 cbp->nsai = 1; /* (don't) disable source addr insert */ 1765 cbp->preamble_length = 2; /* (7 byte) preamble */ 1766 cbp->loopback = 0; /* (don't) loopback */ 1767 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1768 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1769 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1770 cbp->promiscuous = prm; /* promiscuous mode */ 1771 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1772 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1773 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1774 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1775 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1776 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1777 cbp->padding = 1; /* (do) pad short tx packets */ 1778 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1779 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1780 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1781 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1782 /* must set wake_en in PMCSR also */ 1783 cbp->force_fdx = 0; /* (don't) force full duplex */ 1784 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1785 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1786 cbp->mc_all = allm; /* accept all multicasts */ 1787 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1788 cbp->vlan_drop_en = vlan_drop; 1789 1790 if (sc->sc_rev < FXP_REV_82558_A4) { 1791 /* 1792 * The i82557 has no hardware flow control, the values 1793 * here are the defaults for the chip. 1794 */ 1795 cbp->fc_delay_lsb = 0; 1796 cbp->fc_delay_msb = 0x40; 1797 cbp->pri_fc_thresh = 3; 1798 cbp->tx_fc_dis = 0; 1799 cbp->rx_fc_restop = 0; 1800 cbp->rx_fc_restart = 0; 1801 cbp->fc_filter = 0; 1802 cbp->pri_fc_loc = 1; 1803 } else { 1804 cbp->fc_delay_lsb = 0x1f; 1805 cbp->fc_delay_msb = 0x01; 1806 cbp->pri_fc_thresh = 3; 1807 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1808 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1809 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1810 cbp->fc_filter = !prm; /* drop FC frames to host */ 1811 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1812 cbp->ext_stats_dis = 0; /* enable extended stats */ 1813 } 1814 1815 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1816 1817 /* 1818 * Start the config command/DMA. 1819 */ 1820 fxp_scb_wait(sc); 1821 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1822 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1823 /* ...and wait for it to complete. */ 1824 i = 1000; 1825 do { 1826 FXP_CDCONFIGSYNC(sc, 1827 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1828 DELAY(1); 1829 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1830 if (i == 0) { 1831 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1832 sc->sc_dev.dv_xname, __LINE__); 1833 return (ETIMEDOUT); 1834 } 1835 1836 /* 1837 * Initialize the station address. 1838 */ 1839 cb_ias = &sc->sc_control_data->fcd_iascb; 1840 /* BIG_ENDIAN: no need to swap to store 0 */ 1841 cb_ias->cb_status = 0; 1842 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1843 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1844 cb_ias->link_addr = 0xffffffff; 1845 memcpy(cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1846 1847 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1848 1849 /* 1850 * Start the IAS (Individual Address Setup) command/DMA. 1851 */ 1852 fxp_scb_wait(sc); 1853 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1854 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1855 /* ...and wait for it to complete. */ 1856 i = 1000; 1857 do { 1858 FXP_CDIASSYNC(sc, 1859 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1860 DELAY(1); 1861 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1862 if (i == 0) { 1863 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1864 sc->sc_dev.dv_xname, __LINE__); 1865 return (ETIMEDOUT); 1866 } 1867 1868 /* 1869 * Initialize the transmit descriptor ring. txlast is initialized 1870 * to the end of the list so that it will wrap around to the first 1871 * descriptor when the first packet is transmitted. 1872 */ 1873 for (i = 0; i < FXP_NTXCB; i++) { 1874 txd = FXP_CDTX(sc, i); 1875 memset(txd, 0, sizeof(*txd)); 1876 txd->txd_txcb.cb_command = 1877 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1878 txd->txd_txcb.link_addr = 1879 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1880 if (sc->sc_flags & FXPF_EXT_TXCB) 1881 txd->txd_txcb.tbd_array_addr = 1882 htole32(FXP_CDTBDADDR(sc, i) + 1883 (2 * sizeof(struct fxp_tbd))); 1884 else 1885 txd->txd_txcb.tbd_array_addr = 1886 htole32(FXP_CDTBDADDR(sc, i)); 1887 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1888 } 1889 sc->sc_txpending = 0; 1890 sc->sc_txdirty = 0; 1891 sc->sc_txlast = FXP_NTXCB - 1; 1892 1893 /* 1894 * Initialize the receive buffer list. 1895 */ 1896 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1897 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1898 rxmap = FXP_RXMAP_GET(sc); 1899 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1900 log(LOG_ERR, "%s: unable to allocate or map rx " 1901 "buffer %d, error = %d\n", 1902 sc->sc_dev.dv_xname, 1903 sc->sc_rxq.ifq_len, error); 1904 /* 1905 * XXX Should attempt to run with fewer receive 1906 * XXX buffers instead of just failing. 1907 */ 1908 FXP_RXMAP_PUT(sc, rxmap); 1909 fxp_rxdrain(sc); 1910 goto out; 1911 } 1912 } 1913 sc->sc_rxidle = 0; 1914 1915 /* 1916 * Give the transmit ring to the chip. We do this by pointing 1917 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1918 * issuing a start command. It will execute the NOP and then 1919 * suspend, pointing at the first descriptor. 1920 */ 1921 fxp_scb_wait(sc); 1922 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1923 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1924 1925 /* 1926 * Initialize receiver buffer area - RFA. 1927 */ 1928 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1929 fxp_scb_wait(sc); 1930 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1931 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1932 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1933 1934 if (sc->sc_flags & FXPF_MII) { 1935 /* 1936 * Set current media. 1937 */ 1938 mii_mediachg(&sc->sc_mii); 1939 } 1940 1941 /* 1942 * ...all done! 1943 */ 1944 ifp->if_flags |= IFF_RUNNING; 1945 ifp->if_flags &= ~IFF_OACTIVE; 1946 1947 /* 1948 * Start the one second timer. 1949 */ 1950 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1951 1952 /* 1953 * Attempt to start output on the interface. 1954 */ 1955 fxp_start(ifp); 1956 1957 out: 1958 if (error) { 1959 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1960 ifp->if_timer = 0; 1961 log(LOG_ERR, "%s: interface not running\n", 1962 sc->sc_dev.dv_xname); 1963 } 1964 return (error); 1965 } 1966 1967 /* 1968 * Change media according to request. 1969 */ 1970 int 1971 fxp_mii_mediachange(struct ifnet *ifp) 1972 { 1973 struct fxp_softc *sc = ifp->if_softc; 1974 1975 if (ifp->if_flags & IFF_UP) 1976 mii_mediachg(&sc->sc_mii); 1977 return (0); 1978 } 1979 1980 /* 1981 * Notify the world which media we're using. 1982 */ 1983 void 1984 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1985 { 1986 struct fxp_softc *sc = ifp->if_softc; 1987 1988 if (sc->sc_enabled == 0) { 1989 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1990 ifmr->ifm_status = 0; 1991 return; 1992 } 1993 1994 mii_pollstat(&sc->sc_mii); 1995 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1996 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1997 1998 /* 1999 * XXX Flow control is always turned on if the chip supports 2000 * XXX it; we can't easily control it dynamically, since it 2001 * XXX requires sending a setup packet. 2002 */ 2003 if (sc->sc_rev >= FXP_REV_82558_A4) 2004 ifmr->ifm_active |= IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE; 2005 } 2006 2007 int 2008 fxp_80c24_mediachange(struct ifnet *ifp) 2009 { 2010 2011 /* Nothing to do here. */ 2012 return (0); 2013 } 2014 2015 void 2016 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2017 { 2018 struct fxp_softc *sc = ifp->if_softc; 2019 2020 /* 2021 * Media is currently-selected media. We cannot determine 2022 * the link status. 2023 */ 2024 ifmr->ifm_status = 0; 2025 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2026 } 2027 2028 /* 2029 * Add a buffer to the end of the RFA buffer list. 2030 * Return 0 if successful, error code on failure. 2031 * 2032 * The RFA struct is stuck at the beginning of mbuf cluster and the 2033 * data pointer is fixed up to point just past it. 2034 */ 2035 int 2036 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2037 { 2038 struct mbuf *m; 2039 int error; 2040 2041 MGETHDR(m, M_DONTWAIT, MT_DATA); 2042 if (m == NULL) 2043 return (ENOBUFS); 2044 2045 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2046 MCLGET(m, M_DONTWAIT); 2047 if ((m->m_flags & M_EXT) == 0) { 2048 m_freem(m); 2049 return (ENOBUFS); 2050 } 2051 2052 if (unload) 2053 bus_dmamap_unload(sc->sc_dmat, rxmap); 2054 2055 M_SETCTX(m, rxmap); 2056 2057 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2058 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2059 BUS_DMA_READ|BUS_DMA_NOWAIT); 2060 if (error) { 2061 /* XXX XXX XXX */ 2062 printf("%s: can't load rx DMA map %d, error = %d\n", 2063 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 2064 panic("fxp_add_rfabuf"); 2065 } 2066 2067 FXP_INIT_RFABUF(sc, m); 2068 2069 return (0); 2070 } 2071 2072 int 2073 fxp_mdi_read(struct device *self, int phy, int reg) 2074 { 2075 struct fxp_softc *sc = (struct fxp_softc *)self; 2076 int count = 10000; 2077 int value; 2078 2079 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2080 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2081 2082 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2083 0x10000000) == 0 && count--) 2084 DELAY(10); 2085 2086 if (count <= 0) 2087 log(LOG_WARNING, 2088 "%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 2089 2090 return (value & 0xffff); 2091 } 2092 2093 void 2094 fxp_statchg(struct device *self) 2095 { 2096 2097 /* Nothing to do. */ 2098 } 2099 2100 void 2101 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2102 { 2103 struct fxp_softc *sc = (struct fxp_softc *)self; 2104 int count = 10000; 2105 2106 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2107 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2108 (value & 0xffff)); 2109 2110 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2111 count--) 2112 DELAY(10); 2113 2114 if (count <= 0) 2115 log(LOG_WARNING, 2116 "%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2117 } 2118 2119 int 2120 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2121 { 2122 struct fxp_softc *sc = ifp->if_softc; 2123 struct ifreq *ifr = (struct ifreq *)data; 2124 int s, error; 2125 2126 s = splnet(); 2127 2128 switch (cmd) { 2129 case SIOCSIFMEDIA: 2130 case SIOCGIFMEDIA: 2131 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2132 break; 2133 2134 default: 2135 error = ether_ioctl(ifp, cmd, data); 2136 if (error == ENETRESET) { 2137 if (ifp->if_flags & IFF_RUNNING) { 2138 /* 2139 * Multicast list has changed; set the 2140 * hardware filter accordingly. 2141 */ 2142 if (sc->sc_txpending) { 2143 sc->sc_flags |= FXPF_WANTINIT; 2144 error = 0; 2145 } else 2146 error = fxp_init(ifp); 2147 } else 2148 error = 0; 2149 } 2150 break; 2151 } 2152 2153 /* Try to get more packets going. */ 2154 if (sc->sc_enabled) 2155 fxp_start(ifp); 2156 2157 splx(s); 2158 return (error); 2159 } 2160 2161 /* 2162 * Program the multicast filter. 2163 * 2164 * This function must be called at splnet(). 2165 */ 2166 void 2167 fxp_mc_setup(struct fxp_softc *sc) 2168 { 2169 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2170 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2171 struct ethercom *ec = &sc->sc_ethercom; 2172 struct ether_multi *enm; 2173 struct ether_multistep step; 2174 int count, nmcasts; 2175 2176 #ifdef DIAGNOSTIC 2177 if (sc->sc_txpending) 2178 panic("fxp_mc_setup: pending transmissions"); 2179 #endif 2180 2181 ifp->if_flags &= ~IFF_ALLMULTI; 2182 2183 /* 2184 * Initialize multicast setup descriptor. 2185 */ 2186 nmcasts = 0; 2187 ETHER_FIRST_MULTI(step, ec, enm); 2188 while (enm != NULL) { 2189 /* 2190 * Check for too many multicast addresses or if we're 2191 * listening to a range. Either way, we simply have 2192 * to accept all multicasts. 2193 */ 2194 if (nmcasts >= MAXMCADDR || 2195 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2196 ETHER_ADDR_LEN) != 0) { 2197 /* 2198 * Callers of this function must do the 2199 * right thing with this. If we're called 2200 * from outside fxp_init(), the caller must 2201 * detect if the state if IFF_ALLMULTI changes. 2202 * If it does, the caller must then call 2203 * fxp_init(), since allmulti is handled by 2204 * the config block. 2205 */ 2206 ifp->if_flags |= IFF_ALLMULTI; 2207 return; 2208 } 2209 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2210 ETHER_ADDR_LEN); 2211 nmcasts++; 2212 ETHER_NEXT_MULTI(step, enm); 2213 } 2214 2215 /* BIG_ENDIAN: no need to swap to store 0 */ 2216 mcsp->cb_status = 0; 2217 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2218 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2219 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2220 2221 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2222 2223 /* 2224 * Wait until the command unit is not active. This should never 2225 * happen since nothing is queued, but make sure anyway. 2226 */ 2227 count = 100; 2228 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2229 FXP_SCB_CUS_ACTIVE && --count) 2230 DELAY(1); 2231 if (count == 0) { 2232 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2233 sc->sc_dev.dv_xname, __LINE__); 2234 return; 2235 } 2236 2237 /* 2238 * Start the multicast setup command/DMA. 2239 */ 2240 fxp_scb_wait(sc); 2241 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2242 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2243 2244 /* ...and wait for it to complete. */ 2245 count = 1000; 2246 do { 2247 FXP_CDMCSSYNC(sc, 2248 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2249 DELAY(1); 2250 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2251 if (count == 0) { 2252 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2253 sc->sc_dev.dv_xname, __LINE__); 2254 return; 2255 } 2256 } 2257 2258 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2259 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2260 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2261 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2262 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2263 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2264 2265 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2266 2267 static const struct ucode { 2268 int32_t revision; 2269 const uint32_t *ucode; 2270 size_t length; 2271 uint16_t int_delay_offset; 2272 uint16_t bundle_max_offset; 2273 } ucode_table[] = { 2274 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2275 D101_CPUSAVER_DWORD, 0 }, 2276 2277 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2278 D101_CPUSAVER_DWORD, 0 }, 2279 2280 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2281 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2282 2283 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2284 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2285 2286 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2287 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2288 2289 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2290 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2291 2292 { 0, NULL, 0, 0, 0 } 2293 }; 2294 2295 void 2296 fxp_load_ucode(struct fxp_softc *sc) 2297 { 2298 const struct ucode *uc; 2299 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2300 int count, i; 2301 2302 if (sc->sc_flags & FXPF_UCODE_LOADED) 2303 return; 2304 2305 /* 2306 * Only load the uCode if the user has requested that 2307 * we do so. 2308 */ 2309 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2310 sc->sc_int_delay = 0; 2311 sc->sc_bundle_max = 0; 2312 return; 2313 } 2314 2315 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2316 if (sc->sc_rev == uc->revision) 2317 break; 2318 } 2319 if (uc->ucode == NULL) 2320 return; 2321 2322 /* BIG ENDIAN: no need to swap to store 0 */ 2323 cbp->cb_status = 0; 2324 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2325 cbp->link_addr = 0xffffffff; /* (no) next command */ 2326 for (i = 0; i < uc->length; i++) 2327 cbp->ucode[i] = htole32(uc->ucode[i]); 2328 2329 if (uc->int_delay_offset) 2330 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2331 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2332 2333 if (uc->bundle_max_offset) 2334 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2335 htole16(fxp_bundle_max); 2336 2337 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2338 2339 /* 2340 * Download the uCode to the chip. 2341 */ 2342 fxp_scb_wait(sc); 2343 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2344 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2345 2346 /* ...and wait for it to complete. */ 2347 count = 10000; 2348 do { 2349 FXP_CDUCODESYNC(sc, 2350 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2351 DELAY(2); 2352 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2353 if (count == 0) { 2354 sc->sc_int_delay = 0; 2355 sc->sc_bundle_max = 0; 2356 log(LOG_WARNING, "%s: timeout loading microcode\n", 2357 sc->sc_dev.dv_xname); 2358 return; 2359 } 2360 2361 if (sc->sc_int_delay != fxp_int_delay || 2362 sc->sc_bundle_max != fxp_bundle_max) { 2363 sc->sc_int_delay = fxp_int_delay; 2364 sc->sc_bundle_max = fxp_bundle_max; 2365 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2366 "max bundle: %d\n", sc->sc_dev.dv_xname, 2367 sc->sc_int_delay, 2368 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2369 } 2370 2371 sc->sc_flags |= FXPF_UCODE_LOADED; 2372 } 2373 2374 int 2375 fxp_enable(struct fxp_softc *sc) 2376 { 2377 2378 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2379 if ((*sc->sc_enable)(sc) != 0) { 2380 log(LOG_ERR, "%s: device enable failed\n", 2381 sc->sc_dev.dv_xname); 2382 return (EIO); 2383 } 2384 } 2385 2386 sc->sc_enabled = 1; 2387 return (0); 2388 } 2389 2390 void 2391 fxp_disable(struct fxp_softc *sc) 2392 { 2393 2394 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2395 (*sc->sc_disable)(sc); 2396 sc->sc_enabled = 0; 2397 } 2398 } 2399 2400 /* 2401 * fxp_activate: 2402 * 2403 * Handle device activation/deactivation requests. 2404 */ 2405 int 2406 fxp_activate(struct device *self, enum devact act) 2407 { 2408 struct fxp_softc *sc = (void *) self; 2409 int s, error = 0; 2410 2411 s = splnet(); 2412 switch (act) { 2413 case DVACT_ACTIVATE: 2414 error = EOPNOTSUPP; 2415 break; 2416 2417 case DVACT_DEACTIVATE: 2418 if (sc->sc_flags & FXPF_MII) 2419 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2420 MII_OFFSET_ANY); 2421 if_deactivate(&sc->sc_ethercom.ec_if); 2422 break; 2423 } 2424 splx(s); 2425 2426 return (error); 2427 } 2428 2429 /* 2430 * fxp_detach: 2431 * 2432 * Detach an i82557 interface. 2433 */ 2434 int 2435 fxp_detach(struct fxp_softc *sc) 2436 { 2437 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2438 int i; 2439 2440 /* Succeed now if there's no work to do. */ 2441 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2442 return (0); 2443 2444 /* Unhook our tick handler. */ 2445 callout_stop(&sc->sc_callout); 2446 2447 if (sc->sc_flags & FXPF_MII) { 2448 /* Detach all PHYs */ 2449 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2450 } 2451 2452 /* Delete all remaining media. */ 2453 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2454 2455 #if NRND > 0 2456 rnd_detach_source(&sc->rnd_source); 2457 #endif 2458 ether_ifdetach(ifp); 2459 if_detach(ifp); 2460 2461 for (i = 0; i < FXP_NRFABUFS; i++) { 2462 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2463 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2464 } 2465 2466 for (i = 0; i < FXP_NTXCB; i++) { 2467 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2468 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2469 } 2470 2471 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2472 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2473 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2474 sizeof(struct fxp_control_data)); 2475 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2476 2477 shutdownhook_disestablish(sc->sc_sdhook); 2478 powerhook_disestablish(sc->sc_powerhook); 2479 2480 return (0); 2481 } 2482
Indexes created Sun Sep 28 16:09:52 GMT 2025