i82557reg.h revision 1.1
1 /* $NetBSD: i82557reg.h,v 1.1 1999/06/20 16:33:28 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxpreg.h,v 1.11 1997/09/29 11:27:42 davidg Exp 67 */ 68 69 #define FXP_VENDORID_INTEL 0x8086 70 #define FXP_DEVICEID_i82557 0x1229 71 72 #define FXP_PCI_MMBA 0x10 73 #define FXP_PCI_IOBA 0x14 74 75 /* 76 * Control/status registers. 77 */ 78 #define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 79 #define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 80 #define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 81 #define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 82 #define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 83 #define FXP_CSR_PORT 8 /* port (4 bytes) */ 84 #define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 85 #define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 86 #define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 87 88 /* 89 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 90 * 91 * volatile u_int8_t :2, 92 * scb_rus:4, 93 * scb_cus:2; 94 */ 95 96 #define FXP_PORT_SOFTWARE_RESET 0 97 #define FXP_PORT_SELFTEST 1 98 #define FXP_PORT_SELECTIVE_RESET 2 99 #define FXP_PORT_DUMP 3 100 101 #define FXP_SCB_RUS_IDLE 0 102 #define FXP_SCB_RUS_SUSPENDED 1 103 #define FXP_SCB_RUS_NORESOURCES 2 104 #define FXP_SCB_RUS_READY 4 105 #define FXP_SCB_RUS_SUSP_NORBDS 9 106 #define FXP_SCB_RUS_NORES_NORBDS 10 107 #define FXP_SCB_RUS_READY_NORBDS 12 108 109 #define FXP_SCB_CUS_IDLE 0 110 #define FXP_SCB_CUS_SUSPENDED 1 111 #define FXP_SCB_CUS_ACTIVE 2 112 113 #define FXP_SCB_STATACK_SWI 0x04 114 #define FXP_SCB_STATACK_MDI 0x08 115 #define FXP_SCB_STATACK_RNR 0x10 116 #define FXP_SCB_STATACK_CNA 0x20 117 #define FXP_SCB_STATACK_FR 0x40 118 #define FXP_SCB_STATACK_CXTNO 0x80 119 120 #define FXP_SCB_COMMAND_CU_NOP 0x00 121 #define FXP_SCB_COMMAND_CU_START 0x10 122 #define FXP_SCB_COMMAND_CU_RESUME 0x20 123 #define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 124 #define FXP_SCB_COMMAND_CU_DUMP 0x50 125 #define FXP_SCB_COMMAND_CU_BASE 0x60 126 #define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 127 128 #define FXP_SCB_COMMAND_RU_NOP 0 129 #define FXP_SCB_COMMAND_RU_START 1 130 #define FXP_SCB_COMMAND_RU_RESUME 2 131 #define FXP_SCB_COMMAND_RU_ABORT 4 132 #define FXP_SCB_COMMAND_RU_LOADHDS 5 133 #define FXP_SCB_COMMAND_RU_BASE 6 134 #define FXP_SCB_COMMAND_RU_RBDRESUME 7 135 136 /* 137 * Software-use only part of the command block. 138 */ 139 struct fxp_cb_soft { 140 void *next; /* pointer to next command block */ 141 struct mbuf *mb_head; /* pointer to data for this command */ 142 bus_dmamap_t dmamap; /* our DMA map */ 143 }; 144 145 /* 146 * Command block definitions 147 */ 148 struct fxp_cb_nop { 149 struct fxp_cb_soft cb_soft; 150 volatile u_int16_t cb_status; 151 volatile u_int16_t cb_command; 152 volatile u_int32_t link_addr; 153 }; 154 struct fxp_cb_ias { 155 struct fxp_cb_soft cb_soft; 156 volatile u_int16_t cb_status; 157 volatile u_int16_t cb_command; 158 volatile u_int32_t link_addr; 159 volatile u_int8_t macaddr[6]; 160 }; 161 /* I hate bit-fields :-( */ 162 struct fxp_cb_config { 163 struct fxp_cb_soft cb_soft; 164 volatile u_int16_t cb_status; 165 volatile u_int16_t cb_command; 166 volatile u_int32_t link_addr; 167 volatile u_int8_t byte_count:6, 168 :2; 169 volatile u_int8_t rx_fifo_limit:4, 170 tx_fifo_limit:3, 171 :1; 172 volatile u_int8_t adaptive_ifs; 173 volatile u_int8_t :8; 174 volatile u_int8_t rx_dma_bytecount:7, 175 :1; 176 volatile u_int8_t tx_dma_bytecount:7, 177 dma_bce:1; 178 volatile u_int8_t late_scb:1, 179 :1, 180 tno_int:1, 181 ci_int:1, 182 :3, 183 save_bf:1; 184 volatile u_int8_t disc_short_rx:1, 185 underrun_retry:2, 186 :5; 187 volatile u_int8_t mediatype:1, 188 :7; 189 volatile u_int8_t :8; 190 volatile u_int8_t :3, 191 nsai:1, 192 preamble_length:2, 193 loopback:2; 194 volatile u_int8_t linear_priority:3, 195 :5; 196 volatile u_int8_t linear_pri_mode:1, 197 :3, 198 interfrm_spacing:4; 199 volatile u_int8_t :8; 200 volatile u_int8_t :8; 201 volatile u_int8_t promiscuous:1, 202 bcast_disable:1, 203 :5, 204 crscdt:1; 205 volatile u_int8_t :8; 206 volatile u_int8_t :8; 207 volatile u_int8_t stripping:1, 208 padding:1, 209 rcv_crc_xfer:1, 210 :5; 211 volatile u_int8_t :6, 212 force_fdx:1, 213 fdx_pin_en:1; 214 volatile u_int8_t :6, 215 multi_ia:1, 216 :1; 217 volatile u_int8_t :3, 218 mc_all:1, 219 :4; 220 }; 221 222 /* 223 * Size of the hardware portion of a given transmit descriptor, including 224 * the DMA segment array. 225 */ 226 #define FXP_MCSDESCSIZE \ 227 (sizeof(struct fxp_cb_mcs) - offsetof(struct fxp_cb_mcs, cb_status)) 228 229 #define MAXMCADDR 80 230 struct fxp_cb_mcs { 231 struct fxp_cb_soft cb_soft; 232 volatile u_int16_t cb_status; 233 volatile u_int16_t cb_command; 234 volatile u_int32_t link_addr; 235 volatile u_int16_t mc_cnt; 236 volatile u_int8_t mc_addr[MAXMCADDR][6]; 237 }; 238 239 /* 240 * Number of DMA segments in a TxCB. The TxCB must map to a 241 * contiguous region from the DMA engine's perspective. Since 242 * we allocate memory conforming to those contraints, we can 243 * arbitrarily choose the number of segments. 244 */ 245 #define FXP_NTXSEG 32 246 247 struct fxp_tbd { 248 volatile u_int32_t tb_addr; 249 volatile u_int32_t tb_size; 250 }; 251 struct fxp_cb_tx { 252 struct fxp_cb_soft cb_soft; 253 volatile u_int16_t cb_status; 254 volatile u_int16_t cb_command; 255 volatile u_int32_t link_addr; 256 volatile u_int32_t tbd_array_addr; 257 volatile u_int16_t byte_count; 258 volatile u_int8_t tx_threshold; 259 volatile u_int8_t tbd_number; 260 /* 261 * The following isn't actually part of the TxCB, but we 262 * allocate it here for convenience. 263 */ 264 volatile struct fxp_tbd tbd[FXP_NTXSEG]; 265 }; 266 267 /* 268 * Offset of the hardware portion of a given transmit descriptor from the 269 * base of the control data DMA mapping. 270 */ 271 #define FXP_TXDESCOFF(sc, txd) \ 272 (FXP_CDOFF(fcd_txcbs[0]) + \ 273 (((u_long)(txd)) - ((u_long)&(sc)->control_data->fcd_txcbs[0])) + \ 274 offsetof(struct fxp_cb_tx, cb_status)) 275 276 /* 277 * Size of the hardware portion of a given transmit descriptor, including 278 * the DMA segment array. 279 */ 280 #define FXP_TXDESCSIZE \ 281 (sizeof(struct fxp_cb_tx) - offsetof(struct fxp_cb_tx, cb_status)) 282 283 /* 284 * Control Block (CB) definitions 285 */ 286 287 /* status */ 288 #define FXP_CB_STATUS_OK 0x2000 289 #define FXP_CB_STATUS_C 0x8000 290 /* commands */ 291 #define FXP_CB_COMMAND_NOP 0x0 292 #define FXP_CB_COMMAND_IAS 0x1 293 #define FXP_CB_COMMAND_CONFIG 0x2 294 #define FXP_CB_COMMAND_MCAS 0x3 295 #define FXP_CB_COMMAND_XMIT 0x4 296 #define FXP_CB_COMMAND_RESRV 0x5 297 #define FXP_CB_COMMAND_DUMP 0x6 298 #define FXP_CB_COMMAND_DIAG 0x7 299 /* command flags */ 300 #define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 301 #define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 302 #define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 303 #define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 304 305 /* 306 * RFA definitions 307 * NOTE! The RFA will NOT be aligned on a 4-byte boundary in the DMA 308 * area! To prevent EGCS from optimizing the copy of link_addr and 309 * rbd_addr (which would cause an unaligned access fault on RISC systems), 310 * we must make them an array of bytes! 311 */ 312 313 struct fxp_rfa { 314 volatile u_int16_t rfa_status; 315 volatile u_int16_t rfa_control; 316 volatile u_int8_t link_addr[4]; 317 volatile u_int8_t rbd_addr[4]; 318 volatile u_int16_t actual_size; 319 volatile u_int16_t size; 320 }; 321 #define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 322 #define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 323 #define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 324 #define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 325 #define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 326 #define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 327 #define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 328 #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 329 #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 330 #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 331 #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 332 #define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 333 #define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 334 #define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 335 #define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 336 337 /* 338 * Statistics dump area definitions 339 */ 340 struct fxp_stats { 341 volatile u_int32_t tx_good; 342 volatile u_int32_t tx_maxcols; 343 volatile u_int32_t tx_latecols; 344 volatile u_int32_t tx_underruns; 345 volatile u_int32_t tx_lostcrs; 346 volatile u_int32_t tx_deffered; 347 volatile u_int32_t tx_single_collisions; 348 volatile u_int32_t tx_multiple_collisions; 349 volatile u_int32_t tx_total_collisions; 350 volatile u_int32_t rx_good; 351 volatile u_int32_t rx_crc_errors; 352 volatile u_int32_t rx_alignment_errors; 353 volatile u_int32_t rx_rnr_errors; 354 volatile u_int32_t rx_overrun_errors; 355 volatile u_int32_t rx_cdt_errors; 356 volatile u_int32_t rx_shortframes; 357 volatile u_int32_t completion_status; 358 }; 359 #define FXP_STATS_DUMP_COMPLETE 0xa005 360 #define FXP_STATS_DR_COMPLETE 0xa007 361 362 /* 363 * Serial EEPROM control register bits 364 */ 365 /* shift clock */ 366 #define FXP_EEPROM_EESK 0x01 367 /* chip select */ 368 #define FXP_EEPROM_EECS 0x02 369 /* data in */ 370 #define FXP_EEPROM_EEDI 0x04 371 /* data out */ 372 #define FXP_EEPROM_EEDO 0x08 373 374 /* 375 * Serial EEPROM opcodes, including start bit 376 */ 377 #define FXP_EEPROM_OPC_ERASE 0x4 378 #define FXP_EEPROM_OPC_WRITE 0x5 379 #define FXP_EEPROM_OPC_READ 0x6 380 381 /* 382 * Management Data Interface opcodes 383 */ 384 #define FXP_MDI_WRITE 0x1 385 #define FXP_MDI_READ 0x2 386 387 /* 388 * PHY device types 389 */ 390 #define FXP_PHY_NONE 0 391 #define FXP_PHY_82553A 1 392 #define FXP_PHY_82553C 2 393 #define FXP_PHY_82503 3 394 #define FXP_PHY_DP83840 4 395 #define FXP_PHY_80C240 5 396 #define FXP_PHY_80C24 6 397 #define FXP_PHY_82555 7 398 #define FXP_PHY_DP83840A 10 399
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