i82557reg.h revision 1.13
1 /* $NetBSD: i82557reg.h,v 1.13 2003/11/02 10:50:40 wiz Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxpreg.h,v 1.24 2001/05/15 18:52:40 jlemon Exp 68 */ 69 70 #define FXP_PCI_MMBA 0x10 71 #define FXP_PCI_IOBA 0x14 72 73 /* 74 * Control/status registers. 75 */ 76 #define FXP_CSR_SCB_RUSCUS 0x00 /* scb_rus/scb_cus (1 byte) */ 77 #define FXP_CSR_SCB_STATACK 0x01 /* scb_statack (1 byte) */ 78 #define FXP_CSR_SCB_COMMAND 0x02 /* scb_command (1 byte) */ 79 #define FXP_CSR_SCB_INTRCNTL 0x03 /* scb_intrcntl (1 byte) */ 80 #define FXP_CSR_SCB_GENERAL 0x04 /* scb_general (4 bytes) */ 81 #define FXP_CSR_PORT 0x08 /* port (4 bytes) */ 82 #define FXP_CSR_FLASHCONTROL 0x0c /* flash control (2 bytes) */ 83 #define FXP_CSR_EEPROMCONTROL 0x0e /* eeprom control (2 bytes) */ 84 #define FXP_CSR_MDICONTROL 0x10 /* mdi control (4 bytes) */ 85 #define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */ 86 87 /* 88 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 89 * 90 * volatile u_int8_t :2, 91 * scb_rus:4, 92 * scb_cus:2; 93 */ 94 95 #define FXP_PORT_SOFTWARE_RESET 0 96 #define FXP_PORT_SELFTEST 1 97 #define FXP_PORT_SELECTIVE_RESET 2 98 #define FXP_PORT_DUMP 3 99 100 #define FXP_SCB_RUS_IDLE 0 101 #define FXP_SCB_RUS_SUSPENDED 1 102 #define FXP_SCB_RUS_NORESOURCES 2 103 #define FXP_SCB_RUS_READY 4 104 #define FXP_SCB_RUS_SUSP_NORBDS 9 105 #define FXP_SCB_RUS_NORES_NORBDS 10 106 #define FXP_SCB_RUS_READY_NORBDS 12 107 108 #define FXP_SCB_CUS_IDLE 0 109 #define FXP_SCB_CUS_SUSPENDED 1 110 #define FXP_SCB_CUS_ACTIVE 2 111 112 #define FXP_SCB_INTR_DISABLE 0x01 /* disable all interrupts */ 113 #define FXP_SCB_INTR_SWI 0x02 /* generate SWI */ 114 #define FXP_SCB_INTMASK_FCP 0x04 115 #define FXP_SCB_INTMASK_ER 0x08 116 #define FXP_SCB_INTMASK_RNR 0x10 117 #define FXP_SCB_INTMASK_CNA 0x20 118 #define FXP_SCB_INTMASK_FR 0x40 119 #define FXP_SCB_INTMASK_CXTNO 0x80 120 121 #define FXP_SCB_STATACK_FCP 0x01 /* flow control pause */ 122 #define FXP_SCB_STATACK_ER 0x02 /* early receive */ 123 #define FXP_SCB_STATACK_SWI 0x04 124 #define FXP_SCB_STATACK_MDI 0x08 125 #define FXP_SCB_STATACK_RNR 0x10 126 #define FXP_SCB_STATACK_CNA 0x20 127 #define FXP_SCB_STATACK_FR 0x40 128 #define FXP_SCB_STATACK_CXTNO 0x80 129 130 #define FXP_SCB_COMMAND_CU_NOP 0x00 131 #define FXP_SCB_COMMAND_CU_START 0x10 132 #define FXP_SCB_COMMAND_CU_RESUME 0x20 133 #define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 134 #define FXP_SCB_COMMAND_CU_DUMP 0x50 135 #define FXP_SCB_COMMAND_CU_BASE 0x60 136 #define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 137 138 #define FXP_SCB_COMMAND_RU_NOP 0 139 #define FXP_SCB_COMMAND_RU_START 1 140 #define FXP_SCB_COMMAND_RU_RESUME 2 141 #define FXP_SCB_COMMAND_RU_ABORT 4 142 #define FXP_SCB_COMMAND_RU_LOADHDS 5 143 #define FXP_SCB_COMMAND_RU_BASE 6 144 #define FXP_SCB_COMMAND_RU_RBDRESUME 7 145 146 /* 147 * Command block definitions 148 */ 149 150 /* 151 * NOP command. 152 */ 153 struct fxp_cb_nop { 154 volatile u_int16_t cb_status; 155 volatile u_int16_t cb_command; 156 volatile u_int32_t link_addr; 157 }; 158 159 /* 160 * Individual Address command. 161 */ 162 struct fxp_cb_ias { 163 volatile u_int16_t cb_status; 164 volatile u_int16_t cb_command; 165 volatile u_int32_t link_addr; 166 volatile u_int8_t macaddr[6]; 167 }; 168 169 #if BYTE_ORDER == LITTLE_ENDIAN 170 #define __FXP_BITFIELD2(a, b) a, b 171 #define __FXP_BITFIELD3(a, b, c) a, b, c 172 #define __FXP_BITFIELD4(a, b, c, d) a, b, c, d 173 #define __FXP_BITFIELD5(a, b, c, d, e) a, b, c, d, e 174 #define __FXP_BITFIELD6(a, b, c, d, e, f) a, b, c, d, e, f 175 #define __FXP_BITFIELD7(a, b, c, d, e, f, g) a, b, c, d, e, f, g 176 #define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) a, b, c, d, e, f, g, h 177 #else 178 #define __FXP_BITFIELD2(a, b) b, a 179 #define __FXP_BITFIELD3(a, b, c) c, b, a 180 #define __FXP_BITFIELD4(a, b, c, d) d, c, b, a 181 #define __FXP_BITFIELD5(a, b, c, d, e) e, d, c, b, a 182 #define __FXP_BITFIELD6(a, b, c, d, e, f) f, e, d, c, b, a 183 #define __FXP_BITFIELD7(a, b, c, d, e, f, g) g, f, e, d, c, b, a 184 #define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) h, g, f, e, d, c, b, a 185 #endif 186 187 /* 188 * Configure command. 189 */ 190 struct fxp_cb_config { 191 volatile u_int16_t cb_status; 192 volatile u_int16_t cb_command; 193 volatile u_int32_t link_addr; 194 195 /* Bytes 0 - 21 -- common to all i8255x */ 196 /*0*/ volatile u_int8_t __FXP_BITFIELD2(byte_count:6, :2); 197 /*1*/ volatile u_int8_t __FXP_BITFIELD3(rx_fifo_limit:4, 198 tx_fifo_limit:3, 199 :1); 200 /*2*/ volatile u_int8_t adaptive_ifs; 201 /*3*/ volatile u_int8_t __FXP_BITFIELD5(mwi_enable:1, /* 8,9 */ 202 type_enable:1, /* 8,9 */ 203 read_align_en:1, /* 8,9 */ 204 end_wr_on_cl:1, /* 8,9 */ 205 :4); 206 /*4*/ volatile u_int8_t __FXP_BITFIELD2(rx_dma_bytecount:7, 207 :1); 208 /*5*/ volatile u_int8_t __FXP_BITFIELD2(tx_dma_bytecount:7, 209 dma_mbce:1); 210 /*6*/ volatile u_int8_t __FXP_BITFIELD8(late_scb:1, /* 7 */ 211 direct_dma_dis:1, /* 8,9 */ 212 tno_int_or_tco_en:1, /* 7,9 */ 213 ci_int:1, 214 ext_txcb_dis:1, /* 8,9 */ 215 ext_stats_dis:1, /* 8,9 */ 216 keep_overrun_rx:1, 217 save_bf:1); 218 /*7*/ volatile u_int8_t __FXP_BITFIELD6(disc_short_rx:1, 219 underrun_retry:2, 220 :2, 221 ext_rfa:1, /* 0 */ 222 two_frames:1, /* 8,9 */ 223 dyn_tbd:1); /* 8,9 */ 224 /*8*/ volatile u_int8_t __FXP_BITFIELD3(mediatype:1, /* 7 */ 225 :6, 226 csma_dis:1); /* 8,9 */ 227 /*9*/ volatile u_int8_t __FXP_BITFIELD6(tcp_udp_cksum:1,/* 9 */ 228 :3, 229 vlan_tco:1, /* 8,9 */ 230 link_wake_en:1, /* 8,9 */ 231 arp_wake_en:1, /* 8 */ 232 mc_wake_en:1); /* 8 */ 233 /*10*/ volatile u_int8_t __FXP_BITFIELD4(:3, 234 nsai:1, 235 preamble_length:2, 236 loopback:2); 237 /*11*/ volatile u_int8_t __FXP_BITFIELD2(linear_priority:3,/* 7 */ 238 :5); 239 /*12*/ volatile u_int8_t __FXP_BITFIELD3(linear_pri_mode:1,/* 7 */ 240 :3, 241 interfrm_spacing:4); 242 /*13*/ volatile u_int8_t :8; 243 /*14*/ volatile u_int8_t :8; 244 /*15*/ volatile u_int8_t __FXP_BITFIELD8(promiscuous:1, 245 bcast_disable:1, 246 wait_after_win:1, /* 8,9 */ 247 :1, 248 ignore_ul:1, /* 8,9 */ 249 crc16_en:1, /* 9 */ 250 :1, 251 crscdt:1); 252 /*16*/ volatile u_int8_t fc_delay_lsb:8; /* 8,9 */ 253 /*17*/ volatile u_int8_t fc_delay_msb:8; /* 8,9 */ 254 /*18*/ volatile u_int8_t __FXP_BITFIELD6(stripping:1, 255 padding:1, 256 rcv_crc_xfer:1, 257 long_rx_en:1, /* 8,9 */ 258 pri_fc_thresh:3, /* 8,9 */ 259 :1); 260 /*19*/ volatile u_int8_t __FXP_BITFIELD8(ia_wake_en:1, /* 8 */ 261 magic_pkt_dis:1, /* 8,9,!9ER */ 262 tx_fc_dis:1, /* 8,9 */ 263 rx_fc_restop:1, /* 8,9 */ 264 rx_fc_restart:1, /* 8,9 */ 265 fc_filter:1, /* 8,9 */ 266 force_fdx:1, 267 fdx_pin_en:1); 268 /*20*/ volatile u_int8_t __FXP_BITFIELD4(:5, 269 pri_fc_loc:1 /* 8,9 */, 270 multi_ia:1, 271 :1); 272 /*21*/ volatile u_int8_t __FXP_BITFIELD3(:3, mc_all:1, :4); 273 274 /* Bytes 22 - 31 -- i82550 only */ 275 /*22*/ volatile u_int8_t __FXP_BITFIELD3(ext_rx_mode:1, 276 vlan_drop_en:1, 277 :6); 278 volatile u_int8_t reserved[9]; 279 }; 280 281 #define FXP_CONFIG_LEN 22 /* i8255x */ 282 #define FXP_EXT_CONFIG_LEN 32 /* i82550 */ 283 284 /* 285 * Multicast setup command. 286 */ 287 #define MAXMCADDR 80 288 struct fxp_cb_mcs { 289 volatile u_int16_t cb_status; 290 volatile u_int16_t cb_command; 291 volatile u_int32_t link_addr; 292 volatile u_int16_t mc_cnt; 293 volatile u_int8_t mc_addr[MAXMCADDR][6]; 294 }; 295 296 #define MAXUCODESIZE 192 297 struct fxp_cb_ucode { 298 volatile u_int16_t cb_status; 299 volatile u_int16_t cb_command; 300 volatile u_int32_t link_addr; 301 volatile u_int32_t ucode[MAXUCODESIZE]; 302 }; 303 304 struct fxp_ipcb { 305 /* 306 * The following fields are valid only when 307 * using the IPCB command block for TX checksum offload 308 * (and TCP large send, VLANs, and (I think) IPsec). To use 309 * them, you must enable extended TxCBs (available only 310 * on the 82559 and later) and use the IPCBXMIT command. 311 * Note that Intel defines the IPCB to be 32 bytes long, 312 * the last 8 bytes of which comprise the first entry 313 * in the TBD array. This means we only have to define 314 * 8 extra bytes here. 315 */ 316 volatile u_int16_t ipcb_schedule_low; 317 volatile u_int8_t ipcb_ip_schedule; 318 volatile u_int8_t ipcb_ip_activation_high; 319 volatile u_int16_t ipcb_vlan_id; 320 volatile u_int8_t ipcb_ip_header_offset; 321 volatile u_int8_t ipcb_tcp_header_offset; 322 }; 323 324 /* 325 * IPCB field definitions 326 */ 327 /* for ipcb_ip_schedule */ 328 #define FXP_IPCB_IP_CHECKSUM_ENABLE 0x10 329 #define FXP_IPCB_TCPUDP_CHECKSUM_ENABLE 0x20 330 #define FXP_IPCB_TCP_PACKET 0x40 331 #define FXP_IPCB_LARGESEND_ENABLE 0x80 332 /* for ipcb_ip_activation_high */ 333 #define FXP_IPCB_HARDWAREPARSING_ENABLE 0x01 334 #define FXP_IPCB_INSERTVLAN_ENABLE 0x02 335 336 /* 337 * Transmit command. 338 */ 339 struct fxp_cb_tx { 340 volatile u_int16_t cb_status; 341 volatile u_int16_t cb_command; 342 volatile u_int32_t link_addr; 343 volatile u_int32_t tbd_array_addr; 344 volatile u_int16_t byte_count; 345 volatile u_int8_t tx_threshold; 346 volatile u_int8_t tbd_number; 347 /* 348 * If using the extended TxCB feature, there is a 349 * two TBDs right here. We handle this in the 350 * fxp_control_data in i82557var.h. 351 */ 352 }; 353 354 /* 355 * Transmit buffer descriptors. 356 */ 357 struct fxp_tbd { 358 volatile u_int32_t tb_addr; 359 volatile u_int32_t tb_size; 360 }; 361 362 /* 363 * Control Block (CB) definitions 364 */ 365 366 /* status */ 367 #define FXP_CB_STATUS_OK 0x2000 368 #define FXP_CB_STATUS_C 0x8000 369 370 /* commands */ 371 #define FXP_CB_COMMAND_NOP 0x0 372 #define FXP_CB_COMMAND_IAS 0x1 373 #define FXP_CB_COMMAND_CONFIG 0x2 374 #define FXP_CB_COMMAND_MCAS 0x3 375 #define FXP_CB_COMMAND_XMIT 0x4 376 #define FXP_CB_COMMAND_UCODE 0x5 377 #define FXP_CB_COMMAND_DUMP 0x6 378 #define FXP_CB_COMMAND_DIAG 0x7 379 #define FXP_CB_COMMAND_IPCBXMIT 0x9 380 381 /* command flags */ 382 #define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 383 #define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 384 #define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 385 #define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 386 387 /* 388 * Receive Frame Area. 389 * 390 * NOTE! The RFA will NOT be aligned on a 4-byte boundary in the DMA 391 * area! To prevent EGCS from optimizing the copy of link_addr and 392 * rbd_addr (which would cause an unaligned access fault on RISC systems), 393 * we must make them an array of bytes! 394 */ 395 struct fxp_rfa { 396 /* Fields common to all i8255x chips. */ 397 volatile u_int16_t rfa_status; 398 volatile u_int16_t rfa_control; 399 volatile u_int8_t link_addr[4]; 400 volatile u_int8_t rbd_addr[4]; 401 volatile u_int16_t actual_size; 402 volatile u_int16_t size; 403 404 /* Fields available only on the i82550/i82551 in extended RFD mode. */ 405 volatile u_int16_t vlan_id; 406 volatile u_int8_t rx_parse_stat; 407 volatile u_int8_t reserved; 408 volatile u_int16_t security_stat; 409 volatile u_int8_t cksum_stat; 410 volatile u_int8_t zerocopy_stat; 411 volatile u_int8_t unused[8]; 412 }; 413 414 #define RFA_SIZE 16 415 #define RFA_EXT_SIZE 32 416 417 #define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 418 #define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 419 #define FXP_RFA_STATUS_NOAMATCH 0x0004 /* 1 = doesn't match anything */ 420 #define FXP_RFA_STATUS_PARSE 0x0008 /* pkt parse ok (82550/1 only) */ 421 #define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 422 #define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 423 #define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 424 #define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 425 #define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 426 #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 427 #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 428 #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 429 #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 430 431 #define FXP_RFA_CONTROL_SF 0x0008 /* simple/flexible memory mode */ 432 #define FXP_RFA_CONTROL_H 0x0010 /* header RFD */ 433 #define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 434 #define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 435 436 /* Bits in the 'cksum_stat' byte */ 437 #define FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID 0x10 438 #define FXP_RFDX_CS_TCPUDP_CSUM_VALID 0x20 439 #define FXP_RFDX_CS_IP_CSUM_BIT_VALID 0x01 440 #define FXP_RFDX_CS_IP_CSUM_VALID 0x02 441 442 /* Bits in the 'rx_parse_stat' byte */ 443 #define FXP_RFDX_P_PARSE_BIT 0x08 444 #define FXP_RFDX_P_CSUM_PROTOCOL_MASK 0x03 445 #define FXP_RFDX_P_TCP_PACKET 0x00 446 #define FXP_RFDX_P_UDP_PACKET 0x01 447 #define FXP_RFDX_P_IP_PACKET 0x03 448 449 /* 450 * Statistics dump area definitions 451 */ 452 struct fxp_stats { 453 volatile u_int32_t tx_good; 454 volatile u_int32_t tx_maxcols; 455 volatile u_int32_t tx_latecols; 456 volatile u_int32_t tx_underruns; 457 volatile u_int32_t tx_lostcrs; 458 volatile u_int32_t tx_deferred; 459 volatile u_int32_t tx_single_collisions; 460 volatile u_int32_t tx_multiple_collisions; 461 volatile u_int32_t tx_total_collisions; 462 volatile u_int32_t rx_good; 463 volatile u_int32_t rx_crc_errors; 464 volatile u_int32_t rx_alignment_errors; 465 volatile u_int32_t rx_rnr_errors; 466 volatile u_int32_t rx_overrun_errors; 467 volatile u_int32_t rx_cdt_errors; 468 volatile u_int32_t rx_shortframes; 469 volatile u_int32_t completion_status; 470 }; 471 #define FXP_STATS_DUMP_COMPLETE 0xa005 472 #define FXP_STATS_DR_COMPLETE 0xa007 473 474 /* 475 * Serial EEPROM control register bits 476 */ 477 #define FXP_EEPROM_EESK 0x01 /* shift clock */ 478 #define FXP_EEPROM_EECS 0x02 /* chip select */ 479 #define FXP_EEPROM_EEDI 0x04 /* data in */ 480 #define FXP_EEPROM_EEDO 0x08 /* data out */ 481 482 /* 483 * Serial EEPROM opcodes, including start bit 484 */ 485 #define FXP_EEPROM_OPC_ERASE 0x4 486 #define FXP_EEPROM_OPC_WRITE 0x5 487 #define FXP_EEPROM_OPC_READ 0x6 488 489 /* 490 * Management Data Interface opcodes 491 */ 492 #define FXP_MDI_WRITE 0x1 493 #define FXP_MDI_READ 0x2 494 495 /* 496 * PHY device types (from EEPROM) 497 */ 498 #define FXP_PHY_DEVICE_MASK 0x3f00 499 #define FXP_PHY_DEVICE_SHIFT 8 500 #define FXP_PHY_DEVADDR_MASK 0x00ff 501 #define FXP_PHY_SERIAL_ONLY 0x8000 502 #define FXP_PHY_NONE 0 503 #define FXP_PHY_82553A 1 504 #define FXP_PHY_82553C 2 505 #define FXP_PHY_82503 3 506 #define FXP_PHY_DP83840 4 507 #define FXP_PHY_80C240 5 508 #define FXP_PHY_80C24 6 509 #define FXP_PHY_82555 7 510 #define FXP_PHY_DP83840A 10 511 #define FXP_PHY_DP82555B 11 512 513 /* 514 * PCI revisions. 515 */ 516 #define FXP_REV_82558_A4 4 517 #define FXP_REV_82558_B0 5 518 #define FXP_REV_82559_A0 8 519 #define FXP_REV_82559S_A 9 520 #define FXP_REV_82550 12 521 #define FXP_REV_82550_C 13 522
Indexes created Wed Oct 01 13:09:50 GMT 2025