i82557reg.h revision 1.2
1 /* $NetBSD: i82557reg.h,v 1.2 1999/08/03 22:43:28 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxpreg.h,v 1.11 1997/09/29 11:27:42 davidg Exp 67 */ 68 69 #define FXP_VENDORID_INTEL 0x8086 70 #define FXP_DEVICEID_i82557 0x1229 71 72 #define FXP_PCI_MMBA 0x10 73 #define FXP_PCI_IOBA 0x14 74 75 /* 76 * Control/status registers. 77 */ 78 #define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 79 #define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 80 #define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 81 #define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 82 #define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 83 #define FXP_CSR_PORT 8 /* port (4 bytes) */ 84 #define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 85 #define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 86 #define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 87 88 /* 89 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 90 * 91 * volatile u_int8_t :2, 92 * scb_rus:4, 93 * scb_cus:2; 94 */ 95 96 #define FXP_PORT_SOFTWARE_RESET 0 97 #define FXP_PORT_SELFTEST 1 98 #define FXP_PORT_SELECTIVE_RESET 2 99 #define FXP_PORT_DUMP 3 100 101 #define FXP_SCB_RUS_IDLE 0 102 #define FXP_SCB_RUS_SUSPENDED 1 103 #define FXP_SCB_RUS_NORESOURCES 2 104 #define FXP_SCB_RUS_READY 4 105 #define FXP_SCB_RUS_SUSP_NORBDS 9 106 #define FXP_SCB_RUS_NORES_NORBDS 10 107 #define FXP_SCB_RUS_READY_NORBDS 12 108 109 #define FXP_SCB_CUS_IDLE 0 110 #define FXP_SCB_CUS_SUSPENDED 1 111 #define FXP_SCB_CUS_ACTIVE 2 112 113 #define FXP_SCB_STATACK_SWI 0x04 114 #define FXP_SCB_STATACK_MDI 0x08 115 #define FXP_SCB_STATACK_RNR 0x10 116 #define FXP_SCB_STATACK_CNA 0x20 117 #define FXP_SCB_STATACK_FR 0x40 118 #define FXP_SCB_STATACK_CXTNO 0x80 119 120 #define FXP_SCB_COMMAND_CU_NOP 0x00 121 #define FXP_SCB_COMMAND_CU_START 0x10 122 #define FXP_SCB_COMMAND_CU_RESUME 0x20 123 #define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 124 #define FXP_SCB_COMMAND_CU_DUMP 0x50 125 #define FXP_SCB_COMMAND_CU_BASE 0x60 126 #define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 127 128 #define FXP_SCB_COMMAND_RU_NOP 0 129 #define FXP_SCB_COMMAND_RU_START 1 130 #define FXP_SCB_COMMAND_RU_RESUME 2 131 #define FXP_SCB_COMMAND_RU_ABORT 4 132 #define FXP_SCB_COMMAND_RU_LOADHDS 5 133 #define FXP_SCB_COMMAND_RU_BASE 6 134 #define FXP_SCB_COMMAND_RU_RBDRESUME 7 135 136 /* 137 * Command block definitions 138 */ 139 140 /* 141 * NOP command. 142 */ 143 struct fxp_cb_nop { 144 volatile u_int16_t cb_status; 145 volatile u_int16_t cb_command; 146 volatile u_int32_t link_addr; 147 }; 148 149 /* 150 * Individual Address command. 151 */ 152 struct fxp_cb_ias { 153 volatile u_int16_t cb_status; 154 volatile u_int16_t cb_command; 155 volatile u_int32_t link_addr; 156 volatile u_int8_t macaddr[6]; 157 }; 158 159 /* 160 * Configure command. 161 */ 162 struct fxp_cb_config { 163 volatile u_int16_t cb_status; 164 volatile u_int16_t cb_command; 165 volatile u_int32_t link_addr; 166 volatile u_int8_t byte_count:6, 167 :2; 168 volatile u_int8_t rx_fifo_limit:4, 169 tx_fifo_limit:3, 170 :1; 171 volatile u_int8_t adaptive_ifs; 172 volatile u_int8_t :8; 173 volatile u_int8_t rx_dma_bytecount:7, 174 :1; 175 volatile u_int8_t tx_dma_bytecount:7, 176 dma_bce:1; 177 volatile u_int8_t late_scb:1, 178 :1, 179 tno_int:1, 180 ci_int:1, 181 :3, 182 save_bf:1; 183 volatile u_int8_t disc_short_rx:1, 184 underrun_retry:2, 185 :5; 186 volatile u_int8_t mediatype:1, 187 :7; 188 volatile u_int8_t :8; 189 volatile u_int8_t :3, 190 nsai:1, 191 preamble_length:2, 192 loopback:2; 193 volatile u_int8_t linear_priority:3, 194 :5; 195 volatile u_int8_t linear_pri_mode:1, 196 :3, 197 interfrm_spacing:4; 198 volatile u_int8_t :8; 199 volatile u_int8_t :8; 200 volatile u_int8_t promiscuous:1, 201 bcast_disable:1, 202 :5, 203 crscdt:1; 204 volatile u_int8_t :8; 205 volatile u_int8_t :8; 206 volatile u_int8_t stripping:1, 207 padding:1, 208 rcv_crc_xfer:1, 209 :5; 210 volatile u_int8_t :6, 211 force_fdx:1, 212 fdx_pin_en:1; 213 volatile u_int8_t :6, 214 multi_ia:1, 215 :1; 216 volatile u_int8_t :3, 217 mc_all:1, 218 :4; 219 }; 220 221 /* 222 * Multicast setup command. 223 */ 224 #define MAXMCADDR 80 225 struct fxp_cb_mcs { 226 volatile u_int16_t cb_status; 227 volatile u_int16_t cb_command; 228 volatile u_int32_t link_addr; 229 volatile u_int16_t mc_cnt; 230 volatile u_int8_t mc_addr[MAXMCADDR][6]; 231 }; 232 233 /* 234 * Transmit command. 235 */ 236 struct fxp_cb_tx { 237 volatile u_int16_t cb_status; 238 volatile u_int16_t cb_command; 239 volatile u_int32_t link_addr; 240 volatile u_int32_t tbd_array_addr; 241 volatile u_int16_t byte_count; 242 volatile u_int8_t tx_threshold; 243 volatile u_int8_t tbd_number; 244 }; 245 246 /* 247 * Transmit buffer descriptors. 248 */ 249 struct fxp_tbd { 250 volatile u_int32_t tb_addr; 251 volatile u_int32_t tb_size; 252 }; 253 254 /* 255 * Control Block (CB) definitions 256 */ 257 258 /* status */ 259 #define FXP_CB_STATUS_OK 0x2000 260 #define FXP_CB_STATUS_C 0x8000 261 262 /* commands */ 263 #define FXP_CB_COMMAND_NOP 0x0 264 #define FXP_CB_COMMAND_IAS 0x1 265 #define FXP_CB_COMMAND_CONFIG 0x2 266 #define FXP_CB_COMMAND_MCAS 0x3 267 #define FXP_CB_COMMAND_XMIT 0x4 268 #define FXP_CB_COMMAND_RESRV 0x5 269 #define FXP_CB_COMMAND_DUMP 0x6 270 #define FXP_CB_COMMAND_DIAG 0x7 271 272 /* command flags */ 273 #define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 274 #define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 275 #define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 276 #define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 277 278 /* 279 * Receive Frame Area. 280 * 281 * NOTE! The RFA will NOT be aligned on a 4-byte boundary in the DMA 282 * area! To prevent EGCS from optimizing the copy of link_addr and 283 * rbd_addr (which would cause an unaligned access fault on RISC systems), 284 * we must make them an array of bytes! 285 */ 286 struct fxp_rfa { 287 volatile u_int16_t rfa_status; 288 volatile u_int16_t rfa_control; 289 volatile u_int8_t link_addr[4]; 290 volatile u_int8_t rbd_addr[4]; 291 volatile u_int16_t actual_size; 292 volatile u_int16_t size; 293 }; 294 295 #define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 296 #define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 297 #define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 298 #define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 299 #define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 300 #define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 301 #define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 302 #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 303 #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 304 #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 305 #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 306 307 #define FXP_RFA_CONTROL_SF 0x0008 /* simple/flexible memory mode */ 308 #define FXP_RFA_CONTROL_H 0x0010 /* header RFD */ 309 #define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 310 #define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 311 312 /* 313 * Statistics dump area definitions 314 */ 315 struct fxp_stats { 316 volatile u_int32_t tx_good; 317 volatile u_int32_t tx_maxcols; 318 volatile u_int32_t tx_latecols; 319 volatile u_int32_t tx_underruns; 320 volatile u_int32_t tx_lostcrs; 321 volatile u_int32_t tx_deffered; 322 volatile u_int32_t tx_single_collisions; 323 volatile u_int32_t tx_multiple_collisions; 324 volatile u_int32_t tx_total_collisions; 325 volatile u_int32_t rx_good; 326 volatile u_int32_t rx_crc_errors; 327 volatile u_int32_t rx_alignment_errors; 328 volatile u_int32_t rx_rnr_errors; 329 volatile u_int32_t rx_overrun_errors; 330 volatile u_int32_t rx_cdt_errors; 331 volatile u_int32_t rx_shortframes; 332 volatile u_int32_t completion_status; 333 }; 334 #define FXP_STATS_DUMP_COMPLETE 0xa005 335 #define FXP_STATS_DR_COMPLETE 0xa007 336 337 /* 338 * Serial EEPROM control register bits 339 */ 340 #define FXP_EEPROM_EESK 0x01 /* shift clock */ 341 #define FXP_EEPROM_EECS 0x02 /* chip select */ 342 #define FXP_EEPROM_EEDI 0x04 /* data in */ 343 #define FXP_EEPROM_EEDO 0x08 /* data out */ 344 345 /* 346 * Serial EEPROM opcodes, including start bit 347 */ 348 #define FXP_EEPROM_OPC_ERASE 0x4 349 #define FXP_EEPROM_OPC_WRITE 0x5 350 #define FXP_EEPROM_OPC_READ 0x6 351 352 /* 353 * Management Data Interface opcodes 354 */ 355 #define FXP_MDI_WRITE 0x1 356 #define FXP_MDI_READ 0x2 357 358 /* 359 * PHY device types (from EEPROM) 360 */ 361 #define FXP_PHY_NONE 0 362 #define FXP_PHY_82553A 1 363 #define FXP_PHY_82553C 2 364 #define FXP_PHY_82503 3 365 #define FXP_PHY_DP83840 4 366 #define FXP_PHY_80C240 5 367 #define FXP_PHY_80C24 6 368 #define FXP_PHY_82555 7 369 #define FXP_PHY_DP83840A 10 370
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