i82557reg.h revision 1.7
1 /* $NetBSD: i82557reg.h,v 1.7 2001/05/22 01:23:25 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxpreg.h,v 1.11 1997/09/29 11:27:42 davidg Exp 67 */ 68 69 #define FXP_VENDORID_INTEL 0x8086 70 #define FXP_DEVICEID_i82557 0x1229 71 72 #define FXP_PCI_MMBA 0x10 73 #define FXP_PCI_IOBA 0x14 74 75 /* 76 * Control/status registers. 77 */ 78 #define FXP_CSR_SCB_RUSCUS 0x00 /* scb_rus/scb_cus (1 byte) */ 79 #define FXP_CSR_SCB_STATACK 0x01 /* scb_statack (1 byte) */ 80 #define FXP_CSR_SCB_COMMAND 0x02 /* scb_command (1 byte) */ 81 #define FXP_CSR_SCB_INTRCNTL 0x03 /* scb_intrcntl (1 byte) */ 82 #define FXP_CSR_SCB_GENERAL 0x04 /* scb_general (4 bytes) */ 83 #define FXP_CSR_PORT 0x08 /* port (4 bytes) */ 84 #define FXP_CSR_FLASHCONTROL 0x0c /* flash control (2 bytes) */ 85 #define FXP_CSR_EEPROMCONTROL 0x0e /* eeprom control (2 bytes) */ 86 #define FXP_CSR_MDICONTROL 0x10 /* mdi control (4 bytes) */ 87 #define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */ 88 89 /* 90 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 91 * 92 * volatile u_int8_t :2, 93 * scb_rus:4, 94 * scb_cus:2; 95 */ 96 97 #define FXP_PORT_SOFTWARE_RESET 0 98 #define FXP_PORT_SELFTEST 1 99 #define FXP_PORT_SELECTIVE_RESET 2 100 #define FXP_PORT_DUMP 3 101 102 #define FXP_SCB_RUS_IDLE 0 103 #define FXP_SCB_RUS_SUSPENDED 1 104 #define FXP_SCB_RUS_NORESOURCES 2 105 #define FXP_SCB_RUS_READY 4 106 #define FXP_SCB_RUS_SUSP_NORBDS 9 107 #define FXP_SCB_RUS_NORES_NORBDS 10 108 #define FXP_SCB_RUS_READY_NORBDS 12 109 110 #define FXP_SCB_CUS_IDLE 0 111 #define FXP_SCB_CUS_SUSPENDED 1 112 #define FXP_SCB_CUS_ACTIVE 2 113 114 #define FXP_SCB_INTR_DISABLE 0x01 /* disable all interrupts */ 115 #define FXP_SCB_INTR_SWI 0x02 /* generate SWI */ 116 #define FXP_SCB_INTMASK_FCP 0x04 117 #define FXP_SCB_INTMASK_ER 0x08 118 #define FXP_SCB_INTMASK_RNR 0x10 119 #define FXP_SCB_INTMASK_CNA 0x20 120 #define FXP_SCB_INTMASK_FR 0x40 121 #define FXP_SCB_INTMASK_CXTNO 0x80 122 123 #define FXP_SCB_STATACK_FCP 0x01 /* flow control pause */ 124 #define FXP_SCB_STATACK_ER 0x02 /* early receive */ 125 #define FXP_SCB_STATACK_SWI 0x04 126 #define FXP_SCB_STATACK_MDI 0x08 127 #define FXP_SCB_STATACK_RNR 0x10 128 #define FXP_SCB_STATACK_CNA 0x20 129 #define FXP_SCB_STATACK_FR 0x40 130 #define FXP_SCB_STATACK_CXTNO 0x80 131 132 #define FXP_SCB_COMMAND_CU_NOP 0x00 133 #define FXP_SCB_COMMAND_CU_START 0x10 134 #define FXP_SCB_COMMAND_CU_RESUME 0x20 135 #define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 136 #define FXP_SCB_COMMAND_CU_DUMP 0x50 137 #define FXP_SCB_COMMAND_CU_BASE 0x60 138 #define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 139 140 #define FXP_SCB_COMMAND_RU_NOP 0 141 #define FXP_SCB_COMMAND_RU_START 1 142 #define FXP_SCB_COMMAND_RU_RESUME 2 143 #define FXP_SCB_COMMAND_RU_ABORT 4 144 #define FXP_SCB_COMMAND_RU_LOADHDS 5 145 #define FXP_SCB_COMMAND_RU_BASE 6 146 #define FXP_SCB_COMMAND_RU_RBDRESUME 7 147 148 /* 149 * Command block definitions 150 */ 151 152 /* 153 * NOP command. 154 */ 155 struct fxp_cb_nop { 156 volatile u_int16_t cb_status; 157 volatile u_int16_t cb_command; 158 volatile u_int32_t link_addr; 159 }; 160 161 /* 162 * Individual Address command. 163 */ 164 struct fxp_cb_ias { 165 volatile u_int16_t cb_status; 166 volatile u_int16_t cb_command; 167 volatile u_int32_t link_addr; 168 volatile u_int8_t macaddr[6]; 169 }; 170 171 #if BYTE_ORDER == LITTLE_ENDIAN 172 #define __FXP_BITFIELD2(a, b) a, b 173 #define __FXP_BITFIELD3(a, b, c) a, b, c 174 #define __FXP_BITFIELD4(a, b, c, d) a, b, c, d 175 #define __FXP_BITFIELD6(a, b, c, d, e, f) a, b, c, d, e, f 176 #else 177 #define __FXP_BITFIELD2(a, b) b, a 178 #define __FXP_BITFIELD3(a, b, c) c, b, a 179 #define __FXP_BITFIELD4(a, b, c, d) d, c, b, a 180 #define __FXP_BITFIELD6(a, b, c, d, e, f) f, e, d, c, b, a 181 #endif 182 183 /* 184 * Configure command. 185 */ 186 struct fxp_cb_config { 187 volatile u_int16_t cb_status; 188 volatile u_int16_t cb_command; 189 volatile u_int32_t link_addr; 190 volatile u_int8_t __FXP_BITFIELD2(byte_count:6, :2); 191 volatile u_int8_t __FXP_BITFIELD3(rx_fifo_limit:4, 192 tx_fifo_limit:3, 193 :1); 194 volatile u_int8_t adaptive_ifs; 195 volatile u_int8_t :8; 196 volatile u_int8_t __FXP_BITFIELD2(rx_dma_bytecount:7, :1); 197 volatile u_int8_t __FXP_BITFIELD2(tx_dma_bytecount:7, 198 dma_bce:1); 199 volatile u_int8_t __FXP_BITFIELD6(late_scb:1, :1, 200 tno_int:1, 201 ci_int:1, :3, 202 save_bf:1); 203 volatile u_int8_t __FXP_BITFIELD3(disc_short_rx:1, 204 underrun_retry:2, :5); 205 volatile u_int8_t __FXP_BITFIELD2(mediatype:1, :7); 206 volatile u_int8_t :8; 207 volatile u_int8_t __FXP_BITFIELD4(:3, 208 nsai:1, 209 preamble_length:2, 210 loopback:2); 211 volatile u_int8_t __FXP_BITFIELD2(linear_priority:3, :5); 212 volatile u_int8_t __FXP_BITFIELD3(linear_pri_mode:1, :3, 213 interfrm_spacing:4); 214 volatile u_int8_t :8; 215 volatile u_int8_t :8; 216 volatile u_int8_t __FXP_BITFIELD4(promiscuous:1, 217 bcast_disable:1, :5, 218 crscdt:1); 219 volatile u_int8_t :8; 220 volatile u_int8_t :8; 221 volatile u_int8_t __FXP_BITFIELD4(stripping:1, 222 padding:1, 223 rcv_crc_xfer:1, :5); 224 volatile u_int8_t __FXP_BITFIELD3(:6, force_fdx:1, 225 fdx_pin_en:1); 226 volatile u_int8_t __FXP_BITFIELD3(:6, multi_ia:1, :1); 227 volatile u_int8_t __FXP_BITFIELD3(:3, mc_all:1, :4); 228 }; 229 230 /* 231 * Multicast setup command. 232 */ 233 #define MAXMCADDR 80 234 struct fxp_cb_mcs { 235 volatile u_int16_t cb_status; 236 volatile u_int16_t cb_command; 237 volatile u_int32_t link_addr; 238 volatile u_int16_t mc_cnt; 239 volatile u_int8_t mc_addr[MAXMCADDR][6]; 240 }; 241 242 /* 243 * Transmit command. 244 */ 245 struct fxp_cb_tx { 246 volatile u_int16_t cb_status; 247 volatile u_int16_t cb_command; 248 volatile u_int32_t link_addr; 249 volatile u_int32_t tbd_array_addr; 250 volatile u_int16_t byte_count; 251 volatile u_int8_t tx_threshold; 252 volatile u_int8_t tbd_number; 253 /* 254 * If using the extended TxCB feature, there is a 255 * single TBD right here. We handle this in the 256 * fxp_control_data in i82557var.h. 257 */ 258 }; 259 260 /* 261 * Transmit buffer descriptors. 262 */ 263 struct fxp_tbd { 264 volatile u_int32_t tb_addr; 265 volatile u_int32_t tb_size; 266 }; 267 268 /* 269 * Control Block (CB) definitions 270 */ 271 272 /* status */ 273 #define FXP_CB_STATUS_OK 0x2000 274 #define FXP_CB_STATUS_C 0x8000 275 276 /* commands */ 277 #define FXP_CB_COMMAND_NOP 0x0 278 #define FXP_CB_COMMAND_IAS 0x1 279 #define FXP_CB_COMMAND_CONFIG 0x2 280 #define FXP_CB_COMMAND_MCAS 0x3 281 #define FXP_CB_COMMAND_XMIT 0x4 282 #define FXP_CB_COMMAND_RESRV 0x5 283 #define FXP_CB_COMMAND_DUMP 0x6 284 #define FXP_CB_COMMAND_DIAG 0x7 285 286 /* command flags */ 287 #define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 288 #define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 289 #define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 290 #define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 291 292 /* 293 * Receive Frame Area. 294 * 295 * NOTE! The RFA will NOT be aligned on a 4-byte boundary in the DMA 296 * area! To prevent EGCS from optimizing the copy of link_addr and 297 * rbd_addr (which would cause an unaligned access fault on RISC systems), 298 * we must make them an array of bytes! 299 */ 300 struct fxp_rfa { 301 volatile u_int16_t rfa_status; 302 volatile u_int16_t rfa_control; 303 volatile u_int8_t link_addr[4]; 304 volatile u_int8_t rbd_addr[4]; 305 volatile u_int16_t actual_size; 306 volatile u_int16_t size; 307 }; 308 309 #define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 310 #define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 311 #define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 312 #define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 313 #define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 314 #define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 315 #define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 316 #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 317 #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 318 #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 319 #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 320 321 #define FXP_RFA_CONTROL_SF 0x0008 /* simple/flexible memory mode */ 322 #define FXP_RFA_CONTROL_H 0x0010 /* header RFD */ 323 #define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 324 #define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 325 326 /* 327 * Statistics dump area definitions 328 */ 329 struct fxp_stats { 330 volatile u_int32_t tx_good; 331 volatile u_int32_t tx_maxcols; 332 volatile u_int32_t tx_latecols; 333 volatile u_int32_t tx_underruns; 334 volatile u_int32_t tx_lostcrs; 335 volatile u_int32_t tx_deffered; 336 volatile u_int32_t tx_single_collisions; 337 volatile u_int32_t tx_multiple_collisions; 338 volatile u_int32_t tx_total_collisions; 339 volatile u_int32_t rx_good; 340 volatile u_int32_t rx_crc_errors; 341 volatile u_int32_t rx_alignment_errors; 342 volatile u_int32_t rx_rnr_errors; 343 volatile u_int32_t rx_overrun_errors; 344 volatile u_int32_t rx_cdt_errors; 345 volatile u_int32_t rx_shortframes; 346 volatile u_int32_t completion_status; 347 }; 348 #define FXP_STATS_DUMP_COMPLETE 0xa005 349 #define FXP_STATS_DR_COMPLETE 0xa007 350 351 /* 352 * Serial EEPROM control register bits 353 */ 354 #define FXP_EEPROM_EESK 0x01 /* shift clock */ 355 #define FXP_EEPROM_EECS 0x02 /* chip select */ 356 #define FXP_EEPROM_EEDI 0x04 /* data in */ 357 #define FXP_EEPROM_EEDO 0x08 /* data out */ 358 359 /* 360 * Serial EEPROM opcodes, including start bit 361 */ 362 #define FXP_EEPROM_OPC_ERASE 0x4 363 #define FXP_EEPROM_OPC_WRITE 0x5 364 #define FXP_EEPROM_OPC_READ 0x6 365 366 /* 367 * Management Data Interface opcodes 368 */ 369 #define FXP_MDI_WRITE 0x1 370 #define FXP_MDI_READ 0x2 371 372 /* 373 * PHY device types (from EEPROM) 374 */ 375 #define FXP_PHY_DEVICE_MASK 0x3f00 376 #define FXP_PHY_DEVICE_SHIFT 8 377 #define FXP_PHY_DEVADDR_MASK 0x00ff 378 #define FXP_PHY_SERIAL_ONLY 0x8000 379 #define FXP_PHY_NONE 0 380 #define FXP_PHY_82553A 1 381 #define FXP_PHY_82553C 2 382 #define FXP_PHY_82503 3 383 #define FXP_PHY_DP83840 4 384 #define FXP_PHY_80C240 5 385 #define FXP_PHY_80C24 6 386 #define FXP_PHY_82555 7 387 #define FXP_PHY_DP83840A 10 388 #define FXP_PHY_DP82555B 11 389 390 /* 391 * PCI revisions. 392 */ 393 #define FXP_REV_82558_A4 4 394 #define FXP_REV_82558_B0 5 395 #define FXP_REV_82559_A0 8 396 #define FXP_REV_82559S_A 9 397 #define FXP_REV_82550 12 398 #define FXP_REV_82550_C 13 399
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