i82557reg.h revision 1.9
1 /* $NetBSD: i82557reg.h,v 1.9 2001/05/25 08:54:40 hannken Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxpreg.h,v 1.24 2001/05/15 18:52:40 jlemon Exp 68 */ 69 70 #define FXP_PCI_MMBA 0x10 71 #define FXP_PCI_IOBA 0x14 72 73 /* 74 * Control/status registers. 75 */ 76 #define FXP_CSR_SCB_RUSCUS 0x00 /* scb_rus/scb_cus (1 byte) */ 77 #define FXP_CSR_SCB_STATACK 0x01 /* scb_statack (1 byte) */ 78 #define FXP_CSR_SCB_COMMAND 0x02 /* scb_command (1 byte) */ 79 #define FXP_CSR_SCB_INTRCNTL 0x03 /* scb_intrcntl (1 byte) */ 80 #define FXP_CSR_SCB_GENERAL 0x04 /* scb_general (4 bytes) */ 81 #define FXP_CSR_PORT 0x08 /* port (4 bytes) */ 82 #define FXP_CSR_FLASHCONTROL 0x0c /* flash control (2 bytes) */ 83 #define FXP_CSR_EEPROMCONTROL 0x0e /* eeprom control (2 bytes) */ 84 #define FXP_CSR_MDICONTROL 0x10 /* mdi control (4 bytes) */ 85 #define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */ 86 87 /* 88 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 89 * 90 * volatile u_int8_t :2, 91 * scb_rus:4, 92 * scb_cus:2; 93 */ 94 95 #define FXP_PORT_SOFTWARE_RESET 0 96 #define FXP_PORT_SELFTEST 1 97 #define FXP_PORT_SELECTIVE_RESET 2 98 #define FXP_PORT_DUMP 3 99 100 #define FXP_SCB_RUS_IDLE 0 101 #define FXP_SCB_RUS_SUSPENDED 1 102 #define FXP_SCB_RUS_NORESOURCES 2 103 #define FXP_SCB_RUS_READY 4 104 #define FXP_SCB_RUS_SUSP_NORBDS 9 105 #define FXP_SCB_RUS_NORES_NORBDS 10 106 #define FXP_SCB_RUS_READY_NORBDS 12 107 108 #define FXP_SCB_CUS_IDLE 0 109 #define FXP_SCB_CUS_SUSPENDED 1 110 #define FXP_SCB_CUS_ACTIVE 2 111 112 #define FXP_SCB_INTR_DISABLE 0x01 /* disable all interrupts */ 113 #define FXP_SCB_INTR_SWI 0x02 /* generate SWI */ 114 #define FXP_SCB_INTMASK_FCP 0x04 115 #define FXP_SCB_INTMASK_ER 0x08 116 #define FXP_SCB_INTMASK_RNR 0x10 117 #define FXP_SCB_INTMASK_CNA 0x20 118 #define FXP_SCB_INTMASK_FR 0x40 119 #define FXP_SCB_INTMASK_CXTNO 0x80 120 121 #define FXP_SCB_STATACK_FCP 0x01 /* flow control pause */ 122 #define FXP_SCB_STATACK_ER 0x02 /* early receive */ 123 #define FXP_SCB_STATACK_SWI 0x04 124 #define FXP_SCB_STATACK_MDI 0x08 125 #define FXP_SCB_STATACK_RNR 0x10 126 #define FXP_SCB_STATACK_CNA 0x20 127 #define FXP_SCB_STATACK_FR 0x40 128 #define FXP_SCB_STATACK_CXTNO 0x80 129 130 #define FXP_SCB_COMMAND_CU_NOP 0x00 131 #define FXP_SCB_COMMAND_CU_START 0x10 132 #define FXP_SCB_COMMAND_CU_RESUME 0x20 133 #define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 134 #define FXP_SCB_COMMAND_CU_DUMP 0x50 135 #define FXP_SCB_COMMAND_CU_BASE 0x60 136 #define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 137 138 #define FXP_SCB_COMMAND_RU_NOP 0 139 #define FXP_SCB_COMMAND_RU_START 1 140 #define FXP_SCB_COMMAND_RU_RESUME 2 141 #define FXP_SCB_COMMAND_RU_ABORT 4 142 #define FXP_SCB_COMMAND_RU_LOADHDS 5 143 #define FXP_SCB_COMMAND_RU_BASE 6 144 #define FXP_SCB_COMMAND_RU_RBDRESUME 7 145 146 /* 147 * Command block definitions 148 */ 149 150 /* 151 * NOP command. 152 */ 153 struct fxp_cb_nop { 154 volatile u_int16_t cb_status; 155 volatile u_int16_t cb_command; 156 volatile u_int32_t link_addr; 157 }; 158 159 /* 160 * Individual Address command. 161 */ 162 struct fxp_cb_ias { 163 volatile u_int16_t cb_status; 164 volatile u_int16_t cb_command; 165 volatile u_int32_t link_addr; 166 volatile u_int8_t macaddr[6]; 167 }; 168 169 #if BYTE_ORDER == LITTLE_ENDIAN 170 #define __FXP_BITFIELD2(a, b) a, b 171 #define __FXP_BITFIELD3(a, b, c) a, b, c 172 #define __FXP_BITFIELD4(a, b, c, d) a, b, c, d 173 #define __FXP_BITFIELD5(a, b, c, d, e) a, b, c, d, e 174 #define __FXP_BITFIELD6(a, b, c, d, e, f) a, b, c, d, e, f 175 #define __FXP_BITFIELD7(a, b, c, d, e, f, g) a, b, c, d, e, f, g 176 #define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) a, b, c, d, e, f, g, h 177 #else 178 #define __FXP_BITFIELD2(a, b) b, a 179 #define __FXP_BITFIELD3(a, b, c) c, b, a 180 #define __FXP_BITFIELD4(a, b, c, d) d, c, b, a 181 #define __FXP_BITFIELD5(a, b, c, d, e) e, d, c, b, a 182 #define __FXP_BITFIELD6(a, b, c, d, e, f) f, e, d, c, b, a 183 #define __FXP_BITFIELD7(a, b, c, d, e, f, g) g, f, e, d, c, b, a 184 #define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) h, g, f, e, d, c, b, a 185 #endif 186 187 /* 188 * Configure command. 189 */ 190 struct fxp_cb_config { 191 volatile u_int16_t cb_status; 192 volatile u_int16_t cb_command; 193 volatile u_int32_t link_addr; 194 volatile u_int8_t __FXP_BITFIELD2(byte_count:6, :2); 195 volatile u_int8_t __FXP_BITFIELD3(rx_fifo_limit:4, 196 tx_fifo_limit:3, 197 :1); 198 volatile u_int8_t adaptive_ifs; 199 volatile u_int8_t __FXP_BITFIELD5(mwi_enable:1, /* 8,9 */ 200 type_enable:1, /* 8,9 */ 201 read_align_en:1, /* 8,9 */ 202 end_wr_on_cl:1, /* 8,9 */ 203 :4); 204 volatile u_int8_t __FXP_BITFIELD2(rx_dma_bytecount:7, 205 :1); 206 volatile u_int8_t __FXP_BITFIELD2(tx_dma_bytecount:7, 207 dma_mbce:1); 208 volatile u_int8_t __FXP_BITFIELD8(late_scb:1, /* 7 */ 209 direct_dma_dis:1, /* 8,9 */ 210 tno_int_or_tco_en:1, /* 7,9 */ 211 ci_int:1, 212 ext_txcb_dis:1, /* 8,9 */ 213 ext_stats_dis:1, /* 8,9 */ 214 keep_overrun_rx:1, 215 save_bf:1); 216 volatile u_int8_t __FXP_BITFIELD5(disc_short_rx:1, 217 underrun_retry:2, 218 :3, 219 two_frames:1, /* 8,9 */ 220 dyn_tbd:1); /* 8,9 */ 221 volatile u_int8_t __FXP_BITFIELD3(mediatype:1, /* 7 */ 222 :6, 223 csma_dis:1); /* 8,9 */ 224 volatile u_int8_t __FXP_BITFIELD6(tcp_udp_cksum:1,/* 9 */ 225 :3, 226 vlan_tco:1, /* 8,9 */ 227 link_wake_en:1, /* 8,9 */ 228 arp_wake_en:1, /* 8 */ 229 mc_wake_en:1); /* 8 */ 230 volatile u_int8_t __FXP_BITFIELD4(:3, 231 nsai:1, 232 preamble_length:2, 233 loopback:2); 234 volatile u_int8_t __FXP_BITFIELD2(linear_priority:3,/* 7 */ 235 :5); 236 volatile u_int8_t __FXP_BITFIELD3(linear_pri_mode:1,/* 7 */ 237 :3, 238 interfrm_spacing:4); 239 volatile u_int8_t :8; 240 volatile u_int8_t :8; 241 volatile u_int8_t __FXP_BITFIELD8(promiscuous:1, 242 bcast_disable:1, 243 wait_after_win:1, /* 8,9 */ 244 :1, 245 ignore_ul:1, /* 8,9 */ 246 crc16_en:1, /* 9 */ 247 :1, 248 crscdt:1); 249 volatile u_int8_t fc_delay_lsb:8; /* 8,9 */ 250 volatile u_int8_t fc_delay_msb:8; /* 8,9 */ 251 volatile u_int8_t __FXP_BITFIELD6(stripping:1, 252 padding:1, 253 rcv_crc_xfer:1, 254 long_rx_en:1, /* 8,9 */ 255 pri_fc_thresh:3, /* 8,9 */ 256 :1); 257 volatile u_int8_t __FXP_BITFIELD8(ia_wake_en:1, /* 8 */ 258 magic_pkt_dis:1, /* 8,9,!9ER */ 259 tx_fc_dis:1, /* 8,9 */ 260 rx_fc_restop:1, /* 8,9 */ 261 rx_fc_restart:1, /* 8,9 */ 262 fc_filter:1, /* 8,9 */ 263 force_fdx:1, 264 fdx_pin_en:1); 265 volatile u_int8_t __FXP_BITFIELD4(:5, 266 pri_fc_loc:1 /* 8,9 */, 267 multi_ia:1, 268 :1); 269 volatile u_int8_t __FXP_BITFIELD3(:3, mc_all:1, :4); 270 }; 271 272 /* 273 * Multicast setup command. 274 */ 275 #define MAXMCADDR 80 276 struct fxp_cb_mcs { 277 volatile u_int16_t cb_status; 278 volatile u_int16_t cb_command; 279 volatile u_int32_t link_addr; 280 volatile u_int16_t mc_cnt; 281 volatile u_int8_t mc_addr[MAXMCADDR][6]; 282 }; 283 284 /* 285 * Transmit command. 286 */ 287 struct fxp_cb_tx { 288 volatile u_int16_t cb_status; 289 volatile u_int16_t cb_command; 290 volatile u_int32_t link_addr; 291 volatile u_int32_t tbd_array_addr; 292 volatile u_int16_t byte_count; 293 volatile u_int8_t tx_threshold; 294 volatile u_int8_t tbd_number; 295 /* 296 * If using the extended TxCB feature, there is a 297 * two TBDs right here. We handle this in the 298 * fxp_control_data in i82557var.h. 299 */ 300 }; 301 302 /* 303 * Transmit buffer descriptors. 304 */ 305 struct fxp_tbd { 306 volatile u_int32_t tb_addr; 307 volatile u_int32_t tb_size; 308 }; 309 310 /* 311 * Control Block (CB) definitions 312 */ 313 314 /* status */ 315 #define FXP_CB_STATUS_OK 0x2000 316 #define FXP_CB_STATUS_C 0x8000 317 318 /* commands */ 319 #define FXP_CB_COMMAND_NOP 0x0 320 #define FXP_CB_COMMAND_IAS 0x1 321 #define FXP_CB_COMMAND_CONFIG 0x2 322 #define FXP_CB_COMMAND_MCAS 0x3 323 #define FXP_CB_COMMAND_XMIT 0x4 324 #define FXP_CB_COMMAND_RESRV 0x5 325 #define FXP_CB_COMMAND_DUMP 0x6 326 #define FXP_CB_COMMAND_DIAG 0x7 327 328 /* command flags */ 329 #define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 330 #define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 331 #define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 332 #define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 333 334 /* 335 * Receive Frame Area. 336 * 337 * NOTE! The RFA will NOT be aligned on a 4-byte boundary in the DMA 338 * area! To prevent EGCS from optimizing the copy of link_addr and 339 * rbd_addr (which would cause an unaligned access fault on RISC systems), 340 * we must make them an array of bytes! 341 */ 342 struct fxp_rfa { 343 volatile u_int16_t rfa_status; 344 volatile u_int16_t rfa_control; 345 volatile u_int8_t link_addr[4]; 346 volatile u_int8_t rbd_addr[4]; 347 volatile u_int16_t actual_size; 348 volatile u_int16_t size; 349 }; 350 351 #define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 352 #define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 353 #define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 354 #define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 355 #define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 356 #define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 357 #define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 358 #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 359 #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 360 #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 361 #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 362 363 #define FXP_RFA_CONTROL_SF 0x0008 /* simple/flexible memory mode */ 364 #define FXP_RFA_CONTROL_H 0x0010 /* header RFD */ 365 #define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 366 #define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 367 368 /* 369 * Statistics dump area definitions 370 */ 371 struct fxp_stats { 372 volatile u_int32_t tx_good; 373 volatile u_int32_t tx_maxcols; 374 volatile u_int32_t tx_latecols; 375 volatile u_int32_t tx_underruns; 376 volatile u_int32_t tx_lostcrs; 377 volatile u_int32_t tx_deffered; 378 volatile u_int32_t tx_single_collisions; 379 volatile u_int32_t tx_multiple_collisions; 380 volatile u_int32_t tx_total_collisions; 381 volatile u_int32_t rx_good; 382 volatile u_int32_t rx_crc_errors; 383 volatile u_int32_t rx_alignment_errors; 384 volatile u_int32_t rx_rnr_errors; 385 volatile u_int32_t rx_overrun_errors; 386 volatile u_int32_t rx_cdt_errors; 387 volatile u_int32_t rx_shortframes; 388 volatile u_int32_t completion_status; 389 }; 390 #define FXP_STATS_DUMP_COMPLETE 0xa005 391 #define FXP_STATS_DR_COMPLETE 0xa007 392 393 /* 394 * Serial EEPROM control register bits 395 */ 396 #define FXP_EEPROM_EESK 0x01 /* shift clock */ 397 #define FXP_EEPROM_EECS 0x02 /* chip select */ 398 #define FXP_EEPROM_EEDI 0x04 /* data in */ 399 #define FXP_EEPROM_EEDO 0x08 /* data out */ 400 401 /* 402 * Serial EEPROM opcodes, including start bit 403 */ 404 #define FXP_EEPROM_OPC_ERASE 0x4 405 #define FXP_EEPROM_OPC_WRITE 0x5 406 #define FXP_EEPROM_OPC_READ 0x6 407 408 /* 409 * Management Data Interface opcodes 410 */ 411 #define FXP_MDI_WRITE 0x1 412 #define FXP_MDI_READ 0x2 413 414 /* 415 * PHY device types (from EEPROM) 416 */ 417 #define FXP_PHY_DEVICE_MASK 0x3f00 418 #define FXP_PHY_DEVICE_SHIFT 8 419 #define FXP_PHY_DEVADDR_MASK 0x00ff 420 #define FXP_PHY_SERIAL_ONLY 0x8000 421 #define FXP_PHY_NONE 0 422 #define FXP_PHY_82553A 1 423 #define FXP_PHY_82553C 2 424 #define FXP_PHY_82503 3 425 #define FXP_PHY_DP83840 4 426 #define FXP_PHY_80C240 5 427 #define FXP_PHY_80C24 6 428 #define FXP_PHY_82555 7 429 #define FXP_PHY_DP83840A 10 430 #define FXP_PHY_DP82555B 11 431 432 /* 433 * PCI revisions. 434 */ 435 #define FXP_REV_82558_A4 4 436 #define FXP_REV_82558_B0 5 437 #define FXP_REV_82559_A0 8 438 #define FXP_REV_82559S_A 9 439 #define FXP_REV_82550 12 440 #define FXP_REV_82550_C 13 441
Indexes created Wed Oct 01 19:09:53 GMT 2025