i82557var.h revision 1.9
1 /* $NetBSD: i82557var.h,v 1.9 1999/12/12 17:46:36 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxpvar.h,v 1.4 1997/11/29 08:11:01 davidg Exp 67 */ 68 69 /* 70 * Misc. defintions for the Intel i82557 fast Ethernet controller 71 * driver. 72 */ 73 74 /* 75 * Transmit descriptor list size. 76 */ 77 #define FXP_NTXCB 128 78 #define FXP_NTXCB_MASK (FXP_NTXCB - 1) 79 #define FXP_NEXTTX(x) ((x + 1) & FXP_NTXCB_MASK) 80 #define FXP_NTXSEG 16 81 82 /* 83 * Number of receive frame area buffers. These are large, so 84 * choose wisely. 85 */ 86 #define FXP_NRFABUFS 64 87 88 /* 89 * Maximum number of seconds that the reciever can be idle before we 90 * assume it's dead and attempt to reset it by reprogramming the 91 * multicast filter. This is part of a work-around for a bug in the 92 * NIC. See fxp_stats_update(). 93 */ 94 #define FXP_MAX_RX_IDLE 15 95 96 /* 97 * Misc. DMA'd data structures are allocated in a single clump, that 98 * maps to a single DMA segment, to make several things easier (computing 99 * offsets, setting up DMA maps, etc.) 100 */ 101 struct fxp_control_data { 102 /* 103 * The transmit control blocks. The first if these 104 * is also used as the config CB. 105 */ 106 struct fxp_cb_tx fcd_txcbs[FXP_NTXCB]; 107 108 /* 109 * The transmit buffer descriptors. 110 */ 111 struct fxp_tbdlist { 112 struct fxp_tbd tbd_d[FXP_NTXSEG]; 113 } fcd_tbdl[FXP_NTXCB]; 114 115 /* 116 * The configuration CB. 117 */ 118 struct fxp_cb_config fcd_configcb; 119 120 /* 121 * The Individual Address CB. 122 */ 123 struct fxp_cb_ias fcd_iascb; 124 125 /* 126 * The multicast setup CB. 127 */ 128 struct fxp_cb_mcs fcd_mcscb; 129 130 /* 131 * The NIC statistics. 132 */ 133 struct fxp_stats fcd_stats; 134 }; 135 136 #define FXP_CDOFF(x) offsetof(struct fxp_control_data, x) 137 #define FXP_CDTXOFF(x) FXP_CDOFF(fcd_txcbs[(x)]) 138 #define FXP_CDTBDOFF(x) FXP_CDOFF(fcd_tbdl[(x)]) 139 #define FXP_CDCONFIGOFF FXP_CDOFF(fcd_configcb) 140 #define FXP_CDIASOFF FXP_CDOFF(fcd_iascb) 141 #define FXP_CDMCSOFF FXP_CDOFF(fcd_mcscb) 142 #define FXP_CDSTATSOFF FXP_CDOFF(fcd_stats) 143 144 /* 145 * Software state for transmit descriptors. 146 */ 147 struct fxp_txsoft { 148 struct mbuf *txs_mbuf; /* head of mbuf chain */ 149 bus_dmamap_t txs_dmamap; /* our DMA map */ 150 }; 151 152 /* 153 * Software state per device. 154 */ 155 struct fxp_softc { 156 struct device sc_dev; /* generic device structures */ 157 bus_space_tag_t sc_st; /* bus space tag */ 158 bus_space_handle_t sc_sh; /* bus space handle */ 159 bus_dma_tag_t sc_dmat; /* bus dma tag */ 160 struct ethercom sc_ethercom; /* ethernet common part */ 161 void *sc_sdhook; /* shutdown hook */ 162 void *sc_powerhook; /* power hook */ 163 void *sc_ih; /* interrupt handler cookie */ 164 165 struct mii_data sc_mii; /* MII/media information */ 166 167 /* 168 * We create a single DMA map that maps all data structure 169 * overhead, except for RFAs, which are mapped by the 170 * fxp_rxdesc DMA map on a per-mbuf basis. 171 */ 172 bus_dmamap_t sc_dmamap; 173 #define sc_cddma sc_dmamap->dm_segs[0].ds_addr 174 175 /* 176 * Software state for transmit descriptors. 177 */ 178 struct fxp_txsoft sc_txsoft[FXP_NTXCB]; 179 180 struct ifqueue sc_rxq; /* receive buffer queue */ 181 bus_dmamap_t sc_rxmaps[FXP_NRFABUFS]; /* free receive buffer DMA maps */ 182 int sc_rxfree; /* free map index */ 183 int sc_rxidle; /* # of seconds RX has been idle */ 184 185 /* 186 * Control data structures. 187 */ 188 struct fxp_control_data *sc_control_data; 189 190 int sc_flags; /* misc. flags */ 191 192 #define FXPF_WANTINIT 0x01 /* want a re-init */ 193 #define FXPF_MII 0x02 /* device uses MII */ 194 195 int sc_txpending; /* number of TX requests pending */ 196 int sc_txdirty; /* first dirty TX descriptor */ 197 int sc_txlast; /* last used TX descriptor */ 198 199 int phy_primary_addr; /* address of primary PHY */ 200 int phy_primary_device; /* device type of primary PHY */ 201 int phy_10Mbps_only; /* PHY is 10Mbps-only device */ 202 203 int sc_enabled; /* boolean; power enabled on interface */ 204 int (*sc_enable) __P((struct fxp_softc *)); 205 void (*sc_disable) __P((struct fxp_softc *)); 206 207 int sc_eeprom_size; /* log2 size of EEPROM */ 208 #if NRND > 0 209 rndsource_element_t rnd_source; /* random source */ 210 #endif 211 212 }; 213 214 #define FXP_RXMAP_GET(sc) ((sc)->sc_rxmaps[(sc)->sc_rxfree++]) 215 #define FXP_RXMAP_PUT(sc, map) (sc)->sc_rxmaps[--(sc)->sc_rxfree] = (map) 216 217 #define FXP_CDTXADDR(sc, x) ((sc)->sc_cddma + FXP_CDTXOFF((x))) 218 #define FXP_CDTBDADDR(sc, x) ((sc)->sc_cddma + FXP_CDTBDOFF((x))) 219 220 #define FXP_CDTX(sc, x) (&(sc)->sc_control_data->fcd_txcbs[(x)]) 221 #define FXP_CDTBD(sc, x) (&(sc)->sc_control_data->fcd_tbdl[(x)]) 222 223 #define FXP_DSTX(sc, x) (&(sc)->sc_txsoft[(x)]) 224 225 #define FXP_CDTXSYNC(sc, x, ops) \ 226 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 227 FXP_CDTXOFF((x)), sizeof(struct fxp_cb_tx), (ops)) 228 229 #define FXP_CDTBDSYNC(sc, x, ops) \ 230 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 231 FXP_CDTBDOFF((x)), sizeof(struct fxp_tbdlist), (ops)) 232 233 #define FXP_CDCONFIGSYNC(sc, ops) \ 234 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 235 FXP_CDCONFIGOFF, sizeof(struct fxp_cb_config), (ops)) 236 237 #define FXP_CDIASSYNC(sc, ops) \ 238 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 239 FXP_CDIASOFF, sizeof(struct fxp_cb_ias), (ops)) 240 241 #define FXP_CDMCSSYNC(sc, ops) \ 242 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \ 243 FXP_CDMCSOFF, sizeof(struct fxp_cb_mcs), (ops)) 244 245 #define FXP_RXBUFSIZE(m) ((m)->m_ext.ext_size - \ 246 (sizeof(struct fxp_rfa) + \ 247 RFA_ALIGNMENT_FUDGE)) 248 249 #define FXP_RFASYNC(sc, m, ops) \ 250 bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t), \ 251 RFA_ALIGNMENT_FUDGE, sizeof(struct fxp_rfa), (ops)) 252 253 #define FXP_RXBUFSYNC(sc, m, ops) \ 254 bus_dmamap_sync((sc)->sc_dmat, M_GETCTX((m), bus_dmamap_t), \ 255 RFA_ALIGNMENT_FUDGE + sizeof(struct fxp_rfa), \ 256 FXP_RXBUFSIZE((m)), (ops)) 257 258 #define FXP_MTORFA(m) (struct fxp_rfa *)((m)->m_ext.ext_buf + \ 259 RFA_ALIGNMENT_FUDGE) 260 261 #define FXP_INIT_RFABUF(sc, m) \ 262 do { \ 263 bus_dmamap_t __rxmap = M_GETCTX((m), bus_dmamap_t); \ 264 struct mbuf *__p_m; \ 265 struct fxp_rfa *__rfa, *__p_rfa; \ 266 u_int32_t __v; \ 267 \ 268 (m)->m_data = (m)->m_ext.ext_buf + sizeof(struct fxp_rfa) + \ 269 RFA_ALIGNMENT_FUDGE; \ 270 \ 271 __rfa = FXP_MTORFA((m)); \ 272 __rfa->size = htole16(FXP_RXBUFSIZE((m))); \ 273 /* BIG_ENDIAN: no need to swap to store 0 */ \ 274 __rfa->rfa_status = 0; \ 275 __rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); \ 276 /* BIG_ENDIAN: no need to swap to store 0 */ \ 277 __rfa->actual_size = 0; \ 278 \ 279 /* NOTE: the RFA is misaligned, so we must copy. */ \ 280 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ \ 281 __v = 0xffffffff; \ 282 memcpy((void *)&__rfa->link_addr, &__v, sizeof(__v)); \ 283 memcpy((void *)&__rfa->rbd_addr, &__v, sizeof(__v)); \ 284 \ 285 FXP_RFASYNC((sc), (m), \ 286 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 287 \ 288 FXP_RXBUFSYNC((sc), (m), BUS_DMASYNC_PREREAD); \ 289 \ 290 if ((__p_m = (sc)->sc_rxq.ifq_tail) != NULL) { \ 291 __p_rfa = FXP_MTORFA(__p_m); \ 292 __v = htole32(__rxmap->dm_segs[0].ds_addr + \ 293 RFA_ALIGNMENT_FUDGE); \ 294 FXP_RFASYNC((sc), __p_m, \ 295 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); \ 296 memcpy((void *)&__p_rfa->link_addr, &__v, \ 297 sizeof(__v)); \ 298 __p_rfa->rfa_control &= htole16(~FXP_RFA_CONTROL_EL); \ 299 FXP_RFASYNC((sc), __p_m, \ 300 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 301 } \ 302 IF_ENQUEUE(&(sc)->sc_rxq, (m)); \ 303 } while (0) 304 305 /* Macros to ease CSR access. */ 306 #define CSR_READ_1(sc, reg) \ 307 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 308 #define CSR_READ_2(sc, reg) \ 309 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 310 #define CSR_READ_4(sc, reg) \ 311 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 312 #define CSR_WRITE_1(sc, reg, val) \ 313 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 314 #define CSR_WRITE_2(sc, reg, val) \ 315 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 316 #define CSR_WRITE_4(sc, reg, val) \ 317 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 318 319 void fxp_attach __P((struct fxp_softc *)); 320 int fxp_intr __P((void *)); 321 322 int fxp_enable __P((struct fxp_softc*)); 323 void fxp_disable __P((struct fxp_softc*)); 324 325
Indexes created Tue Sep 30 07:10:03 GMT 2025