i82595reg.h revision 1.7 1 1.7 perry /* $NetBSD: i82595reg.h,v 1.7 2005/02/27 00:27:01 perry Exp $ */
2 1.1 is
3 1.3 is /*-
4 1.4 is * Copyright (c) 1996 The NetBSD Foundation, Inc.
5 1.1 is * All rights reserved.
6 1.1 is *
7 1.3 is * This code is derived from software contributed to The NetBSD Foundation
8 1.3 is * by Ignatios Souvatzis.
9 1.3 is *
10 1.1 is * Redistribution and use in source and binary forms, with or without
11 1.1 is * modification, are permitted provided that the following conditions
12 1.1 is * are met:
13 1.1 is * 1. Redistributions of source code must retain the above copyright
14 1.1 is * notice, this list of conditions and the following disclaimer.
15 1.1 is * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 is * notice, this list of conditions and the following disclaimer in the
17 1.1 is * documentation and/or other materials provided with the distribution.
18 1.1 is * 3. All advertising materials mentioning features or use of this software
19 1.1 is * must display the following acknowledgement:
20 1.3 is * This product includes software developed by the NetBSD
21 1.3 is * Foundation, Inc. and its contributors.
22 1.3 is * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.3 is * contributors may be used to endorse or promote products derived
24 1.3 is * from this software without specific prior written permission.
25 1.1 is *
26 1.3 is * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.3 is * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.3 is * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.3 is * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.3 is * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.3 is * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.3 is * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.3 is * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.3 is * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.3 is * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.3 is * POSSIBILITY OF SUCH DAMAGE.
37 1.1 is */
38 1.1 is
39 1.1 is /*
40 1.1 is * Intel 82595 Ethernet chip register, bit, and structure definitions.
41 1.1 is *
42 1.7 perry * Written by is with reference to Intel's i82595FX data sheet, with some
43 1.1 is * clarification coming from looking at the Clarkson Packet Driver code for this
44 1.1 is * chip written by Russ Nelson and others;
45 1.1 is *
46 1.1 is * and
47 1.1 is *
48 1.1 is * configuration EEPROM layout. Written with reference to Intels
49 1.1 is * public "LAN595 Hardware and Software Specifications" document.
50 1.1 is */
51 1.1 is
52 1.1 is /* registers */
53 1.1 is
54 1.1 is /* bank0 */
55 1.1 is
56 1.1 is #define COMMAND_REG 0 /* available in any bank */
57 1.1 is
58 1.1 is #define MC_SETUP_CMD 0x03
59 1.1 is #define XMT_CMD 0x04
60 1.1 is #define TDR_CMD 0x05
61 1.1 is #define DUMP_CMD 0x06
62 1.1 is #define DIAG_CMD 0x07
63 1.1 is #define RCV_ENABLE_CMD 0x08
64 1.1 is #define RCV_DISABLE_CMD 0x0a
65 1.1 is #define RCV_STOP_CMD 0x0b
66 1.1 is #define RESET_CMD 0x0e
67 1.1 is #define TRISTATE_CMD 0x16
68 1.1 is #define NO_TRISTATE_CMD 0x17
69 1.1 is #define POWER_DOWN_CMD 0x18
70 1.1 is #define SLEEP_MODE_CMD 0x19
71 1.1 is #define NEGOTIATE_CMD 0x1a
72 1.1 is #define RESUME_XMT_CMD 0x1c
73 1.1 is #define SEL_RESET_CMD 0x1e
74 1.1 is #define BANK_SEL(n) (n<<6) /* 0, 1, 2 */
75 1.1 is
76 1.1 is #define STATUS_REG 1
77 1.1 is
78 1.1 is #define RX_STP_INT 0x01
79 1.1 is #define RX_INT 0x02
80 1.1 is #define TX_INT 0x04
81 1.1 is #define EXEC_INT 0x08
82 1.1 is #define EXEC_STATUS 0x30
83 1.1 is
84 1.1 is #define ID_REG 2
85 1.1 is
86 1.1 is #define ID_REG_MASK 0x2c
87 1.1 is #define ID_REG_SIG 0x24
88 1.1 is #define R_ROBIN_BITS 0xc0
89 1.1 is #define R_ROBIN_SHIFT 6
90 1.1 is #define AUTO_ENABLE 0x10
91 1.1 is
92 1.1 is #define INT_MASK_REG 3
93 1.1 is
94 1.1 is #define RX_STOP_BIT 0x01
95 1.1 is #define RX_BIT 0x02
96 1.1 is #define TX_BIT 0x04
97 1.1 is #define EXEC_BIT 0x08
98 1.1 is #define ALL_INTS 0x0f
99 1.1 is
100 1.1 is #define RCV_START_LOW 4
101 1.1 is #define RCV_START_HIGH 5
102 1.1 is
103 1.1 is #define RCV_STOP_LOW 6
104 1.1 is #define RCV_STOP_HIGH 7
105 1.1 is
106 1.5 is #define RCV_COPY_THRESHOLD 8 /* byte */
107 1.5 is
108 1.1 is #define XMT_ADDR_REG 0x0a
109 1.1 is #define HOST_ADDR_REG 0x0c
110 1.1 is #define MEM_PORT_REG 0x0e
111 1.1 is
112 1.1 is /* -------------------- bank1 -------------------- */
113 1.1 is
114 1.1 is #define REG1 1
115 1.1 is
116 1.1 is #define WORD_WIDTH 0x02
117 1.1 is #define INT_ENABLE 0x80
118 1.1 is
119 1.1 is #define INT_NO_REG 2
120 1.1 is
121 1.1 is #define RCV_LOWER_LIMIT_REG 8
122 1.1 is #define RCV_UPPER_LIMIT_REG 9
123 1.1 is
124 1.1 is #define XMT_LOWER_LIMIT_REG 10
125 1.1 is #define XMT_UPPER_LIMIT_REG 11
126 1.1 is
127 1.1 is /* bank2 */
128 1.1 is
129 1.1 is /* reg1, apparently */
130 1.1 is
131 1.6 wiz #define XMT_CHAIN_INT 0x20 /* interrupt at end of xmt chain */
132 1.1 is #define XMT_CHAIN_ERRSTOP 0x40 /* int at end of chain even if err */
133 1.1 is #define RCV_DISCARD_BAD 0x80 /* Throw bad frames away and continue */
134 1.1 is
135 1.1 is #define RECV_MODES_REG 2
136 1.1 is
137 1.1 is #define PROMISC_MODE 0x01
138 1.2 is #define NO_BRDCST 0x02
139 1.1 is #define NO_RX_CRC 0x04
140 1.1 is #define NO_ADD_INS 0x10
141 1.1 is #define MULTI_IA 0x20
142 1.1 is
143 1.2 is #define MATCH_ID (NO_ADD_INS | NO_RX_CRC | NO_BRDCST)
144 1.1 is #define MATCH_BRDCST (NO_ADD_INS | NO_RX_CRC)
145 1.2 is #define MATCH_MULTI (NO_ADD_INS | NO_RX_CRC | MULTI_IA)
146 1.2 is #define MATCH_ALL (NO_ADD_INS | NO_RX_CRC | PROMISC_MODE)
147 1.1 is
148 1.1 is #define MEDIA_SELECT 3
149 1.1 is
150 1.1 is #define TPE_BIT 0x04
151 1.1 is #define BNC_BIT 0x20
152 1.1 is #define TEST_MODE_MASK 0x3f
153 1.1 is
154 1.1 is #define I_ADD(n) (n+4) /* 0..5 -> 4..9 */
155 1.1 is
156 1.1 is #define EEPROM_REG 10
157 1.1 is
158 1.1 is #define EEDO 8
159 1.1 is #define EEDI 4
160 1.1 is #define EECS 2
161 1.1 is #define EESK 1
162 1.1 is
163 1.1 is /*
164 1.1 is * EEPROM layout. Written with reference to Intels public "LAN595 Hardware and
165 1.1 is * Software Specifications" document.
166 1.1 is */
167 1.1 is
168 1.1 is #define EEPPW0 0
169 1.1 is #define EEPP_BusWidth 0x0004
170 1.1 is #define EEPP_FlashAdrs 0x0038
171 1.1 is #define EEPP_FLASHTRANSFORM {-1, -1, 0xC8000, 0xCC000, 0xD0000, \
172 1.1 is 0xD4000, 0xD8000, 0xDC000}
173 1.1 is #define EEPP_AutoIO 0x0040
174 1.1 is #define EEPP_IOMapping 0xfc00
175 1.1 is
176 1.1 is #define EEPPW1 1
177 1.1 is #define EEPP_Int 0x0007
178 1.1 is #define EEPP_INTMAP {3, 5, 9, 10, 11, -1, -1, -1}
179 1.1 is #define EEPP_RINTMAP {0xff, 0xff, 0x02, 0x00, 0xff, 0x01, 0xff, \
180 1.1 is 0xff, 0xff, 0x02, 0x03, 0x04 }
181 1.1 is
182 1.1 is #define EEPP_LinkInteg 0x0008
183 1.1 is #define EEPP_PolarCorr 0x0010
184 1.1 is #define EEPP_AuiTpe 0x0020
185 1.1 is #define EEPP_Jabber 0x0040
186 1.1 is #define EEPP_AutoPort 0x0080
187 1.1 is #define EEPP_SmOut 0x0100
188 1.1 is #define EEPP_BootFls 0x0200
189 1.1 is #define EEPP_DramSize 0x1000
190 1.1 is #define EEPP_AltReady 0x2000
191 1.1 is
192 1.1 is #define EEPPEther2 2
193 1.1 is #define EEPPEther1 3
194 1.1 is #define EEPPEther0 4
195 1.1 is
196 1.1 is #define EEPPEther2a 0x3c
197 1.1 is #define EEPPEther1a 0x3d
198 1.1 is #define EEPPEther0a 0x3e
199 1.1 is
200 1.1 is #define EEPPW5 5
201 1.1 is #define EEPP_BncTpe 0x0001
202 1.1 is #define EEPP_RomSlct 0x0006 /* none, NetWare, NDIS, rsrvd. */
203 1.1 is #define EEPP_NumConn 0x0008 /* 0=2, 1=3 */
204 1.1 is
205 1.1 is #define EEPW6 6
206 1.1 is #define EEPP_BoardRev 0x00FF
207 1.1 is
208 1.1 is #define EEPP_LENGTH 0x40
209 1.1 is #define EEPP_CHKSUM 0xBABA /* Intel claim 0x0, but this seems to be wrong */
210 1.5 is
211 1.5 is #define RCV_NO_RSC_REG 11
212 1.5 is /* How many packets were dropped due to insufficient space */
213 1.5 is
214 1.5 is /* ---- xmt /rcv /exec buffer format ---- */
215 1.1 is
216 1.1 is #define I595_XMT_HDRLEN 8
217 1.1 is
218 1.1 is #define CMD_MASK 0x001f
219 1.1 is #define TX_DONE 0x0080
220 1.1 is #define CHAIN 0x8000
221 1.1 is
222 1.1 is #define XMT_STATUS 0x02
223 1.1 is #define XMT_CHAIN 0x04
224 1.1 is #define XMT_COUNT 0x06
225 1.1 is
226 1.1 is #define I595_RCV_HDRLEN 8
227 1.1 is
228 1.1 is #define RCV_DONE 0x0008
229 1.1 is #define RX_OK 0x2000
230 1.1 is #define RX_ERR 0x0d81
231 1.1 is
232 1.1 is
233