i82596.c revision 1.25
1 /* $NetBSD: i82596.c,v 1.25 2009/05/10 04:26:19 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Jochen Kunz. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Jochen Kunz may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY JOCHEN KUNZ 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL JOCHEN KUNZ 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the Intel i82596CA and i82596DX/SX 10MBit/s Ethernet chips. 34 * 35 * It operates the i82596 in 32-Bit Linear Mode, opposed to the old i82586 36 * ie(4) driver (src/sys/dev/ic/i82586.c), that degrades the i82596 to 37 * i82586 compatibility mode. 38 * 39 * Documentation about these chips can be found at 40 * 41 * http://developer.intel.com/design/network/datashts/290218.htm 42 * http://developer.intel.com/design/network/datashts/290219.htm 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: i82596.c,v 1.25 2009/05/10 04:26:19 tsutsui Exp $"); 47 48 /* autoconfig and device stuff */ 49 #include <sys/param.h> 50 #include <sys/device.h> 51 #include <sys/conf.h> 52 #include "locators.h" 53 #include "ioconf.h" 54 55 /* bus_space / bus_dma etc. */ 56 #include <sys/bus.h> 57 #include <sys/intr.h> 58 59 /* general system data and functions */ 60 #include <sys/systm.h> 61 #include <sys/ioctl.h> 62 63 /* tsleep / sleep / wakeup */ 64 #include <sys/proc.h> 65 /* hz for above */ 66 #include <sys/kernel.h> 67 68 /* network stuff */ 69 #include <net/if.h> 70 #include <net/if_dl.h> 71 #include <net/if_media.h> 72 #include <net/if_ether.h> 73 #include <sys/socket.h> 74 #include <sys/mbuf.h> 75 76 #include "bpfilter.h" 77 #if NBPFILTER > 0 78 #include <net/bpf.h> 79 #endif 80 81 #include <dev/ic/i82596reg.h> 82 #include <dev/ic/i82596var.h> 83 84 /* Supported chip variants */ 85 const char *i82596_typenames[] = { "unknown", "DX/SX", "CA" }; 86 87 /* media change and status callback */ 88 static int iee_mediachange(struct ifnet *); 89 static void iee_mediastatus(struct ifnet *, struct ifmediareq *); 90 91 /* interface routines to upper protocols */ 92 static void iee_start(struct ifnet *); /* initiate output */ 93 static int iee_ioctl(struct ifnet *, u_long, void *); /* ioctl routine */ 94 static int iee_init(struct ifnet *); /* init routine */ 95 static void iee_stop(struct ifnet *, int); /* stop routine */ 96 static void iee_watchdog(struct ifnet *); /* timer routine */ 97 98 /* internal helper functions */ 99 static void iee_cb_setup(struct iee_softc *, uint32_t); 100 101 /* 102 * Things a MD frontend has to provide: 103 * 104 * The functions via function pointers in the softc: 105 * int (*sc_iee_cmd)(struct iee_softc *sc, uint32_t cmd); 106 * int (*sc_iee_reset)(struct iee_softc *sc); 107 * void (*sc_mediastatus)(struct ifnet *, struct ifmediareq *); 108 * int (*sc_mediachange)(struct ifnet *); 109 * 110 * sc_iee_cmd(): send a command to the i82596 by writing the cmd parameter 111 * to the SCP cmd word and issuing a Channel Attention. 112 * sc_iee_reset(): initiate a reset, supply the address of the SCP to the 113 * chip, wait for the chip to initialize and ACK interrupts that 114 * this may have caused by calling (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 115 * This functions must carefully bus_dmamap_sync() all data they have touched! 116 * 117 * sc_mediastatus() and sc_mediachange() are just MD hooks to the according 118 * MI functions. The MD frontend may set this pointers to NULL when they 119 * are not needed. 120 * 121 * sc->sc_type has to be set to I82596_UNKNOWN or I82596_DX or I82596_CA. 122 * This is for printing out the correct chip type at attach time only. The 123 * MI backend doesn't distinguish different chip types when programming 124 * the chip. 125 * 126 * IEE_NEED_SWAP in sc->sc_flags has to be cleared on little endian hardware 127 * and set on big endian hardware, when endianess conversion is not done 128 * by the bus attachment but done by i82596 chip itself. 129 * Usually you need to set IEE_NEED_SWAP on big endian machines 130 * where the hardware (the LE/~BE pin) is configured as BE mode. 131 * 132 * If the chip is configured as BE mode, all 8 bit (byte) and 16 bit (word) 133 * entities can be written in big endian. But Rev A chip doesn't support 134 * 32 bit (dword) entities with big endian byte ordering, so we have to 135 * treat all 32 bit (dword) entities as two 16 bit big endian entities. 136 * Rev B and C chips support big endian byte ordering for 32 bit entities, 137 * and this new feature is enabled by IEE_SYSBUS_BE in the sysbus byte. 138 * 139 * With the IEE_SYSBUS_BE feature, all 32 bit address ponters are 140 * treated as true 32 bit entities but the SCB absolute address and 141 * statistical counters are still treated as two 16 bit big endian entities, 142 * so we have to always swap high and low words for these entities. 143 * IEE_SWAP32() should be used for the SCB address and statistical counters, 144 * and IEE_SWAPA32() should be used for other 32 bit pointers in the shmem. 145 * 146 * IEE_REV_A flag must be set in sc->sc_flags if the IEE_SYSBUS_BE feature 147 * is disabled even on big endian machines for the old Rev A chip in backend. 148 * 149 * sc->sc_cl_align must be set to 1 or to the cache line size. When set to 150 * 1 no special alignment of DMA descriptors is done. If sc->sc_cl_align != 1 151 * it forces alignment of the data structures in the shared memory to a multiple 152 * of sc->sc_cl_align. This is needed on archs like hp700 that have non DMA 153 * I/O coherent caches and are unable to map the shared memory uncachable. 154 * (At least pre PA7100LC CPUs are unable to map memory uncachable.) 155 * 156 * sc->sc_cl_align MUST BE INITIALIZED BEFORE THE FOLLOWING MACROS ARE USED: 157 * SC_* IEE_*_SZ IEE_*_OFF IEE_SHMEM_MAX (shell style glob(3) pattern) 158 * 159 * The MD frontend also has to set sc->sc_cl_align and sc->sc_sysbus 160 * to allocate and setup shared DMA memory in MI iee_attach(). 161 * All communication with the chip is done via this shared memory. 162 * This memory is mapped with BUS_DMA_COHERENT so it will be uncached 163 * if possible for archs with non DMA I/O coherent caches. 164 * The base of the memory needs to be aligned to an even address 165 * if sc->sc_cl_align == 1 and aligned to a cache line if sc->sc_cl_align != 1. 166 * 167 * An interrupt with iee_intr() as handler must be established. 168 * 169 * Call void iee_attach(struct iee_softc *sc, uint8_t *ether_address, 170 * int *media, int nmedia, int defmedia); when everything is set up. First 171 * parameter is a pointer to the MI softc, ether_address is an array that 172 * contains the ethernet address. media is an array of the media types 173 * provided by the hardware. The members of this array are supplied to 174 * ifmedia_add() in sequence. nmedia is the count of elements in media. 175 * defmedia is the default media that is set via ifmedia_set(). 176 * nmedia and defmedia are ignored when media == NULL. 177 * 178 * The MD backend may call iee_detach() to detach the device. 179 * 180 * See sys/arch/hp700/gsc/if_iee_gsc.c for an example. 181 */ 182 183 184 /* 185 * How frame reception is done: 186 * Each Receive Frame Descriptor has one associated Receive Buffer Descriptor. 187 * Each RBD points to the data area of an mbuf cluster. The RFDs are linked 188 * together in a circular list. sc->sc_rx_done is the count of RFDs in the 189 * list already processed / the number of the RFD that has to be checked for 190 * a new frame first at the next RX interrupt. Upon successful reception of 191 * a frame the mbuf cluster is handled to upper protocol layers, a new mbuf 192 * cluster is allocated and the RFD / RBD are reinitialized accordingly. 193 * 194 * When a RFD list overrun occurred the whole RFD and RBD lists are reinitialized 195 * and frame reception is started again. 196 */ 197 int 198 iee_intr(void *intarg) 199 { 200 struct iee_softc *sc = intarg; 201 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 202 struct iee_rfd *rfd; 203 struct iee_rbd *rbd; 204 bus_dmamap_t rx_map; 205 struct mbuf *rx_mbuf; 206 struct mbuf *new_mbuf; 207 int scb_status; 208 int scb_cmd; 209 int n, col; 210 uint16_t status, count, cmd; 211 212 if ((ifp->if_flags & IFF_RUNNING) == 0) { 213 (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 214 return 1; 215 } 216 IEE_SCBSYNC(sc, BUS_DMASYNC_POSTREAD); 217 scb_status = SC_SCB(sc)->scb_status; 218 scb_cmd = SC_SCB(sc)->scb_cmd; 219 for (;;) { 220 rfd = SC_RFD(sc, sc->sc_rx_done); 221 IEE_RFDSYNC(sc, sc->sc_rx_done, 222 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 223 status = rfd->rfd_status; 224 if ((status & IEE_RFD_C) == 0) { 225 IEE_RFDSYNC(sc, sc->sc_rx_done, BUS_DMASYNC_PREREAD); 226 break; 227 } 228 rfd->rfd_status = 0; 229 IEE_RFDSYNC(sc, sc->sc_rx_done, 230 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 231 232 /* At least one packet was received. */ 233 rx_map = sc->sc_rx_map[sc->sc_rx_done]; 234 rx_mbuf = sc->sc_rx_mbuf[sc->sc_rx_done]; 235 IEE_RBDSYNC(sc, (sc->sc_rx_done + IEE_NRFD - 1) % IEE_NRFD, 236 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 237 SC_RBD(sc, (sc->sc_rx_done + IEE_NRFD - 1) % IEE_NRFD)->rbd_size 238 &= ~IEE_RBD_EL; 239 IEE_RBDSYNC(sc, (sc->sc_rx_done + IEE_NRFD - 1) % IEE_NRFD, 240 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 241 rbd = SC_RBD(sc, sc->sc_rx_done); 242 IEE_RBDSYNC(sc, sc->sc_rx_done, 243 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 244 count = rbd->rbd_count; 245 if ((status & IEE_RFD_OK) == 0 246 || (count & IEE_RBD_EOF) == 0 247 || (count & IEE_RBD_F) == 0){ 248 /* Receive error, skip frame and reuse buffer. */ 249 rbd->rbd_count = 0; 250 rbd->rbd_size = IEE_RBD_EL | rx_map->dm_segs[0].ds_len; 251 IEE_RBDSYNC(sc, sc->sc_rx_done, 252 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 253 printf("%s: iee_intr: receive error %d, rfd_status=" 254 "0x%.4x, rfd_count=0x%.4x\n", 255 device_xname(sc->sc_dev), 256 ++sc->sc_rx_err, status, count); 257 sc->sc_rx_done = (sc->sc_rx_done + 1) % IEE_NRFD; 258 continue; 259 } 260 bus_dmamap_sync(sc->sc_dmat, rx_map, 0, rx_mbuf->m_ext.ext_size, 261 BUS_DMASYNC_POSTREAD); 262 rx_mbuf->m_pkthdr.len = rx_mbuf->m_len = 263 count & IEE_RBD_COUNT; 264 rx_mbuf->m_pkthdr.rcvif = ifp; 265 MGETHDR(new_mbuf, M_DONTWAIT, MT_DATA); 266 if (new_mbuf == NULL) { 267 printf("%s: iee_intr: can't allocate mbuf\n", 268 device_xname(sc->sc_dev)); 269 break; 270 } 271 MCLAIM(new_mbuf, &sc->sc_ethercom.ec_rx_mowner); 272 MCLGET(new_mbuf, M_DONTWAIT); 273 if ((new_mbuf->m_flags & M_EXT) == 0) { 274 printf("%s: iee_intr: can't alloc mbuf cluster\n", 275 device_xname(sc->sc_dev)); 276 m_freem(new_mbuf); 277 break; 278 } 279 bus_dmamap_unload(sc->sc_dmat, rx_map); 280 new_mbuf->m_len = new_mbuf->m_pkthdr.len = MCLBYTES - 2; 281 new_mbuf->m_data += 2; 282 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_map, 283 new_mbuf, BUS_DMA_READ | BUS_DMA_NOWAIT) != 0) 284 panic("%s: iee_intr: can't load RX DMA map\n", 285 device_xname(sc->sc_dev)); 286 bus_dmamap_sync(sc->sc_dmat, rx_map, 0, 287 rx_map->dm_mapsize, BUS_DMASYNC_PREREAD); 288 #if NBPFILTER > 0 289 if (ifp->if_bpf != 0) 290 bpf_mtap(ifp->if_bpf, rx_mbuf); 291 #endif /* NBPFILTER > 0 */ 292 (*ifp->if_input)(ifp, rx_mbuf); 293 ifp->if_ipackets++; 294 sc->sc_rx_mbuf[sc->sc_rx_done] = new_mbuf; 295 rbd->rbd_count = 0; 296 rbd->rbd_size = IEE_RBD_EL | rx_map->dm_segs[0].ds_len; 297 rbd->rbd_rb_addr = IEE_SWAPA32(rx_map->dm_segs[0].ds_addr); 298 IEE_RBDSYNC(sc, sc->sc_rx_done, 299 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 300 sc->sc_rx_done = (sc->sc_rx_done + 1) % IEE_NRFD; 301 } 302 if ((scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR1 303 || (scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR2 304 || (scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR3) { 305 /* Receive Overrun, reinit receive ring buffer. */ 306 for (n = 0 ; n < IEE_NRFD ; n++) { 307 rfd = SC_RFD(sc, n); 308 rbd = SC_RBD(sc, n); 309 rfd->rfd_cmd = IEE_RFD_SF; 310 rfd->rfd_link_addr = 311 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off 312 + sc->sc_rfd_sz * ((n + 1) % IEE_NRFD))); 313 rbd->rbd_next_rbd = 314 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off 315 + sc->sc_rbd_sz * ((n + 1) % IEE_NRFD))); 316 rbd->rbd_size = IEE_RBD_EL | 317 sc->sc_rx_map[n]->dm_segs[0].ds_len; 318 rbd->rbd_rb_addr = 319 IEE_SWAPA32(sc->sc_rx_map[n]->dm_segs[0].ds_addr); 320 } 321 SC_RFD(sc, 0)->rfd_rbd_addr = 322 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off)); 323 sc->sc_rx_done = 0; 324 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, sc->sc_rfd_off, 325 sc->sc_rfd_sz * IEE_NRFD + sc->sc_rbd_sz * IEE_NRFD, 326 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 327 (sc->sc_iee_cmd)(sc, IEE_SCB_RUC_ST); 328 printf("%s: iee_intr: receive ring buffer overrun\n", 329 device_xname(sc->sc_dev)); 330 } 331 332 if (sc->sc_next_cb != 0) { 333 IEE_CBSYNC(sc, sc->sc_next_cb - 1, 334 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 335 status = SC_CB(sc, sc->sc_next_cb - 1)->cb_status; 336 IEE_CBSYNC(sc, sc->sc_next_cb - 1, 337 BUS_DMASYNC_PREREAD); 338 if ((status & IEE_CB_C) != 0) { 339 /* CMD list finished */ 340 ifp->if_timer = 0; 341 if (sc->sc_next_tbd != 0) { 342 /* A TX CMD list finished, cleanup */ 343 for (n = 0 ; n < sc->sc_next_cb ; n++) { 344 m_freem(sc->sc_tx_mbuf[n]); 345 sc->sc_tx_mbuf[n] = NULL; 346 bus_dmamap_unload(sc->sc_dmat, 347 sc->sc_tx_map[n]); 348 IEE_CBSYNC(sc, n, 349 BUS_DMASYNC_POSTREAD| 350 BUS_DMASYNC_POSTWRITE); 351 status = SC_CB(sc, n)->cb_status; 352 IEE_CBSYNC(sc, n, 353 BUS_DMASYNC_PREREAD); 354 if ((status & IEE_CB_COL) != 0 && 355 (status & IEE_CB_MAXCOL) == 0) 356 col = 16; 357 else 358 col = status 359 & IEE_CB_MAXCOL; 360 sc->sc_tx_col += col; 361 if ((status & IEE_CB_OK) != 0) { 362 ifp->if_opackets++; 363 ifp->if_collisions += col; 364 } 365 } 366 sc->sc_next_tbd = 0; 367 ifp->if_flags &= ~IFF_OACTIVE; 368 } 369 for (n = 0 ; n < sc->sc_next_cb; n++) { 370 /* 371 * Check if a CMD failed, but ignore TX errors. 372 */ 373 IEE_CBSYNC(sc, n, 374 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 375 cmd = SC_CB(sc, n)->cb_cmd; 376 status = SC_CB(sc, n)->cb_status; 377 IEE_CBSYNC(sc, n, BUS_DMASYNC_PREREAD); 378 if ((cmd & IEE_CB_CMD) != IEE_CB_CMD_TR && 379 (status & IEE_CB_OK) == 0) 380 printf("%s: iee_intr: scb_status=0x%x " 381 "scb_cmd=0x%x failed command %d: " 382 "cb_status[%d]=0x%.4x " 383 "cb_cmd[%d]=0x%.4x\n", 384 device_xname(sc->sc_dev), 385 scb_status, scb_cmd, 386 ++sc->sc_cmd_err, 387 n, status, n, cmd); 388 } 389 sc->sc_next_cb = 0; 390 if ((sc->sc_flags & IEE_WANT_MCAST) != 0) { 391 iee_cb_setup(sc, IEE_CB_CMD_MCS | 392 IEE_CB_S | IEE_CB_EL | IEE_CB_I); 393 (sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE); 394 } else 395 /* Try to get deferred packets going. */ 396 iee_start(ifp); 397 } 398 } 399 if (IEE_SWAP32(SC_SCB(sc)->scb_crc_err) != sc->sc_crc_err) { 400 sc->sc_crc_err = IEE_SWAP32(SC_SCB(sc)->scb_crc_err); 401 printf("%s: iee_intr: crc_err=%d\n", device_xname(sc->sc_dev), 402 sc->sc_crc_err); 403 } 404 if (IEE_SWAP32(SC_SCB(sc)->scb_align_err) != sc->sc_align_err) { 405 sc->sc_align_err = IEE_SWAP32(SC_SCB(sc)->scb_align_err); 406 printf("%s: iee_intr: align_err=%d\n", device_xname(sc->sc_dev), 407 sc->sc_align_err); 408 } 409 if (IEE_SWAP32(SC_SCB(sc)->scb_resource_err) != sc->sc_resource_err) { 410 sc->sc_resource_err = IEE_SWAP32(SC_SCB(sc)->scb_resource_err); 411 printf("%s: iee_intr: resource_err=%d\n", 412 device_xname(sc->sc_dev), sc->sc_resource_err); 413 } 414 if (IEE_SWAP32(SC_SCB(sc)->scb_overrun_err) != sc->sc_overrun_err) { 415 sc->sc_overrun_err = IEE_SWAP32(SC_SCB(sc)->scb_overrun_err); 416 printf("%s: iee_intr: overrun_err=%d\n", 417 device_xname(sc->sc_dev), sc->sc_overrun_err); 418 } 419 if (IEE_SWAP32(SC_SCB(sc)->scb_rcvcdt_err) != sc->sc_rcvcdt_err) { 420 sc->sc_rcvcdt_err = IEE_SWAP32(SC_SCB(sc)->scb_rcvcdt_err); 421 printf("%s: iee_intr: rcvcdt_err=%d\n", 422 device_xname(sc->sc_dev), sc->sc_rcvcdt_err); 423 } 424 if (IEE_SWAP32(SC_SCB(sc)->scb_short_fr_err) != sc->sc_short_fr_err) { 425 sc->sc_short_fr_err = IEE_SWAP32(SC_SCB(sc)->scb_short_fr_err); 426 printf("%s: iee_intr: short_fr_err=%d\n", 427 device_xname(sc->sc_dev), sc->sc_short_fr_err); 428 } 429 IEE_SCBSYNC(sc, BUS_DMASYNC_PREREAD); 430 (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 431 return 1; 432 } 433 434 435 436 /* 437 * How Command Block List Processing is done. 438 * 439 * A running CBL is never manipulated. If there is a CBL already running, 440 * further CMDs are deferred until the current list is done. A new list is 441 * setup when the old one has finished. 442 * This eases programming. To manipulate a running CBL it is necessary to 443 * suspend the Command Unit to avoid race conditions. After a suspend 444 * is sent we have to wait for an interrupt that ACKs the suspend. Then 445 * we can manipulate the CBL and resume operation. I am not sure that this 446 * is more effective then the current, much simpler approach. => KISS 447 * See i82596CA data sheet page 26. 448 * 449 * A CBL is running or on the way to be set up when (sc->sc_next_cb != 0). 450 * 451 * A CBL may consist of TX CMDs, and _only_ TX CMDs. 452 * A TX CBL is running or on the way to be set up when 453 * ((sc->sc_next_cb != 0) && (sc->sc_next_tbd != 0)). 454 * 455 * A CBL may consist of other non-TX CMDs like IAS or CONF, and _only_ 456 * non-TX CMDs. 457 * 458 * This comes mostly through the way how an Ethernet driver works and 459 * because running CBLs are not manipulated when they are on the way. If 460 * if_start() is called there will be TX CMDs enqueued so we have a running 461 * CBL and other CMDs from e.g. if_ioctl() will be deferred and vice versa. 462 * 463 * The Multicast Setup Command is special. A MCS needs more space than 464 * a single CB has. Actual space requirement depends on the length of the 465 * multicast list. So we always defer MCS until other CBLs are finished, 466 * then we setup a CONF CMD in the first CB. The CONF CMD is needed to 467 * turn ALLMULTI on the hardware on or off. The MCS is the 2nd CB and may 468 * use all the remaining space in the CBL and the Transmit Buffer Descriptor 469 * List. (Therefore CBL and TBDL must be continuous in physical and virtual 470 * memory. This is guaranteed through the definitions of the list offsets 471 * in i82596reg.h and because it is only a single DMA segment used for all 472 * lists.) When ALLMULTI is enabled via the CONF CMD, the MCS is run with 473 * a multicast list length of 0, thus disabling the multicast filter. 474 * A deferred MCS is signaled via ((sc->sc_flags & IEE_WANT_MCAST) != 0) 475 */ 476 void 477 iee_cb_setup(struct iee_softc *sc, uint32_t cmd) 478 { 479 struct iee_cb *cb = SC_CB(sc, sc->sc_next_cb); 480 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 481 struct ether_multistep step; 482 struct ether_multi *enm; 483 484 memset(cb, 0, sc->sc_cb_sz); 485 cb->cb_cmd = cmd; 486 switch (cmd & IEE_CB_CMD) { 487 case IEE_CB_CMD_NOP: /* NOP CMD */ 488 break; 489 case IEE_CB_CMD_IAS: /* Individual Address Setup */ 490 memcpy(__UNVOLATILE(cb->cb_ind_addr), CLLADDR(ifp->if_sadl), 491 ETHER_ADDR_LEN); 492 break; 493 case IEE_CB_CMD_CONF: /* Configure */ 494 memcpy(__UNVOLATILE(cb->cb_cf), sc->sc_cf, sc->sc_cf[0] 495 & IEE_CF_0_CNT_M); 496 break; 497 case IEE_CB_CMD_MCS: /* Multicast Setup */ 498 if (sc->sc_next_cb != 0) { 499 sc->sc_flags |= IEE_WANT_MCAST; 500 return; 501 } 502 sc->sc_flags &= ~IEE_WANT_MCAST; 503 if ((sc->sc_cf[8] & IEE_CF_8_PRM) != 0) { 504 /* Need no multicast filter in promisc mode. */ 505 iee_cb_setup(sc, IEE_CB_CMD_CONF | IEE_CB_S | IEE_CB_EL 506 | IEE_CB_I); 507 return; 508 } 509 /* Leave room for a CONF CMD to en/dis-able ALLMULTI mode */ 510 cb = SC_CB(sc, sc->sc_next_cb + 1); 511 cb->cb_cmd = cmd; 512 cb->cb_mcast.mc_size = 0; 513 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 514 while (enm != NULL) { 515 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 516 ETHER_ADDR_LEN) != 0 || cb->cb_mcast.mc_size 517 * ETHER_ADDR_LEN + 2 * sc->sc_cb_sz > 518 sc->sc_cb_sz * IEE_NCB + 519 sc->sc_tbd_sz * IEE_NTBD * IEE_NCB) { 520 cb->cb_mcast.mc_size = 0; 521 break; 522 } 523 memcpy(__UNVOLATILE(&cb->cb_mcast.mc_addrs[ 524 cb->cb_mcast.mc_size * ETHER_ADDR_LEN]), 525 enm->enm_addrlo, ETHER_ADDR_LEN); 526 ETHER_NEXT_MULTI(step, enm); 527 cb->cb_mcast.mc_size++; 528 } 529 if (cb->cb_mcast.mc_size == 0) { 530 /* Can't do exact mcast filtering, do ALLMULTI mode. */ 531 ifp->if_flags |= IFF_ALLMULTI; 532 sc->sc_cf[11] &= ~IEE_CF_11_MCALL; 533 } else { 534 /* disable ALLMULTI and load mcast list */ 535 ifp->if_flags &= ~IFF_ALLMULTI; 536 sc->sc_cf[11] |= IEE_CF_11_MCALL; 537 /* Mcast setup may need more then sc->sc_cb_sz bytes. */ 538 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 539 sc->sc_cb_off, 540 sc->sc_cb_sz * IEE_NCB + 541 sc->sc_tbd_sz * IEE_NTBD * IEE_NCB, 542 BUS_DMASYNC_PREWRITE); 543 } 544 iee_cb_setup(sc, IEE_CB_CMD_CONF); 545 break; 546 case IEE_CB_CMD_TR: /* Transmit */ 547 cb->cb_transmit.tx_tbd_addr = 548 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_tbd_off 549 + sc->sc_tbd_sz * sc->sc_next_tbd)); 550 cb->cb_cmd |= IEE_CB_SF; /* Always use Flexible Mode. */ 551 break; 552 case IEE_CB_CMD_TDR: /* Time Domain Reflectometry */ 553 break; 554 case IEE_CB_CMD_DUMP: /* Dump */ 555 break; 556 case IEE_CB_CMD_DIAG: /* Diagnose */ 557 break; 558 default: 559 /* can't happen */ 560 break; 561 } 562 cb->cb_link_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_cb_off + 563 sc->sc_cb_sz * (sc->sc_next_cb + 1))); 564 IEE_CBSYNC(sc, sc->sc_next_cb, 565 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 566 sc->sc_next_cb++; 567 ifp->if_timer = 5; 568 } 569 570 571 572 void 573 iee_attach(struct iee_softc *sc, uint8_t *eth_addr, int *media, int nmedia, 574 int defmedia) 575 { 576 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 577 int n; 578 579 KASSERT(sc->sc_cl_align > 0 && powerof2(sc->sc_cl_align)); 580 581 sc->sc_scp_off = 0; 582 sc->sc_scp_sz = roundup2(sizeof(struct iee_scp), sc->sc_cl_align); 583 sc->sc_iscp_off = sc->sc_scp_sz; 584 sc->sc_iscp_sz = roundup2(sizeof(struct iee_iscp), sc->sc_cl_align); 585 sc->sc_scb_off = sc->sc_iscp_off + sc->sc_iscp_sz; 586 sc->sc_scb_sz = roundup2(sizeof(struct iee_scb), sc->sc_cl_align); 587 sc->sc_rfd_off = sc->sc_scb_off + sc->sc_scb_sz; 588 sc->sc_rfd_sz = roundup2(sizeof(struct iee_rfd), sc->sc_cl_align); 589 sc->sc_rbd_off = sc->sc_rfd_off + sc->sc_rfd_sz * IEE_NRFD; 590 sc->sc_rbd_sz = roundup2(sizeof(struct iee_rbd), sc->sc_cl_align); 591 sc->sc_cb_off = sc->sc_rbd_off + sc->sc_rbd_sz * IEE_NRFD; 592 sc->sc_cb_sz = roundup2(sizeof(struct iee_cb), sc->sc_cl_align); 593 sc->sc_tbd_off = sc->sc_cb_off + sc->sc_cb_sz * IEE_NCB; 594 sc->sc_tbd_sz = roundup2(sizeof(struct iee_tbd), sc->sc_cl_align); 595 sc->sc_shmem_sz = sc->sc_tbd_off + sc->sc_tbd_sz * IEE_NTBD * IEE_NCB; 596 597 /* allocate memory for shared DMA descriptors */ 598 if (bus_dmamem_alloc(sc->sc_dmat, sc->sc_shmem_sz, PAGE_SIZE, 0, 599 &sc->sc_dma_segs, 1, &sc->sc_dma_rsegs, BUS_DMA_NOWAIT) != 0) { 600 aprint_error(": can't allocate %d bytes of DMA memory\n", 601 sc->sc_shmem_sz); 602 return; 603 } 604 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_dma_segs, sc->sc_dma_rsegs, 605 sc->sc_shmem_sz, (void **)&sc->sc_shmem_addr, 606 BUS_DMA_COHERENT | BUS_DMA_NOWAIT) != 0) { 607 aprint_error(": can't map DMA memory\n"); 608 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, 609 sc->sc_dma_rsegs); 610 return; 611 } 612 if (bus_dmamap_create(sc->sc_dmat, sc->sc_shmem_sz, sc->sc_dma_rsegs, 613 sc->sc_shmem_sz, 0, BUS_DMA_NOWAIT, &sc->sc_shmem_map) != 0) { 614 aprint_error(": can't create DMA map\n"); 615 bus_dmamem_unmap(sc->sc_dmat, sc->sc_shmem_addr, 616 sc->sc_shmem_sz); 617 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, 618 sc->sc_dma_rsegs); 619 return; 620 } 621 if (bus_dmamap_load(sc->sc_dmat, sc->sc_shmem_map, sc->sc_shmem_addr, 622 sc->sc_shmem_sz, NULL, BUS_DMA_NOWAIT) != 0) { 623 aprint_error(": can't load DMA map\n"); 624 bus_dmamap_destroy(sc->sc_dmat, sc->sc_shmem_map); 625 bus_dmamem_unmap(sc->sc_dmat, sc->sc_shmem_addr, 626 sc->sc_shmem_sz); 627 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, 628 sc->sc_dma_rsegs); 629 return; 630 } 631 memset(sc->sc_shmem_addr, 0, sc->sc_shmem_sz); 632 633 /* Set pointer to Intermediate System Configuration Pointer. */ 634 /* Phys. addr. in big endian order. (Big endian as defined by Intel.) */ 635 SC_SCP(sc)->scp_iscp_addr = IEE_SWAP32(IEE_PHYS_SHMEM(sc->sc_iscp_off)); 636 SC_SCP(sc)->scp_sysbus = sc->sc_sysbus; 637 /* Set pointer to System Control Block. */ 638 /* Phys. addr. in big endian order. (Big endian as defined by Intel.) */ 639 SC_ISCP(sc)->iscp_scb_addr = IEE_SWAP32(IEE_PHYS_SHMEM(sc->sc_scb_off)); 640 /* Set pointer to Receive Frame Area. (physical address) */ 641 SC_SCB(sc)->scb_rfa_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off)); 642 /* Set pointer to Command Block. (physical address) */ 643 SC_SCB(sc)->scb_cmd_blk_addr = 644 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_cb_off)); 645 646 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 0, sc->sc_shmem_sz, 647 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 648 649 ifmedia_init(&sc->sc_ifmedia, 0, iee_mediachange, iee_mediastatus); 650 if (media != NULL) { 651 for (n = 0 ; n < nmedia ; n++) 652 ifmedia_add(&sc->sc_ifmedia, media[n], 0, NULL); 653 ifmedia_set(&sc->sc_ifmedia, defmedia); 654 } else { 655 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_NONE, 0, NULL); 656 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_NONE); 657 } 658 659 ifp->if_softc = sc; 660 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 661 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 662 ifp->if_start = iee_start; /* initiate output routine */ 663 ifp->if_ioctl = iee_ioctl; /* ioctl routine */ 664 ifp->if_init = iee_init; /* init routine */ 665 ifp->if_stop = iee_stop; /* stop routine */ 666 ifp->if_watchdog = iee_watchdog; /* timer routine */ 667 IFQ_SET_READY(&ifp->if_snd); 668 /* iee supports IEEE 802.1Q Virtual LANs, see vlan(4). */ 669 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 670 671 if_attach(ifp); 672 ether_ifattach(ifp, eth_addr); 673 674 aprint_normal(": Intel 82596%s address %s\n", 675 i82596_typenames[sc->sc_type], ether_sprintf(eth_addr)); 676 677 for (n = 0 ; n < IEE_NCB ; n++) 678 sc->sc_tx_map[n] = NULL; 679 for (n = 0 ; n < IEE_NRFD ; n++) { 680 sc->sc_rx_mbuf[n] = NULL; 681 sc->sc_rx_map[n] = NULL; 682 } 683 sc->sc_tx_timeout = 0; 684 sc->sc_setup_timeout = 0; 685 (sc->sc_iee_reset)(sc); 686 } 687 688 689 690 void 691 iee_detach(struct iee_softc *sc, int flags) 692 { 693 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 694 695 if ((ifp->if_flags & IFF_RUNNING) != 0) 696 iee_stop(ifp, 1); 697 ether_ifdetach(ifp); 698 if_detach(ifp); 699 bus_dmamap_unload(sc->sc_dmat, sc->sc_shmem_map); 700 bus_dmamap_destroy(sc->sc_dmat, sc->sc_shmem_map); 701 bus_dmamem_unmap(sc->sc_dmat, sc->sc_shmem_addr, sc->sc_shmem_sz); 702 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, sc->sc_dma_rsegs); 703 } 704 705 706 707 /* media change and status callback */ 708 int 709 iee_mediachange(struct ifnet *ifp) 710 { 711 struct iee_softc *sc = ifp->if_softc; 712 713 if (sc->sc_mediachange != NULL) 714 return (sc->sc_mediachange)(ifp); 715 return 0; 716 } 717 718 719 720 void 721 iee_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmreq) 722 { 723 struct iee_softc *sc = ifp->if_softc; 724 725 if (sc->sc_mediastatus != NULL) 726 (sc->sc_mediastatus)(ifp, ifmreq); 727 } 728 729 730 731 /* initiate output routine */ 732 void 733 iee_start(struct ifnet *ifp) 734 { 735 struct iee_softc *sc = ifp->if_softc; 736 struct mbuf *m = NULL; 737 struct iee_tbd *tbd; 738 int t; 739 int n; 740 741 if (sc->sc_next_cb != 0) 742 /* There is already a CMD running. Defer packet enqueuing. */ 743 return; 744 for (t = 0 ; t < IEE_NCB ; t++) { 745 IFQ_DEQUEUE(&ifp->if_snd, sc->sc_tx_mbuf[t]); 746 if (sc->sc_tx_mbuf[t] == NULL) 747 break; 748 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_tx_map[t], 749 sc->sc_tx_mbuf[t], BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 750 /* 751 * The packet needs more TBD then we support. 752 * Copy the packet into a mbuf cluster to get it out. 753 */ 754 printf("%s: iee_start: failed to load DMA map\n", 755 device_xname(sc->sc_dev)); 756 MGETHDR(m, M_DONTWAIT, MT_DATA); 757 if (m == NULL) { 758 printf("%s: iee_start: can't allocate mbuf\n", 759 device_xname(sc->sc_dev)); 760 m_freem(sc->sc_tx_mbuf[t]); 761 t--; 762 continue; 763 } 764 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 765 MCLGET(m, M_DONTWAIT); 766 if ((m->m_flags & M_EXT) == 0) { 767 printf("%s: iee_start: can't allocate mbuf " 768 "cluster\n", device_xname(sc->sc_dev)); 769 m_freem(sc->sc_tx_mbuf[t]); 770 m_freem(m); 771 t--; 772 continue; 773 } 774 m_copydata(sc->sc_tx_mbuf[t], 0, 775 sc->sc_tx_mbuf[t]->m_pkthdr.len, mtod(m, void *)); 776 m->m_pkthdr.len = sc->sc_tx_mbuf[t]->m_pkthdr.len; 777 m->m_len = sc->sc_tx_mbuf[t]->m_pkthdr.len; 778 m_freem(sc->sc_tx_mbuf[t]); 779 sc->sc_tx_mbuf[t] = m; 780 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_tx_map[t], 781 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 782 printf("%s: iee_start: can't load TX DMA map\n", 783 device_xname(sc->sc_dev)); 784 m_freem(sc->sc_tx_mbuf[t]); 785 t--; 786 continue; 787 } 788 } 789 for (n = 0 ; n < sc->sc_tx_map[t]->dm_nsegs ; n++) { 790 tbd = SC_TBD(sc, sc->sc_next_tbd + n); 791 tbd->tbd_tb_addr = 792 IEE_SWAPA32(sc->sc_tx_map[t]->dm_segs[n].ds_addr); 793 tbd->tbd_size = 794 sc->sc_tx_map[t]->dm_segs[n].ds_len; 795 tbd->tbd_link_addr = 796 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_tbd_off + 797 sc->sc_tbd_sz * (sc->sc_next_tbd + n + 1))); 798 } 799 SC_TBD(sc, sc->sc_next_tbd + n - 1)->tbd_size |= IEE_CB_EL; 800 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 801 sc->sc_tbd_off + sc->sc_next_tbd * sc->sc_tbd_sz, 802 sc->sc_tbd_sz * sc->sc_tx_map[t]->dm_nsegs, 803 BUS_DMASYNC_PREWRITE); 804 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_map[t], 0, 805 sc->sc_tx_map[t]->dm_mapsize, BUS_DMASYNC_PREWRITE); 806 IFQ_POLL(&ifp->if_snd, m); 807 if (m == NULL) 808 iee_cb_setup(sc, IEE_CB_CMD_TR | IEE_CB_S | IEE_CB_EL 809 | IEE_CB_I); 810 else 811 iee_cb_setup(sc, IEE_CB_CMD_TR); 812 sc->sc_next_tbd += n; 813 #if NBPFILTER > 0 814 /* Pass packet to bpf if someone listens. */ 815 if (ifp->if_bpf) 816 bpf_mtap(ifp->if_bpf, sc->sc_tx_mbuf[t]); 817 #endif 818 } 819 if (t == 0) 820 /* No packets got set up for TX. */ 821 return; 822 if (t == IEE_NCB) 823 ifp->if_flags |= IFF_OACTIVE; 824 (sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE); 825 } 826 827 828 829 /* ioctl routine */ 830 int 831 iee_ioctl(struct ifnet *ifp, u_long cmd, void *data) 832 { 833 struct iee_softc *sc = ifp->if_softc; 834 int s; 835 int err; 836 837 s = splnet(); 838 switch (cmd) { 839 case SIOCSIFMEDIA: 840 case SIOCGIFMEDIA: 841 err = ifmedia_ioctl(ifp, (struct ifreq *) data, 842 &sc->sc_ifmedia, cmd); 843 break; 844 845 default: 846 err = ether_ioctl(ifp, cmd, data); 847 if (err == ENETRESET) { 848 /* 849 * Multicast list as changed; set the hardware filter 850 * accordingly. 851 */ 852 if (ifp->if_flags & IFF_RUNNING) { 853 iee_cb_setup(sc, IEE_CB_CMD_MCS | IEE_CB_S | 854 IEE_CB_EL | IEE_CB_I); 855 if ((sc->sc_flags & IEE_WANT_MCAST) == 0) 856 (*sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE); 857 } 858 err = 0; 859 } 860 break; 861 } 862 splx(s); 863 return err; 864 } 865 866 867 868 /* init routine */ 869 int 870 iee_init(struct ifnet *ifp) 871 { 872 struct iee_softc *sc = ifp->if_softc; 873 int r; 874 int t; 875 int n; 876 int err; 877 878 sc->sc_next_cb = 0; 879 sc->sc_next_tbd = 0; 880 sc->sc_flags &= ~IEE_WANT_MCAST; 881 sc->sc_rx_done = 0; 882 SC_SCB(sc)->scb_crc_err = 0; 883 SC_SCB(sc)->scb_align_err = 0; 884 SC_SCB(sc)->scb_resource_err = 0; 885 SC_SCB(sc)->scb_overrun_err = 0; 886 SC_SCB(sc)->scb_rcvcdt_err = 0; 887 SC_SCB(sc)->scb_short_fr_err = 0; 888 sc->sc_crc_err = 0; 889 sc->sc_align_err = 0; 890 sc->sc_resource_err = 0; 891 sc->sc_overrun_err = 0; 892 sc->sc_rcvcdt_err = 0; 893 sc->sc_short_fr_err = 0; 894 sc->sc_tx_col = 0; 895 sc->sc_rx_err = 0; 896 sc->sc_cmd_err = 0; 897 /* Create Transmit DMA maps. */ 898 for (t = 0 ; t < IEE_NCB ; t++) { 899 if (sc->sc_tx_map[t] == NULL && bus_dmamap_create(sc->sc_dmat, 900 MCLBYTES, IEE_NTBD, MCLBYTES, 0, BUS_DMA_NOWAIT, 901 &sc->sc_tx_map[t]) != 0) { 902 printf("%s: iee_init: can't create TX DMA map\n", 903 device_xname(sc->sc_dev)); 904 for (n = 0 ; n < t ; n++) 905 bus_dmamap_destroy(sc->sc_dmat, 906 sc->sc_tx_map[n]); 907 return ENOBUFS; 908 } 909 } 910 /* Initialize Receive Frame and Receive Buffer Descriptors */ 911 err = 0; 912 memset(SC_RFD(sc, 0), 0, sc->sc_rfd_sz * IEE_NRFD); 913 memset(SC_RBD(sc, 0), 0, sc->sc_rbd_sz * IEE_NRFD); 914 for (r = 0 ; r < IEE_NRFD ; r++) { 915 SC_RFD(sc, r)->rfd_cmd = IEE_RFD_SF; 916 SC_RFD(sc, r)->rfd_link_addr = 917 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off 918 + sc->sc_rfd_sz * ((r + 1) % IEE_NRFD))); 919 920 SC_RBD(sc, r)->rbd_next_rbd = 921 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off 922 + sc->sc_rbd_sz * ((r + 1) % IEE_NRFD))); 923 if (sc->sc_rx_mbuf[r] == NULL) { 924 MGETHDR(sc->sc_rx_mbuf[r], M_DONTWAIT, MT_DATA); 925 if (sc->sc_rx_mbuf[r] == NULL) { 926 printf("%s: iee_init: can't allocate mbuf\n", 927 device_xname(sc->sc_dev)); 928 err = 1; 929 break; 930 } 931 MCLAIM(sc->sc_rx_mbuf[r],&sc->sc_ethercom.ec_rx_mowner); 932 MCLGET(sc->sc_rx_mbuf[r], M_DONTWAIT); 933 if ((sc->sc_rx_mbuf[r]->m_flags & M_EXT) == 0) { 934 printf("%s: iee_init: can't allocate mbuf" 935 " cluster\n", device_xname(sc->sc_dev)); 936 m_freem(sc->sc_rx_mbuf[r]); 937 err = 1; 938 break; 939 } 940 sc->sc_rx_mbuf[r]->m_len = 941 sc->sc_rx_mbuf[r]->m_pkthdr.len = MCLBYTES - 2; 942 sc->sc_rx_mbuf[r]->m_data += 2; 943 } 944 if (sc->sc_rx_map[r] == NULL && bus_dmamap_create(sc->sc_dmat, 945 MCLBYTES, 1, MCLBYTES , 0, BUS_DMA_NOWAIT, 946 &sc->sc_rx_map[r]) != 0) { 947 printf("%s: iee_init: can't create RX " 948 "DMA map\n", device_xname(sc->sc_dev)); 949 m_freem(sc->sc_rx_mbuf[r]); 950 err = 1; 951 break; 952 } 953 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_rx_map[r], 954 sc->sc_rx_mbuf[r], BUS_DMA_READ | BUS_DMA_NOWAIT) != 0) { 955 printf("%s: iee_init: can't load RX DMA map\n", 956 device_xname(sc->sc_dev)); 957 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[r]); 958 m_freem(sc->sc_rx_mbuf[r]); 959 err = 1; 960 break; 961 } 962 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_map[r], 0, 963 sc->sc_rx_map[r]->dm_mapsize, BUS_DMASYNC_PREREAD); 964 SC_RBD(sc, r)->rbd_size = sc->sc_rx_map[r]->dm_segs[0].ds_len; 965 SC_RBD(sc, r)->rbd_rb_addr = 966 IEE_SWAPA32(sc->sc_rx_map[r]->dm_segs[0].ds_addr); 967 } 968 SC_RFD(sc, 0)->rfd_rbd_addr = 969 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off)); 970 if (err != 0) { 971 for (n = 0 ; n < r; n++) { 972 m_freem(sc->sc_rx_mbuf[n]); 973 sc->sc_rx_mbuf[n] = NULL; 974 bus_dmamap_unload(sc->sc_dmat, sc->sc_rx_map[n]); 975 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[n]); 976 sc->sc_rx_map[n] = NULL; 977 } 978 for (n = 0 ; n < t ; n++) { 979 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_map[n]); 980 sc->sc_tx_map[n] = NULL; 981 } 982 return ENOBUFS; 983 } 984 985 (sc->sc_iee_reset)(sc); 986 iee_cb_setup(sc, IEE_CB_CMD_IAS); 987 sc->sc_cf[0] = IEE_CF_0_DEF | IEE_CF_0_PREF; 988 sc->sc_cf[1] = IEE_CF_1_DEF; 989 sc->sc_cf[2] = IEE_CF_2_DEF; 990 sc->sc_cf[3] = IEE_CF_3_ADDRLEN_DEF | IEE_CF_3_NSAI 991 | IEE_CF_3_PREAMLEN_DEF; 992 sc->sc_cf[4] = IEE_CF_4_DEF; 993 sc->sc_cf[5] = IEE_CF_5_DEF; 994 sc->sc_cf[6] = IEE_CF_6_DEF; 995 sc->sc_cf[7] = IEE_CF_7_DEF; 996 sc->sc_cf[8] = IEE_CF_8_DEF; 997 sc->sc_cf[9] = IEE_CF_9_DEF; 998 sc->sc_cf[10] = IEE_CF_10_DEF; 999 sc->sc_cf[11] = IEE_CF_11_DEF & ~IEE_CF_11_LNGFLD; 1000 sc->sc_cf[12] = IEE_CF_12_DEF; 1001 sc->sc_cf[13] = IEE_CF_13_DEF; 1002 iee_cb_setup(sc, IEE_CB_CMD_CONF | IEE_CB_S | IEE_CB_EL); 1003 SC_SCB(sc)->scb_rfa_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off)); 1004 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 0, sc->sc_shmem_sz, 1005 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1006 (sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE | IEE_SCB_RUC_ST); 1007 /* Issue a Channel Attention to ACK interrupts we may have caused. */ 1008 (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 1009 1010 /* Mark the interface as running and ready to RX/TX packets. */ 1011 ifp->if_flags |= IFF_RUNNING; 1012 ifp->if_flags &= ~IFF_OACTIVE; 1013 return 0; 1014 } 1015 1016 1017 1018 /* stop routine */ 1019 void 1020 iee_stop(struct ifnet *ifp, int disable) 1021 { 1022 struct iee_softc *sc = ifp->if_softc; 1023 int n; 1024 1025 ifp->if_flags &= ~IFF_RUNNING; 1026 ifp->if_flags |= IFF_OACTIVE; 1027 ifp->if_timer = 0; 1028 /* Reset the chip to get it quiet. */ 1029 (sc->sc_iee_reset)(ifp->if_softc); 1030 /* Issue a Channel Attention to ACK interrupts we may have caused. */ 1031 (sc->sc_iee_cmd)(ifp->if_softc, IEE_SCB_ACK); 1032 /* Release any dynamically allocated resources. */ 1033 for (n = 0 ; n < IEE_NCB ; n++) { 1034 if (sc->sc_tx_map[n] != NULL) 1035 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_map[n]); 1036 sc->sc_tx_map[n] = NULL; 1037 } 1038 for (n = 0 ; n < IEE_NRFD ; n++) { 1039 if (sc->sc_rx_mbuf[n] != NULL) 1040 m_freem(sc->sc_rx_mbuf[n]); 1041 sc->sc_rx_mbuf[n] = NULL; 1042 if (sc->sc_rx_map[n] != NULL) { 1043 bus_dmamap_unload(sc->sc_dmat, sc->sc_rx_map[n]); 1044 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[n]); 1045 } 1046 sc->sc_rx_map[n] = NULL; 1047 } 1048 } 1049 1050 1051 1052 /* timer routine */ 1053 void 1054 iee_watchdog(struct ifnet *ifp) 1055 { 1056 struct iee_softc *sc = ifp->if_softc; 1057 1058 (sc->sc_iee_reset)(sc); 1059 if (sc->sc_next_tbd != 0) 1060 printf("%s: iee_watchdog: transmit timeout %d\n", 1061 device_xname(sc->sc_dev), ++sc->sc_tx_timeout); 1062 else 1063 printf("%s: iee_watchdog: setup timeout %d\n", 1064 device_xname(sc->sc_dev), ++sc->sc_setup_timeout); 1065 iee_init(ifp); 1066 } 1067
Indexes created Tue Sep 30 20:09:53 GMT 2025