i82596.c revision 1.29
1 /* $NetBSD: i82596.c,v 1.29 2010/04/05 07:19:35 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Jochen Kunz. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Jochen Kunz may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY JOCHEN KUNZ 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL JOCHEN KUNZ 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the Intel i82596CA and i82596DX/SX 10MBit/s Ethernet chips. 34 * 35 * It operates the i82596 in 32-Bit Linear Mode, opposed to the old i82586 36 * ie(4) driver (src/sys/dev/ic/i82586.c), that degrades the i82596 to 37 * i82586 compatibility mode. 38 * 39 * Documentation about these chips can be found at 40 * 41 * http://developer.intel.com/design/network/datashts/290218.htm 42 * http://developer.intel.com/design/network/datashts/290219.htm 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: i82596.c,v 1.29 2010/04/05 07:19:35 joerg Exp $"); 47 48 /* autoconfig and device stuff */ 49 #include <sys/param.h> 50 #include <sys/device.h> 51 #include <sys/conf.h> 52 #include "locators.h" 53 #include "ioconf.h" 54 55 /* bus_space / bus_dma etc. */ 56 #include <sys/bus.h> 57 #include <sys/intr.h> 58 59 /* general system data and functions */ 60 #include <sys/systm.h> 61 #include <sys/ioctl.h> 62 63 /* tsleep / sleep / wakeup */ 64 #include <sys/proc.h> 65 /* hz for above */ 66 #include <sys/kernel.h> 67 68 /* network stuff */ 69 #include <net/if.h> 70 #include <net/if_dl.h> 71 #include <net/if_media.h> 72 #include <net/if_ether.h> 73 #include <sys/socket.h> 74 #include <sys/mbuf.h> 75 76 #include <net/bpf.h> 77 78 #include <dev/ic/i82596reg.h> 79 #include <dev/ic/i82596var.h> 80 81 /* Supported chip variants */ 82 const char *i82596_typenames[] = { "unknown", "DX/SX", "CA" }; 83 84 /* media change and status callback */ 85 static int iee_mediachange(struct ifnet *); 86 static void iee_mediastatus(struct ifnet *, struct ifmediareq *); 87 88 /* interface routines to upper protocols */ 89 static void iee_start(struct ifnet *); /* initiate output */ 90 static int iee_ioctl(struct ifnet *, u_long, void *); /* ioctl routine */ 91 static int iee_init(struct ifnet *); /* init routine */ 92 static void iee_stop(struct ifnet *, int); /* stop routine */ 93 static void iee_watchdog(struct ifnet *); /* timer routine */ 94 95 /* internal helper functions */ 96 static void iee_cb_setup(struct iee_softc *, uint32_t); 97 98 /* 99 * Things a MD frontend has to provide: 100 * 101 * The functions via function pointers in the softc: 102 * int (*sc_iee_cmd)(struct iee_softc *sc, uint32_t cmd); 103 * int (*sc_iee_reset)(struct iee_softc *sc); 104 * void (*sc_mediastatus)(struct ifnet *, struct ifmediareq *); 105 * int (*sc_mediachange)(struct ifnet *); 106 * 107 * sc_iee_cmd(): send a command to the i82596 by writing the cmd parameter 108 * to the SCP cmd word and issuing a Channel Attention. 109 * sc_iee_reset(): initiate a reset, supply the address of the SCP to the 110 * chip, wait for the chip to initialize and ACK interrupts that 111 * this may have caused by calling (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 112 * This functions must carefully bus_dmamap_sync() all data they have touched! 113 * 114 * sc_mediastatus() and sc_mediachange() are just MD hooks to the according 115 * MI functions. The MD frontend may set this pointers to NULL when they 116 * are not needed. 117 * 118 * sc->sc_type has to be set to I82596_UNKNOWN or I82596_DX or I82596_CA. 119 * This is for printing out the correct chip type at attach time only. The 120 * MI backend doesn't distinguish different chip types when programming 121 * the chip. 122 * 123 * IEE_NEED_SWAP in sc->sc_flags has to be cleared on little endian hardware 124 * and set on big endian hardware, when endianess conversion is not done 125 * by the bus attachment but done by i82596 chip itself. 126 * Usually you need to set IEE_NEED_SWAP on big endian machines 127 * where the hardware (the LE/~BE pin) is configured as BE mode. 128 * 129 * If the chip is configured as BE mode, all 8 bit (byte) and 16 bit (word) 130 * entities can be written in big endian. But Rev A chip doesn't support 131 * 32 bit (dword) entities with big endian byte ordering, so we have to 132 * treat all 32 bit (dword) entities as two 16 bit big endian entities. 133 * Rev B and C chips support big endian byte ordering for 32 bit entities, 134 * and this new feature is enabled by IEE_SYSBUS_BE in the sysbus byte. 135 * 136 * With the IEE_SYSBUS_BE feature, all 32 bit address ponters are 137 * treated as true 32 bit entities but the SCB absolute address and 138 * statistical counters are still treated as two 16 bit big endian entities, 139 * so we have to always swap high and low words for these entities. 140 * IEE_SWAP32() should be used for the SCB address and statistical counters, 141 * and IEE_SWAPA32() should be used for other 32 bit pointers in the shmem. 142 * 143 * IEE_REV_A flag must be set in sc->sc_flags if the IEE_SYSBUS_BE feature 144 * is disabled even on big endian machines for the old Rev A chip in backend. 145 * 146 * sc->sc_cl_align must be set to 1 or to the cache line size. When set to 147 * 1 no special alignment of DMA descriptors is done. If sc->sc_cl_align != 1 148 * it forces alignment of the data structures in the shared memory to a multiple 149 * of sc->sc_cl_align. This is needed on archs like hp700 that have non DMA 150 * I/O coherent caches and are unable to map the shared memory uncachable. 151 * (At least pre PA7100LC CPUs are unable to map memory uncachable.) 152 * 153 * The MD frontend also has to set sc->sc_cl_align and sc->sc_sysbus 154 * to allocate and setup shared DMA memory in MI iee_attach(). 155 * All communication with the chip is done via this shared memory. 156 * This memory is mapped with BUS_DMA_COHERENT so it will be uncached 157 * if possible for archs with non DMA I/O coherent caches. 158 * The base of the memory needs to be aligned to an even address 159 * if sc->sc_cl_align == 1 and aligned to a cache line if sc->sc_cl_align != 1. 160 * Each descriptor offsets are calculated in iee_attach() to handle this. 161 * 162 * An interrupt with iee_intr() as handler must be established. 163 * 164 * Call void iee_attach(struct iee_softc *sc, uint8_t *ether_address, 165 * int *media, int nmedia, int defmedia); when everything is set up. First 166 * parameter is a pointer to the MI softc, ether_address is an array that 167 * contains the ethernet address. media is an array of the media types 168 * provided by the hardware. The members of this array are supplied to 169 * ifmedia_add() in sequence. nmedia is the count of elements in media. 170 * defmedia is the default media that is set via ifmedia_set(). 171 * nmedia and defmedia are ignored when media == NULL. 172 * 173 * The MD backend may call iee_detach() to detach the device. 174 * 175 * See sys/arch/hp700/gsc/if_iee_gsc.c for an example. 176 */ 177 178 179 /* 180 * How frame reception is done: 181 * Each Receive Frame Descriptor has one associated Receive Buffer Descriptor. 182 * Each RBD points to the data area of an mbuf cluster. The RFDs are linked 183 * together in a circular list. sc->sc_rx_done is the count of RFDs in the 184 * list already processed / the number of the RFD that has to be checked for 185 * a new frame first at the next RX interrupt. Upon successful reception of 186 * a frame the mbuf cluster is handled to upper protocol layers, a new mbuf 187 * cluster is allocated and the RFD / RBD are reinitialized accordingly. 188 * 189 * When a RFD list overrun occurred the whole RFD and RBD lists are 190 * reinitialized and frame reception is started again. 191 */ 192 int 193 iee_intr(void *intarg) 194 { 195 struct iee_softc *sc = intarg; 196 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 197 struct iee_rfd *rfd; 198 struct iee_rbd *rbd; 199 bus_dmamap_t rx_map; 200 struct mbuf *rx_mbuf; 201 struct mbuf *new_mbuf; 202 int scb_status; 203 int scb_cmd; 204 int n, col; 205 uint16_t status, count, cmd; 206 207 if ((ifp->if_flags & IFF_RUNNING) == 0) { 208 (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 209 return 1; 210 } 211 IEE_SCBSYNC(sc, BUS_DMASYNC_POSTREAD); 212 scb_status = SC_SCB(sc)->scb_status; 213 scb_cmd = SC_SCB(sc)->scb_cmd; 214 for (;;) { 215 rfd = SC_RFD(sc, sc->sc_rx_done); 216 IEE_RFDSYNC(sc, sc->sc_rx_done, 217 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 218 status = rfd->rfd_status; 219 if ((status & IEE_RFD_C) == 0) { 220 IEE_RFDSYNC(sc, sc->sc_rx_done, BUS_DMASYNC_PREREAD); 221 break; 222 } 223 rfd->rfd_status = 0; 224 IEE_RFDSYNC(sc, sc->sc_rx_done, 225 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 226 227 /* At least one packet was received. */ 228 rx_map = sc->sc_rx_map[sc->sc_rx_done]; 229 rx_mbuf = sc->sc_rx_mbuf[sc->sc_rx_done]; 230 IEE_RBDSYNC(sc, (sc->sc_rx_done + IEE_NRFD - 1) % IEE_NRFD, 231 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 232 SC_RBD(sc, (sc->sc_rx_done + IEE_NRFD - 1) % IEE_NRFD)->rbd_size 233 &= ~IEE_RBD_EL; 234 IEE_RBDSYNC(sc, (sc->sc_rx_done + IEE_NRFD - 1) % IEE_NRFD, 235 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 236 rbd = SC_RBD(sc, sc->sc_rx_done); 237 IEE_RBDSYNC(sc, sc->sc_rx_done, 238 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 239 count = rbd->rbd_count; 240 if ((status & IEE_RFD_OK) == 0 241 || (count & IEE_RBD_EOF) == 0 242 || (count & IEE_RBD_F) == 0){ 243 /* Receive error, skip frame and reuse buffer. */ 244 rbd->rbd_count = 0; 245 rbd->rbd_size = IEE_RBD_EL | rx_map->dm_segs[0].ds_len; 246 IEE_RBDSYNC(sc, sc->sc_rx_done, 247 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 248 printf("%s: iee_intr: receive error %d, rfd_status=" 249 "0x%.4x, rfd_count=0x%.4x\n", 250 device_xname(sc->sc_dev), 251 ++sc->sc_rx_err, status, count); 252 sc->sc_rx_done = (sc->sc_rx_done + 1) % IEE_NRFD; 253 continue; 254 } 255 bus_dmamap_sync(sc->sc_dmat, rx_map, 0, rx_map->dm_mapsize, 256 BUS_DMASYNC_POSTREAD); 257 rx_mbuf->m_pkthdr.len = rx_mbuf->m_len = 258 count & IEE_RBD_COUNT; 259 rx_mbuf->m_pkthdr.rcvif = ifp; 260 MGETHDR(new_mbuf, M_DONTWAIT, MT_DATA); 261 if (new_mbuf == NULL) { 262 printf("%s: iee_intr: can't allocate mbuf\n", 263 device_xname(sc->sc_dev)); 264 break; 265 } 266 MCLAIM(new_mbuf, &sc->sc_ethercom.ec_rx_mowner); 267 MCLGET(new_mbuf, M_DONTWAIT); 268 if ((new_mbuf->m_flags & M_EXT) == 0) { 269 printf("%s: iee_intr: can't alloc mbuf cluster\n", 270 device_xname(sc->sc_dev)); 271 m_freem(new_mbuf); 272 break; 273 } 274 bus_dmamap_unload(sc->sc_dmat, rx_map); 275 new_mbuf->m_len = new_mbuf->m_pkthdr.len = MCLBYTES - 2; 276 new_mbuf->m_data += 2; 277 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_map, 278 new_mbuf, BUS_DMA_READ | BUS_DMA_NOWAIT) != 0) 279 panic("%s: iee_intr: can't load RX DMA map\n", 280 device_xname(sc->sc_dev)); 281 bus_dmamap_sync(sc->sc_dmat, rx_map, 0, 282 rx_map->dm_mapsize, BUS_DMASYNC_PREREAD); 283 bpf_mtap(ifp, rx_mbuf); 284 (*ifp->if_input)(ifp, rx_mbuf); 285 ifp->if_ipackets++; 286 sc->sc_rx_mbuf[sc->sc_rx_done] = new_mbuf; 287 rbd->rbd_count = 0; 288 rbd->rbd_size = IEE_RBD_EL | rx_map->dm_segs[0].ds_len; 289 rbd->rbd_rb_addr = IEE_SWAPA32(rx_map->dm_segs[0].ds_addr); 290 IEE_RBDSYNC(sc, sc->sc_rx_done, 291 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 292 sc->sc_rx_done = (sc->sc_rx_done + 1) % IEE_NRFD; 293 } 294 if ((scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR1 295 || (scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR2 296 || (scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR3) { 297 /* Receive Overrun, reinit receive ring buffer. */ 298 for (n = 0 ; n < IEE_NRFD ; n++) { 299 rfd = SC_RFD(sc, n); 300 rbd = SC_RBD(sc, n); 301 rfd->rfd_cmd = IEE_RFD_SF; 302 rfd->rfd_link_addr = 303 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off 304 + sc->sc_rfd_sz * ((n + 1) % IEE_NRFD))); 305 rbd->rbd_next_rbd = 306 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off 307 + sc->sc_rbd_sz * ((n + 1) % IEE_NRFD))); 308 rbd->rbd_size = IEE_RBD_EL | 309 sc->sc_rx_map[n]->dm_segs[0].ds_len; 310 rbd->rbd_rb_addr = 311 IEE_SWAPA32(sc->sc_rx_map[n]->dm_segs[0].ds_addr); 312 } 313 SC_RFD(sc, 0)->rfd_rbd_addr = 314 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off)); 315 sc->sc_rx_done = 0; 316 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, sc->sc_rfd_off, 317 sc->sc_rfd_sz * IEE_NRFD + sc->sc_rbd_sz * IEE_NRFD, 318 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 319 (sc->sc_iee_cmd)(sc, IEE_SCB_RUC_ST); 320 printf("%s: iee_intr: receive ring buffer overrun\n", 321 device_xname(sc->sc_dev)); 322 } 323 324 if (sc->sc_next_cb != 0) { 325 IEE_CBSYNC(sc, sc->sc_next_cb - 1, 326 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 327 status = SC_CB(sc, sc->sc_next_cb - 1)->cb_status; 328 IEE_CBSYNC(sc, sc->sc_next_cb - 1, 329 BUS_DMASYNC_PREREAD); 330 if ((status & IEE_CB_C) != 0) { 331 /* CMD list finished */ 332 ifp->if_timer = 0; 333 if (sc->sc_next_tbd != 0) { 334 /* A TX CMD list finished, cleanup */ 335 for (n = 0 ; n < sc->sc_next_cb ; n++) { 336 m_freem(sc->sc_tx_mbuf[n]); 337 sc->sc_tx_mbuf[n] = NULL; 338 bus_dmamap_unload(sc->sc_dmat, 339 sc->sc_tx_map[n]); 340 IEE_CBSYNC(sc, n, 341 BUS_DMASYNC_POSTREAD| 342 BUS_DMASYNC_POSTWRITE); 343 status = SC_CB(sc, n)->cb_status; 344 IEE_CBSYNC(sc, n, 345 BUS_DMASYNC_PREREAD); 346 if ((status & IEE_CB_COL) != 0 && 347 (status & IEE_CB_MAXCOL) == 0) 348 col = 16; 349 else 350 col = status 351 & IEE_CB_MAXCOL; 352 sc->sc_tx_col += col; 353 if ((status & IEE_CB_OK) != 0) { 354 ifp->if_opackets++; 355 ifp->if_collisions += col; 356 } 357 } 358 sc->sc_next_tbd = 0; 359 ifp->if_flags &= ~IFF_OACTIVE; 360 } 361 for (n = 0 ; n < sc->sc_next_cb; n++) { 362 /* 363 * Check if a CMD failed, but ignore TX errors. 364 */ 365 IEE_CBSYNC(sc, n, 366 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 367 cmd = SC_CB(sc, n)->cb_cmd; 368 status = SC_CB(sc, n)->cb_status; 369 IEE_CBSYNC(sc, n, BUS_DMASYNC_PREREAD); 370 if ((cmd & IEE_CB_CMD) != IEE_CB_CMD_TR && 371 (status & IEE_CB_OK) == 0) 372 printf("%s: iee_intr: scb_status=0x%x " 373 "scb_cmd=0x%x failed command %d: " 374 "cb_status[%d]=0x%.4x " 375 "cb_cmd[%d]=0x%.4x\n", 376 device_xname(sc->sc_dev), 377 scb_status, scb_cmd, 378 ++sc->sc_cmd_err, 379 n, status, n, cmd); 380 } 381 sc->sc_next_cb = 0; 382 if ((sc->sc_flags & IEE_WANT_MCAST) != 0) { 383 iee_cb_setup(sc, IEE_CB_CMD_MCS | 384 IEE_CB_S | IEE_CB_EL | IEE_CB_I); 385 (sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE); 386 } else 387 /* Try to get deferred packets going. */ 388 iee_start(ifp); 389 } 390 } 391 if (IEE_SWAP32(SC_SCB(sc)->scb_crc_err) != sc->sc_crc_err) { 392 sc->sc_crc_err = IEE_SWAP32(SC_SCB(sc)->scb_crc_err); 393 printf("%s: iee_intr: crc_err=%d\n", device_xname(sc->sc_dev), 394 sc->sc_crc_err); 395 } 396 if (IEE_SWAP32(SC_SCB(sc)->scb_align_err) != sc->sc_align_err) { 397 sc->sc_align_err = IEE_SWAP32(SC_SCB(sc)->scb_align_err); 398 printf("%s: iee_intr: align_err=%d\n", device_xname(sc->sc_dev), 399 sc->sc_align_err); 400 } 401 if (IEE_SWAP32(SC_SCB(sc)->scb_resource_err) != sc->sc_resource_err) { 402 sc->sc_resource_err = IEE_SWAP32(SC_SCB(sc)->scb_resource_err); 403 printf("%s: iee_intr: resource_err=%d\n", 404 device_xname(sc->sc_dev), sc->sc_resource_err); 405 } 406 if (IEE_SWAP32(SC_SCB(sc)->scb_overrun_err) != sc->sc_overrun_err) { 407 sc->sc_overrun_err = IEE_SWAP32(SC_SCB(sc)->scb_overrun_err); 408 printf("%s: iee_intr: overrun_err=%d\n", 409 device_xname(sc->sc_dev), sc->sc_overrun_err); 410 } 411 if (IEE_SWAP32(SC_SCB(sc)->scb_rcvcdt_err) != sc->sc_rcvcdt_err) { 412 sc->sc_rcvcdt_err = IEE_SWAP32(SC_SCB(sc)->scb_rcvcdt_err); 413 printf("%s: iee_intr: rcvcdt_err=%d\n", 414 device_xname(sc->sc_dev), sc->sc_rcvcdt_err); 415 } 416 if (IEE_SWAP32(SC_SCB(sc)->scb_short_fr_err) != sc->sc_short_fr_err) { 417 sc->sc_short_fr_err = IEE_SWAP32(SC_SCB(sc)->scb_short_fr_err); 418 printf("%s: iee_intr: short_fr_err=%d\n", 419 device_xname(sc->sc_dev), sc->sc_short_fr_err); 420 } 421 IEE_SCBSYNC(sc, BUS_DMASYNC_PREREAD); 422 (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 423 return 1; 424 } 425 426 427 428 /* 429 * How Command Block List Processing is done. 430 * 431 * A running CBL is never manipulated. If there is a CBL already running, 432 * further CMDs are deferred until the current list is done. A new list is 433 * setup when the old one has finished. 434 * This eases programming. To manipulate a running CBL it is necessary to 435 * suspend the Command Unit to avoid race conditions. After a suspend 436 * is sent we have to wait for an interrupt that ACKs the suspend. Then 437 * we can manipulate the CBL and resume operation. I am not sure that this 438 * is more effective then the current, much simpler approach. => KISS 439 * See i82596CA data sheet page 26. 440 * 441 * A CBL is running or on the way to be set up when (sc->sc_next_cb != 0). 442 * 443 * A CBL may consist of TX CMDs, and _only_ TX CMDs. 444 * A TX CBL is running or on the way to be set up when 445 * ((sc->sc_next_cb != 0) && (sc->sc_next_tbd != 0)). 446 * 447 * A CBL may consist of other non-TX CMDs like IAS or CONF, and _only_ 448 * non-TX CMDs. 449 * 450 * This comes mostly through the way how an Ethernet driver works and 451 * because running CBLs are not manipulated when they are on the way. If 452 * if_start() is called there will be TX CMDs enqueued so we have a running 453 * CBL and other CMDs from e.g. if_ioctl() will be deferred and vice versa. 454 * 455 * The Multicast Setup Command is special. A MCS needs more space than 456 * a single CB has. Actual space requirement depends on the length of the 457 * multicast list. So we always defer MCS until other CBLs are finished, 458 * then we setup a CONF CMD in the first CB. The CONF CMD is needed to 459 * turn ALLMULTI on the hardware on or off. The MCS is the 2nd CB and may 460 * use all the remaining space in the CBL and the Transmit Buffer Descriptor 461 * List. (Therefore CBL and TBDL must be continuous in physical and virtual 462 * memory. This is guaranteed through the definitions of the list offsets 463 * in i82596reg.h and because it is only a single DMA segment used for all 464 * lists.) When ALLMULTI is enabled via the CONF CMD, the MCS is run with 465 * a multicast list length of 0, thus disabling the multicast filter. 466 * A deferred MCS is signaled via ((sc->sc_flags & IEE_WANT_MCAST) != 0) 467 */ 468 void 469 iee_cb_setup(struct iee_softc *sc, uint32_t cmd) 470 { 471 struct iee_cb *cb = SC_CB(sc, sc->sc_next_cb); 472 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 473 struct ether_multistep step; 474 struct ether_multi *enm; 475 476 memset(cb, 0, sc->sc_cb_sz); 477 cb->cb_cmd = cmd; 478 switch (cmd & IEE_CB_CMD) { 479 case IEE_CB_CMD_NOP: /* NOP CMD */ 480 break; 481 case IEE_CB_CMD_IAS: /* Individual Address Setup */ 482 memcpy(__UNVOLATILE(cb->cb_ind_addr), CLLADDR(ifp->if_sadl), 483 ETHER_ADDR_LEN); 484 break; 485 case IEE_CB_CMD_CONF: /* Configure */ 486 memcpy(__UNVOLATILE(cb->cb_cf), sc->sc_cf, sc->sc_cf[0] 487 & IEE_CF_0_CNT_M); 488 break; 489 case IEE_CB_CMD_MCS: /* Multicast Setup */ 490 if (sc->sc_next_cb != 0) { 491 sc->sc_flags |= IEE_WANT_MCAST; 492 return; 493 } 494 sc->sc_flags &= ~IEE_WANT_MCAST; 495 if ((sc->sc_cf[8] & IEE_CF_8_PRM) != 0) { 496 /* Need no multicast filter in promisc mode. */ 497 iee_cb_setup(sc, IEE_CB_CMD_CONF | IEE_CB_S | IEE_CB_EL 498 | IEE_CB_I); 499 return; 500 } 501 /* Leave room for a CONF CMD to en/dis-able ALLMULTI mode */ 502 cb = SC_CB(sc, sc->sc_next_cb + 1); 503 cb->cb_cmd = cmd; 504 cb->cb_mcast.mc_size = 0; 505 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 506 while (enm != NULL) { 507 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 508 ETHER_ADDR_LEN) != 0 || cb->cb_mcast.mc_size 509 * ETHER_ADDR_LEN + 2 * sc->sc_cb_sz > 510 sc->sc_cb_sz * IEE_NCB + 511 sc->sc_tbd_sz * IEE_NTBD * IEE_NCB) { 512 cb->cb_mcast.mc_size = 0; 513 break; 514 } 515 memcpy(__UNVOLATILE(&cb->cb_mcast.mc_addrs[ 516 cb->cb_mcast.mc_size * ETHER_ADDR_LEN]), 517 enm->enm_addrlo, ETHER_ADDR_LEN); 518 ETHER_NEXT_MULTI(step, enm); 519 cb->cb_mcast.mc_size++; 520 } 521 if (cb->cb_mcast.mc_size == 0) { 522 /* Can't do exact mcast filtering, do ALLMULTI mode. */ 523 ifp->if_flags |= IFF_ALLMULTI; 524 sc->sc_cf[11] &= ~IEE_CF_11_MCALL; 525 } else { 526 /* disable ALLMULTI and load mcast list */ 527 ifp->if_flags &= ~IFF_ALLMULTI; 528 sc->sc_cf[11] |= IEE_CF_11_MCALL; 529 /* Mcast setup may need more then sc->sc_cb_sz bytes. */ 530 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 531 sc->sc_cb_off, 532 sc->sc_cb_sz * IEE_NCB + 533 sc->sc_tbd_sz * IEE_NTBD * IEE_NCB, 534 BUS_DMASYNC_PREWRITE); 535 } 536 iee_cb_setup(sc, IEE_CB_CMD_CONF); 537 break; 538 case IEE_CB_CMD_TR: /* Transmit */ 539 cb->cb_transmit.tx_tbd_addr = 540 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_tbd_off 541 + sc->sc_tbd_sz * sc->sc_next_tbd)); 542 cb->cb_cmd |= IEE_CB_SF; /* Always use Flexible Mode. */ 543 break; 544 case IEE_CB_CMD_TDR: /* Time Domain Reflectometry */ 545 break; 546 case IEE_CB_CMD_DUMP: /* Dump */ 547 break; 548 case IEE_CB_CMD_DIAG: /* Diagnose */ 549 break; 550 default: 551 /* can't happen */ 552 break; 553 } 554 cb->cb_link_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_cb_off + 555 sc->sc_cb_sz * (sc->sc_next_cb + 1))); 556 IEE_CBSYNC(sc, sc->sc_next_cb, 557 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 558 sc->sc_next_cb++; 559 ifp->if_timer = 5; 560 } 561 562 563 564 void 565 iee_attach(struct iee_softc *sc, uint8_t *eth_addr, int *media, int nmedia, 566 int defmedia) 567 { 568 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 569 int n; 570 571 KASSERT(sc->sc_cl_align > 0 && powerof2(sc->sc_cl_align)); 572 573 /* 574 * Calculate DMA descriptor offsets and sizes in shmem 575 * which should be cache line aligned. 576 */ 577 sc->sc_scp_off = 0; 578 sc->sc_scp_sz = roundup2(sizeof(struct iee_scp), sc->sc_cl_align); 579 sc->sc_iscp_off = sc->sc_scp_sz; 580 sc->sc_iscp_sz = roundup2(sizeof(struct iee_iscp), sc->sc_cl_align); 581 sc->sc_scb_off = sc->sc_iscp_off + sc->sc_iscp_sz; 582 sc->sc_scb_sz = roundup2(sizeof(struct iee_scb), sc->sc_cl_align); 583 sc->sc_rfd_off = sc->sc_scb_off + sc->sc_scb_sz; 584 sc->sc_rfd_sz = roundup2(sizeof(struct iee_rfd), sc->sc_cl_align); 585 sc->sc_rbd_off = sc->sc_rfd_off + sc->sc_rfd_sz * IEE_NRFD; 586 sc->sc_rbd_sz = roundup2(sizeof(struct iee_rbd), sc->sc_cl_align); 587 sc->sc_cb_off = sc->sc_rbd_off + sc->sc_rbd_sz * IEE_NRFD; 588 sc->sc_cb_sz = roundup2(sizeof(struct iee_cb), sc->sc_cl_align); 589 sc->sc_tbd_off = sc->sc_cb_off + sc->sc_cb_sz * IEE_NCB; 590 sc->sc_tbd_sz = roundup2(sizeof(struct iee_tbd), sc->sc_cl_align); 591 sc->sc_shmem_sz = sc->sc_tbd_off + sc->sc_tbd_sz * IEE_NTBD * IEE_NCB; 592 593 /* allocate memory for shared DMA descriptors */ 594 if (bus_dmamem_alloc(sc->sc_dmat, sc->sc_shmem_sz, PAGE_SIZE, 0, 595 &sc->sc_dma_segs, 1, &sc->sc_dma_rsegs, BUS_DMA_NOWAIT) != 0) { 596 aprint_error(": can't allocate %d bytes of DMA memory\n", 597 sc->sc_shmem_sz); 598 return; 599 } 600 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_dma_segs, sc->sc_dma_rsegs, 601 sc->sc_shmem_sz, (void **)&sc->sc_shmem_addr, 602 BUS_DMA_COHERENT | BUS_DMA_NOWAIT) != 0) { 603 aprint_error(": can't map DMA memory\n"); 604 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, 605 sc->sc_dma_rsegs); 606 return; 607 } 608 if (bus_dmamap_create(sc->sc_dmat, sc->sc_shmem_sz, sc->sc_dma_rsegs, 609 sc->sc_shmem_sz, 0, BUS_DMA_NOWAIT, &sc->sc_shmem_map) != 0) { 610 aprint_error(": can't create DMA map\n"); 611 bus_dmamem_unmap(sc->sc_dmat, sc->sc_shmem_addr, 612 sc->sc_shmem_sz); 613 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, 614 sc->sc_dma_rsegs); 615 return; 616 } 617 if (bus_dmamap_load(sc->sc_dmat, sc->sc_shmem_map, sc->sc_shmem_addr, 618 sc->sc_shmem_sz, NULL, BUS_DMA_NOWAIT) != 0) { 619 aprint_error(": can't load DMA map\n"); 620 bus_dmamap_destroy(sc->sc_dmat, sc->sc_shmem_map); 621 bus_dmamem_unmap(sc->sc_dmat, sc->sc_shmem_addr, 622 sc->sc_shmem_sz); 623 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, 624 sc->sc_dma_rsegs); 625 return; 626 } 627 memset(sc->sc_shmem_addr, 0, sc->sc_shmem_sz); 628 629 /* Set pointer to Intermediate System Configuration Pointer. */ 630 /* Phys. addr. in big endian order. (Big endian as defined by Intel.) */ 631 SC_SCP(sc)->scp_iscp_addr = IEE_SWAP32(IEE_PHYS_SHMEM(sc->sc_iscp_off)); 632 SC_SCP(sc)->scp_sysbus = sc->sc_sysbus; 633 /* Set pointer to System Control Block. */ 634 /* Phys. addr. in big endian order. (Big endian as defined by Intel.) */ 635 SC_ISCP(sc)->iscp_scb_addr = IEE_SWAP32(IEE_PHYS_SHMEM(sc->sc_scb_off)); 636 /* Set pointer to Receive Frame Area. (physical address) */ 637 SC_SCB(sc)->scb_rfa_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off)); 638 /* Set pointer to Command Block. (physical address) */ 639 SC_SCB(sc)->scb_cmd_blk_addr = 640 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_cb_off)); 641 642 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 0, sc->sc_shmem_sz, 643 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 644 645 ifmedia_init(&sc->sc_ifmedia, 0, iee_mediachange, iee_mediastatus); 646 if (media != NULL) { 647 for (n = 0 ; n < nmedia ; n++) 648 ifmedia_add(&sc->sc_ifmedia, media[n], 0, NULL); 649 ifmedia_set(&sc->sc_ifmedia, defmedia); 650 } else { 651 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_NONE, 0, NULL); 652 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_NONE); 653 } 654 655 ifp->if_softc = sc; 656 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 657 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 658 ifp->if_start = iee_start; /* initiate output routine */ 659 ifp->if_ioctl = iee_ioctl; /* ioctl routine */ 660 ifp->if_init = iee_init; /* init routine */ 661 ifp->if_stop = iee_stop; /* stop routine */ 662 ifp->if_watchdog = iee_watchdog; /* timer routine */ 663 IFQ_SET_READY(&ifp->if_snd); 664 /* iee supports IEEE 802.1Q Virtual LANs, see vlan(4). */ 665 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 666 667 if_attach(ifp); 668 ether_ifattach(ifp, eth_addr); 669 670 aprint_normal(": Intel 82596%s address %s\n", 671 i82596_typenames[sc->sc_type], ether_sprintf(eth_addr)); 672 673 for (n = 0 ; n < IEE_NCB ; n++) 674 sc->sc_tx_map[n] = NULL; 675 for (n = 0 ; n < IEE_NRFD ; n++) { 676 sc->sc_rx_mbuf[n] = NULL; 677 sc->sc_rx_map[n] = NULL; 678 } 679 sc->sc_tx_timeout = 0; 680 sc->sc_setup_timeout = 0; 681 (sc->sc_iee_reset)(sc); 682 } 683 684 685 686 void 687 iee_detach(struct iee_softc *sc, int flags) 688 { 689 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 690 691 if ((ifp->if_flags & IFF_RUNNING) != 0) 692 iee_stop(ifp, 1); 693 ether_ifdetach(ifp); 694 if_detach(ifp); 695 bus_dmamap_unload(sc->sc_dmat, sc->sc_shmem_map); 696 bus_dmamap_destroy(sc->sc_dmat, sc->sc_shmem_map); 697 bus_dmamem_unmap(sc->sc_dmat, sc->sc_shmem_addr, sc->sc_shmem_sz); 698 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, sc->sc_dma_rsegs); 699 } 700 701 702 703 /* media change and status callback */ 704 int 705 iee_mediachange(struct ifnet *ifp) 706 { 707 struct iee_softc *sc = ifp->if_softc; 708 709 if (sc->sc_mediachange != NULL) 710 return (sc->sc_mediachange)(ifp); 711 return 0; 712 } 713 714 715 716 void 717 iee_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmreq) 718 { 719 struct iee_softc *sc = ifp->if_softc; 720 721 if (sc->sc_mediastatus != NULL) 722 (sc->sc_mediastatus)(ifp, ifmreq); 723 } 724 725 726 727 /* initiate output routine */ 728 void 729 iee_start(struct ifnet *ifp) 730 { 731 struct iee_softc *sc = ifp->if_softc; 732 struct mbuf *m = NULL; 733 struct iee_tbd *tbd; 734 int t; 735 int n; 736 737 if (sc->sc_next_cb != 0) 738 /* There is already a CMD running. Defer packet enqueuing. */ 739 return; 740 for (t = 0 ; t < IEE_NCB ; t++) { 741 IFQ_DEQUEUE(&ifp->if_snd, sc->sc_tx_mbuf[t]); 742 if (sc->sc_tx_mbuf[t] == NULL) 743 break; 744 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_tx_map[t], 745 sc->sc_tx_mbuf[t], BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 746 /* 747 * The packet needs more TBD then we support. 748 * Copy the packet into a mbuf cluster to get it out. 749 */ 750 printf("%s: iee_start: failed to load DMA map\n", 751 device_xname(sc->sc_dev)); 752 MGETHDR(m, M_DONTWAIT, MT_DATA); 753 if (m == NULL) { 754 printf("%s: iee_start: can't allocate mbuf\n", 755 device_xname(sc->sc_dev)); 756 m_freem(sc->sc_tx_mbuf[t]); 757 t--; 758 continue; 759 } 760 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 761 MCLGET(m, M_DONTWAIT); 762 if ((m->m_flags & M_EXT) == 0) { 763 printf("%s: iee_start: can't allocate mbuf " 764 "cluster\n", device_xname(sc->sc_dev)); 765 m_freem(sc->sc_tx_mbuf[t]); 766 m_freem(m); 767 t--; 768 continue; 769 } 770 m_copydata(sc->sc_tx_mbuf[t], 0, 771 sc->sc_tx_mbuf[t]->m_pkthdr.len, mtod(m, void *)); 772 m->m_pkthdr.len = sc->sc_tx_mbuf[t]->m_pkthdr.len; 773 m->m_len = sc->sc_tx_mbuf[t]->m_pkthdr.len; 774 m_freem(sc->sc_tx_mbuf[t]); 775 sc->sc_tx_mbuf[t] = m; 776 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_tx_map[t], 777 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 778 printf("%s: iee_start: can't load TX DMA map\n", 779 device_xname(sc->sc_dev)); 780 m_freem(sc->sc_tx_mbuf[t]); 781 t--; 782 continue; 783 } 784 } 785 for (n = 0 ; n < sc->sc_tx_map[t]->dm_nsegs ; n++) { 786 tbd = SC_TBD(sc, sc->sc_next_tbd + n); 787 tbd->tbd_tb_addr = 788 IEE_SWAPA32(sc->sc_tx_map[t]->dm_segs[n].ds_addr); 789 tbd->tbd_size = 790 sc->sc_tx_map[t]->dm_segs[n].ds_len; 791 tbd->tbd_link_addr = 792 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_tbd_off + 793 sc->sc_tbd_sz * (sc->sc_next_tbd + n + 1))); 794 } 795 SC_TBD(sc, sc->sc_next_tbd + n - 1)->tbd_size |= IEE_CB_EL; 796 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 797 sc->sc_tbd_off + sc->sc_next_tbd * sc->sc_tbd_sz, 798 sc->sc_tbd_sz * sc->sc_tx_map[t]->dm_nsegs, 799 BUS_DMASYNC_PREWRITE); 800 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_map[t], 0, 801 sc->sc_tx_map[t]->dm_mapsize, BUS_DMASYNC_PREWRITE); 802 IFQ_POLL(&ifp->if_snd, m); 803 if (m == NULL) 804 iee_cb_setup(sc, IEE_CB_CMD_TR | IEE_CB_S | IEE_CB_EL 805 | IEE_CB_I); 806 else 807 iee_cb_setup(sc, IEE_CB_CMD_TR); 808 sc->sc_next_tbd += n; 809 /* Pass packet to bpf if someone listens. */ 810 bpf_mtap(ifp, sc->sc_tx_mbuf[t]); 811 } 812 if (t == 0) 813 /* No packets got set up for TX. */ 814 return; 815 if (t == IEE_NCB) 816 ifp->if_flags |= IFF_OACTIVE; 817 (sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE); 818 } 819 820 821 822 /* ioctl routine */ 823 int 824 iee_ioctl(struct ifnet *ifp, u_long cmd, void *data) 825 { 826 struct iee_softc *sc = ifp->if_softc; 827 int s; 828 int err; 829 830 s = splnet(); 831 switch (cmd) { 832 case SIOCSIFMEDIA: 833 case SIOCGIFMEDIA: 834 err = ifmedia_ioctl(ifp, (struct ifreq *) data, 835 &sc->sc_ifmedia, cmd); 836 break; 837 838 default: 839 err = ether_ioctl(ifp, cmd, data); 840 if (err == ENETRESET) { 841 /* 842 * Multicast list as changed; set the hardware filter 843 * accordingly. 844 */ 845 if (ifp->if_flags & IFF_RUNNING) { 846 iee_cb_setup(sc, IEE_CB_CMD_MCS | IEE_CB_S | 847 IEE_CB_EL | IEE_CB_I); 848 if ((sc->sc_flags & IEE_WANT_MCAST) == 0) 849 (*sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE); 850 } 851 err = 0; 852 } 853 break; 854 } 855 splx(s); 856 return err; 857 } 858 859 860 861 /* init routine */ 862 int 863 iee_init(struct ifnet *ifp) 864 { 865 struct iee_softc *sc = ifp->if_softc; 866 int r; 867 int t; 868 int n; 869 int err; 870 871 sc->sc_next_cb = 0; 872 sc->sc_next_tbd = 0; 873 sc->sc_flags &= ~IEE_WANT_MCAST; 874 sc->sc_rx_done = 0; 875 SC_SCB(sc)->scb_crc_err = 0; 876 SC_SCB(sc)->scb_align_err = 0; 877 SC_SCB(sc)->scb_resource_err = 0; 878 SC_SCB(sc)->scb_overrun_err = 0; 879 SC_SCB(sc)->scb_rcvcdt_err = 0; 880 SC_SCB(sc)->scb_short_fr_err = 0; 881 sc->sc_crc_err = 0; 882 sc->sc_align_err = 0; 883 sc->sc_resource_err = 0; 884 sc->sc_overrun_err = 0; 885 sc->sc_rcvcdt_err = 0; 886 sc->sc_short_fr_err = 0; 887 sc->sc_tx_col = 0; 888 sc->sc_rx_err = 0; 889 sc->sc_cmd_err = 0; 890 /* Create Transmit DMA maps. */ 891 for (t = 0 ; t < IEE_NCB ; t++) { 892 if (sc->sc_tx_map[t] == NULL && bus_dmamap_create(sc->sc_dmat, 893 MCLBYTES, IEE_NTBD, MCLBYTES, 0, BUS_DMA_NOWAIT, 894 &sc->sc_tx_map[t]) != 0) { 895 printf("%s: iee_init: can't create TX DMA map\n", 896 device_xname(sc->sc_dev)); 897 for (n = 0 ; n < t ; n++) 898 bus_dmamap_destroy(sc->sc_dmat, 899 sc->sc_tx_map[n]); 900 return ENOBUFS; 901 } 902 } 903 /* Initialize Receive Frame and Receive Buffer Descriptors */ 904 err = 0; 905 memset(SC_RFD(sc, 0), 0, sc->sc_rfd_sz * IEE_NRFD); 906 memset(SC_RBD(sc, 0), 0, sc->sc_rbd_sz * IEE_NRFD); 907 for (r = 0 ; r < IEE_NRFD ; r++) { 908 SC_RFD(sc, r)->rfd_cmd = IEE_RFD_SF; 909 SC_RFD(sc, r)->rfd_link_addr = 910 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off 911 + sc->sc_rfd_sz * ((r + 1) % IEE_NRFD))); 912 913 SC_RBD(sc, r)->rbd_next_rbd = 914 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off 915 + sc->sc_rbd_sz * ((r + 1) % IEE_NRFD))); 916 if (sc->sc_rx_mbuf[r] == NULL) { 917 MGETHDR(sc->sc_rx_mbuf[r], M_DONTWAIT, MT_DATA); 918 if (sc->sc_rx_mbuf[r] == NULL) { 919 printf("%s: iee_init: can't allocate mbuf\n", 920 device_xname(sc->sc_dev)); 921 err = 1; 922 break; 923 } 924 MCLAIM(sc->sc_rx_mbuf[r],&sc->sc_ethercom.ec_rx_mowner); 925 MCLGET(sc->sc_rx_mbuf[r], M_DONTWAIT); 926 if ((sc->sc_rx_mbuf[r]->m_flags & M_EXT) == 0) { 927 printf("%s: iee_init: can't allocate mbuf" 928 " cluster\n", device_xname(sc->sc_dev)); 929 m_freem(sc->sc_rx_mbuf[r]); 930 err = 1; 931 break; 932 } 933 sc->sc_rx_mbuf[r]->m_len = 934 sc->sc_rx_mbuf[r]->m_pkthdr.len = MCLBYTES - 2; 935 sc->sc_rx_mbuf[r]->m_data += 2; 936 } 937 if (sc->sc_rx_map[r] == NULL && bus_dmamap_create(sc->sc_dmat, 938 MCLBYTES, 1, MCLBYTES , 0, BUS_DMA_NOWAIT, 939 &sc->sc_rx_map[r]) != 0) { 940 printf("%s: iee_init: can't create RX " 941 "DMA map\n", device_xname(sc->sc_dev)); 942 m_freem(sc->sc_rx_mbuf[r]); 943 err = 1; 944 break; 945 } 946 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_rx_map[r], 947 sc->sc_rx_mbuf[r], BUS_DMA_READ | BUS_DMA_NOWAIT) != 0) { 948 printf("%s: iee_init: can't load RX DMA map\n", 949 device_xname(sc->sc_dev)); 950 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[r]); 951 m_freem(sc->sc_rx_mbuf[r]); 952 err = 1; 953 break; 954 } 955 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_map[r], 0, 956 sc->sc_rx_map[r]->dm_mapsize, BUS_DMASYNC_PREREAD); 957 SC_RBD(sc, r)->rbd_size = sc->sc_rx_map[r]->dm_segs[0].ds_len; 958 SC_RBD(sc, r)->rbd_rb_addr = 959 IEE_SWAPA32(sc->sc_rx_map[r]->dm_segs[0].ds_addr); 960 } 961 SC_RFD(sc, 0)->rfd_rbd_addr = 962 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off)); 963 if (err != 0) { 964 for (n = 0 ; n < r; n++) { 965 m_freem(sc->sc_rx_mbuf[n]); 966 sc->sc_rx_mbuf[n] = NULL; 967 bus_dmamap_unload(sc->sc_dmat, sc->sc_rx_map[n]); 968 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[n]); 969 sc->sc_rx_map[n] = NULL; 970 } 971 for (n = 0 ; n < t ; n++) { 972 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_map[n]); 973 sc->sc_tx_map[n] = NULL; 974 } 975 return ENOBUFS; 976 } 977 978 (sc->sc_iee_reset)(sc); 979 iee_cb_setup(sc, IEE_CB_CMD_IAS); 980 sc->sc_cf[0] = IEE_CF_0_DEF | IEE_CF_0_PREF; 981 sc->sc_cf[1] = IEE_CF_1_DEF; 982 sc->sc_cf[2] = IEE_CF_2_DEF; 983 sc->sc_cf[3] = IEE_CF_3_ADDRLEN_DEF | IEE_CF_3_NSAI 984 | IEE_CF_3_PREAMLEN_DEF; 985 sc->sc_cf[4] = IEE_CF_4_DEF; 986 sc->sc_cf[5] = IEE_CF_5_DEF; 987 sc->sc_cf[6] = IEE_CF_6_DEF; 988 sc->sc_cf[7] = IEE_CF_7_DEF; 989 sc->sc_cf[8] = IEE_CF_8_DEF; 990 sc->sc_cf[9] = IEE_CF_9_DEF; 991 sc->sc_cf[10] = IEE_CF_10_DEF; 992 sc->sc_cf[11] = IEE_CF_11_DEF & ~IEE_CF_11_LNGFLD; 993 sc->sc_cf[12] = IEE_CF_12_DEF; 994 sc->sc_cf[13] = IEE_CF_13_DEF; 995 iee_cb_setup(sc, IEE_CB_CMD_CONF | IEE_CB_S | IEE_CB_EL); 996 SC_SCB(sc)->scb_rfa_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off)); 997 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 0, sc->sc_shmem_sz, 998 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 999 (sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE | IEE_SCB_RUC_ST); 1000 /* Issue a Channel Attention to ACK interrupts we may have caused. */ 1001 (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 1002 1003 /* Mark the interface as running and ready to RX/TX packets. */ 1004 ifp->if_flags |= IFF_RUNNING; 1005 ifp->if_flags &= ~IFF_OACTIVE; 1006 return 0; 1007 } 1008 1009 1010 1011 /* stop routine */ 1012 void 1013 iee_stop(struct ifnet *ifp, int disable) 1014 { 1015 struct iee_softc *sc = ifp->if_softc; 1016 int n; 1017 1018 ifp->if_flags &= ~IFF_RUNNING; 1019 ifp->if_flags |= IFF_OACTIVE; 1020 ifp->if_timer = 0; 1021 /* Reset the chip to get it quiet. */ 1022 (sc->sc_iee_reset)(ifp->if_softc); 1023 /* Issue a Channel Attention to ACK interrupts we may have caused. */ 1024 (sc->sc_iee_cmd)(ifp->if_softc, IEE_SCB_ACK); 1025 /* Release any dynamically allocated resources. */ 1026 for (n = 0 ; n < IEE_NCB ; n++) { 1027 if (sc->sc_tx_map[n] != NULL) 1028 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_map[n]); 1029 sc->sc_tx_map[n] = NULL; 1030 } 1031 for (n = 0 ; n < IEE_NRFD ; n++) { 1032 if (sc->sc_rx_mbuf[n] != NULL) 1033 m_freem(sc->sc_rx_mbuf[n]); 1034 sc->sc_rx_mbuf[n] = NULL; 1035 if (sc->sc_rx_map[n] != NULL) { 1036 bus_dmamap_unload(sc->sc_dmat, sc->sc_rx_map[n]); 1037 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[n]); 1038 } 1039 sc->sc_rx_map[n] = NULL; 1040 } 1041 } 1042 1043 1044 1045 /* timer routine */ 1046 void 1047 iee_watchdog(struct ifnet *ifp) 1048 { 1049 struct iee_softc *sc = ifp->if_softc; 1050 1051 (sc->sc_iee_reset)(sc); 1052 if (sc->sc_next_tbd != 0) 1053 printf("%s: iee_watchdog: transmit timeout %d\n", 1054 device_xname(sc->sc_dev), ++sc->sc_tx_timeout); 1055 else 1056 printf("%s: iee_watchdog: setup timeout %d\n", 1057 device_xname(sc->sc_dev), ++sc->sc_setup_timeout); 1058 iee_init(ifp); 1059 } 1060
Indexes created Mon Sep 29 03:10:08 GMT 2025