i82596.c revision 1.37
1 /* $NetBSD: i82596.c,v 1.37 2017/07/29 01:45:22 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Jochen Kunz. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Jochen Kunz may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY JOCHEN KUNZ 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL JOCHEN KUNZ 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the Intel i82596CA and i82596DX/SX 10MBit/s Ethernet chips. 34 * 35 * It operates the i82596 in 32-Bit Linear Mode, opposed to the old i82586 36 * ie(4) driver (src/sys/dev/ic/i82586.c), that degrades the i82596 to 37 * i82586 compatibility mode. 38 * 39 * Documentation about these chips can be found at 40 * 41 * http://developer.intel.com/design/network/datashts/290218.htm 42 * http://developer.intel.com/design/network/datashts/290219.htm 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: i82596.c,v 1.37 2017/07/29 01:45:22 riastradh Exp $"); 47 48 /* autoconfig and device stuff */ 49 #include <sys/param.h> 50 #include <sys/device.h> 51 #include <sys/conf.h> 52 #include "locators.h" 53 #include "ioconf.h" 54 55 /* bus_space / bus_dma etc. */ 56 #include <sys/bus.h> 57 #include <sys/intr.h> 58 59 /* general system data and functions */ 60 #include <sys/systm.h> 61 #include <sys/ioctl.h> 62 63 /* tsleep / sleep / wakeup */ 64 #include <sys/proc.h> 65 /* hz for above */ 66 #include <sys/kernel.h> 67 68 /* network stuff */ 69 #include <net/if.h> 70 #include <net/if_dl.h> 71 #include <net/if_media.h> 72 #include <net/if_ether.h> 73 #include <sys/socket.h> 74 #include <sys/mbuf.h> 75 76 #include <net/bpf.h> 77 78 #include <dev/ic/i82596reg.h> 79 #include <dev/ic/i82596var.h> 80 81 /* Supported chip variants */ 82 const char *i82596_typenames[] = { "unknown", "DX/SX", "CA" }; 83 84 /* media change and status callback */ 85 static int iee_mediachange(struct ifnet *); 86 static void iee_mediastatus(struct ifnet *, struct ifmediareq *); 87 88 /* interface routines to upper protocols */ 89 static void iee_start(struct ifnet *); /* initiate output */ 90 static int iee_ioctl(struct ifnet *, u_long, void *); /* ioctl routine */ 91 static int iee_init(struct ifnet *); /* init routine */ 92 static void iee_stop(struct ifnet *, int); /* stop routine */ 93 static void iee_watchdog(struct ifnet *); /* timer routine */ 94 95 /* internal helper functions */ 96 static void iee_cb_setup(struct iee_softc *, uint32_t); 97 98 /* 99 * Things a MD frontend has to provide: 100 * 101 * The functions via function pointers in the softc: 102 * int (*sc_iee_cmd)(struct iee_softc *sc, uint32_t cmd); 103 * int (*sc_iee_reset)(struct iee_softc *sc); 104 * void (*sc_mediastatus)(struct ifnet *, struct ifmediareq *); 105 * int (*sc_mediachange)(struct ifnet *); 106 * 107 * sc_iee_cmd(): send a command to the i82596 by writing the cmd parameter 108 * to the SCP cmd word and issuing a Channel Attention. 109 * sc_iee_reset(): initiate a reset, supply the address of the SCP to the 110 * chip, wait for the chip to initialize and ACK interrupts that 111 * this may have caused by calling (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 112 * This functions must carefully bus_dmamap_sync() all data they have touched! 113 * 114 * sc_mediastatus() and sc_mediachange() are just MD hooks to the according 115 * MI functions. The MD frontend may set this pointers to NULL when they 116 * are not needed. 117 * 118 * sc->sc_type has to be set to I82596_UNKNOWN or I82596_DX or I82596_CA. 119 * This is for printing out the correct chip type at attach time only. The 120 * MI backend doesn't distinguish different chip types when programming 121 * the chip. 122 * 123 * IEE_NEED_SWAP in sc->sc_flags has to be cleared on little endian hardware 124 * and set on big endian hardware, when endianess conversion is not done 125 * by the bus attachment but done by i82596 chip itself. 126 * Usually you need to set IEE_NEED_SWAP on big endian machines 127 * where the hardware (the LE/~BE pin) is configured as BE mode. 128 * 129 * If the chip is configured as BE mode, all 8 bit (byte) and 16 bit (word) 130 * entities can be written in big endian. But Rev A chip doesn't support 131 * 32 bit (dword) entities with big endian byte ordering, so we have to 132 * treat all 32 bit (dword) entities as two 16 bit big endian entities. 133 * Rev B and C chips support big endian byte ordering for 32 bit entities, 134 * and this new feature is enabled by IEE_SYSBUS_BE in the sysbus byte. 135 * 136 * With the IEE_SYSBUS_BE feature, all 32 bit address ponters are 137 * treated as true 32 bit entities but the SCB absolute address and 138 * statistical counters are still treated as two 16 bit big endian entities, 139 * so we have to always swap high and low words for these entities. 140 * IEE_SWAP32() should be used for the SCB address and statistical counters, 141 * and IEE_SWAPA32() should be used for other 32 bit pointers in the shmem. 142 * 143 * IEE_REV_A flag must be set in sc->sc_flags if the IEE_SYSBUS_BE feature 144 * is disabled even on big endian machines for the old Rev A chip in backend. 145 * 146 * sc->sc_cl_align must be set to 1 or to the cache line size. When set to 147 * 1 no special alignment of DMA descriptors is done. If sc->sc_cl_align != 1 148 * it forces alignment of the data structures in the shared memory to a multiple 149 * of sc->sc_cl_align. This is needed on some hppa machines that have non DMA 150 * I/O coherent caches and are unable to map the shared memory uncachable. 151 * (At least pre PA7100LC CPUs are unable to map memory uncachable.) 152 * 153 * The MD frontend also has to set sc->sc_cl_align and sc->sc_sysbus 154 * to allocate and setup shared DMA memory in MI iee_attach(). 155 * All communication with the chip is done via this shared memory. 156 * This memory is mapped with BUS_DMA_COHERENT so it will be uncached 157 * if possible for archs with non DMA I/O coherent caches. 158 * The base of the memory needs to be aligned to an even address 159 * if sc->sc_cl_align == 1 and aligned to a cache line if sc->sc_cl_align != 1. 160 * Each descriptor offsets are calculated in iee_attach() to handle this. 161 * 162 * An interrupt with iee_intr() as handler must be established. 163 * 164 * Call void iee_attach(struct iee_softc *sc, uint8_t *ether_address, 165 * int *media, int nmedia, int defmedia); when everything is set up. First 166 * parameter is a pointer to the MI softc, ether_address is an array that 167 * contains the ethernet address. media is an array of the media types 168 * provided by the hardware. The members of this array are supplied to 169 * ifmedia_add() in sequence. nmedia is the count of elements in media. 170 * defmedia is the default media that is set via ifmedia_set(). 171 * nmedia and defmedia are ignored when media == NULL. 172 * 173 * The MD backend may call iee_detach() to detach the device. 174 * 175 * See sys/arch/hppa/gsc/if_iee_gsc.c for an example. 176 */ 177 178 179 /* 180 * How frame reception is done: 181 * Each Receive Frame Descriptor has one associated Receive Buffer Descriptor. 182 * Each RBD points to the data area of an mbuf cluster. The RFDs are linked 183 * together in a circular list. sc->sc_rx_done is the count of RFDs in the 184 * list already processed / the number of the RFD that has to be checked for 185 * a new frame first at the next RX interrupt. Upon successful reception of 186 * a frame the mbuf cluster is handled to upper protocol layers, a new mbuf 187 * cluster is allocated and the RFD / RBD are reinitialized accordingly. 188 * 189 * When a RFD list overrun occurred the whole RFD and RBD lists are 190 * reinitialized and frame reception is started again. 191 */ 192 int 193 iee_intr(void *intarg) 194 { 195 struct iee_softc *sc = intarg; 196 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 197 struct iee_rfd *rfd; 198 struct iee_rbd *rbd; 199 bus_dmamap_t rx_map; 200 struct mbuf *rx_mbuf; 201 struct mbuf *new_mbuf; 202 int scb_status; 203 int scb_cmd; 204 int n, col; 205 uint16_t status, count, cmd; 206 207 if ((ifp->if_flags & IFF_RUNNING) == 0) { 208 (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 209 return 1; 210 } 211 IEE_SCBSYNC(sc, BUS_DMASYNC_POSTREAD); 212 scb_status = SC_SCB(sc)->scb_status; 213 scb_cmd = SC_SCB(sc)->scb_cmd; 214 for (;;) { 215 rfd = SC_RFD(sc, sc->sc_rx_done); 216 IEE_RFDSYNC(sc, sc->sc_rx_done, 217 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 218 status = rfd->rfd_status; 219 if ((status & IEE_RFD_C) == 0) { 220 IEE_RFDSYNC(sc, sc->sc_rx_done, BUS_DMASYNC_PREREAD); 221 break; 222 } 223 rfd->rfd_status = 0; 224 IEE_RFDSYNC(sc, sc->sc_rx_done, 225 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 226 227 /* At least one packet was received. */ 228 rx_map = sc->sc_rx_map[sc->sc_rx_done]; 229 rx_mbuf = sc->sc_rx_mbuf[sc->sc_rx_done]; 230 IEE_RBDSYNC(sc, (sc->sc_rx_done + IEE_NRFD - 1) % IEE_NRFD, 231 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 232 SC_RBD(sc, (sc->sc_rx_done + IEE_NRFD - 1) % IEE_NRFD)->rbd_size 233 &= ~IEE_RBD_EL; 234 IEE_RBDSYNC(sc, (sc->sc_rx_done + IEE_NRFD - 1) % IEE_NRFD, 235 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 236 rbd = SC_RBD(sc, sc->sc_rx_done); 237 IEE_RBDSYNC(sc, sc->sc_rx_done, 238 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 239 count = rbd->rbd_count; 240 if ((status & IEE_RFD_OK) == 0 241 || (count & IEE_RBD_EOF) == 0 242 || (count & IEE_RBD_F) == 0){ 243 /* Receive error, skip frame and reuse buffer. */ 244 rbd->rbd_count = 0; 245 rbd->rbd_size = IEE_RBD_EL | rx_map->dm_segs[0].ds_len; 246 IEE_RBDSYNC(sc, sc->sc_rx_done, 247 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 248 printf("%s: iee_intr: receive error %d, rfd_status=" 249 "0x%.4x, rfd_count=0x%.4x\n", 250 device_xname(sc->sc_dev), 251 ++sc->sc_rx_err, status, count); 252 sc->sc_rx_done = (sc->sc_rx_done + 1) % IEE_NRFD; 253 continue; 254 } 255 bus_dmamap_sync(sc->sc_dmat, rx_map, 0, rx_map->dm_mapsize, 256 BUS_DMASYNC_POSTREAD); 257 rx_mbuf->m_pkthdr.len = rx_mbuf->m_len = 258 count & IEE_RBD_COUNT; 259 m_set_rcvif(rx_mbuf, ifp); 260 MGETHDR(new_mbuf, M_DONTWAIT, MT_DATA); 261 if (new_mbuf == NULL) { 262 printf("%s: iee_intr: can't allocate mbuf\n", 263 device_xname(sc->sc_dev)); 264 break; 265 } 266 MCLAIM(new_mbuf, &sc->sc_ethercom.ec_rx_mowner); 267 MCLGET(new_mbuf, M_DONTWAIT); 268 if ((new_mbuf->m_flags & M_EXT) == 0) { 269 printf("%s: iee_intr: can't alloc mbuf cluster\n", 270 device_xname(sc->sc_dev)); 271 m_freem(new_mbuf); 272 break; 273 } 274 bus_dmamap_unload(sc->sc_dmat, rx_map); 275 new_mbuf->m_len = new_mbuf->m_pkthdr.len = MCLBYTES - 2; 276 new_mbuf->m_data += 2; 277 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_map, 278 new_mbuf, BUS_DMA_READ | BUS_DMA_NOWAIT) != 0) 279 panic("%s: iee_intr: can't load RX DMA map\n", 280 device_xname(sc->sc_dev)); 281 bus_dmamap_sync(sc->sc_dmat, rx_map, 0, 282 rx_map->dm_mapsize, BUS_DMASYNC_PREREAD); 283 if_percpuq_enqueue(ifp->if_percpuq, rx_mbuf); 284 sc->sc_rx_mbuf[sc->sc_rx_done] = new_mbuf; 285 rbd->rbd_count = 0; 286 rbd->rbd_size = IEE_RBD_EL | rx_map->dm_segs[0].ds_len; 287 rbd->rbd_rb_addr = IEE_SWAPA32(rx_map->dm_segs[0].ds_addr); 288 IEE_RBDSYNC(sc, sc->sc_rx_done, 289 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 290 sc->sc_rx_done = (sc->sc_rx_done + 1) % IEE_NRFD; 291 } 292 if ((scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR1 293 || (scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR2 294 || (scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR3) { 295 /* Receive Overrun, reinit receive ring buffer. */ 296 for (n = 0 ; n < IEE_NRFD ; n++) { 297 rfd = SC_RFD(sc, n); 298 rbd = SC_RBD(sc, n); 299 rfd->rfd_cmd = IEE_RFD_SF; 300 rfd->rfd_link_addr = 301 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off 302 + sc->sc_rfd_sz * ((n + 1) % IEE_NRFD))); 303 rbd->rbd_next_rbd = 304 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off 305 + sc->sc_rbd_sz * ((n + 1) % IEE_NRFD))); 306 rbd->rbd_size = IEE_RBD_EL | 307 sc->sc_rx_map[n]->dm_segs[0].ds_len; 308 rbd->rbd_rb_addr = 309 IEE_SWAPA32(sc->sc_rx_map[n]->dm_segs[0].ds_addr); 310 } 311 SC_RFD(sc, 0)->rfd_rbd_addr = 312 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off)); 313 sc->sc_rx_done = 0; 314 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, sc->sc_rfd_off, 315 sc->sc_rfd_sz * IEE_NRFD + sc->sc_rbd_sz * IEE_NRFD, 316 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 317 (sc->sc_iee_cmd)(sc, IEE_SCB_RUC_ST); 318 printf("%s: iee_intr: receive ring buffer overrun\n", 319 device_xname(sc->sc_dev)); 320 } 321 322 if (sc->sc_next_cb != 0) { 323 IEE_CBSYNC(sc, sc->sc_next_cb - 1, 324 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 325 status = SC_CB(sc, sc->sc_next_cb - 1)->cb_status; 326 IEE_CBSYNC(sc, sc->sc_next_cb - 1, 327 BUS_DMASYNC_PREREAD); 328 if ((status & IEE_CB_C) != 0) { 329 /* CMD list finished */ 330 ifp->if_timer = 0; 331 if (sc->sc_next_tbd != 0) { 332 /* A TX CMD list finished, cleanup */ 333 for (n = 0 ; n < sc->sc_next_cb ; n++) { 334 m_freem(sc->sc_tx_mbuf[n]); 335 sc->sc_tx_mbuf[n] = NULL; 336 bus_dmamap_unload(sc->sc_dmat, 337 sc->sc_tx_map[n]); 338 IEE_CBSYNC(sc, n, 339 BUS_DMASYNC_POSTREAD| 340 BUS_DMASYNC_POSTWRITE); 341 status = SC_CB(sc, n)->cb_status; 342 IEE_CBSYNC(sc, n, 343 BUS_DMASYNC_PREREAD); 344 if ((status & IEE_CB_COL) != 0 && 345 (status & IEE_CB_MAXCOL) == 0) 346 col = 16; 347 else 348 col = status 349 & IEE_CB_MAXCOL; 350 sc->sc_tx_col += col; 351 if ((status & IEE_CB_OK) != 0) { 352 ifp->if_opackets++; 353 ifp->if_collisions += col; 354 } 355 } 356 sc->sc_next_tbd = 0; 357 ifp->if_flags &= ~IFF_OACTIVE; 358 } 359 for (n = 0 ; n < sc->sc_next_cb; n++) { 360 /* 361 * Check if a CMD failed, but ignore TX errors. 362 */ 363 IEE_CBSYNC(sc, n, 364 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 365 cmd = SC_CB(sc, n)->cb_cmd; 366 status = SC_CB(sc, n)->cb_status; 367 IEE_CBSYNC(sc, n, BUS_DMASYNC_PREREAD); 368 if ((cmd & IEE_CB_CMD) != IEE_CB_CMD_TR && 369 (status & IEE_CB_OK) == 0) 370 printf("%s: iee_intr: scb_status=0x%x " 371 "scb_cmd=0x%x failed command %d: " 372 "cb_status[%d]=0x%.4x " 373 "cb_cmd[%d]=0x%.4x\n", 374 device_xname(sc->sc_dev), 375 scb_status, scb_cmd, 376 ++sc->sc_cmd_err, 377 n, status, n, cmd); 378 } 379 sc->sc_next_cb = 0; 380 if ((sc->sc_flags & IEE_WANT_MCAST) != 0) { 381 iee_cb_setup(sc, IEE_CB_CMD_MCS | 382 IEE_CB_S | IEE_CB_EL | IEE_CB_I); 383 (sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE); 384 } else 385 /* Try to get deferred packets going. */ 386 if_schedule_deferred_start(ifp); 387 } 388 } 389 if (IEE_SWAP32(SC_SCB(sc)->scb_crc_err) != sc->sc_crc_err) { 390 sc->sc_crc_err = IEE_SWAP32(SC_SCB(sc)->scb_crc_err); 391 printf("%s: iee_intr: crc_err=%d\n", device_xname(sc->sc_dev), 392 sc->sc_crc_err); 393 } 394 if (IEE_SWAP32(SC_SCB(sc)->scb_align_err) != sc->sc_align_err) { 395 sc->sc_align_err = IEE_SWAP32(SC_SCB(sc)->scb_align_err); 396 printf("%s: iee_intr: align_err=%d\n", device_xname(sc->sc_dev), 397 sc->sc_align_err); 398 } 399 if (IEE_SWAP32(SC_SCB(sc)->scb_resource_err) != sc->sc_resource_err) { 400 sc->sc_resource_err = IEE_SWAP32(SC_SCB(sc)->scb_resource_err); 401 printf("%s: iee_intr: resource_err=%d\n", 402 device_xname(sc->sc_dev), sc->sc_resource_err); 403 } 404 if (IEE_SWAP32(SC_SCB(sc)->scb_overrun_err) != sc->sc_overrun_err) { 405 sc->sc_overrun_err = IEE_SWAP32(SC_SCB(sc)->scb_overrun_err); 406 printf("%s: iee_intr: overrun_err=%d\n", 407 device_xname(sc->sc_dev), sc->sc_overrun_err); 408 } 409 if (IEE_SWAP32(SC_SCB(sc)->scb_rcvcdt_err) != sc->sc_rcvcdt_err) { 410 sc->sc_rcvcdt_err = IEE_SWAP32(SC_SCB(sc)->scb_rcvcdt_err); 411 printf("%s: iee_intr: rcvcdt_err=%d\n", 412 device_xname(sc->sc_dev), sc->sc_rcvcdt_err); 413 } 414 if (IEE_SWAP32(SC_SCB(sc)->scb_short_fr_err) != sc->sc_short_fr_err) { 415 sc->sc_short_fr_err = IEE_SWAP32(SC_SCB(sc)->scb_short_fr_err); 416 printf("%s: iee_intr: short_fr_err=%d\n", 417 device_xname(sc->sc_dev), sc->sc_short_fr_err); 418 } 419 IEE_SCBSYNC(sc, BUS_DMASYNC_PREREAD); 420 (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 421 return 1; 422 } 423 424 425 426 /* 427 * How Command Block List Processing is done. 428 * 429 * A running CBL is never manipulated. If there is a CBL already running, 430 * further CMDs are deferred until the current list is done. A new list is 431 * setup when the old one has finished. 432 * This eases programming. To manipulate a running CBL it is necessary to 433 * suspend the Command Unit to avoid race conditions. After a suspend 434 * is sent we have to wait for an interrupt that ACKs the suspend. Then 435 * we can manipulate the CBL and resume operation. I am not sure that this 436 * is more effective than the current, much simpler approach. => KISS 437 * See i82596CA data sheet page 26. 438 * 439 * A CBL is running or on the way to be set up when (sc->sc_next_cb != 0). 440 * 441 * A CBL may consist of TX CMDs, and _only_ TX CMDs. 442 * A TX CBL is running or on the way to be set up when 443 * ((sc->sc_next_cb != 0) && (sc->sc_next_tbd != 0)). 444 * 445 * A CBL may consist of other non-TX CMDs like IAS or CONF, and _only_ 446 * non-TX CMDs. 447 * 448 * This comes mostly through the way how an Ethernet driver works and 449 * because running CBLs are not manipulated when they are on the way. If 450 * if_start() is called there will be TX CMDs enqueued so we have a running 451 * CBL and other CMDs from e.g. if_ioctl() will be deferred and vice versa. 452 * 453 * The Multicast Setup Command is special. A MCS needs more space than 454 * a single CB has. Actual space requirement depends on the length of the 455 * multicast list. So we always defer MCS until other CBLs are finished, 456 * then we setup a CONF CMD in the first CB. The CONF CMD is needed to 457 * turn ALLMULTI on the hardware on or off. The MCS is the 2nd CB and may 458 * use all the remaining space in the CBL and the Transmit Buffer Descriptor 459 * List. (Therefore CBL and TBDL must be continuous in physical and virtual 460 * memory. This is guaranteed through the definitions of the list offsets 461 * in i82596reg.h and because it is only a single DMA segment used for all 462 * lists.) When ALLMULTI is enabled via the CONF CMD, the MCS is run with 463 * a multicast list length of 0, thus disabling the multicast filter. 464 * A deferred MCS is signaled via ((sc->sc_flags & IEE_WANT_MCAST) != 0) 465 */ 466 void 467 iee_cb_setup(struct iee_softc *sc, uint32_t cmd) 468 { 469 struct iee_cb *cb = SC_CB(sc, sc->sc_next_cb); 470 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 471 struct ether_multistep step; 472 struct ether_multi *enm; 473 474 memset(cb, 0, sc->sc_cb_sz); 475 cb->cb_cmd = cmd; 476 switch (cmd & IEE_CB_CMD) { 477 case IEE_CB_CMD_NOP: /* NOP CMD */ 478 break; 479 case IEE_CB_CMD_IAS: /* Individual Address Setup */ 480 memcpy(__UNVOLATILE(cb->cb_ind_addr), CLLADDR(ifp->if_sadl), 481 ETHER_ADDR_LEN); 482 break; 483 case IEE_CB_CMD_CONF: /* Configure */ 484 memcpy(__UNVOLATILE(cb->cb_cf), sc->sc_cf, sc->sc_cf[0] 485 & IEE_CF_0_CNT_M); 486 break; 487 case IEE_CB_CMD_MCS: /* Multicast Setup */ 488 if (sc->sc_next_cb != 0) { 489 sc->sc_flags |= IEE_WANT_MCAST; 490 return; 491 } 492 sc->sc_flags &= ~IEE_WANT_MCAST; 493 if ((sc->sc_cf[8] & IEE_CF_8_PRM) != 0) { 494 /* Need no multicast filter in promisc mode. */ 495 iee_cb_setup(sc, IEE_CB_CMD_CONF | IEE_CB_S | IEE_CB_EL 496 | IEE_CB_I); 497 return; 498 } 499 /* Leave room for a CONF CMD to en/dis-able ALLMULTI mode */ 500 cb = SC_CB(sc, sc->sc_next_cb + 1); 501 cb->cb_cmd = cmd; 502 cb->cb_mcast.mc_size = 0; 503 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 504 while (enm != NULL) { 505 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 506 ETHER_ADDR_LEN) != 0 || cb->cb_mcast.mc_size 507 * ETHER_ADDR_LEN + 2 * sc->sc_cb_sz > 508 sc->sc_cb_sz * IEE_NCB + 509 sc->sc_tbd_sz * IEE_NTBD * IEE_NCB) { 510 cb->cb_mcast.mc_size = 0; 511 break; 512 } 513 memcpy(__UNVOLATILE(&cb->cb_mcast.mc_addrs[ 514 cb->cb_mcast.mc_size]), 515 enm->enm_addrlo, ETHER_ADDR_LEN); 516 ETHER_NEXT_MULTI(step, enm); 517 cb->cb_mcast.mc_size += ETHER_ADDR_LEN; 518 } 519 if (cb->cb_mcast.mc_size == 0) { 520 /* Can't do exact mcast filtering, do ALLMULTI mode. */ 521 ifp->if_flags |= IFF_ALLMULTI; 522 sc->sc_cf[11] &= ~IEE_CF_11_MCALL; 523 } else { 524 /* disable ALLMULTI and load mcast list */ 525 ifp->if_flags &= ~IFF_ALLMULTI; 526 sc->sc_cf[11] |= IEE_CF_11_MCALL; 527 /* Mcast setup may need more than sc->sc_cb_sz bytes. */ 528 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 529 sc->sc_cb_off, 530 sc->sc_cb_sz * IEE_NCB + 531 sc->sc_tbd_sz * IEE_NTBD * IEE_NCB, 532 BUS_DMASYNC_PREWRITE); 533 } 534 iee_cb_setup(sc, IEE_CB_CMD_CONF); 535 break; 536 case IEE_CB_CMD_TR: /* Transmit */ 537 cb->cb_transmit.tx_tbd_addr = 538 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_tbd_off 539 + sc->sc_tbd_sz * sc->sc_next_tbd)); 540 cb->cb_cmd |= IEE_CB_SF; /* Always use Flexible Mode. */ 541 break; 542 case IEE_CB_CMD_TDR: /* Time Domain Reflectometry */ 543 break; 544 case IEE_CB_CMD_DUMP: /* Dump */ 545 break; 546 case IEE_CB_CMD_DIAG: /* Diagnose */ 547 break; 548 default: 549 /* can't happen */ 550 break; 551 } 552 cb->cb_link_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_cb_off + 553 sc->sc_cb_sz * (sc->sc_next_cb + 1))); 554 IEE_CBSYNC(sc, sc->sc_next_cb, 555 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 556 sc->sc_next_cb++; 557 ifp->if_timer = 5; 558 } 559 560 561 562 void 563 iee_attach(struct iee_softc *sc, uint8_t *eth_addr, int *media, int nmedia, 564 int defmedia) 565 { 566 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 567 int n; 568 569 KASSERT(sc->sc_cl_align > 0 && powerof2(sc->sc_cl_align)); 570 571 /* 572 * Calculate DMA descriptor offsets and sizes in shmem 573 * which should be cache line aligned. 574 */ 575 sc->sc_scp_off = 0; 576 sc->sc_scp_sz = roundup2(sizeof(struct iee_scp), sc->sc_cl_align); 577 sc->sc_iscp_off = sc->sc_scp_sz; 578 sc->sc_iscp_sz = roundup2(sizeof(struct iee_iscp), sc->sc_cl_align); 579 sc->sc_scb_off = sc->sc_iscp_off + sc->sc_iscp_sz; 580 sc->sc_scb_sz = roundup2(sizeof(struct iee_scb), sc->sc_cl_align); 581 sc->sc_rfd_off = sc->sc_scb_off + sc->sc_scb_sz; 582 sc->sc_rfd_sz = roundup2(sizeof(struct iee_rfd), sc->sc_cl_align); 583 sc->sc_rbd_off = sc->sc_rfd_off + sc->sc_rfd_sz * IEE_NRFD; 584 sc->sc_rbd_sz = roundup2(sizeof(struct iee_rbd), sc->sc_cl_align); 585 sc->sc_cb_off = sc->sc_rbd_off + sc->sc_rbd_sz * IEE_NRFD; 586 sc->sc_cb_sz = roundup2(sizeof(struct iee_cb), sc->sc_cl_align); 587 sc->sc_tbd_off = sc->sc_cb_off + sc->sc_cb_sz * IEE_NCB; 588 sc->sc_tbd_sz = roundup2(sizeof(struct iee_tbd), sc->sc_cl_align); 589 sc->sc_shmem_sz = sc->sc_tbd_off + sc->sc_tbd_sz * IEE_NTBD * IEE_NCB; 590 591 /* allocate memory for shared DMA descriptors */ 592 if (bus_dmamem_alloc(sc->sc_dmat, sc->sc_shmem_sz, PAGE_SIZE, 0, 593 &sc->sc_dma_segs, 1, &sc->sc_dma_rsegs, BUS_DMA_NOWAIT) != 0) { 594 aprint_error(": can't allocate %d bytes of DMA memory\n", 595 sc->sc_shmem_sz); 596 return; 597 } 598 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_dma_segs, sc->sc_dma_rsegs, 599 sc->sc_shmem_sz, (void **)&sc->sc_shmem_addr, 600 BUS_DMA_COHERENT | BUS_DMA_NOWAIT) != 0) { 601 aprint_error(": can't map DMA memory\n"); 602 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, 603 sc->sc_dma_rsegs); 604 return; 605 } 606 if (bus_dmamap_create(sc->sc_dmat, sc->sc_shmem_sz, sc->sc_dma_rsegs, 607 sc->sc_shmem_sz, 0, BUS_DMA_NOWAIT, &sc->sc_shmem_map) != 0) { 608 aprint_error(": can't create DMA map\n"); 609 bus_dmamem_unmap(sc->sc_dmat, sc->sc_shmem_addr, 610 sc->sc_shmem_sz); 611 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, 612 sc->sc_dma_rsegs); 613 return; 614 } 615 if (bus_dmamap_load(sc->sc_dmat, sc->sc_shmem_map, sc->sc_shmem_addr, 616 sc->sc_shmem_sz, NULL, BUS_DMA_NOWAIT) != 0) { 617 aprint_error(": can't load DMA map\n"); 618 bus_dmamap_destroy(sc->sc_dmat, sc->sc_shmem_map); 619 bus_dmamem_unmap(sc->sc_dmat, sc->sc_shmem_addr, 620 sc->sc_shmem_sz); 621 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, 622 sc->sc_dma_rsegs); 623 return; 624 } 625 memset(sc->sc_shmem_addr, 0, sc->sc_shmem_sz); 626 627 /* Set pointer to Intermediate System Configuration Pointer. */ 628 /* Phys. addr. in big endian order. (Big endian as defined by Intel.) */ 629 SC_SCP(sc)->scp_iscp_addr = IEE_SWAP32(IEE_PHYS_SHMEM(sc->sc_iscp_off)); 630 SC_SCP(sc)->scp_sysbus = sc->sc_sysbus; 631 /* Set pointer to System Control Block. */ 632 /* Phys. addr. in big endian order. (Big endian as defined by Intel.) */ 633 SC_ISCP(sc)->iscp_scb_addr = IEE_SWAP32(IEE_PHYS_SHMEM(sc->sc_scb_off)); 634 /* Set pointer to Receive Frame Area. (physical address) */ 635 SC_SCB(sc)->scb_rfa_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off)); 636 /* Set pointer to Command Block. (physical address) */ 637 SC_SCB(sc)->scb_cmd_blk_addr = 638 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_cb_off)); 639 640 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 0, sc->sc_shmem_sz, 641 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 642 643 ifmedia_init(&sc->sc_ifmedia, 0, iee_mediachange, iee_mediastatus); 644 if (media != NULL) { 645 for (n = 0 ; n < nmedia ; n++) 646 ifmedia_add(&sc->sc_ifmedia, media[n], 0, NULL); 647 ifmedia_set(&sc->sc_ifmedia, defmedia); 648 } else { 649 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_NONE, 0, NULL); 650 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_NONE); 651 } 652 653 ifp->if_softc = sc; 654 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 655 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 656 ifp->if_start = iee_start; /* initiate output routine */ 657 ifp->if_ioctl = iee_ioctl; /* ioctl routine */ 658 ifp->if_init = iee_init; /* init routine */ 659 ifp->if_stop = iee_stop; /* stop routine */ 660 ifp->if_watchdog = iee_watchdog; /* timer routine */ 661 IFQ_SET_READY(&ifp->if_snd); 662 /* iee supports IEEE 802.1Q Virtual LANs, see vlan(4). */ 663 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 664 665 if_attach(ifp); 666 if_deferred_start_init(ifp, NULL); 667 ether_ifattach(ifp, eth_addr); 668 669 aprint_normal(": Intel 82596%s address %s\n", 670 i82596_typenames[sc->sc_type], ether_sprintf(eth_addr)); 671 672 for (n = 0 ; n < IEE_NCB ; n++) 673 sc->sc_tx_map[n] = NULL; 674 for (n = 0 ; n < IEE_NRFD ; n++) { 675 sc->sc_rx_mbuf[n] = NULL; 676 sc->sc_rx_map[n] = NULL; 677 } 678 sc->sc_tx_timeout = 0; 679 sc->sc_setup_timeout = 0; 680 (sc->sc_iee_reset)(sc); 681 } 682 683 684 685 void 686 iee_detach(struct iee_softc *sc, int flags) 687 { 688 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 689 690 if ((ifp->if_flags & IFF_RUNNING) != 0) 691 iee_stop(ifp, 1); 692 ether_ifdetach(ifp); 693 if_detach(ifp); 694 bus_dmamap_unload(sc->sc_dmat, sc->sc_shmem_map); 695 bus_dmamap_destroy(sc->sc_dmat, sc->sc_shmem_map); 696 bus_dmamem_unmap(sc->sc_dmat, sc->sc_shmem_addr, sc->sc_shmem_sz); 697 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, sc->sc_dma_rsegs); 698 } 699 700 701 702 /* media change and status callback */ 703 int 704 iee_mediachange(struct ifnet *ifp) 705 { 706 struct iee_softc *sc = ifp->if_softc; 707 708 if (sc->sc_mediachange != NULL) 709 return (sc->sc_mediachange)(ifp); 710 return 0; 711 } 712 713 714 715 void 716 iee_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmreq) 717 { 718 struct iee_softc *sc = ifp->if_softc; 719 720 if (sc->sc_mediastatus != NULL) 721 (sc->sc_mediastatus)(ifp, ifmreq); 722 } 723 724 725 726 /* initiate output routine */ 727 void 728 iee_start(struct ifnet *ifp) 729 { 730 struct iee_softc *sc = ifp->if_softc; 731 struct mbuf *m = NULL; 732 struct iee_tbd *tbd; 733 int t; 734 int n; 735 736 if (sc->sc_next_cb != 0) 737 /* There is already a CMD running. Defer packet enqueuing. */ 738 return; 739 for (t = 0 ; t < IEE_NCB ; t++) { 740 IFQ_DEQUEUE(&ifp->if_snd, sc->sc_tx_mbuf[t]); 741 if (sc->sc_tx_mbuf[t] == NULL) 742 break; 743 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_tx_map[t], 744 sc->sc_tx_mbuf[t], BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 745 /* 746 * The packet needs more TBD than we support. 747 * Copy the packet into a mbuf cluster to get it out. 748 */ 749 printf("%s: iee_start: failed to load DMA map\n", 750 device_xname(sc->sc_dev)); 751 MGETHDR(m, M_DONTWAIT, MT_DATA); 752 if (m == NULL) { 753 printf("%s: iee_start: can't allocate mbuf\n", 754 device_xname(sc->sc_dev)); 755 m_freem(sc->sc_tx_mbuf[t]); 756 sc->sc_tx_mbuf[t] = NULL; 757 t--; 758 continue; 759 } 760 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 761 MCLGET(m, M_DONTWAIT); 762 if ((m->m_flags & M_EXT) == 0) { 763 printf("%s: iee_start: can't allocate mbuf " 764 "cluster\n", device_xname(sc->sc_dev)); 765 m_freem(sc->sc_tx_mbuf[t]); 766 sc->sc_tx_mbuf[t] = NULL; 767 m_freem(m); 768 t--; 769 continue; 770 } 771 m_copydata(sc->sc_tx_mbuf[t], 0, 772 sc->sc_tx_mbuf[t]->m_pkthdr.len, mtod(m, void *)); 773 m->m_pkthdr.len = sc->sc_tx_mbuf[t]->m_pkthdr.len; 774 m->m_len = sc->sc_tx_mbuf[t]->m_pkthdr.len; 775 m_freem(sc->sc_tx_mbuf[t]); 776 sc->sc_tx_mbuf[t] = m; 777 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_tx_map[t], 778 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 779 printf("%s: iee_start: can't load TX DMA map\n", 780 device_xname(sc->sc_dev)); 781 m_freem(sc->sc_tx_mbuf[t]); 782 sc->sc_tx_mbuf[t] = NULL; 783 t--; 784 continue; 785 } 786 } 787 for (n = 0 ; n < sc->sc_tx_map[t]->dm_nsegs ; n++) { 788 tbd = SC_TBD(sc, sc->sc_next_tbd + n); 789 tbd->tbd_tb_addr = 790 IEE_SWAPA32(sc->sc_tx_map[t]->dm_segs[n].ds_addr); 791 tbd->tbd_size = 792 sc->sc_tx_map[t]->dm_segs[n].ds_len; 793 tbd->tbd_link_addr = 794 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_tbd_off + 795 sc->sc_tbd_sz * (sc->sc_next_tbd + n + 1))); 796 } 797 SC_TBD(sc, sc->sc_next_tbd + n - 1)->tbd_size |= IEE_CB_EL; 798 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 799 sc->sc_tbd_off + sc->sc_next_tbd * sc->sc_tbd_sz, 800 sc->sc_tbd_sz * sc->sc_tx_map[t]->dm_nsegs, 801 BUS_DMASYNC_PREWRITE); 802 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_map[t], 0, 803 sc->sc_tx_map[t]->dm_mapsize, BUS_DMASYNC_PREWRITE); 804 IFQ_POLL(&ifp->if_snd, m); 805 if (m == NULL) 806 iee_cb_setup(sc, IEE_CB_CMD_TR | IEE_CB_S | IEE_CB_EL 807 | IEE_CB_I); 808 else 809 iee_cb_setup(sc, IEE_CB_CMD_TR); 810 sc->sc_next_tbd += n; 811 /* Pass packet to bpf if someone listens. */ 812 bpf_mtap(ifp, sc->sc_tx_mbuf[t]); 813 } 814 if (t == 0) 815 /* No packets got set up for TX. */ 816 return; 817 if (t == IEE_NCB) 818 ifp->if_flags |= IFF_OACTIVE; 819 (sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE); 820 } 821 822 823 824 /* ioctl routine */ 825 int 826 iee_ioctl(struct ifnet *ifp, u_long cmd, void *data) 827 { 828 struct iee_softc *sc = ifp->if_softc; 829 int s; 830 int err; 831 832 s = splnet(); 833 switch (cmd) { 834 case SIOCSIFMEDIA: 835 case SIOCGIFMEDIA: 836 err = ifmedia_ioctl(ifp, (struct ifreq *) data, 837 &sc->sc_ifmedia, cmd); 838 break; 839 840 default: 841 err = ether_ioctl(ifp, cmd, data); 842 if (err == ENETRESET) { 843 /* 844 * Multicast list as changed; set the hardware filter 845 * accordingly. 846 */ 847 if (ifp->if_flags & IFF_RUNNING) { 848 iee_cb_setup(sc, IEE_CB_CMD_MCS | IEE_CB_S | 849 IEE_CB_EL | IEE_CB_I); 850 if ((sc->sc_flags & IEE_WANT_MCAST) == 0) 851 (*sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE); 852 } 853 err = 0; 854 } 855 break; 856 } 857 splx(s); 858 return err; 859 } 860 861 862 863 /* init routine */ 864 int 865 iee_init(struct ifnet *ifp) 866 { 867 struct iee_softc *sc = ifp->if_softc; 868 int r; 869 int t; 870 int n; 871 int err; 872 873 sc->sc_next_cb = 0; 874 sc->sc_next_tbd = 0; 875 sc->sc_flags &= ~IEE_WANT_MCAST; 876 sc->sc_rx_done = 0; 877 SC_SCB(sc)->scb_crc_err = 0; 878 SC_SCB(sc)->scb_align_err = 0; 879 SC_SCB(sc)->scb_resource_err = 0; 880 SC_SCB(sc)->scb_overrun_err = 0; 881 SC_SCB(sc)->scb_rcvcdt_err = 0; 882 SC_SCB(sc)->scb_short_fr_err = 0; 883 sc->sc_crc_err = 0; 884 sc->sc_align_err = 0; 885 sc->sc_resource_err = 0; 886 sc->sc_overrun_err = 0; 887 sc->sc_rcvcdt_err = 0; 888 sc->sc_short_fr_err = 0; 889 sc->sc_tx_col = 0; 890 sc->sc_rx_err = 0; 891 sc->sc_cmd_err = 0; 892 /* Create Transmit DMA maps. */ 893 for (t = 0 ; t < IEE_NCB ; t++) { 894 if (sc->sc_tx_map[t] == NULL && bus_dmamap_create(sc->sc_dmat, 895 MCLBYTES, IEE_NTBD, MCLBYTES, 0, BUS_DMA_NOWAIT, 896 &sc->sc_tx_map[t]) != 0) { 897 printf("%s: iee_init: can't create TX DMA map\n", 898 device_xname(sc->sc_dev)); 899 for (n = 0 ; n < t ; n++) 900 bus_dmamap_destroy(sc->sc_dmat, 901 sc->sc_tx_map[n]); 902 return ENOBUFS; 903 } 904 } 905 /* Initialize Receive Frame and Receive Buffer Descriptors */ 906 err = 0; 907 memset(SC_RFD(sc, 0), 0, sc->sc_rfd_sz * IEE_NRFD); 908 memset(SC_RBD(sc, 0), 0, sc->sc_rbd_sz * IEE_NRFD); 909 for (r = 0 ; r < IEE_NRFD ; r++) { 910 SC_RFD(sc, r)->rfd_cmd = IEE_RFD_SF; 911 SC_RFD(sc, r)->rfd_link_addr = 912 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off 913 + sc->sc_rfd_sz * ((r + 1) % IEE_NRFD))); 914 915 SC_RBD(sc, r)->rbd_next_rbd = 916 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off 917 + sc->sc_rbd_sz * ((r + 1) % IEE_NRFD))); 918 if (sc->sc_rx_mbuf[r] == NULL) { 919 MGETHDR(sc->sc_rx_mbuf[r], M_DONTWAIT, MT_DATA); 920 if (sc->sc_rx_mbuf[r] == NULL) { 921 printf("%s: iee_init: can't allocate mbuf\n", 922 device_xname(sc->sc_dev)); 923 err = 1; 924 break; 925 } 926 MCLAIM(sc->sc_rx_mbuf[r],&sc->sc_ethercom.ec_rx_mowner); 927 MCLGET(sc->sc_rx_mbuf[r], M_DONTWAIT); 928 if ((sc->sc_rx_mbuf[r]->m_flags & M_EXT) == 0) { 929 printf("%s: iee_init: can't allocate mbuf" 930 " cluster\n", device_xname(sc->sc_dev)); 931 m_freem(sc->sc_rx_mbuf[r]); 932 sc->sc_rx_mbuf[r] = NULL; 933 err = 1; 934 break; 935 } 936 sc->sc_rx_mbuf[r]->m_len = 937 sc->sc_rx_mbuf[r]->m_pkthdr.len = MCLBYTES - 2; 938 sc->sc_rx_mbuf[r]->m_data += 2; 939 } 940 if (sc->sc_rx_map[r] == NULL && bus_dmamap_create(sc->sc_dmat, 941 MCLBYTES, 1, MCLBYTES , 0, BUS_DMA_NOWAIT, 942 &sc->sc_rx_map[r]) != 0) { 943 printf("%s: iee_init: can't create RX " 944 "DMA map\n", device_xname(sc->sc_dev)); 945 m_freem(sc->sc_rx_mbuf[r]); 946 sc->sc_rx_mbuf[r] = NULL; 947 err = 1; 948 break; 949 } 950 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_rx_map[r], 951 sc->sc_rx_mbuf[r], BUS_DMA_READ | BUS_DMA_NOWAIT) != 0) { 952 printf("%s: iee_init: can't load RX DMA map\n", 953 device_xname(sc->sc_dev)); 954 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[r]); 955 m_freem(sc->sc_rx_mbuf[r]); 956 sc->sc_rx_mbuf[r] = NULL; 957 err = 1; 958 break; 959 } 960 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_map[r], 0, 961 sc->sc_rx_map[r]->dm_mapsize, BUS_DMASYNC_PREREAD); 962 SC_RBD(sc, r)->rbd_size = sc->sc_rx_map[r]->dm_segs[0].ds_len; 963 SC_RBD(sc, r)->rbd_rb_addr = 964 IEE_SWAPA32(sc->sc_rx_map[r]->dm_segs[0].ds_addr); 965 } 966 SC_RFD(sc, 0)->rfd_rbd_addr = 967 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off)); 968 if (err != 0) { 969 for (n = 0 ; n < r; n++) { 970 m_freem(sc->sc_rx_mbuf[n]); 971 sc->sc_rx_mbuf[n] = NULL; 972 bus_dmamap_unload(sc->sc_dmat, sc->sc_rx_map[n]); 973 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[n]); 974 sc->sc_rx_map[n] = NULL; 975 } 976 for (n = 0 ; n < t ; n++) { 977 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_map[n]); 978 sc->sc_tx_map[n] = NULL; 979 } 980 return ENOBUFS; 981 } 982 983 (sc->sc_iee_reset)(sc); 984 iee_cb_setup(sc, IEE_CB_CMD_IAS); 985 sc->sc_cf[0] = IEE_CF_0_DEF | IEE_CF_0_PREF; 986 sc->sc_cf[1] = IEE_CF_1_DEF; 987 sc->sc_cf[2] = IEE_CF_2_DEF; 988 sc->sc_cf[3] = IEE_CF_3_ADDRLEN_DEF | IEE_CF_3_NSAI 989 | IEE_CF_3_PREAMLEN_DEF; 990 sc->sc_cf[4] = IEE_CF_4_DEF; 991 sc->sc_cf[5] = IEE_CF_5_DEF; 992 sc->sc_cf[6] = IEE_CF_6_DEF; 993 sc->sc_cf[7] = IEE_CF_7_DEF; 994 sc->sc_cf[8] = IEE_CF_8_DEF; 995 sc->sc_cf[9] = IEE_CF_9_DEF; 996 sc->sc_cf[10] = IEE_CF_10_DEF; 997 sc->sc_cf[11] = IEE_CF_11_DEF & ~IEE_CF_11_LNGFLD; 998 sc->sc_cf[12] = IEE_CF_12_DEF; 999 sc->sc_cf[13] = IEE_CF_13_DEF; 1000 iee_cb_setup(sc, IEE_CB_CMD_CONF | IEE_CB_S | IEE_CB_EL); 1001 SC_SCB(sc)->scb_rfa_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off)); 1002 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 0, sc->sc_shmem_sz, 1003 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1004 (sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE | IEE_SCB_RUC_ST); 1005 /* Issue a Channel Attention to ACK interrupts we may have caused. */ 1006 (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 1007 1008 /* Mark the interface as running and ready to RX/TX packets. */ 1009 ifp->if_flags |= IFF_RUNNING; 1010 ifp->if_flags &= ~IFF_OACTIVE; 1011 return 0; 1012 } 1013 1014 1015 1016 /* stop routine */ 1017 void 1018 iee_stop(struct ifnet *ifp, int disable) 1019 { 1020 struct iee_softc *sc = ifp->if_softc; 1021 int n; 1022 1023 ifp->if_flags &= ~IFF_RUNNING; 1024 ifp->if_flags |= IFF_OACTIVE; 1025 ifp->if_timer = 0; 1026 /* Reset the chip to get it quiet. */ 1027 (sc->sc_iee_reset)(ifp->if_softc); 1028 /* Issue a Channel Attention to ACK interrupts we may have caused. */ 1029 (sc->sc_iee_cmd)(ifp->if_softc, IEE_SCB_ACK); 1030 /* Release any dynamically allocated resources. */ 1031 for (n = 0 ; n < IEE_NCB ; n++) { 1032 if (sc->sc_tx_map[n] != NULL) 1033 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_map[n]); 1034 sc->sc_tx_map[n] = NULL; 1035 } 1036 for (n = 0 ; n < IEE_NRFD ; n++) { 1037 if (sc->sc_rx_mbuf[n] != NULL) 1038 m_freem(sc->sc_rx_mbuf[n]); 1039 sc->sc_rx_mbuf[n] = NULL; 1040 if (sc->sc_rx_map[n] != NULL) { 1041 bus_dmamap_unload(sc->sc_dmat, sc->sc_rx_map[n]); 1042 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[n]); 1043 } 1044 sc->sc_rx_map[n] = NULL; 1045 } 1046 } 1047 1048 1049 1050 /* timer routine */ 1051 void 1052 iee_watchdog(struct ifnet *ifp) 1053 { 1054 struct iee_softc *sc = ifp->if_softc; 1055 1056 (sc->sc_iee_reset)(sc); 1057 if (sc->sc_next_tbd != 0) 1058 printf("%s: iee_watchdog: transmit timeout %d\n", 1059 device_xname(sc->sc_dev), ++sc->sc_tx_timeout); 1060 else 1061 printf("%s: iee_watchdog: setup timeout %d\n", 1062 device_xname(sc->sc_dev), ++sc->sc_setup_timeout); 1063 iee_init(ifp); 1064 } 1065
Indexes created Mon Sep 29 18:09:42 GMT 2025