i82596.c revision 1.42
1 /* $NetBSD: i82596.c,v 1.42 2019/05/29 10:07:29 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Jochen Kunz. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Jochen Kunz may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY JOCHEN KUNZ 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL JOCHEN KUNZ 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the Intel i82596CA and i82596DX/SX 10MBit/s Ethernet chips. 34 * 35 * It operates the i82596 in 32-Bit Linear Mode, opposed to the old i82586 36 * ie(4) driver (src/sys/dev/ic/i82586.c), that degrades the i82596 to 37 * i82586 compatibility mode. 38 * 39 * Documentation about these chips can be found at 40 * 41 * http://developer.intel.com/design/network/datashts/290218.htm 42 * http://developer.intel.com/design/network/datashts/290219.htm 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: i82596.c,v 1.42 2019/05/29 10:07:29 msaitoh Exp $"); 47 48 /* autoconfig and device stuff */ 49 #include <sys/param.h> 50 #include <sys/device.h> 51 #include <sys/conf.h> 52 #include "locators.h" 53 #include "ioconf.h" 54 55 /* bus_space / bus_dma etc. */ 56 #include <sys/bus.h> 57 #include <sys/intr.h> 58 59 /* general system data and functions */ 60 #include <sys/systm.h> 61 #include <sys/ioctl.h> 62 63 /* tsleep / sleep / wakeup */ 64 #include <sys/proc.h> 65 /* hz for above */ 66 #include <sys/kernel.h> 67 68 /* network stuff */ 69 #include <net/if.h> 70 #include <net/if_dl.h> 71 #include <net/if_media.h> 72 #include <net/if_ether.h> 73 #include <net/bpf.h> 74 #include <sys/socket.h> 75 #include <sys/mbuf.h> 76 77 #include <dev/ic/i82596reg.h> 78 #include <dev/ic/i82596var.h> 79 80 /* Supported chip variants */ 81 const char *i82596_typenames[] = { "unknown", "DX/SX", "CA" }; 82 83 /* media change and status callback */ 84 static int iee_mediachange(struct ifnet *); 85 static void iee_mediastatus(struct ifnet *, struct ifmediareq *); 86 87 /* interface routines to upper protocols */ 88 static void iee_start(struct ifnet *); /* initiate output */ 89 static int iee_ioctl(struct ifnet *, u_long, void *); /* ioctl routine */ 90 static int iee_init(struct ifnet *); /* init routine */ 91 static void iee_stop(struct ifnet *, int); /* stop routine */ 92 static void iee_watchdog(struct ifnet *); /* timer routine */ 93 94 /* internal helper functions */ 95 static void iee_cb_setup(struct iee_softc *, uint32_t); 96 97 /* 98 * Things a MD frontend has to provide: 99 * 100 * The functions via function pointers in the softc: 101 * int (*sc_iee_cmd)(struct iee_softc *sc, uint32_t cmd); 102 * int (*sc_iee_reset)(struct iee_softc *sc); 103 * void (*sc_mediastatus)(struct ifnet *, struct ifmediareq *); 104 * int (*sc_mediachange)(struct ifnet *); 105 * 106 * sc_iee_cmd(): send a command to the i82596 by writing the cmd parameter 107 * to the SCP cmd word and issuing a Channel Attention. 108 * sc_iee_reset(): initiate a reset, supply the address of the SCP to the 109 * chip, wait for the chip to initialize and ACK interrupts that 110 * this may have caused by calling (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 111 * This functions must carefully bus_dmamap_sync() all data they have touched! 112 * 113 * sc_mediastatus() and sc_mediachange() are just MD hooks to the according 114 * MI functions. The MD frontend may set this pointers to NULL when they 115 * are not needed. 116 * 117 * sc->sc_type has to be set to I82596_UNKNOWN or I82596_DX or I82596_CA. 118 * This is for printing out the correct chip type at attach time only. The 119 * MI backend doesn't distinguish different chip types when programming 120 * the chip. 121 * 122 * IEE_NEED_SWAP in sc->sc_flags has to be cleared on little endian hardware 123 * and set on big endian hardware, when endianess conversion is not done 124 * by the bus attachment but done by i82596 chip itself. 125 * Usually you need to set IEE_NEED_SWAP on big endian machines 126 * where the hardware (the LE/~BE pin) is configured as BE mode. 127 * 128 * If the chip is configured as BE mode, all 8 bit (byte) and 16 bit (word) 129 * entities can be written in big endian. But Rev A chip doesn't support 130 * 32 bit (dword) entities with big endian byte ordering, so we have to 131 * treat all 32 bit (dword) entities as two 16 bit big endian entities. 132 * Rev B and C chips support big endian byte ordering for 32 bit entities, 133 * and this new feature is enabled by IEE_SYSBUS_BE in the sysbus byte. 134 * 135 * With the IEE_SYSBUS_BE feature, all 32 bit address ponters are 136 * treated as true 32 bit entities but the SCB absolute address and 137 * statistical counters are still treated as two 16 bit big endian entities, 138 * so we have to always swap high and low words for these entities. 139 * IEE_SWAP32() should be used for the SCB address and statistical counters, 140 * and IEE_SWAPA32() should be used for other 32 bit pointers in the shmem. 141 * 142 * IEE_REV_A flag must be set in sc->sc_flags if the IEE_SYSBUS_BE feature 143 * is disabled even on big endian machines for the old Rev A chip in backend. 144 * 145 * sc->sc_cl_align must be set to 1 or to the cache line size. When set to 146 * 1 no special alignment of DMA descriptors is done. If sc->sc_cl_align != 1 147 * it forces alignment of the data structures in the shared memory to a multiple 148 * of sc->sc_cl_align. This is needed on some hppa machines that have non DMA 149 * I/O coherent caches and are unable to map the shared memory uncachable. 150 * (At least pre PA7100LC CPUs are unable to map memory uncachable.) 151 * 152 * The MD frontend also has to set sc->sc_cl_align and sc->sc_sysbus 153 * to allocate and setup shared DMA memory in MI iee_attach(). 154 * All communication with the chip is done via this shared memory. 155 * This memory is mapped with BUS_DMA_COHERENT so it will be uncached 156 * if possible for archs with non DMA I/O coherent caches. 157 * The base of the memory needs to be aligned to an even address 158 * if sc->sc_cl_align == 1 and aligned to a cache line if sc->sc_cl_align != 1. 159 * Each descriptor offsets are calculated in iee_attach() to handle this. 160 * 161 * An interrupt with iee_intr() as handler must be established. 162 * 163 * Call void iee_attach(struct iee_softc *sc, uint8_t *ether_address, 164 * int *media, int nmedia, int defmedia); when everything is set up. First 165 * parameter is a pointer to the MI softc, ether_address is an array that 166 * contains the ethernet address. media is an array of the media types 167 * provided by the hardware. The members of this array are supplied to 168 * ifmedia_add() in sequence. nmedia is the count of elements in media. 169 * defmedia is the default media that is set via ifmedia_set(). 170 * nmedia and defmedia are ignored when media == NULL. 171 * 172 * The MD backend may call iee_detach() to detach the device. 173 * 174 * See sys/arch/hppa/gsc/if_iee_gsc.c for an example. 175 */ 176 177 178 /* 179 * How frame reception is done: 180 * Each Receive Frame Descriptor has one associated Receive Buffer Descriptor. 181 * Each RBD points to the data area of an mbuf cluster. The RFDs are linked 182 * together in a circular list. sc->sc_rx_done is the count of RFDs in the 183 * list already processed / the number of the RFD that has to be checked for 184 * a new frame first at the next RX interrupt. Upon successful reception of 185 * a frame the mbuf cluster is handled to upper protocol layers, a new mbuf 186 * cluster is allocated and the RFD / RBD are reinitialized accordingly. 187 * 188 * When a RFD list overrun occurred the whole RFD and RBD lists are 189 * reinitialized and frame reception is started again. 190 */ 191 int 192 iee_intr(void *intarg) 193 { 194 struct iee_softc *sc = intarg; 195 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 196 struct iee_rfd *rfd; 197 struct iee_rbd *rbd; 198 bus_dmamap_t rx_map; 199 struct mbuf *rx_mbuf; 200 struct mbuf *new_mbuf; 201 int scb_status; 202 int scb_cmd; 203 int n, col; 204 uint16_t status, count, cmd; 205 206 if ((ifp->if_flags & IFF_RUNNING) == 0) { 207 (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 208 return 1; 209 } 210 IEE_SCBSYNC(sc, BUS_DMASYNC_POSTREAD); 211 scb_status = SC_SCB(sc)->scb_status; 212 scb_cmd = SC_SCB(sc)->scb_cmd; 213 for (;;) { 214 rfd = SC_RFD(sc, sc->sc_rx_done); 215 IEE_RFDSYNC(sc, sc->sc_rx_done, 216 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 217 status = rfd->rfd_status; 218 if ((status & IEE_RFD_C) == 0) { 219 IEE_RFDSYNC(sc, sc->sc_rx_done, BUS_DMASYNC_PREREAD); 220 break; 221 } 222 rfd->rfd_status = 0; 223 IEE_RFDSYNC(sc, sc->sc_rx_done, 224 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 225 226 /* At least one packet was received. */ 227 rx_map = sc->sc_rx_map[sc->sc_rx_done]; 228 rx_mbuf = sc->sc_rx_mbuf[sc->sc_rx_done]; 229 IEE_RBDSYNC(sc, (sc->sc_rx_done + IEE_NRFD - 1) % IEE_NRFD, 230 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 231 SC_RBD(sc, (sc->sc_rx_done + IEE_NRFD - 1) % IEE_NRFD)->rbd_size 232 &= ~IEE_RBD_EL; 233 IEE_RBDSYNC(sc, (sc->sc_rx_done + IEE_NRFD - 1) % IEE_NRFD, 234 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 235 rbd = SC_RBD(sc, sc->sc_rx_done); 236 IEE_RBDSYNC(sc, sc->sc_rx_done, 237 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 238 count = rbd->rbd_count; 239 if ((status & IEE_RFD_OK) == 0 240 || (count & IEE_RBD_EOF) == 0 241 || (count & IEE_RBD_F) == 0){ 242 /* Receive error, skip frame and reuse buffer. */ 243 rbd->rbd_count = 0; 244 rbd->rbd_size = IEE_RBD_EL | rx_map->dm_segs[0].ds_len; 245 IEE_RBDSYNC(sc, sc->sc_rx_done, 246 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 247 printf("%s: iee_intr: receive error %d, rfd_status=" 248 "0x%.4x, rfd_count=0x%.4x\n", 249 device_xname(sc->sc_dev), 250 ++sc->sc_rx_err, status, count); 251 sc->sc_rx_done = (sc->sc_rx_done + 1) % IEE_NRFD; 252 continue; 253 } 254 bus_dmamap_sync(sc->sc_dmat, rx_map, 0, rx_map->dm_mapsize, 255 BUS_DMASYNC_POSTREAD); 256 rx_mbuf->m_pkthdr.len = rx_mbuf->m_len = 257 count & IEE_RBD_COUNT; 258 m_set_rcvif(rx_mbuf, ifp); 259 MGETHDR(new_mbuf, M_DONTWAIT, MT_DATA); 260 if (new_mbuf == NULL) { 261 printf("%s: iee_intr: can't allocate mbuf\n", 262 device_xname(sc->sc_dev)); 263 break; 264 } 265 MCLAIM(new_mbuf, &sc->sc_ethercom.ec_rx_mowner); 266 MCLGET(new_mbuf, M_DONTWAIT); 267 if ((new_mbuf->m_flags & M_EXT) == 0) { 268 printf("%s: iee_intr: can't alloc mbuf cluster\n", 269 device_xname(sc->sc_dev)); 270 m_freem(new_mbuf); 271 break; 272 } 273 bus_dmamap_unload(sc->sc_dmat, rx_map); 274 new_mbuf->m_len = new_mbuf->m_pkthdr.len = MCLBYTES - 2; 275 new_mbuf->m_data += 2; 276 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_map, 277 new_mbuf, BUS_DMA_READ | BUS_DMA_NOWAIT) != 0) 278 panic("%s: iee_intr: can't load RX DMA map\n", 279 device_xname(sc->sc_dev)); 280 bus_dmamap_sync(sc->sc_dmat, rx_map, 0, 281 rx_map->dm_mapsize, BUS_DMASYNC_PREREAD); 282 if_percpuq_enqueue(ifp->if_percpuq, rx_mbuf); 283 sc->sc_rx_mbuf[sc->sc_rx_done] = new_mbuf; 284 rbd->rbd_count = 0; 285 rbd->rbd_size = IEE_RBD_EL | rx_map->dm_segs[0].ds_len; 286 rbd->rbd_rb_addr = IEE_SWAPA32(rx_map->dm_segs[0].ds_addr); 287 IEE_RBDSYNC(sc, sc->sc_rx_done, 288 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 289 sc->sc_rx_done = (sc->sc_rx_done + 1) % IEE_NRFD; 290 } 291 if ((scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR1 292 || (scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR2 293 || (scb_status & IEE_SCB_RUS) == IEE_SCB_RUS_NR3) { 294 /* Receive Overrun, reinit receive ring buffer. */ 295 for (n = 0 ; n < IEE_NRFD ; n++) { 296 rfd = SC_RFD(sc, n); 297 rbd = SC_RBD(sc, n); 298 rfd->rfd_cmd = IEE_RFD_SF; 299 rfd->rfd_link_addr = 300 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off 301 + sc->sc_rfd_sz * ((n + 1) % IEE_NRFD))); 302 rbd->rbd_next_rbd = 303 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off 304 + sc->sc_rbd_sz * ((n + 1) % IEE_NRFD))); 305 rbd->rbd_size = IEE_RBD_EL | 306 sc->sc_rx_map[n]->dm_segs[0].ds_len; 307 rbd->rbd_rb_addr = 308 IEE_SWAPA32(sc->sc_rx_map[n]->dm_segs[0].ds_addr); 309 } 310 SC_RFD(sc, 0)->rfd_rbd_addr = 311 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off)); 312 sc->sc_rx_done = 0; 313 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, sc->sc_rfd_off, 314 sc->sc_rfd_sz * IEE_NRFD + sc->sc_rbd_sz * IEE_NRFD, 315 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 316 (sc->sc_iee_cmd)(sc, IEE_SCB_RUC_ST); 317 printf("%s: iee_intr: receive ring buffer overrun\n", 318 device_xname(sc->sc_dev)); 319 } 320 321 if (sc->sc_next_cb != 0) { 322 IEE_CBSYNC(sc, sc->sc_next_cb - 1, 323 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 324 status = SC_CB(sc, sc->sc_next_cb - 1)->cb_status; 325 IEE_CBSYNC(sc, sc->sc_next_cb - 1, 326 BUS_DMASYNC_PREREAD); 327 if ((status & IEE_CB_C) != 0) { 328 /* CMD list finished */ 329 ifp->if_timer = 0; 330 if (sc->sc_next_tbd != 0) { 331 /* A TX CMD list finished, cleanup */ 332 for (n = 0 ; n < sc->sc_next_cb ; n++) { 333 m_freem(sc->sc_tx_mbuf[n]); 334 sc->sc_tx_mbuf[n] = NULL; 335 bus_dmamap_unload(sc->sc_dmat, 336 sc->sc_tx_map[n]); 337 IEE_CBSYNC(sc, n, 338 BUS_DMASYNC_POSTREAD | 339 BUS_DMASYNC_POSTWRITE); 340 status = SC_CB(sc, n)->cb_status; 341 IEE_CBSYNC(sc, n, 342 BUS_DMASYNC_PREREAD); 343 if ((status & IEE_CB_COL) != 0 && 344 (status & IEE_CB_MAXCOL) == 0) 345 col = 16; 346 else 347 col = status 348 & IEE_CB_MAXCOL; 349 sc->sc_tx_col += col; 350 if ((status & IEE_CB_OK) != 0) { 351 ifp->if_opackets++; 352 ifp->if_collisions += col; 353 } 354 } 355 sc->sc_next_tbd = 0; 356 ifp->if_flags &= ~IFF_OACTIVE; 357 } 358 for (n = 0 ; n < sc->sc_next_cb; n++) { 359 /* 360 * Check if a CMD failed, but ignore TX errors. 361 */ 362 IEE_CBSYNC(sc, n, BUS_DMASYNC_POSTREAD | 363 BUS_DMASYNC_POSTWRITE); 364 cmd = SC_CB(sc, n)->cb_cmd; 365 status = SC_CB(sc, n)->cb_status; 366 IEE_CBSYNC(sc, n, BUS_DMASYNC_PREREAD); 367 if ((cmd & IEE_CB_CMD) != IEE_CB_CMD_TR && 368 (status & IEE_CB_OK) == 0) 369 printf("%s: iee_intr: scb_status=0x%x " 370 "scb_cmd=0x%x failed command %d: " 371 "cb_status[%d]=0x%.4x " 372 "cb_cmd[%d]=0x%.4x\n", 373 device_xname(sc->sc_dev), 374 scb_status, scb_cmd, 375 ++sc->sc_cmd_err, 376 n, status, n, cmd); 377 } 378 sc->sc_next_cb = 0; 379 if ((sc->sc_flags & IEE_WANT_MCAST) != 0) { 380 iee_cb_setup(sc, IEE_CB_CMD_MCS | 381 IEE_CB_S | IEE_CB_EL | IEE_CB_I); 382 (sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE); 383 } else 384 /* Try to get deferred packets going. */ 385 if_schedule_deferred_start(ifp); 386 } 387 } 388 if (IEE_SWAP32(SC_SCB(sc)->scb_crc_err) != sc->sc_crc_err) { 389 sc->sc_crc_err = IEE_SWAP32(SC_SCB(sc)->scb_crc_err); 390 printf("%s: iee_intr: crc_err=%d\n", device_xname(sc->sc_dev), 391 sc->sc_crc_err); 392 } 393 if (IEE_SWAP32(SC_SCB(sc)->scb_align_err) != sc->sc_align_err) { 394 sc->sc_align_err = IEE_SWAP32(SC_SCB(sc)->scb_align_err); 395 printf("%s: iee_intr: align_err=%d\n", 396 device_xname(sc->sc_dev), sc->sc_align_err); 397 } 398 if (IEE_SWAP32(SC_SCB(sc)->scb_resource_err) != sc->sc_resource_err) { 399 sc->sc_resource_err = IEE_SWAP32(SC_SCB(sc)->scb_resource_err); 400 printf("%s: iee_intr: resource_err=%d\n", 401 device_xname(sc->sc_dev), sc->sc_resource_err); 402 } 403 if (IEE_SWAP32(SC_SCB(sc)->scb_overrun_err) != sc->sc_overrun_err) { 404 sc->sc_overrun_err = IEE_SWAP32(SC_SCB(sc)->scb_overrun_err); 405 printf("%s: iee_intr: overrun_err=%d\n", 406 device_xname(sc->sc_dev), sc->sc_overrun_err); 407 } 408 if (IEE_SWAP32(SC_SCB(sc)->scb_rcvcdt_err) != sc->sc_rcvcdt_err) { 409 sc->sc_rcvcdt_err = IEE_SWAP32(SC_SCB(sc)->scb_rcvcdt_err); 410 printf("%s: iee_intr: rcvcdt_err=%d\n", 411 device_xname(sc->sc_dev), sc->sc_rcvcdt_err); 412 } 413 if (IEE_SWAP32(SC_SCB(sc)->scb_short_fr_err) != sc->sc_short_fr_err) { 414 sc->sc_short_fr_err = IEE_SWAP32(SC_SCB(sc)->scb_short_fr_err); 415 printf("%s: iee_intr: short_fr_err=%d\n", 416 device_xname(sc->sc_dev), sc->sc_short_fr_err); 417 } 418 IEE_SCBSYNC(sc, BUS_DMASYNC_PREREAD); 419 (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 420 return 1; 421 } 422 423 424 425 /* 426 * How Command Block List Processing is done. 427 * 428 * A running CBL is never manipulated. If there is a CBL already running, 429 * further CMDs are deferred until the current list is done. A new list is 430 * setup when the old one has finished. 431 * This eases programming. To manipulate a running CBL it is necessary to 432 * suspend the Command Unit to avoid race conditions. After a suspend 433 * is sent we have to wait for an interrupt that ACKs the suspend. Then 434 * we can manipulate the CBL and resume operation. I am not sure that this 435 * is more effective than the current, much simpler approach. => KISS 436 * See i82596CA data sheet page 26. 437 * 438 * A CBL is running or on the way to be set up when (sc->sc_next_cb != 0). 439 * 440 * A CBL may consist of TX CMDs, and _only_ TX CMDs. 441 * A TX CBL is running or on the way to be set up when 442 * ((sc->sc_next_cb != 0) && (sc->sc_next_tbd != 0)). 443 * 444 * A CBL may consist of other non-TX CMDs like IAS or CONF, and _only_ 445 * non-TX CMDs. 446 * 447 * This comes mostly through the way how an Ethernet driver works and 448 * because running CBLs are not manipulated when they are on the way. If 449 * if_start() is called there will be TX CMDs enqueued so we have a running 450 * CBL and other CMDs from e.g. if_ioctl() will be deferred and vice versa. 451 * 452 * The Multicast Setup Command is special. A MCS needs more space than 453 * a single CB has. Actual space requirement depends on the length of the 454 * multicast list. So we always defer MCS until other CBLs are finished, 455 * then we setup a CONF CMD in the first CB. The CONF CMD is needed to 456 * turn ALLMULTI on the hardware on or off. The MCS is the 2nd CB and may 457 * use all the remaining space in the CBL and the Transmit Buffer Descriptor 458 * List. (Therefore CBL and TBDL must be continuous in physical and virtual 459 * memory. This is guaranteed through the definitions of the list offsets 460 * in i82596reg.h and because it is only a single DMA segment used for all 461 * lists.) When ALLMULTI is enabled via the CONF CMD, the MCS is run with 462 * a multicast list length of 0, thus disabling the multicast filter. 463 * A deferred MCS is signaled via ((sc->sc_flags & IEE_WANT_MCAST) != 0) 464 */ 465 void 466 iee_cb_setup(struct iee_softc *sc, uint32_t cmd) 467 { 468 struct iee_cb *cb = SC_CB(sc, sc->sc_next_cb); 469 struct ethercom *ec = &sc->sc_ethercom; 470 struct ifnet *ifp = &ec->ec_if; 471 struct ether_multistep step; 472 struct ether_multi *enm; 473 474 memset(cb, 0, sc->sc_cb_sz); 475 cb->cb_cmd = cmd; 476 switch (cmd & IEE_CB_CMD) { 477 case IEE_CB_CMD_NOP: /* NOP CMD */ 478 break; 479 case IEE_CB_CMD_IAS: /* Individual Address Setup */ 480 memcpy(__UNVOLATILE(cb->cb_ind_addr), CLLADDR(ifp->if_sadl), 481 ETHER_ADDR_LEN); 482 break; 483 case IEE_CB_CMD_CONF: /* Configure */ 484 memcpy(__UNVOLATILE(cb->cb_cf), sc->sc_cf, sc->sc_cf[0] 485 & IEE_CF_0_CNT_M); 486 break; 487 case IEE_CB_CMD_MCS: /* Multicast Setup */ 488 if (sc->sc_next_cb != 0) { 489 sc->sc_flags |= IEE_WANT_MCAST; 490 return; 491 } 492 sc->sc_flags &= ~IEE_WANT_MCAST; 493 if ((sc->sc_cf[8] & IEE_CF_8_PRM) != 0) { 494 /* Need no multicast filter in promisc mode. */ 495 iee_cb_setup(sc, IEE_CB_CMD_CONF | IEE_CB_S | IEE_CB_EL 496 | IEE_CB_I); 497 return; 498 } 499 /* Leave room for a CONF CMD to en/dis-able ALLMULTI mode */ 500 cb = SC_CB(sc, sc->sc_next_cb + 1); 501 cb->cb_cmd = cmd; 502 cb->cb_mcast.mc_size = 0; 503 ETHER_LOCK(ec); 504 ETHER_FIRST_MULTI(step, ec, enm); 505 while (enm != NULL) { 506 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 507 ETHER_ADDR_LEN) != 0 || cb->cb_mcast.mc_size 508 * ETHER_ADDR_LEN + 2 * sc->sc_cb_sz > 509 sc->sc_cb_sz * IEE_NCB + 510 sc->sc_tbd_sz * IEE_NTBD * IEE_NCB) { 511 cb->cb_mcast.mc_size = 0; 512 break; 513 } 514 memcpy(__UNVOLATILE(&cb->cb_mcast.mc_addrs[ 515 cb->cb_mcast.mc_size]), 516 enm->enm_addrlo, ETHER_ADDR_LEN); 517 ETHER_NEXT_MULTI(step, enm); 518 cb->cb_mcast.mc_size += ETHER_ADDR_LEN; 519 } 520 ETHER_UNLOCK(ec); 521 if (cb->cb_mcast.mc_size == 0) { 522 /* Can't do exact mcast filtering, do ALLMULTI mode. */ 523 ifp->if_flags |= IFF_ALLMULTI; 524 sc->sc_cf[11] &= ~IEE_CF_11_MCALL; 525 } else { 526 /* disable ALLMULTI and load mcast list */ 527 ifp->if_flags &= ~IFF_ALLMULTI; 528 sc->sc_cf[11] |= IEE_CF_11_MCALL; 529 /* Mcast setup may need more than sc->sc_cb_sz bytes. */ 530 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 531 sc->sc_cb_off, 532 sc->sc_cb_sz * IEE_NCB + 533 sc->sc_tbd_sz * IEE_NTBD * IEE_NCB, 534 BUS_DMASYNC_PREWRITE); 535 } 536 iee_cb_setup(sc, IEE_CB_CMD_CONF); 537 break; 538 case IEE_CB_CMD_TR: /* Transmit */ 539 cb->cb_transmit.tx_tbd_addr = 540 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_tbd_off 541 + sc->sc_tbd_sz * sc->sc_next_tbd)); 542 cb->cb_cmd |= IEE_CB_SF; /* Always use Flexible Mode. */ 543 break; 544 case IEE_CB_CMD_TDR: /* Time Domain Reflectometry */ 545 break; 546 case IEE_CB_CMD_DUMP: /* Dump */ 547 break; 548 case IEE_CB_CMD_DIAG: /* Diagnose */ 549 break; 550 default: 551 /* can't happen */ 552 break; 553 } 554 cb->cb_link_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_cb_off + 555 sc->sc_cb_sz * (sc->sc_next_cb + 1))); 556 IEE_CBSYNC(sc, sc->sc_next_cb, 557 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 558 sc->sc_next_cb++; 559 ifp->if_timer = 5; 560 } 561 562 563 564 void 565 iee_attach(struct iee_softc *sc, uint8_t *eth_addr, int *media, int nmedia, 566 int defmedia) 567 { 568 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 569 int n; 570 571 KASSERT(sc->sc_cl_align > 0 && powerof2(sc->sc_cl_align)); 572 573 /* 574 * Calculate DMA descriptor offsets and sizes in shmem 575 * which should be cache line aligned. 576 */ 577 sc->sc_scp_off = 0; 578 sc->sc_scp_sz = roundup2(sizeof(struct iee_scp), sc->sc_cl_align); 579 sc->sc_iscp_off = sc->sc_scp_sz; 580 sc->sc_iscp_sz = roundup2(sizeof(struct iee_iscp), sc->sc_cl_align); 581 sc->sc_scb_off = sc->sc_iscp_off + sc->sc_iscp_sz; 582 sc->sc_scb_sz = roundup2(sizeof(struct iee_scb), sc->sc_cl_align); 583 sc->sc_rfd_off = sc->sc_scb_off + sc->sc_scb_sz; 584 sc->sc_rfd_sz = roundup2(sizeof(struct iee_rfd), sc->sc_cl_align); 585 sc->sc_rbd_off = sc->sc_rfd_off + sc->sc_rfd_sz * IEE_NRFD; 586 sc->sc_rbd_sz = roundup2(sizeof(struct iee_rbd), sc->sc_cl_align); 587 sc->sc_cb_off = sc->sc_rbd_off + sc->sc_rbd_sz * IEE_NRFD; 588 sc->sc_cb_sz = roundup2(sizeof(struct iee_cb), sc->sc_cl_align); 589 sc->sc_tbd_off = sc->sc_cb_off + sc->sc_cb_sz * IEE_NCB; 590 sc->sc_tbd_sz = roundup2(sizeof(struct iee_tbd), sc->sc_cl_align); 591 sc->sc_shmem_sz = sc->sc_tbd_off + sc->sc_tbd_sz * IEE_NTBD * IEE_NCB; 592 593 /* allocate memory for shared DMA descriptors */ 594 if (bus_dmamem_alloc(sc->sc_dmat, sc->sc_shmem_sz, PAGE_SIZE, 0, 595 &sc->sc_dma_segs, 1, &sc->sc_dma_rsegs, BUS_DMA_NOWAIT) != 0) { 596 aprint_error(": can't allocate %d bytes of DMA memory\n", 597 sc->sc_shmem_sz); 598 return; 599 } 600 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_dma_segs, sc->sc_dma_rsegs, 601 sc->sc_shmem_sz, (void **)&sc->sc_shmem_addr, 602 BUS_DMA_COHERENT | BUS_DMA_NOWAIT) != 0) { 603 aprint_error(": can't map DMA memory\n"); 604 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, 605 sc->sc_dma_rsegs); 606 return; 607 } 608 if (bus_dmamap_create(sc->sc_dmat, sc->sc_shmem_sz, sc->sc_dma_rsegs, 609 sc->sc_shmem_sz, 0, BUS_DMA_NOWAIT, &sc->sc_shmem_map) != 0) { 610 aprint_error(": can't create DMA map\n"); 611 bus_dmamem_unmap(sc->sc_dmat, sc->sc_shmem_addr, 612 sc->sc_shmem_sz); 613 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, 614 sc->sc_dma_rsegs); 615 return; 616 } 617 if (bus_dmamap_load(sc->sc_dmat, sc->sc_shmem_map, sc->sc_shmem_addr, 618 sc->sc_shmem_sz, NULL, BUS_DMA_NOWAIT) != 0) { 619 aprint_error(": can't load DMA map\n"); 620 bus_dmamap_destroy(sc->sc_dmat, sc->sc_shmem_map); 621 bus_dmamem_unmap(sc->sc_dmat, sc->sc_shmem_addr, 622 sc->sc_shmem_sz); 623 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, 624 sc->sc_dma_rsegs); 625 return; 626 } 627 memset(sc->sc_shmem_addr, 0, sc->sc_shmem_sz); 628 629 /* 630 * Set pointer to Intermediate System Configuration Pointer. 631 * Phys. addr. in big endian order. (Big endian as defined by Intel.) 632 */ 633 SC_SCP(sc)->scp_iscp_addr = IEE_SWAP32(IEE_PHYS_SHMEM(sc->sc_iscp_off)); 634 SC_SCP(sc)->scp_sysbus = sc->sc_sysbus; 635 /* 636 * Set pointer to System Control Block. 637 * Phys. addr. in big endian order. (Big endian as defined by Intel.) 638 */ 639 SC_ISCP(sc)->iscp_scb_addr = IEE_SWAP32(IEE_PHYS_SHMEM(sc->sc_scb_off)); 640 /* Set pointer to Receive Frame Area. (physical address) */ 641 SC_SCB(sc)->scb_rfa_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off)); 642 /* Set pointer to Command Block. (physical address) */ 643 SC_SCB(sc)->scb_cmd_blk_addr = 644 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_cb_off)); 645 646 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 0, sc->sc_shmem_sz, 647 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 648 649 /* Initialize ifmedia structures. */ 650 sc->sc_ethercom.ec_ifmedia = &sc->sc_ifmedia; 651 ifmedia_init(&sc->sc_ifmedia, 0, iee_mediachange, iee_mediastatus); 652 if (media != NULL) { 653 for (n = 0 ; n < nmedia ; n++) 654 ifmedia_add(&sc->sc_ifmedia, media[n], 0, NULL); 655 ifmedia_set(&sc->sc_ifmedia, defmedia); 656 } else { 657 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_NONE, 0, NULL); 658 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_NONE); 659 } 660 661 ifp->if_softc = sc; 662 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 663 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 664 ifp->if_start = iee_start; /* initiate output routine */ 665 ifp->if_ioctl = iee_ioctl; /* ioctl routine */ 666 ifp->if_init = iee_init; /* init routine */ 667 ifp->if_stop = iee_stop; /* stop routine */ 668 ifp->if_watchdog = iee_watchdog; /* timer routine */ 669 IFQ_SET_READY(&ifp->if_snd); 670 /* iee supports IEEE 802.1Q Virtual LANs, see vlan(4). */ 671 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 672 673 if_attach(ifp); 674 if_deferred_start_init(ifp, NULL); 675 ether_ifattach(ifp, eth_addr); 676 677 aprint_normal(": Intel 82596%s address %s\n", 678 i82596_typenames[sc->sc_type], ether_sprintf(eth_addr)); 679 680 for (n = 0 ; n < IEE_NCB ; n++) 681 sc->sc_tx_map[n] = NULL; 682 for (n = 0 ; n < IEE_NRFD ; n++) { 683 sc->sc_rx_mbuf[n] = NULL; 684 sc->sc_rx_map[n] = NULL; 685 } 686 sc->sc_tx_timeout = 0; 687 sc->sc_setup_timeout = 0; 688 (sc->sc_iee_reset)(sc); 689 } 690 691 692 void 693 iee_detach(struct iee_softc *sc, int flags) 694 { 695 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 696 697 if ((ifp->if_flags & IFF_RUNNING) != 0) 698 iee_stop(ifp, 1); 699 ether_ifdetach(ifp); 700 if_detach(ifp); 701 bus_dmamap_unload(sc->sc_dmat, sc->sc_shmem_map); 702 bus_dmamap_destroy(sc->sc_dmat, sc->sc_shmem_map); 703 bus_dmamem_unmap(sc->sc_dmat, sc->sc_shmem_addr, sc->sc_shmem_sz); 704 bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_segs, sc->sc_dma_rsegs); 705 } 706 707 708 /* Media change and status callback */ 709 int 710 iee_mediachange(struct ifnet *ifp) 711 { 712 struct iee_softc *sc = ifp->if_softc; 713 714 if (sc->sc_mediachange != NULL) 715 return (sc->sc_mediachange)(ifp); 716 return 0; 717 } 718 719 720 void 721 iee_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmreq) 722 { 723 struct iee_softc *sc = ifp->if_softc; 724 725 if (sc->sc_mediastatus != NULL) 726 (sc->sc_mediastatus)(ifp, ifmreq); 727 } 728 729 730 /* Initiate output routine */ 731 void 732 iee_start(struct ifnet *ifp) 733 { 734 struct iee_softc *sc = ifp->if_softc; 735 struct mbuf *m = NULL; 736 struct iee_tbd *tbd; 737 int t; 738 int n; 739 740 if (sc->sc_next_cb != 0) 741 /* There is already a CMD running. Defer packet enqueuing. */ 742 return; 743 for (t = 0 ; t < IEE_NCB ; t++) { 744 IFQ_DEQUEUE(&ifp->if_snd, sc->sc_tx_mbuf[t]); 745 if (sc->sc_tx_mbuf[t] == NULL) 746 break; 747 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_tx_map[t], 748 sc->sc_tx_mbuf[t], BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 749 /* 750 * The packet needs more TBD than we support. 751 * Copy the packet into a mbuf cluster to get it out. 752 */ 753 printf("%s: iee_start: failed to load DMA map\n", 754 device_xname(sc->sc_dev)); 755 MGETHDR(m, M_DONTWAIT, MT_DATA); 756 if (m == NULL) { 757 printf("%s: iee_start: can't allocate mbuf\n", 758 device_xname(sc->sc_dev)); 759 m_freem(sc->sc_tx_mbuf[t]); 760 sc->sc_tx_mbuf[t] = NULL; 761 t--; 762 continue; 763 } 764 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 765 MCLGET(m, M_DONTWAIT); 766 if ((m->m_flags & M_EXT) == 0) { 767 printf("%s: iee_start: can't allocate mbuf " 768 "cluster\n", device_xname(sc->sc_dev)); 769 m_freem(sc->sc_tx_mbuf[t]); 770 sc->sc_tx_mbuf[t] = NULL; 771 m_freem(m); 772 t--; 773 continue; 774 } 775 m_copydata(sc->sc_tx_mbuf[t], 0, 776 sc->sc_tx_mbuf[t]->m_pkthdr.len, mtod(m, void *)); 777 m->m_pkthdr.len = sc->sc_tx_mbuf[t]->m_pkthdr.len; 778 m->m_len = sc->sc_tx_mbuf[t]->m_pkthdr.len; 779 m_freem(sc->sc_tx_mbuf[t]); 780 sc->sc_tx_mbuf[t] = m; 781 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_tx_map[t], 782 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 783 printf("%s: iee_start: can't load TX DMA map\n", 784 device_xname(sc->sc_dev)); 785 m_freem(sc->sc_tx_mbuf[t]); 786 sc->sc_tx_mbuf[t] = NULL; 787 t--; 788 continue; 789 } 790 } 791 for (n = 0 ; n < sc->sc_tx_map[t]->dm_nsegs ; n++) { 792 tbd = SC_TBD(sc, sc->sc_next_tbd + n); 793 tbd->tbd_tb_addr = 794 IEE_SWAPA32(sc->sc_tx_map[t]->dm_segs[n].ds_addr); 795 tbd->tbd_size = 796 sc->sc_tx_map[t]->dm_segs[n].ds_len; 797 tbd->tbd_link_addr = 798 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_tbd_off + 799 sc->sc_tbd_sz * (sc->sc_next_tbd + n + 1))); 800 } 801 SC_TBD(sc, sc->sc_next_tbd + n - 1)->tbd_size |= IEE_CB_EL; 802 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 803 sc->sc_tbd_off + sc->sc_next_tbd * sc->sc_tbd_sz, 804 sc->sc_tbd_sz * sc->sc_tx_map[t]->dm_nsegs, 805 BUS_DMASYNC_PREWRITE); 806 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_map[t], 0, 807 sc->sc_tx_map[t]->dm_mapsize, BUS_DMASYNC_PREWRITE); 808 IFQ_POLL(&ifp->if_snd, m); 809 if (m == NULL) 810 iee_cb_setup(sc, IEE_CB_CMD_TR | IEE_CB_S | IEE_CB_EL 811 | IEE_CB_I); 812 else 813 iee_cb_setup(sc, IEE_CB_CMD_TR); 814 sc->sc_next_tbd += n; 815 /* Pass packet to bpf if someone listens. */ 816 bpf_mtap(ifp, sc->sc_tx_mbuf[t], BPF_D_OUT); 817 } 818 if (t == 0) 819 /* No packets got set up for TX. */ 820 return; 821 if (t == IEE_NCB) 822 ifp->if_flags |= IFF_OACTIVE; 823 (sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE); 824 } 825 826 827 828 /* ioctl routine */ 829 int 830 iee_ioctl(struct ifnet *ifp, u_long cmd, void *data) 831 { 832 struct iee_softc *sc = ifp->if_softc; 833 int s; 834 int err; 835 836 s = splnet(); 837 switch (cmd) { 838 default: 839 err = ether_ioctl(ifp, cmd, data); 840 if (err == ENETRESET) { 841 /* 842 * Multicast list as changed; set the hardware filter 843 * accordingly. 844 */ 845 if (ifp->if_flags & IFF_RUNNING) { 846 iee_cb_setup(sc, IEE_CB_CMD_MCS | IEE_CB_S | 847 IEE_CB_EL | IEE_CB_I); 848 if ((sc->sc_flags & IEE_WANT_MCAST) == 0) 849 (*sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE); 850 } 851 err = 0; 852 } 853 break; 854 } 855 splx(s); 856 return err; 857 } 858 859 860 861 /* init routine */ 862 int 863 iee_init(struct ifnet *ifp) 864 { 865 struct iee_softc *sc = ifp->if_softc; 866 int r; 867 int t; 868 int n; 869 int err; 870 871 sc->sc_next_cb = 0; 872 sc->sc_next_tbd = 0; 873 sc->sc_flags &= ~IEE_WANT_MCAST; 874 sc->sc_rx_done = 0; 875 SC_SCB(sc)->scb_crc_err = 0; 876 SC_SCB(sc)->scb_align_err = 0; 877 SC_SCB(sc)->scb_resource_err = 0; 878 SC_SCB(sc)->scb_overrun_err = 0; 879 SC_SCB(sc)->scb_rcvcdt_err = 0; 880 SC_SCB(sc)->scb_short_fr_err = 0; 881 sc->sc_crc_err = 0; 882 sc->sc_align_err = 0; 883 sc->sc_resource_err = 0; 884 sc->sc_overrun_err = 0; 885 sc->sc_rcvcdt_err = 0; 886 sc->sc_short_fr_err = 0; 887 sc->sc_tx_col = 0; 888 sc->sc_rx_err = 0; 889 sc->sc_cmd_err = 0; 890 /* Create Transmit DMA maps. */ 891 for (t = 0 ; t < IEE_NCB ; t++) { 892 if (sc->sc_tx_map[t] == NULL && bus_dmamap_create(sc->sc_dmat, 893 MCLBYTES, IEE_NTBD, MCLBYTES, 0, BUS_DMA_NOWAIT, 894 &sc->sc_tx_map[t]) != 0) { 895 printf("%s: iee_init: can't create TX DMA map\n", 896 device_xname(sc->sc_dev)); 897 for (n = 0 ; n < t ; n++) 898 bus_dmamap_destroy(sc->sc_dmat, 899 sc->sc_tx_map[n]); 900 return ENOBUFS; 901 } 902 } 903 /* Initialize Receive Frame and Receive Buffer Descriptors */ 904 err = 0; 905 memset(SC_RFD(sc, 0), 0, sc->sc_rfd_sz * IEE_NRFD); 906 memset(SC_RBD(sc, 0), 0, sc->sc_rbd_sz * IEE_NRFD); 907 for (r = 0 ; r < IEE_NRFD ; r++) { 908 SC_RFD(sc, r)->rfd_cmd = IEE_RFD_SF; 909 SC_RFD(sc, r)->rfd_link_addr = 910 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off 911 + sc->sc_rfd_sz * ((r + 1) % IEE_NRFD))); 912 913 SC_RBD(sc, r)->rbd_next_rbd = 914 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off 915 + sc->sc_rbd_sz * ((r + 1) % IEE_NRFD))); 916 if (sc->sc_rx_mbuf[r] == NULL) { 917 MGETHDR(sc->sc_rx_mbuf[r], M_DONTWAIT, MT_DATA); 918 if (sc->sc_rx_mbuf[r] == NULL) { 919 printf("%s: iee_init: can't allocate mbuf\n", 920 device_xname(sc->sc_dev)); 921 err = 1; 922 break; 923 } 924 MCLAIM(sc->sc_rx_mbuf[r], 925 &sc->sc_ethercom.ec_rx_mowner); 926 MCLGET(sc->sc_rx_mbuf[r], M_DONTWAIT); 927 if ((sc->sc_rx_mbuf[r]->m_flags & M_EXT) == 0) { 928 printf("%s: iee_init: can't allocate mbuf" 929 " cluster\n", device_xname(sc->sc_dev)); 930 m_freem(sc->sc_rx_mbuf[r]); 931 sc->sc_rx_mbuf[r] = NULL; 932 err = 1; 933 break; 934 } 935 sc->sc_rx_mbuf[r]->m_len = 936 sc->sc_rx_mbuf[r]->m_pkthdr.len = MCLBYTES - 2; 937 sc->sc_rx_mbuf[r]->m_data += 2; 938 } 939 if (sc->sc_rx_map[r] == NULL && bus_dmamap_create(sc->sc_dmat, 940 MCLBYTES, 1, MCLBYTES , 0, BUS_DMA_NOWAIT, 941 &sc->sc_rx_map[r]) != 0) { 942 printf("%s: iee_init: can't create RX DMA map\n", 943 device_xname(sc->sc_dev)); 944 m_freem(sc->sc_rx_mbuf[r]); 945 sc->sc_rx_mbuf[r] = NULL; 946 err = 1; 947 break; 948 } 949 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_rx_map[r], 950 sc->sc_rx_mbuf[r], BUS_DMA_READ | BUS_DMA_NOWAIT) != 0) { 951 printf("%s: iee_init: can't load RX DMA map\n", 952 device_xname(sc->sc_dev)); 953 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[r]); 954 m_freem(sc->sc_rx_mbuf[r]); 955 sc->sc_rx_mbuf[r] = NULL; 956 err = 1; 957 break; 958 } 959 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_map[r], 0, 960 sc->sc_rx_map[r]->dm_mapsize, BUS_DMASYNC_PREREAD); 961 SC_RBD(sc, r)->rbd_size = sc->sc_rx_map[r]->dm_segs[0].ds_len; 962 SC_RBD(sc, r)->rbd_rb_addr = 963 IEE_SWAPA32(sc->sc_rx_map[r]->dm_segs[0].ds_addr); 964 } 965 SC_RFD(sc, 0)->rfd_rbd_addr = 966 IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rbd_off)); 967 if (err != 0) { 968 for (n = 0 ; n < r; n++) { 969 m_freem(sc->sc_rx_mbuf[n]); 970 sc->sc_rx_mbuf[n] = NULL; 971 bus_dmamap_unload(sc->sc_dmat, sc->sc_rx_map[n]); 972 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[n]); 973 sc->sc_rx_map[n] = NULL; 974 } 975 for (n = 0 ; n < t ; n++) { 976 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_map[n]); 977 sc->sc_tx_map[n] = NULL; 978 } 979 return ENOBUFS; 980 } 981 982 (sc->sc_iee_reset)(sc); 983 iee_cb_setup(sc, IEE_CB_CMD_IAS); 984 sc->sc_cf[0] = IEE_CF_0_DEF | IEE_CF_0_PREF; 985 sc->sc_cf[1] = IEE_CF_1_DEF; 986 sc->sc_cf[2] = IEE_CF_2_DEF; 987 sc->sc_cf[3] = IEE_CF_3_ADDRLEN_DEF | IEE_CF_3_NSAI 988 | IEE_CF_3_PREAMLEN_DEF; 989 sc->sc_cf[4] = IEE_CF_4_DEF; 990 sc->sc_cf[5] = IEE_CF_5_DEF; 991 sc->sc_cf[6] = IEE_CF_6_DEF; 992 sc->sc_cf[7] = IEE_CF_7_DEF; 993 sc->sc_cf[8] = IEE_CF_8_DEF; 994 sc->sc_cf[9] = IEE_CF_9_DEF; 995 sc->sc_cf[10] = IEE_CF_10_DEF; 996 sc->sc_cf[11] = IEE_CF_11_DEF & ~IEE_CF_11_LNGFLD; 997 sc->sc_cf[12] = IEE_CF_12_DEF; 998 sc->sc_cf[13] = IEE_CF_13_DEF; 999 iee_cb_setup(sc, IEE_CB_CMD_CONF | IEE_CB_S | IEE_CB_EL); 1000 SC_SCB(sc)->scb_rfa_addr = IEE_SWAPA32(IEE_PHYS_SHMEM(sc->sc_rfd_off)); 1001 bus_dmamap_sync(sc->sc_dmat, sc->sc_shmem_map, 0, sc->sc_shmem_sz, 1002 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1003 (sc->sc_iee_cmd)(sc, IEE_SCB_CUC_EXE | IEE_SCB_RUC_ST); 1004 /* Issue a Channel Attention to ACK interrupts we may have caused. */ 1005 (sc->sc_iee_cmd)(sc, IEE_SCB_ACK); 1006 1007 /* Mark the interface as running and ready to RX/TX packets. */ 1008 ifp->if_flags |= IFF_RUNNING; 1009 ifp->if_flags &= ~IFF_OACTIVE; 1010 return 0; 1011 } 1012 1013 1014 /* Stop routine */ 1015 void 1016 iee_stop(struct ifnet *ifp, int disable) 1017 { 1018 struct iee_softc *sc = ifp->if_softc; 1019 int n; 1020 1021 ifp->if_flags &= ~IFF_RUNNING; 1022 ifp->if_flags |= IFF_OACTIVE; 1023 ifp->if_timer = 0; 1024 /* Reset the chip to get it quiet. */ 1025 (sc->sc_iee_reset)(ifp->if_softc); 1026 /* Issue a Channel Attention to ACK interrupts we may have caused. */ 1027 (sc->sc_iee_cmd)(ifp->if_softc, IEE_SCB_ACK); 1028 /* Release any dynamically allocated resources. */ 1029 for (n = 0 ; n < IEE_NCB ; n++) { 1030 if (sc->sc_tx_map[n] != NULL) 1031 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_map[n]); 1032 sc->sc_tx_map[n] = NULL; 1033 } 1034 for (n = 0 ; n < IEE_NRFD ; n++) { 1035 if (sc->sc_rx_mbuf[n] != NULL) 1036 m_freem(sc->sc_rx_mbuf[n]); 1037 sc->sc_rx_mbuf[n] = NULL; 1038 if (sc->sc_rx_map[n] != NULL) { 1039 bus_dmamap_unload(sc->sc_dmat, sc->sc_rx_map[n]); 1040 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_map[n]); 1041 } 1042 sc->sc_rx_map[n] = NULL; 1043 } 1044 } 1045 1046 1047 /* Timer routine */ 1048 void 1049 iee_watchdog(struct ifnet *ifp) 1050 { 1051 struct iee_softc *sc = ifp->if_softc; 1052 1053 (sc->sc_iee_reset)(sc); 1054 if (sc->sc_next_tbd != 0) 1055 printf("%s: iee_watchdog: transmit timeout %d\n", 1056 device_xname(sc->sc_dev), ++sc->sc_tx_timeout); 1057 else 1058 printf("%s: iee_watchdog: setup timeout %d\n", 1059 device_xname(sc->sc_dev), ++sc->sc_setup_timeout); 1060 iee_init(ifp); 1061 } 1062
Indexes created Tue Sep 30 06:09:59 GMT 2025