i82801lpcreg.h revision 1.6
1 /* $NetBSD: i82801lpcreg.h,v 1.6 2007/08/26 18:39:43 xtraeme Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel 82801 Series I/O Controller Hub (ICH) -- LPC Interface Bridge part 41 * register definitions. 42 */ 43 44 #ifndef _DEV_IC_I82801LPGREG_H_ 45 #define _DEV_IC_I82801LPGREG_H_ 46 /* 47 * PCI configuration registers 48 */ 49 #define LPCIB_PCI_PMBASE 0x40 50 #define LPCIB_PCI_ACPI_CNTL 0x44 51 # define LPCIB_PCI_ACPI_CNTL_EN (1 << 4) 52 #define LPCIB_PCI_BIOS_CNTL 0x4e 53 #define LPCIB_PCI_TCO_CNTL 0x54 54 #define LPCIB_PCI_GPIO_BASE 0x58 55 #define LPCIB_PCI_GPIO_CNTL 0x5c 56 #define LPCIB_PCI_PIRQA_ROUT 0x60 57 #define LPCIB_PCI_PIRQB_ROUT 0x61 58 #define LPCIB_PCI_PIRQC_ROUT 0x62 59 #define LPCIB_PCI_PIRQD_ROUT 0x63 60 #define LPCIB_PCI_SIRQ_CNTL 0x64 61 #define LPCIB_PCI_PIRQE_ROUT 0x68 62 #define LPCIB_PCI_PIRQF_ROUT 0x69 63 #define LPCIB_PCI_PIRQG_ROUT 0x6a 64 #define LPCIB_PCI_PIRQH_ROUT 0x6b 65 #define LPCIB_PCI_D31_ERR_CFG 0x88 66 #define LPCIB_PCI_D31_ERR_STS 0x8a 67 #define LPCIB_PCI_PCI_DMA_C 0x90 68 #define LPCIB_PCI_GEN_PMCON_1 0xa0 69 # define LPCIB_PCI_GEN_PMCON_1_SS_EN 0x08 70 #define LPCIB_PCI_GEN_PMCON_2 0xa2 71 #define LPCIB_PCI_GEN_PMCON_3 0xa4 72 #define LPCIB_PCI_STPCLK_DEL 0xa8 73 #define LPCIB_PCI_GPI_ROUT 0xb8 74 #define LPCIB_PCI_TRP_FWD_EN 0xc0 75 #define LPCIB_PCI_MON4_TRP_RNG 0xc4 76 #define LPCIB_PCI_MON5_TRP_RNG 0xc5 77 #define LPCIB_PCI_MON6_TRP_RNG 0xc6 78 #define LPCIB_PCI_MON7_TRP_RNG 0xc7 79 #define LPCIB_PCI_MON_TRP_MSK oxcc 80 #define LPCIB_PCI_GEN_CNTL 0xd0 81 #define LPCIB_PCI_GEN_STA 0xd4 82 # define LPCIB_PCI_GEN_STA_SAFE_MODE (1 << 2) 83 # define LPCIB_PCI_GEN_STA_NO_REBOOT (1 << 1) 84 #define LPCIB_PCI_BACK_CNTL 0xd5 85 #define LPCIB_PCI_RTC_CONF 0xd8 86 #define LPCIB_PCI_COM_DEC 0xe0 87 #define LPCIB_PCI_LPCFDD_DEC 0xe1 88 #define LPCIB_PCI_SND_DEC 0xe2 89 #define LPCIB_PCI_FWH_DEC_EN1 0xe3 90 #define LPCIB_PCI_GEN1_DEC 0xe4 91 #define LPCIB_PCI_LPC_EN 0xe6 92 #define LPCIB_PCI_FWH_SEL1 0xe8 93 #define LPCIB_PCI_GEN2_DEC 0xec 94 #define LPCIB_PCI_FWH_SEL2 0xee 95 #define LPCIB_PCI_FWH_DEC_EN2 0xf0 96 #define LPCIB_PCI_FUNC_DIS 0xf2 97 98 /* 99 * Power management I/O registers 100 * (offset from PMBASE) 101 */ 102 #define LPCIB_PM1_STS 0x00 /* ACPI PM1a_EVT_BLK fixed event status */ 103 #define LPCIB_PM1_EN 0x02 /* ACPI PM1a_EVT_BLK fixed event enable */ 104 #define LPCIB_PM1_CNT 0x04 /* ACPI PM1a_CNT_BLK */ 105 #define LPCIB_PM1_TMR 0x08 /* ACPI PMTMR_BLK power mgmt timer */ 106 #define LPCIB_PROC_CNT 0x10 /* ACPI P_BLK processor control */ 107 #define LPCIB_LV2 0x14 /* ACPI P_BLK processor C2 control */ 108 #define LPCIB_PM_CTRL 0x20 /* ACPI Power Management Control */ 109 # define LPCIB_PM_SS_STATE_LOW 0x01 /* SpeedStep Low Power State */ 110 #define LPCIB_GPE0_STS 0x28 /* ACPI GPE0_BLK GPE0 status */ 111 #define LPCIB_GPE0_EN 0x2c /* ACPI GPE0_BLK GPE0 enable */ 112 #define LPCIB_SMI_EN 0x30 113 # define LPCIB_SMI_EN_INTEL_USB2_EN (1 << 18) 114 # define LPCIB_SMI_EN_LEGACY_USB2_EN (1 << 17) 115 # define LPCIB_SMI_EN_PERIODIC_EN (1 << 14) 116 # define LPCIB_SMI_EN_TCO_EN (1 << 13) 117 # define LPCIB_SMI_EN_MCSMI_EN (1 << 11) 118 # define LPCIB_SMI_EN_BIOS_RLS (1 << 7) 119 # define LPCIB_SMI_EN_SWSMI_TMR_EN (1 << 6) 120 # define LPCIB_SMI_EN_APMC_EN (1 << 5) 121 # define LPCIB_SMI_EN_SLP_SMI_EN (1 << 4) 122 # define LPCIB_SMI_EN_LEGACY_USB_EN (1 << 3) 123 # define LPCIB_SMI_EN_BIOS_EN (1 << 2) 124 # define LPCIB_SMI_EN_EOS (1 << 1) 125 # define LPCIB_SMI_EN_GBL_SMI_EN (1 << 0) 126 #define LPCIB_SMI_STS 0x34 127 #define LPCIB_ALT_GP_SMI_EN 0x38 128 #define LPCIB_ALT_GP_SMI_STS 0x3a 129 #define LPCIB_MON_SMI 0x40 130 #define LPCIB_DEVACT_STS 0x44 131 #define LPCIB_DEVTRAP_EN 0x48 132 #define LPCIB_BUS_ADDR_TRACK 0x4c 133 #define LPCIB_BUS_CYC_TRACK 0x4e 134 #define LPCIB_PM_SS_CNTL 0x50 /* SpeedStep control */ 135 # define LPCIB_PM_SS_CNTL_ARB_DIS 0x01 /* disable arbiter */ 136 137 /* 138 * SMBus controller registers. 139 */ 140 141 /* PCI configuration registers */ 142 #define LPCIB_SMB_BASE 0x20 /* SMBus base address */ 143 #define LPCIB_SMB_HOSTC 0x40 /* host configuration */ 144 #define LPCIB_SMB_HOSTC_HSTEN (1 << 0) /* enable host controller */ 145 #define LPCIB_SMB_HOSTC_SMIEN (1 << 1) /* generate SMI */ 146 #define LPCIB_SMB_HOSTC_I2CEN (1 << 2) /* enable I2C commands */ 147 148 /* SMBus I/O registers */ 149 #define LPCIB_SMB_HS 0x00 /* host status */ 150 #define LPCIB_SMB_HS_BUSY (1 << 0) /* running a command */ 151 #define LPCIB_SMB_HS_INTR (1 << 1) /* command completed */ 152 #define LPCIB_SMB_HS_DEVERR (1 << 2) /* command error */ 153 #define LPCIB_SMB_HS_BUSERR (1 << 3) /* transaction collision */ 154 #define LPCIB_SMB_HS_FAILED (1 << 4) /* failed bus transaction */ 155 #define LPCIB_SMB_HS_SMBAL (1 << 5) /* SMBALERT# asserted */ 156 #define LPCIB_SMB_HS_INUSE (1 << 6) /* bus semaphore */ 157 #define LPCIB_SMB_HS_BDONE (1 << 7) /* byte received/transmitted */ 158 #define LPCIB_SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED\006SMBAL\007INUSE\010BDONE" 159 #define LPCIB_SMB_HC 0x02 /* host control */ 160 #define LPCIB_SMB_HC_INTREN (1 << 0) /* enable interrupts */ 161 #define LPCIB_SMB_HC_KILL (1 << 1) /* kill current transaction */ 162 #define LPCIB_SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */ 163 #define LPCIB_SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */ 164 #define LPCIB_SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */ 165 #define LPCIB_SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */ 166 #define LPCIB_SMB_HC_CMD_PCALL (4 << 2) /* PROCESS CALL command */ 167 #define LPCIB_SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */ 168 #define LPCIB_SMB_HC_CMD_I2CREAD (6 << 2) /* I2C READ command */ 169 #define LPCIB_SMB_HC_CMD_BLOCKP (7 << 2) /* BLOCK PROCESS command */ 170 #define LPCIB_SMB_HC_LASTB (1 << 5) /* last byte in block */ 171 #define LPCIB_SMB_HC_START (1 << 6) /* start transaction */ 172 #define LPCIB_SMB_HC_PECEN (1 << 7) /* enable PEC */ 173 #define LPCIB_SMB_HCMD 0x03 /* host command */ 174 #define LPCIB_SMB_TXSLVA 0x04 /* transmit slave address */ 175 #define LPCIB_SMB_TXSLVA_READ (1 << 0) /* read direction */ 176 #define LPCIB_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */ 177 #define LPCIB_SMB_HD0 0x05 /* host data 0 */ 178 #define LPCIB_SMB_HD1 0x06 /* host data 1 */ 179 #define LPCIB_SMB_HBDB 0x07 /* host block data byte */ 180 #define LPCIB_SMB_PEC 0x08 /* PEC data */ 181 #define LPCIB_SMB_RXSLVA 0x09 /* receive slave address */ 182 #define LPCIB_SMB_SD 0x0a /* receive slave data */ 183 #define LPCIB_SMB_SD_MSG0(x) ((x) & 0xff) /* data message byte 0 */ 184 #define LPCIB_SMB_SD_MSG1(x) ((x) >> 8) /* data message byte 1 */ 185 #define LPCIB_SMB_AS 0x0c /* auxiliary status */ 186 #define LPCIB_SMB_AS_CRCE (1 << 0) /* CRC error */ 187 #define LPCIB_SMB_AS_TCO (1 << 1) /* advanced TCO mode */ 188 #define LPCIB_SMB_AC 0x0d /* auxiliary control */ 189 #define LPCIB_SMB_AC_AAC (1 << 0) /* automatically append CRC */ 190 #define LPCIB_SMB_AC_E32B (1 << 1) /* enable 32-byte buffer */ 191 #define LPCIB_SMB_SMLPC 0x0e /* SMLink pin control */ 192 #define LPCIB_SMB_SMLPC_LINK0 (1 << 0) /* SMLINK0 pin state */ 193 #define LPCIB_SMB_SMLPC_LINK1 (1 << 1) /* SMLINK1 pin state */ 194 #define LPCIB_SMB_SMLPC_CLKC (1 << 2) /* SMLINK0 pin is untouched */ 195 #define LPCIB_SMB_SMBPC 0x0f /* SMBus pin control */ 196 #define LPCIB_SMB_SMBPC_CLK (1 << 0) /* SMBCLK pin state */ 197 #define LPCIB_SMB_SMBPC_DATA (1 << 1) /* SMBDATA pin state */ 198 #define LPCIB_SMB_SMBPC_CLKC (1 << 2) /* SMBCLK pin is untouched */ 199 #define LPCIB_SMB_SS 0x10 /* slave status */ 200 #define LPCIB_SMB_SS_HN (1 << 0) /* Host Notify command */ 201 #define LPCIB_SMB_SCMD 0x11 /* slave command */ 202 #define LPCIB_SMB_SCMD_INTREN (1 << 0) /* enable interrupts on HN */ 203 #define LPCIB_SMB_SCMD_WKEN (1 << 1) /* wake on HN */ 204 #define LPCIB_SMB_SCMD_SMBALDS (1 << 2) /* disable SMBALERT# intr */ 205 #define LPCIB_SMB_NDADDR 0x14 /* notify device address */ 206 #define LPCIB_SMB_NDADDR_ADDR(x) ((x) >> 1) /* 7-bit address */ 207 #define LPCIB_SMB_NDLOW 0x16 /* notify data low byte */ 208 #define LPCIB_SMB_NDHIGH 0x17 /* notify data high byte */ 209 210 /* ICH Chipset Configuration Registers (ICH6 and newer) */ 211 #define LPCIB_RCBA 0xf0 212 #define LPCIB_GCS_OFFSET 0x3410 213 #define LPCIB_GCS_SIZE 4 214 #define LPCIB_GCS_NO_REBOOT 0x20 215 216 /* 217 * System management TCO registers 218 * (offset from PMBASE) 219 */ 220 #define LPCIB_TCO_BASE 0x60 221 #define LPCIB_TCO_RLD (LPCIB_TCO_BASE+0x00) 222 #define LPCIB_TCO_TMR (LPCIB_TCO_BASE+0x01) 223 #define LPCIB_TCO_TMR2 (LPCIB_TCO_BASE+0x12) /* ICH6 and newer */ 224 # define LPCIB_TCO_TMR_MASK 0x3f 225 #define LPCIB_TCO_DAT_IN (LPCIB_TCO_BASE+0x02) 226 #define LPCIB_TCO_DAT_OUT (LPCIB_TCO_BASE+0x03) 227 #define LPCIB_TCO1_STS (LPCIB_TCO_BASE+0x04) 228 # define LPCIB_TCO1_STS_TIMEOUT 0x08 229 #define LPCIB_TCO2_STS (LPCIB_TCO_BASE+0x06) 230 # define LPCIB_TCO2_STS_BOOT_STS 0x04 231 # define LPCIB_TCO2_STS_SECONDS_TO_STS 0x02 232 #define LPCIB_TCO1_CNT (LPCIB_TCO_BASE+0x08) 233 # define LPCIB_TCO1_CNT_TCO_LOCK (1 << 12) 234 # define LPCIB_TCO1_CNT_TCO_TMR_HLT (1 << 11) 235 # define LPCIB_TCO1_CNT_SEND_NOW (1 << 10) 236 # define LPCIB_TCO1_CNT_NMI2SMI_EN (1 << 9) 237 # define LPCIB_TCO1_CNT_NMI_NOW (1 << 8) 238 #define LPCIB_TCO2_CNT (LPCIB_TCO_BASE+0x0a) 239 #define LPCIB_TCO_MESSAGE1 (LPCIB_TCO_BASE+0x0c) 240 #define LPCIB_TCO_MESSAGE2 (LPCIB_TCO_BASE+0x0d) 241 #define LPCIB_TCO_WDSTATUS (LPCIB_TCO_BASE+0x0e) 242 #define LPCIB_SW_IRQ_GEN (LPCIB_TCO_BASE+0x10) 243 244 /* 245 * TCO timer tick. ICH datasheets say: 246 * - The timer is clocked at approximately 0.6 seconds 247 * - 6 bit; values of 0-3 will be ignored and should not be attempted 248 */ 249 static __inline int 250 lpcib_tcotimer_tick_to_second(int ltick) 251 { 252 return ltick * 6 / 10; 253 } 254 255 static __inline int 256 lpcib_tcotimer_second_to_tick(int ltick) 257 { 258 return ltick * 10 / 6; 259 } 260 261 #define LPCIB_TCOTIMER_MIN_TICK 4 262 #define LPCIB_TCOTIMER2_MIN_TICK 2 263 #define LPCIB_TCOTIMER_MAX_TICK 0x3f /* 39 seconds max */ 264 #define LPCIB_TCOTIMER2_MAX_TICK 0x265 /* 613 seconds max */ 265 266 #endif /* _DEV_IC_I82801LPGREG_H_ */ 267
Indexes created Tue Sep 30 20:09:53 GMT 2025