i82801lpcreg.h revision 1.7
1 /* $NetBSD: i82801lpcreg.h,v 1.7 2007/12/09 20:27:58 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel 82801 Series I/O Controller Hub (ICH) -- LPC Interface Bridge part 41 * register definitions. 42 */ 43 44 #ifndef _DEV_IC_I82801LPGREG_H_ 45 #define _DEV_IC_I82801LPGREG_H_ 46 /* 47 * PCI configuration registers 48 */ 49 #define LPCIB_PCI_PMBASE 0x40 50 #define LPCIB_PCI_ACPI_CNTL 0x44 51 # define LPCIB_PCI_ACPI_CNTL_EN (1 << 4) 52 #define LPCIB_PCI_BIOS_CNTL 0x4e 53 #define LPCIB_PCI_TCO_CNTL 0x54 54 #define LPCIB_PCI_GPIO_BASE 0x58 55 #define LPCIB_PCI_GPIO_CNTL 0x5c 56 #define LPCIB_PCI_PIRQA_ROUT 0x60 57 #define LPCIB_PCI_PIRQB_ROUT 0x61 58 #define LPCIB_PCI_PIRQC_ROUT 0x62 59 #define LPCIB_PCI_PIRQD_ROUT 0x63 60 #define LPCIB_PCI_SIRQ_CNTL 0x64 61 #define LPCIB_PCI_PIRQE_ROUT 0x68 62 #define LPCIB_PCI_PIRQF_ROUT 0x69 63 #define LPCIB_PCI_PIRQG_ROUT 0x6a 64 #define LPCIB_PCI_PIRQH_ROUT 0x6b 65 #define LPCIB_PCI_D31_ERR_CFG 0x88 66 #define LPCIB_PCI_D31_ERR_STS 0x8a 67 #define LPCIB_PCI_PCI_DMA_C 0x90 68 #define LPCIB_PCI_GEN_PMCON_1 0xa0 69 # define LPCIB_PCI_GEN_PMCON_1_SS_EN 0x08 70 #define LPCIB_PCI_GEN_PMCON_2 0xa2 71 #define LPCIB_PCI_GEN_PMCON_3 0xa4 72 #define LPCIB_PCI_STPCLK_DEL 0xa8 73 #define LPCIB_PCI_GPI_ROUT 0xb8 74 #define LPCIB_PCI_TRP_FWD_EN 0xc0 75 #define LPCIB_PCI_MON4_TRP_RNG 0xc4 76 #define LPCIB_PCI_MON5_TRP_RNG 0xc5 77 #define LPCIB_PCI_MON6_TRP_RNG 0xc6 78 #define LPCIB_PCI_MON7_TRP_RNG 0xc7 79 #define LPCIB_PCI_MON_TRP_MSK oxcc 80 #define LPCIB_PCI_GEN_CNTL 0xd0 81 #define LPCIB_ICH5_HPTC_EN 0x00020000 82 #define LPCIB_ICH5_HPTC_WIN_MASK 0x0000c000 83 #define LPCIB_ICH5_HPTC_0000 0x00000000 84 #define LPCIB_ICH5_HPTC_0000_BASE 0xfed00000 85 #define LPCIB_ICH5_HPTC_1000 0x00008000 86 #define LPCIB_ICH5_HPTC_1000_BASE 0xfed01000 87 #define LPCIB_ICH5_HPTC_2000 0x00010000 88 #define LPCIB_ICH5_HPTC_2000_BASE 0xfed02000 89 #define LPCIB_ICH5_HPTC_3000 0x00018000 90 #define LPCIB_ICH5_HPTC_3000_BASE 0xfed03000 91 #define LPCIB_PCI_GEN_STA 0xd4 92 # define LPCIB_PCI_GEN_STA_SAFE_MODE (1 << 2) 93 # define LPCIB_PCI_GEN_STA_NO_REBOOT (1 << 1) 94 #define LPCIB_PCI_BACK_CNTL 0xd5 95 #define LPCIB_PCI_RTC_CONF 0xd8 96 #define LPCIB_PCI_COM_DEC 0xe0 97 #define LPCIB_PCI_LPCFDD_DEC 0xe1 98 #define LPCIB_PCI_SND_DEC 0xe2 99 #define LPCIB_PCI_FWH_DEC_EN1 0xe3 100 #define LPCIB_PCI_GEN1_DEC 0xe4 101 #define LPCIB_PCI_LPC_EN 0xe6 102 #define LPCIB_PCI_FWH_SEL1 0xe8 103 #define LPCIB_PCI_GEN2_DEC 0xec 104 #define LPCIB_PCI_FWH_SEL2 0xee 105 #define LPCIB_PCI_FWH_DEC_EN2 0xf0 106 #define LPCIB_PCI_FUNC_DIS 0xf2 107 108 /* 109 * Power management I/O registers 110 * (offset from PMBASE) 111 */ 112 #define LPCIB_PM1_STS 0x00 /* ACPI PM1a_EVT_BLK fixed event status */ 113 #define LPCIB_PM1_EN 0x02 /* ACPI PM1a_EVT_BLK fixed event enable */ 114 #define LPCIB_PM1_CNT 0x04 /* ACPI PM1a_CNT_BLK */ 115 #define LPCIB_PM1_TMR 0x08 /* ACPI PMTMR_BLK power mgmt timer */ 116 #define LPCIB_PROC_CNT 0x10 /* ACPI P_BLK processor control */ 117 #define LPCIB_LV2 0x14 /* ACPI P_BLK processor C2 control */ 118 #define LPCIB_PM_CTRL 0x20 /* ACPI Power Management Control */ 119 # define LPCIB_PM_SS_STATE_LOW 0x01 /* SpeedStep Low Power State */ 120 #define LPCIB_GPE0_STS 0x28 /* ACPI GPE0_BLK GPE0 status */ 121 #define LPCIB_GPE0_EN 0x2c /* ACPI GPE0_BLK GPE0 enable */ 122 #define LPCIB_SMI_EN 0x30 123 # define LPCIB_SMI_EN_INTEL_USB2_EN (1 << 18) 124 # define LPCIB_SMI_EN_LEGACY_USB2_EN (1 << 17) 125 # define LPCIB_SMI_EN_PERIODIC_EN (1 << 14) 126 # define LPCIB_SMI_EN_TCO_EN (1 << 13) 127 # define LPCIB_SMI_EN_MCSMI_EN (1 << 11) 128 # define LPCIB_SMI_EN_BIOS_RLS (1 << 7) 129 # define LPCIB_SMI_EN_SWSMI_TMR_EN (1 << 6) 130 # define LPCIB_SMI_EN_APMC_EN (1 << 5) 131 # define LPCIB_SMI_EN_SLP_SMI_EN (1 << 4) 132 # define LPCIB_SMI_EN_LEGACY_USB_EN (1 << 3) 133 # define LPCIB_SMI_EN_BIOS_EN (1 << 2) 134 # define LPCIB_SMI_EN_EOS (1 << 1) 135 # define LPCIB_SMI_EN_GBL_SMI_EN (1 << 0) 136 #define LPCIB_SMI_STS 0x34 137 #define LPCIB_ALT_GP_SMI_EN 0x38 138 #define LPCIB_ALT_GP_SMI_STS 0x3a 139 #define LPCIB_MON_SMI 0x40 140 #define LPCIB_DEVACT_STS 0x44 141 #define LPCIB_DEVTRAP_EN 0x48 142 #define LPCIB_BUS_ADDR_TRACK 0x4c 143 #define LPCIB_BUS_CYC_TRACK 0x4e 144 #define LPCIB_PM_SS_CNTL 0x50 /* SpeedStep control */ 145 # define LPCIB_PM_SS_CNTL_ARB_DIS 0x01 /* disable arbiter */ 146 147 /* 148 * SMBus controller registers. 149 */ 150 151 /* PCI configuration registers */ 152 #define LPCIB_SMB_BASE 0x20 /* SMBus base address */ 153 #define LPCIB_SMB_HOSTC 0x40 /* host configuration */ 154 #define LPCIB_SMB_HOSTC_HSTEN (1 << 0) /* enable host controller */ 155 #define LPCIB_SMB_HOSTC_SMIEN (1 << 1) /* generate SMI */ 156 #define LPCIB_SMB_HOSTC_I2CEN (1 << 2) /* enable I2C commands */ 157 158 /* SMBus I/O registers */ 159 #define LPCIB_SMB_HS 0x00 /* host status */ 160 #define LPCIB_SMB_HS_BUSY (1 << 0) /* running a command */ 161 #define LPCIB_SMB_HS_INTR (1 << 1) /* command completed */ 162 #define LPCIB_SMB_HS_DEVERR (1 << 2) /* command error */ 163 #define LPCIB_SMB_HS_BUSERR (1 << 3) /* transaction collision */ 164 #define LPCIB_SMB_HS_FAILED (1 << 4) /* failed bus transaction */ 165 #define LPCIB_SMB_HS_SMBAL (1 << 5) /* SMBALERT# asserted */ 166 #define LPCIB_SMB_HS_INUSE (1 << 6) /* bus semaphore */ 167 #define LPCIB_SMB_HS_BDONE (1 << 7) /* byte received/transmitted */ 168 #define LPCIB_SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED\006SMBAL\007INUSE\010BDONE" 169 #define LPCIB_SMB_HC 0x02 /* host control */ 170 #define LPCIB_SMB_HC_INTREN (1 << 0) /* enable interrupts */ 171 #define LPCIB_SMB_HC_KILL (1 << 1) /* kill current transaction */ 172 #define LPCIB_SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */ 173 #define LPCIB_SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */ 174 #define LPCIB_SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */ 175 #define LPCIB_SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */ 176 #define LPCIB_SMB_HC_CMD_PCALL (4 << 2) /* PROCESS CALL command */ 177 #define LPCIB_SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */ 178 #define LPCIB_SMB_HC_CMD_I2CREAD (6 << 2) /* I2C READ command */ 179 #define LPCIB_SMB_HC_CMD_BLOCKP (7 << 2) /* BLOCK PROCESS command */ 180 #define LPCIB_SMB_HC_LASTB (1 << 5) /* last byte in block */ 181 #define LPCIB_SMB_HC_START (1 << 6) /* start transaction */ 182 #define LPCIB_SMB_HC_PECEN (1 << 7) /* enable PEC */ 183 #define LPCIB_SMB_HCMD 0x03 /* host command */ 184 #define LPCIB_SMB_TXSLVA 0x04 /* transmit slave address */ 185 #define LPCIB_SMB_TXSLVA_READ (1 << 0) /* read direction */ 186 #define LPCIB_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */ 187 #define LPCIB_SMB_HD0 0x05 /* host data 0 */ 188 #define LPCIB_SMB_HD1 0x06 /* host data 1 */ 189 #define LPCIB_SMB_HBDB 0x07 /* host block data byte */ 190 #define LPCIB_SMB_PEC 0x08 /* PEC data */ 191 #define LPCIB_SMB_RXSLVA 0x09 /* receive slave address */ 192 #define LPCIB_SMB_SD 0x0a /* receive slave data */ 193 #define LPCIB_SMB_SD_MSG0(x) ((x) & 0xff) /* data message byte 0 */ 194 #define LPCIB_SMB_SD_MSG1(x) ((x) >> 8) /* data message byte 1 */ 195 #define LPCIB_SMB_AS 0x0c /* auxiliary status */ 196 #define LPCIB_SMB_AS_CRCE (1 << 0) /* CRC error */ 197 #define LPCIB_SMB_AS_TCO (1 << 1) /* advanced TCO mode */ 198 #define LPCIB_SMB_AC 0x0d /* auxiliary control */ 199 #define LPCIB_SMB_AC_AAC (1 << 0) /* automatically append CRC */ 200 #define LPCIB_SMB_AC_E32B (1 << 1) /* enable 32-byte buffer */ 201 #define LPCIB_SMB_SMLPC 0x0e /* SMLink pin control */ 202 #define LPCIB_SMB_SMLPC_LINK0 (1 << 0) /* SMLINK0 pin state */ 203 #define LPCIB_SMB_SMLPC_LINK1 (1 << 1) /* SMLINK1 pin state */ 204 #define LPCIB_SMB_SMLPC_CLKC (1 << 2) /* SMLINK0 pin is untouched */ 205 #define LPCIB_SMB_SMBPC 0x0f /* SMBus pin control */ 206 #define LPCIB_SMB_SMBPC_CLK (1 << 0) /* SMBCLK pin state */ 207 #define LPCIB_SMB_SMBPC_DATA (1 << 1) /* SMBDATA pin state */ 208 #define LPCIB_SMB_SMBPC_CLKC (1 << 2) /* SMBCLK pin is untouched */ 209 #define LPCIB_SMB_SS 0x10 /* slave status */ 210 #define LPCIB_SMB_SS_HN (1 << 0) /* Host Notify command */ 211 #define LPCIB_SMB_SCMD 0x11 /* slave command */ 212 #define LPCIB_SMB_SCMD_INTREN (1 << 0) /* enable interrupts on HN */ 213 #define LPCIB_SMB_SCMD_WKEN (1 << 1) /* wake on HN */ 214 #define LPCIB_SMB_SCMD_SMBALDS (1 << 2) /* disable SMBALERT# intr */ 215 #define LPCIB_SMB_NDADDR 0x14 /* notify device address */ 216 #define LPCIB_SMB_NDADDR_ADDR(x) ((x) >> 1) /* 7-bit address */ 217 #define LPCIB_SMB_NDLOW 0x16 /* notify data low byte */ 218 #define LPCIB_SMB_NDHIGH 0x17 /* notify data high byte */ 219 220 /* ICH Chipset Configuration Registers (ICH6 and newer) */ 221 #define LPCIB_RCBA 0xf0 222 #define LPCIB_RCBA_EN 0x00000001 223 #define LPCIB_RCBA_SIZE 0x00004000 224 #define LPCIB_GCS_OFFSET 0x3410 225 #define LPCIB_GCS_NO_REBOOT 0x20 226 #define LPCIB_RCBA_HPTC 0x00003404 227 #define LPCIB_RCBA_HPTC_EN 0x00000080 228 #define LPCIB_RCBA_HPTC_WIN_MASK 0x00000003 229 #define LPCIB_RCBA_HPTC_0000 0x00000000 230 #define LPCIB_RCBA_HPTC_0000_BASE 0xfed00000 231 #define LPCIB_RCBA_HPTC_1000 0x00000001 232 #define LPCIB_RCBA_HPTC_1000_BASE 0xfed01000 233 #define LPCIB_RCBA_HPTC_2000 0x00000002 234 #define LPCIB_RCBA_HPTC_2000_BASE 0xfed02000 235 #define LPCIB_RCBA_HPTC_3000 0x00000003 236 #define LPCIB_RCBA_HPTC_3000_BASE 0xfed03000 237 238 /* 239 * System management TCO registers 240 * (offset from PMBASE) 241 */ 242 #define LPCIB_TCO_BASE 0x60 243 #define LPCIB_TCO_RLD (LPCIB_TCO_BASE+0x00) 244 #define LPCIB_TCO_TMR (LPCIB_TCO_BASE+0x01) 245 #define LPCIB_TCO_TMR2 (LPCIB_TCO_BASE+0x12) /* ICH6 and newer */ 246 # define LPCIB_TCO_TMR_MASK 0x3f 247 #define LPCIB_TCO_DAT_IN (LPCIB_TCO_BASE+0x02) 248 #define LPCIB_TCO_DAT_OUT (LPCIB_TCO_BASE+0x03) 249 #define LPCIB_TCO1_STS (LPCIB_TCO_BASE+0x04) 250 # define LPCIB_TCO1_STS_TIMEOUT 0x08 251 #define LPCIB_TCO2_STS (LPCIB_TCO_BASE+0x06) 252 # define LPCIB_TCO2_STS_BOOT_STS 0x04 253 # define LPCIB_TCO2_STS_SECONDS_TO_STS 0x02 254 #define LPCIB_TCO1_CNT (LPCIB_TCO_BASE+0x08) 255 # define LPCIB_TCO1_CNT_TCO_LOCK (1 << 12) 256 # define LPCIB_TCO1_CNT_TCO_TMR_HLT (1 << 11) 257 # define LPCIB_TCO1_CNT_SEND_NOW (1 << 10) 258 # define LPCIB_TCO1_CNT_NMI2SMI_EN (1 << 9) 259 # define LPCIB_TCO1_CNT_NMI_NOW (1 << 8) 260 #define LPCIB_TCO2_CNT (LPCIB_TCO_BASE+0x0a) 261 #define LPCIB_TCO_MESSAGE1 (LPCIB_TCO_BASE+0x0c) 262 #define LPCIB_TCO_MESSAGE2 (LPCIB_TCO_BASE+0x0d) 263 #define LPCIB_TCO_WDSTATUS (LPCIB_TCO_BASE+0x0e) 264 #define LPCIB_SW_IRQ_GEN (LPCIB_TCO_BASE+0x10) 265 266 /* 267 * TCO timer tick. ICH datasheets say: 268 * - The timer is clocked at approximately 0.6 seconds 269 * - 6 bit; values of 0-3 will be ignored and should not be attempted 270 */ 271 static __inline int 272 lpcib_tcotimer_tick_to_second(int ltick) 273 { 274 return ltick * 6 / 10; 275 } 276 277 static __inline int 278 lpcib_tcotimer_second_to_tick(int ltick) 279 { 280 return ltick * 10 / 6; 281 } 282 283 #define LPCIB_TCOTIMER_MIN_TICK 4 284 #define LPCIB_TCOTIMER2_MIN_TICK 2 285 #define LPCIB_TCOTIMER_MAX_TICK 0x3f /* 39 seconds max */ 286 #define LPCIB_TCOTIMER2_MAX_TICK 0x265 /* 613 seconds max */ 287 288 #endif /* _DEV_IC_I82801LPGREG_H_ */ 289
Indexes created Tue Sep 30 20:09:53 GMT 2025