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      1  1.9    andvar /*	$NetBSD: igsfbreg.h,v 1.9 2023/07/31 20:48:04 andvar Exp $ */
      2  1.1       uwe 
      3  1.1       uwe /*
      4  1.1       uwe  * Copyright (c) 2002 Valeriy E. Ushakov
      5  1.1       uwe  * All rights reserved.
      6  1.1       uwe  *
      7  1.1       uwe  * Redistribution and use in source and binary forms, with or without
      8  1.1       uwe  * modification, are permitted provided that the following conditions
      9  1.1       uwe  * are met:
     10  1.1       uwe  * 1. Redistributions of source code must retain the above copyright
     11  1.1       uwe  *    notice, this list of conditions and the following disclaimer.
     12  1.1       uwe  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.1       uwe  *    notice, this list of conditions and the following disclaimer in the
     14  1.1       uwe  *    documentation and/or other materials provided with the distribution.
     15  1.1       uwe  * 3. The name of the author may not be used to endorse or promote products
     16  1.1       uwe  *    derived from this software without specific prior written permission
     17  1.1       uwe  *
     18  1.1       uwe  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     19  1.1       uwe  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     20  1.1       uwe  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     21  1.1       uwe  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     22  1.1       uwe  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     23  1.1       uwe  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     24  1.1       uwe  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     25  1.1       uwe  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     26  1.1       uwe  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     27  1.1       uwe  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     28  1.1       uwe  */
     29  1.1       uwe 
     30  1.1       uwe /*
     31  1.2       uwe  * Integraphics Systems IGA 168x and CyberPro series.
     32  1.2       uwe  * Only tested on IGA 1682 in Krups JavaStation-NC.
     33  1.1       uwe  */
     34  1.1       uwe #ifndef _DEV_IC_IGSFBREG_H_
     35  1.1       uwe #define _DEV_IC_IGSFBREG_H_
     36  1.1       uwe 
     37  1.1       uwe /*
     38  1.1       uwe  * Magic address decoding for memory space accesses in CyberPro.
     39  1.1       uwe  */
     40  1.1       uwe #define IGS_MEM_MMIO_SELECT	0x00800000 /* memory mapped i/o */
     41  1.2       uwe #define IGS_MEM_BE_SELECT	0x00400000 /* endian select */
     42  1.1       uwe 
     43  1.1       uwe /*
     44  1.2       uwe  * Cursor sprite data in linear memory at IGS_EXT_SPRITE_DATA_{LO,HI}.
     45  1.2       uwe  * 64x64 pixels, 2bpp = 1Kb
     46  1.1       uwe  */
     47  1.2       uwe #define IGS_CURSOR_DATA_SIZE	1024
     48  1.1       uwe 
     49  1.1       uwe 
     50  1.1       uwe /*
     51  1.1       uwe  * Starting up the chip.
     52  1.1       uwe  */
     53  1.1       uwe 
     54  1.1       uwe /* Video Enable/Setup */
     55  1.1       uwe #define IGS_VDO			0x46e8
     56  1.1       uwe #define   IGS_VDO_ENABLE		0x08
     57  1.1       uwe #define   IGS_VDO_SETUP			0x10
     58  1.1       uwe 
     59  1.1       uwe /* Video Enable */
     60  1.1       uwe #define IGS_VSE			0x102
     61  1.1       uwe #define   IGS_VSE_ENABLE		0x01
     62  1.1       uwe 
     63  1.1       uwe 
     64  1.2       uwe /*
     65  1.3       uwe  * We map only 32 bytes of actual IGS registers at 0x3c0..0x3df.
     66  1.3       uwe  * This macro helps to define register names using their "absolute"
     67  1.3       uwe  * locations - it makes matching defines against docs easier.
     68  1.2       uwe  */
     69  1.3       uwe #define IGS_REG_BASE		0x3c0
     70  1.3       uwe #define IGS_REG_SIZE		0x020
     71  1.3       uwe #define IGS_REG_(x)		((x) - IGS_REG_BASE)
     72  1.2       uwe 
     73  1.2       uwe 
     74  1.2       uwe /*
     75  1.3       uwe  * Attribute controller.  Flip-flop reset by IGS_INPUT_STATUS1 at 0x3da.
     76  1.3       uwe  * We don't bother defining actual registers, we only use them once
     77  1.3       uwe  * during video initialization.
     78  1.3       uwe  */
     79  1.3       uwe #define IGS_ATTR_IDX		IGS_REG_(0x3c0)
     80  1.3       uwe #define IGS_ATTR_PORT		IGS_REG_(0x3c1)
     81  1.3       uwe 
     82  1.3       uwe 
     83  1.3       uwe /*
     84  1.3       uwe  * Misc output register.  We only use the _W register during video
     85  1.3       uwe  * initialization.
     86  1.3       uwe  */
     87  1.3       uwe #define IGS_MISC_OUTPUT_W	IGS_REG_(0x3c2)
     88  1.3       uwe #define IGS_MISC_OUTPUT_R	IGS_REG_(0x3cc)
     89  1.3       uwe 
     90  1.3       uwe 
     91  1.3       uwe /*
     92  1.3       uwe  * SEQUENCER.
     93  1.2       uwe  */
     94  1.3       uwe #define IGS_SEQ_IDX		IGS_REG_(0x3c4)
     95  1.3       uwe #define IGS_SEQ_PORT		IGS_REG_(0x3c5)
     96  1.3       uwe 
     97  1.3       uwe #define   IGS_SEQ_RESET			0x0
     98  1.3       uwe #define     IGS_SEQ_RESET_ASYNC			0x01
     99  1.3       uwe #define     IGS_SEQ_RESET_SYNC			0x02
    100  1.3       uwe 
    101  1.3       uwe 
    102  1.3       uwe /* IGS_EXT_SPRITE_CTL/IGS_EXT_SPRITE_DAC_PEL (3cf/56[2]) == 0 */
    103  1.3       uwe #define IGS_PEL_MASK		IGS_REG_(0x3c6)
    104  1.3       uwe 
    105  1.3       uwe /* IGS_EXT_SPRITE_CTL/IGS_EXT_SPRITE_DAC_PEL 3cf/56[2] == 1 */
    106  1.3       uwe #define IGS_DAC_CMD		IGS_REG_(0x3c6)
    107  1.2       uwe 
    108  1.1       uwe 
    109  1.1       uwe /*
    110  1.1       uwe  * Palette Read/Write: write palette index to the index port.
    111  1.1       uwe  * Read/write R/G/B in three consecutive accesses to data port.
    112  1.1       uwe  * After third access to data the index is autoincremented and you can
    113  1.1       uwe  * proceed with reading/writing data port for the next entry.
    114  1.6     perry  *
    115  1.2       uwe  * When IGS_EXT_SPRITE_DAC_PEL bit in sprite control is set, these
    116  1.2       uwe  * registers are used to access sprite (i.e. cursor) 2-color palette.
    117  1.2       uwe  * (NB: apparently, in this mode index autoincrement doesn't work).
    118  1.1       uwe  */
    119  1.2       uwe #define IGS_DAC_PEL_READ_IDX	IGS_REG_(0x3c7)
    120  1.2       uwe #define IGS_DAC_PEL_WRITE_IDX	IGS_REG_(0x3c8)
    121  1.2       uwe #define IGS_DAC_PEL_DATA	IGS_REG_(0x3c9)
    122  1.1       uwe 
    123  1.1       uwe 
    124  1.1       uwe /*
    125  1.3       uwe  * GRAPHICS CONTROLLER registers.
    126  1.3       uwe  */
    127  1.3       uwe #define IGS_GRFX_IDX		IGS_REG_(0x3ce)
    128  1.3       uwe #define IGS_GRFX_PORT		IGS_REG_(0x3cf)
    129  1.3       uwe 
    130  1.3       uwe 
    131  1.3       uwe /*
    132  1.3       uwe  * EXTENDED registers.
    133  1.1       uwe  */
    134  1.2       uwe #define IGS_EXT_IDX		IGS_REG_(0x3ce)
    135  1.2       uwe #define IGS_EXT_PORT		IGS_REG_(0x3cf)
    136  1.1       uwe 
    137  1.3       uwe /* [3..0] -> [19..16] of start addr if IGS_EXT_START_ADDR_ON is set */
    138  1.3       uwe #define   IGS_EXT_START_ADDR		0x10
    139  1.3       uwe #define     IGS_EXT_START_ADDR_ON		0x10
    140  1.3       uwe 
    141  1.3       uwe /* overflow 10th bits for severl crtc registers; interlaced mode select */
    142  1.3       uwe #define   IGS_EXT_VOVFL			0x11
    143  1.3       uwe #define     IGS_EXT_VOVFL_INTERLACED		0x20
    144  1.3       uwe 
    145  1.3       uwe #define   IGS_EXT_IRQ_CTL		0x12
    146  1.3       uwe #define     IGS_EXT_IRQ_ENABLE			0x01
    147  1.3       uwe 
    148  1.3       uwe 
    149  1.1       uwe 
    150  1.1       uwe /*
    151  1.1       uwe  * Sync Control.
    152  1.2       uwe  * Two-bit combinations for h/v:
    153  1.1       uwe  *     00 - normal, 01 - force 0, 1x - force 1
    154  1.1       uwe  */
    155  1.1       uwe #define   IGS_EXT_SYNC_CTL		0x16
    156  1.1       uwe #define     IGS_EXT_SYNC_H0			0x01
    157  1.1       uwe #define     IGS_EXT_SYNC_H1			0x02
    158  1.1       uwe #define     IGS_EXT_SYNC_V0			0x04
    159  1.1       uwe #define     IGS_EXT_SYNC_V1			0x08
    160  1.1       uwe 
    161  1.1       uwe /*
    162  1.1       uwe  * For PCI just use normal BAR config.
    163  1.1       uwe  */
    164  1.1       uwe #define   IGS_EXT_BUS_CTL		0x30
    165  1.1       uwe #define     IGS_EXT_BUS_CTL_LINSIZE_SHIFT	0
    166  1.1       uwe #define     IGS_EXT_BUS_CTL_LINSIZE_MASK	0x03
    167  1.1       uwe #define     IGS_EXT_BUS_CTL_LINSIZE(x) \
    168  1.1       uwe     (((x) >> IGS_EXT_BUS_CTL_LINSIZE_SHIFT) & IGS_EXT_BUS_CTL_LINSIZE_MASK)
    169  1.1       uwe 
    170  1.1       uwe /*
    171  1.1       uwe  * COPREN   - enable direct access to coprocessor registers
    172  1.2       uwe  * COPASELB - select IGS_COP_BASE_B for COP address
    173  1.1       uwe  */
    174  1.1       uwe #define   IGS_EXT_BIU_MISC_CTL		0x33
    175  1.1       uwe #define     IGS_EXT_BIU_LINEAREN		0x01
    176  1.1       uwe #define     IGS_EXT_BIU_LIN2MEM			0x02
    177  1.1       uwe #define     IGS_EXT_BIU_COPREN			0x04
    178  1.1       uwe #define     IGS_EXT_BIU_COPASELB		0x08
    179  1.1       uwe #define     IGS_EXT_BIU_SEGON			0x10
    180  1.1       uwe #define     IGS_EXT_BIU_SEG2MEM			0x20
    181  1.1       uwe 
    182  1.1       uwe /*
    183  1.2       uwe  * Linear Address registers
    184  1.9    andvar  *   PCI: don't write directly, just use normal PCI configuration
    185  1.1       uwe  *   ISA: only bits [23..20] are programmable, the rest MBZ
    186  1.1       uwe  */
    187  1.1       uwe #define   IGS_EXT_LINA_LO		0x34	/* [3..0] -> [23..20] */
    188  1.1       uwe #define   IGS_EXT_LINA_HI		0x35	/* [7..0] -> [31..24] */
    189  1.1       uwe 
    190  1.2       uwe /* Hardware cursor on-screen location and hot spot */
    191  1.1       uwe #define   IGS_EXT_SPRITE_HSTART_LO	0x50
    192  1.1       uwe #define   IGS_EXT_SPRITE_HSTART_HI	0x51	/* bits [2..0] */
    193  1.1       uwe #define   IGS_EXT_SPRITE_HPRESET	0x52	/* bits [5..0] */
    194  1.1       uwe 
    195  1.1       uwe #define   IGS_EXT_SPRITE_VSTART_LO	0x53
    196  1.1       uwe #define   IGS_EXT_SPRITE_VSTART_HI	0x54	/* bits [2..0] */
    197  1.1       uwe #define   IGS_EXT_SPRITE_VPRESET	0x55	/* bits [5..0] */
    198  1.1       uwe 
    199  1.2       uwe /* Hardware cursor control */
    200  1.1       uwe #define   IGS_EXT_SPRITE_CTL		0x56
    201  1.1       uwe #define     IGS_EXT_SPRITE_VISIBLE		0x01
    202  1.1       uwe #define     IGS_EXT_SPRITE_64x64		0x02
    203  1.2       uwe #define     IGS_EXT_SPRITE_DAC_PEL		0x04
    204  1.2       uwe 	  /* bits unrelated to sprite control */
    205  1.2       uwe #define     IGS_EXT_COP_RESET			0x08
    206  1.1       uwe 
    207  1.3       uwe /* Extended graphics mode */
    208  1.3       uwe #define   IGS_EXT_GRFX_MODE		0x57
    209  1.3       uwe #define     IGS_EXT_GRFX_MODE_EXT		0x01
    210  1.3       uwe 
    211  1.1       uwe /* Overscan R/G/B registers */
    212  1.1       uwe #define   IGS_EXT_OVERSCAN_RED		0x58
    213  1.1       uwe #define   IGS_EXT_OVERSCAN_GREEN	0x59
    214  1.1       uwe #define   IGS_EXT_OVERSCAN_BLUE		0x5a
    215  1.1       uwe 
    216  1.3       uwe /* Memory controller */
    217  1.3       uwe #define   IGS_EXT_MEM_CTL0		0x70
    218  1.3       uwe #define   IGS_EXT_MEM_CTL1		0x71
    219  1.3       uwe #define   IGS_EXT_MEM_CTL2		0x72
    220  1.3       uwe 
    221  1.3       uwe /*
    222  1.3       uwe  * SEQ miscellaneous: number of SL between CCLK - controls visual depth.
    223  1.3       uwe  * These values are for MODE256 == 1, SRMODE = 1 in GRFX/5 mode register.
    224  1.3       uwe  */
    225  1.3       uwe #define   IGS_EXT_SEQ_MISC		0x77
    226  1.3       uwe #define     IGS_EXT_SEQ_IBM_STD			0
    227  1.3       uwe #define     IGS_EXT_SEQ_8BPP			1 /* 256 indexed */
    228  1.3       uwe #define     IGS_EXT_SEQ_16BPP			2 /* HiColor 16bpp, 5-6-5 */
    229  1.3       uwe #define     IGS_EXT_SEQ_32BPP			3 /* TrueColor 32bpp */
    230  1.3       uwe #define     IGS_EXT_SEQ_24BPP			4 /* TrueColor 24bpp */
    231  1.3       uwe #define     IGS_EXT_SEQ_15BPP			6 /* HiColor 16bpp, 5-5-5 */
    232  1.3       uwe 
    233  1.2       uwe /* Hardware cursor data location in linear memory */
    234  1.1       uwe #define   IGS_EXT_SPRITE_DATA_LO	0x7e
    235  1.1       uwe #define   IGS_EXT_SPRITE_DATA_HI	0x7f	/* bits [3..0] */
    236  1.3       uwe 
    237  1.3       uwe 
    238  1.3       uwe #define   IGS_EXT_VCLK0			0xb0 /* mult */
    239  1.3       uwe #define   IGS_EXT_VCLK1			0xb1 /*  div */
    240  1.3       uwe #define   IGS_EXT_MCLK0			0xb2 /* mult */
    241  1.3       uwe #define   IGS_EXT_MCLK1			0xb3 /*  div */
    242  1.3       uwe 
    243  1.3       uwe 
    244  1.3       uwe /* ----8<----  end of IGS_EXT registers  ----8<---- */
    245  1.3       uwe 
    246  1.3       uwe 
    247  1.3       uwe 
    248  1.3       uwe /*
    249  1.3       uwe  * CRTC can be at 0x3b4/0x3b5 (mono) or 0x3d4/0x3d5 (color)
    250  1.3       uwe  * controlled by bit 0 in misc output register (r=0x3cc/w=0x3c2).
    251  1.3       uwe  * We forcibly init it to color.
    252  1.3       uwe  */
    253  1.3       uwe #define IGS_CRTC_IDX		IGS_REG_(0x3d4)
    254  1.3       uwe #define IGS_CRTC_PORT		IGS_REG_(0x3d5)
    255  1.3       uwe 
    256  1.3       uwe /*
    257  1.3       uwe  * Reading this register resets flip-flop at 0x3c0 (attribute
    258  1.3       uwe  * controller) to address register.
    259  1.3       uwe  */
    260  1.3       uwe #define IGS_INPUT_STATUS1	IGS_REG_(0x3da)
    261  1.1       uwe 
    262  1.1       uwe 
    263  1.2       uwe 
    264  1.1       uwe /*********************************************************************
    265  1.2       uwe  *		       IGS Graphic Coprocessor
    266  1.2       uwe  */
    267  1.2       uwe 
    268  1.2       uwe /*
    269  1.2       uwe  * Coprocessor registers location in I/O space.
    270  1.2       uwe  * Controlled by COPASELB bit in IGS_EXT_BIU_MISC_CTL.
    271  1.2       uwe  */
    272  1.4       uwe #define IGS_COP_BASE_A	0xaf000		/* COPASELB == 0 */
    273  1.4       uwe #define IGS_COP_BASE_B	0xbf000		/* COPASELB == 1 */
    274  1.2       uwe #define IGS_COP_SIZE	0x00400
    275  1.2       uwe 
    276  1.2       uwe 
    277  1.2       uwe /*
    278  1.2       uwe  * NB: Loaded width values should be 1 less than the actual width!
    279  1.1       uwe  */
    280  1.1       uwe 
    281  1.2       uwe /*
    282  1.2       uwe  * Coprocessor control.
    283  1.2       uwe  */
    284  1.2       uwe #define IGS_COP_CTL_REG		0x011
    285  1.2       uwe #define   IGS_COP_CTL_HBRDYZ		0x01
    286  1.2       uwe #define   IGS_COP_CTL_HFEMPTZ		0x02
    287  1.2       uwe #define   IGS_COP_CTL_CMDFF		0x04
    288  1.2       uwe #define   IGS_COP_CTL_SOP		0x08 /* rw */
    289  1.2       uwe #define   IGS_COP_CTL_OPS		0x10
    290  1.2       uwe #define   IGS_COP_CTL_TER		0x20 /* rw */
    291  1.2       uwe #define   IGS_COP_CTL_HBACKZ		0x40
    292  1.2       uwe #define   IGS_COP_CTL_BUSY		0x80
    293  1.2       uwe 
    294  1.2       uwe 
    295  1.2       uwe /*
    296  1.2       uwe  * Source(s) and destination widths.
    297  1.2       uwe  * 16 bit registers.  Only bits [11..0] are used.
    298  1.2       uwe  */
    299  1.2       uwe #define IGS_COP_SRC_MAP_WIDTH_REG  0x018
    300  1.2       uwe #define IGS_COP_SRC2_MAP_WIDTH_REG 0x118
    301  1.2       uwe #define IGS_COP_DST_MAP_WIDTH_REG  0x218
    302  1.2       uwe 
    303  1.2       uwe 
    304  1.2       uwe /*
    305  1.2       uwe  * Bitmap depth.
    306  1.2       uwe  */
    307  1.2       uwe #define IGS_COP_MAP_FMT_REG	0x01c
    308  1.2       uwe #define   IGS_COP_MAP_8BPP		0x00
    309  1.2       uwe #define   IGS_COP_MAP_16BPP		0x01
    310  1.2       uwe #define   IGS_COP_MAP_24BPP		0x02
    311  1.2       uwe #define   IGS_COP_MAP_32BPP		0x03
    312  1.2       uwe 
    313  1.2       uwe 
    314  1.6     perry /*
    315  1.2       uwe  * Binary operations are defined below.  S - source, D - destination,
    316  1.2       uwe  * N - not; a - and, o - or, x - xor.
    317  1.2       uwe  *
    318  1.2       uwe  * For ternary operations, foreground mix function is one of 256
    319  1.2       uwe  * ternary raster operations defined by Win32 API; background mix is
    320  1.2       uwe  * ignored.
    321  1.2       uwe  */
    322  1.2       uwe #define IGS_COP_FG_MIX_REG	0x048
    323  1.2       uwe #define IGS_COP_BG_MIX_REG	0x049
    324  1.2       uwe 
    325  1.2       uwe #define   IGS_COP_MIX_0			0x0
    326  1.2       uwe #define   IGS_COP_MIX_SaD		0x1
    327  1.2       uwe #define   IGS_COP_MIX_SaND		0x2
    328  1.2       uwe #define   IGS_COP_MIX_S			0x3
    329  1.2       uwe #define   IGS_COP_MIX_NSaD		0x4
    330  1.2       uwe #define   IGS_COP_MIX_D			0x5
    331  1.2       uwe #define   IGS_COP_MIX_SxD		0x6
    332  1.2       uwe #define   IGS_COP_MIX_SoD		0x7
    333  1.2       uwe #define   IGS_COP_MIX_NSaND		0x8
    334  1.2       uwe #define   IGS_COP_MIX_SxND		0x9
    335  1.2       uwe #define   IGS_COP_MIX_ND		0xa
    336  1.2       uwe #define   IGS_COP_MIX_SoND		0xb
    337  1.2       uwe #define   IGS_COP_MIX_NS		0xc
    338  1.2       uwe #define   IGS_COP_MIX_NSoD		0xd
    339  1.2       uwe #define   IGS_COP_MIX_NSoND		0xe
    340  1.2       uwe #define   IGS_COP_MIX_1			0xf
    341  1.2       uwe 
    342  1.2       uwe 
    343  1.2       uwe /*
    344  1.2       uwe  * Foreground/background colours (24 bit).
    345  1.2       uwe  * Selected by bits in IGS_COP_PIXEL_OP_3_REG.
    346  1.2       uwe  */
    347  1.2       uwe #define IGS_COP_FG_REG		0x058
    348  1.2       uwe #define IGS_COP_BG_REG		0x05C
    349  1.2       uwe 
    350  1.2       uwe 
    351  1.2       uwe /*
    352  1.5       wiz  * Horizontal/vertical dimensions of pixel blit function.
    353  1.2       uwe  * 16 bit registers.  Only [11..0] are used.
    354  1.2       uwe  */
    355  1.2       uwe #define IGS_COP_WIDTH_REG	0x060
    356  1.2       uwe #define IGS_COP_HEIGHT_REG	0x062
    357  1.2       uwe 
    358  1.2       uwe 
    359  1.2       uwe /*
    360  1.2       uwe  * Only bits [21..0] are used.
    361  1.2       uwe  */
    362  1.2       uwe #define IGS_COP_SRC_BASE_REG	0x070 /* only for 24bpp Src Color Tiling */
    363  1.2       uwe #define IGS_COP_SRC_START_REG	0x170
    364  1.2       uwe #define IGS_COP_SRC2_START_REG	0x174
    365  1.2       uwe #define IGS_COP_DST_START_REG	0x178
    366  1.2       uwe 
    367  1.2       uwe /*
    368  1.2       uwe  * Destination phase angle for 24bpp.
    369  1.2       uwe  */
    370  1.2       uwe #define IGS_COP_DST_X_PHASE_REG	0x078
    371  1.2       uwe #define   IGS_COP_DST_X_PHASE_MASK	0x07
    372  1.2       uwe 
    373  1.2       uwe 
    374  1.2       uwe /*
    375  1.2       uwe  * Pixel operation: Direction and draw mode.
    376  1.2       uwe  * When an octant bit is set, that axis is traversed backwards.
    377  1.2       uwe  */
    378  1.2       uwe #define IGS_COP_PIXEL_OP_0_REG	0x07c
    379  1.2       uwe 
    380  1.2       uwe #define   IGS_COP_OCTANT_Y_NEG		0x02 /* 0: top down, 1: bottom up */
    381  1.2       uwe #define   IGS_COP_OCTANT_X_NEG		0x04 /* 0: l2r, 1: r2l */
    382  1.2       uwe 
    383  1.2       uwe #define   IGS_COP_DRAW_ALL		0x00
    384  1.2       uwe #define   IGS_COP_DRAW_FIRST_NULL	0x10
    385  1.2       uwe #define   IGS_COP_DRAW_LAST_NULL	0x20
    386  1.2       uwe 
    387  1.2       uwe 
    388  1.2       uwe /*
    389  1.2       uwe  * Pixel operation: Pattern operation.
    390  1.2       uwe  */
    391  1.2       uwe #define IGS_COP_PIXEL_OP_1_REG	0x07d
    392  1.2       uwe 
    393  1.2       uwe #define   IGS_COP_PPM_TEXT		0x10
    394  1.2       uwe #define   IGS_COP_PPM_TILE		0x20
    395  1.2       uwe #define   IGS_COP_PPM_LINE		0x30
    396  1.2       uwe #define   IGS_COP_PPM_TRANSPARENT	0x40 /* "or" with one of the above */
    397  1.6     perry 
    398  1.2       uwe #define   IGS_COP_PPM_FIXED_FG		0x80
    399  1.2       uwe #define   IGS_COP_PPM_SRC_COLOR_TILE	0x90
    400  1.2       uwe 
    401  1.2       uwe 
    402  1.2       uwe /*
    403  1.2       uwe  * Pixel operation: Host CPU access (host blit) to graphics engine.
    404  1.2       uwe  */
    405  1.2       uwe #define IGS_COP_PIXEL_OP_2_REG	0x07e
    406  1.2       uwe #define   IGS_COP_HBLTR			0x01 /* enable read from engine */
    407  1.2       uwe #define   IGS_COP_HBLTW			0x02 /* enable write to engine  */
    408  1.2       uwe 
    409  1.2       uwe 
    410  1.2       uwe /*
    411  1.2       uwe  * Pixel operation: Operation function of graphic engine.
    412  1.2       uwe  */
    413  1.2       uwe #define IGS_COP_PIXEL_OP_3_REG	0x07f
    414  1.2       uwe #define   IGS_COP_OP_STROKE		0x04 /* short stroke */
    415  1.2       uwe #define   IGS_COP_OP_LINE		0x05 /* bresenham line draw */
    416  1.2       uwe #define   IGS_COP_OP_PXBLT		0x08 /* pixel blit */
    417  1.2       uwe #define   IGS_COP_OP_PXBLT_INV		0x09 /* invert pixel blit */
    418  1.2       uwe #define   IGS_COP_OP_PXBLT_3		0x0a /* ternary pixel blit */
    419  1.1       uwe 
    420  1.2       uwe /* select fg/bg source: 0 - fg/bg color reg, 1 - src1 map */
    421  1.2       uwe #define   IGS_COP_OP_FG_FROM_SRC	0x20
    422  1.2       uwe #define   IGS_COP_OP_BG_FROM_SRC	0x80
    423  1.1       uwe 
    424  1.8  macallan #define IGS_CLOCK_REF	14318 /*24576*/	/* KHz */
    425  1.8  macallan 
    426  1.8  macallan #define IGS_SCALE(p)	((p) ? (2 * (p)) : 1)
    427  1.8  macallan 
    428  1.8  macallan #define IGS_CLOCK(m,n,p) \
    429  1.8  macallan 	((IGS_CLOCK_REF * ((m) + 1)) / (((n) + 1) * IGS_SCALE(p)))
    430  1.8  macallan 
    431  1.8  macallan #define IGS_MAX_CLOCK	260000
    432  1.8  macallan 
    433  1.8  macallan #define IGS_MIN_VCO	115000
    434  1.8  macallan 
    435  1.1       uwe #endif /* _DEV_IC_IGSFBREG_H_ */
    436