igsfbreg.h revision 1.1
1 /* $NetBSD: igsfbreg.h,v 1.1 2002/03/30 19:48:56 uwe Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Valeriy E. Ushakov 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Integraphics Systems IGA 1682 and (untested) CyberPro 2k. 32 */ 33 #ifndef _DEV_IC_IGSFBREG_H_ 34 #define _DEV_IC_IGSFBREG_H_ 35 36 /* 37 * Magic address decoding for memory space accesses in CyberPro. 38 */ 39 #define IGS_MEM_MMIO_SELECT 0x00800000 /* memory mapped i/o */ 40 #define IGS_MEM_BE_SELECT 0x00400000 /* endian */ 41 42 /* 43 * Registers in I/O space (could be memory-mapped i/o). 44 */ 45 #define IGS_IO_SIZE 0x400 46 #define IGS_COP_SIZE 0x400 47 48 /* 49 * Cursor sprite data: 64x64 pixels, 2bpp = 1Kb. 50 */ 51 #define IGS_CURSOR_DATA_SIZE 0x0400 52 53 54 /* 55 * Starting up the chip. 56 */ 57 58 /* Video Enable/Setup */ 59 #define IGS_VDO 0x46e8 60 #define IGS_VDO_ENABLE 0x08 61 #define IGS_VDO_SETUP 0x10 62 63 /* Video Enable */ 64 #define IGS_VSE 0x102 65 #define IGS_VSE_ENABLE 0x01 66 67 68 69 /* 70 * Palette Read/Write: write palette index to the index port. 71 * Read/write R/G/B in three consecutive accesses to data port. 72 * After third access to data the index is autoincremented and you can 73 * proceed with reading/writing data port for the next entry. 74 * 75 * When MRS2 bit in sprite control is set, these registers are used to 76 * access sprite (i.e. cursor) 2-color palette. (NB: apparently, in 77 * this mode index autoincrement doesn't work). 78 */ 79 #define IGS_DAC_PEL_READ_IDX 0x3c7 80 #define IGS_DAC_PEL_WRITE_IDX 0x3c8 81 #define IGS_DAC_PEL_DATA 0x3c9 82 83 84 /* 85 * Extended Registers. Indexed access via IGS_EXT_PORT. 86 */ 87 #define IGS_EXT_IDX 0x3ce 88 89 90 /* 91 * Sync Control. 92 * Two bit combinations for h/v: 93 * 00 - normal, 01 - force 0, 1x - force 1 94 */ 95 #define IGS_EXT_SYNC_CTL 0x16 96 #define IGS_EXT_SYNC_H0 0x01 97 #define IGS_EXT_SYNC_H1 0x02 98 #define IGS_EXT_SYNC_V0 0x04 99 #define IGS_EXT_SYNC_V1 0x08 100 101 /* 102 * For PCI just use normal BAR config. 103 */ 104 #define IGS_EXT_BUS_CTL 0x30 105 #define IGS_EXT_BUS_CTL_LINSIZE_SHIFT 0 106 #define IGS_EXT_BUS_CTL_LINSIZE_MASK 0x03 107 #define IGS_EXT_BUS_CTL_LINSIZE(x) \ 108 (((x) >> IGS_EXT_BUS_CTL_LINSIZE_SHIFT) & IGS_EXT_BUS_CTL_LINSIZE_MASK) 109 110 /* 111 * COPREN - enable direct access to coprocessor registers 112 * COPASELB - COP address select 0xbfc00..0xbffff 113 */ 114 #define IGS_EXT_BIU_MISC_CTL 0x33 115 #define IGS_EXT_BIU_LINEAREN 0x01 116 #define IGS_EXT_BIU_LIN2MEM 0x02 117 #define IGS_EXT_BIU_COPREN 0x04 118 #define IGS_EXT_BIU_COPASELB 0x08 119 #define IGS_EXT_BIU_SEGON 0x10 120 #define IGS_EXT_BIU_SEG2MEM 0x20 121 122 /* 123 * Linear Address register 124 * PCI: don't write directly, just use nomral PCI configuration 125 * ISA: only bits [23..20] are programmable, the rest MBZ 126 */ 127 #define IGS_EXT_LINA_LO 0x34 /* [3..0] -> [23..20] */ 128 #define IGS_EXT_LINA_HI 0x35 /* [7..0] -> [31..24] */ 129 130 /* Hardware cursor (sprite) */ 131 #define IGS_EXT_SPRITE_HSTART_LO 0x50 132 #define IGS_EXT_SPRITE_HSTART_HI 0x51 /* bits [2..0] */ 133 #define IGS_EXT_SPRITE_HPRESET 0x52 /* bits [5..0] */ 134 135 #define IGS_EXT_SPRITE_VSTART_LO 0x53 136 #define IGS_EXT_SPRITE_VSTART_HI 0x54 /* bits [2..0] */ 137 #define IGS_EXT_SPRITE_VPRESET 0x55 /* bits [5..0] */ 138 139 #define IGS_EXT_SPRITE_CTL 0x56 140 #define IGS_EXT_SPRITE_VISIBLE 0x01 141 #define IGS_EXT_SPRITE_64x64 0x02 142 #define IGS_EXT_SPRITE_SELECT 0x04 143 144 /* Overscan R/G/B registers */ 145 #define IGS_EXT_OVERSCAN_RED 0x58 146 #define IGS_EXT_OVERSCAN_GREEN 0x59 147 #define IGS_EXT_OVERSCAN_BLUE 0x5a 148 149 /* Hardware cursor (sprite) data location */ 150 #define IGS_EXT_SPRITE_DATA_LO 0x7e 151 #define IGS_EXT_SPRITE_DATA_HI 0x7f /* bits [3..0] */ 152 153 154 /********************************************************************* 155 * Access sugar for indexed registers 156 */ 157 158 static __inline__ u_int8_t 159 igs_idx_read(bus_space_tag_t, bus_space_handle_t, u_int, u_int8_t); 160 161 static __inline__ u_int8_t 162 igs_idx_read(t, h, idxport, idx) 163 bus_space_tag_t t; 164 bus_space_handle_t h; 165 u_int idxport; 166 u_int8_t idx; 167 { 168 bus_space_write_1(t, h, idxport, idx); 169 return (bus_space_read_1(t, h, idxport + 1)); 170 } 171 172 static __inline__ void 173 igs_idx_write(bus_space_tag_t, bus_space_handle_t, u_int, u_int8_t, u_int8_t); 174 175 static __inline__ void 176 igs_idx_write(t, h, idxport, idx, val) 177 bus_space_tag_t t; 178 bus_space_handle_t h; 179 u_int idxport; 180 u_int8_t idx, val; 181 { 182 bus_space_write_1(t, h, idxport, idx); 183 bus_space_write_1(t, h, idxport + 1, val); 184 } 185 186 /* more sugar for extended registers */ 187 #define igs_ext_read(t,h,x) (igs_idx_read((t),(h),IGS_EXT_IDX,(x))) 188 #define igs_ext_write(t,h,x,v) (igs_idx_write((t),(h),IGS_EXT_IDX,(x),(v))) 189 190 #endif /* _DEV_IC_IGSFBREG_H_ */ 191
Indexes created Mon Sep 29 21:09:56 GMT 2025