iha.c revision 1.3.2.2
1 1.3.2.2 nathanw /* $NetBSD: iha.c,v 1.3.2.2 2001/06/21 20:02:35 nathanw Exp $ */ 2 1.3.2.2 nathanw /* 3 1.3.2.2 nathanw * Initio INI-9xxxU/UW SCSI Device Driver 4 1.3.2.2 nathanw * 5 1.3.2.2 nathanw * Copyright (c) 2000 Ken Westerback 6 1.3.2.2 nathanw * All rights reserved. 7 1.3.2.2 nathanw * 8 1.3.2.2 nathanw * Redistribution and use in source and binary forms, with or without 9 1.3.2.2 nathanw * modification, are permitted provided that the following conditions 10 1.3.2.2 nathanw * are met: 11 1.3.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 12 1.3.2.2 nathanw * notice, this list of conditions and the following disclaimer, 13 1.3.2.2 nathanw * without modification, immediately at the beginning of the file. 14 1.3.2.2 nathanw * 2. The name of the author may not be used to endorse or promote products 15 1.3.2.2 nathanw * derived from this software without specific prior written permission. 16 1.3.2.2 nathanw * 17 1.3.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 1.3.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 1.3.2.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 1.3.2.2 nathanw * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 21 1.3.2.2 nathanw * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 1.3.2.2 nathanw * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 1.3.2.2 nathanw * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 1.3.2.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 1.3.2.2 nathanw * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 1.3.2.2 nathanw * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 1.3.2.2 nathanw * THE POSSIBILITY OF SUCH DAMAGE. 28 1.3.2.2 nathanw * 29 1.3.2.2 nathanw *------------------------------------------------------------------------- 30 1.3.2.2 nathanw * 31 1.3.2.2 nathanw * Ported from i91u.c, provided by Initio Corporation, which credits: 32 1.3.2.2 nathanw * 33 1.3.2.2 nathanw * Device driver for the INI-9XXXU/UW or INIC-940/950 PCI SCSI Controller. 34 1.3.2.2 nathanw * 35 1.3.2.2 nathanw * FreeBSD 36 1.3.2.2 nathanw * 37 1.3.2.2 nathanw * Written for 386bsd and FreeBSD by 38 1.3.2.2 nathanw * Winston Hung <winstonh (at) initio.com> 39 1.3.2.2 nathanw * 40 1.3.2.2 nathanw * Copyright (c) 1997-99 Initio Corp. All rights reserved. 41 1.3.2.2 nathanw * 42 1.3.2.2 nathanw *------------------------------------------------------------------------- 43 1.3.2.2 nathanw */ 44 1.3.2.2 nathanw 45 1.3.2.2 nathanw /* 46 1.3.2.2 nathanw * Ported to NetBSD by Izumi Tsutsui <tsutsui (at) ceres.dti.ne.jp> from OpenBSD: 47 1.3.2.2 nathanw * $OpenBSD: iha.c,v 1.3 2001/02/20 00:47:33 krw Exp $ 48 1.3.2.2 nathanw */ 49 1.3.2.2 nathanw 50 1.3.2.2 nathanw #include <sys/param.h> 51 1.3.2.2 nathanw #include <sys/systm.h> 52 1.3.2.2 nathanw #include <sys/kernel.h> 53 1.3.2.2 nathanw #include <sys/buf.h> 54 1.3.2.2 nathanw #include <sys/device.h> 55 1.3.2.2 nathanw #include <sys/malloc.h> 56 1.3.2.2 nathanw 57 1.3.2.2 nathanw #include <uvm/uvm_extern.h> 58 1.3.2.2 nathanw 59 1.3.2.2 nathanw #include <machine/bus.h> 60 1.3.2.2 nathanw #include <machine/intr.h> 61 1.3.2.2 nathanw 62 1.3.2.2 nathanw #include <dev/scsipi/scsi_all.h> 63 1.3.2.2 nathanw #include <dev/scsipi/scsipi_all.h> 64 1.3.2.2 nathanw #include <dev/scsipi/scsiconf.h> 65 1.3.2.2 nathanw #include <dev/scsipi/scsi_message.h> 66 1.3.2.2 nathanw 67 1.3.2.2 nathanw #include <dev/ic/ihareg.h> 68 1.3.2.2 nathanw #include <dev/ic/ihavar.h> 69 1.3.2.2 nathanw 70 1.3.2.2 nathanw /* 71 1.3.2.2 nathanw * SCSI Rate Table, indexed by FLAG_SCSI_RATE field of 72 1.3.2.2 nathanw * tcs flags. 73 1.3.2.2 nathanw */ 74 1.3.2.2 nathanw static u_int8_t tul_rate_tbl[8] = { 75 1.3.2.2 nathanw /* fast 20 */ 76 1.3.2.2 nathanw /* nanosecond divide by 4 */ 77 1.3.2.2 nathanw 12, /* 50ns, 20M */ 78 1.3.2.2 nathanw 18, /* 75ns, 13.3M */ 79 1.3.2.2 nathanw 25, /* 100ns, 10M */ 80 1.3.2.2 nathanw 31, /* 125ns, 8M */ 81 1.3.2.2 nathanw 37, /* 150ns, 6.6M */ 82 1.3.2.2 nathanw 43, /* 175ns, 5.7M */ 83 1.3.2.2 nathanw 50, /* 200ns, 5M */ 84 1.3.2.2 nathanw 62 /* 250ns, 4M */ 85 1.3.2.2 nathanw }; 86 1.3.2.2 nathanw 87 1.3.2.2 nathanw static u_int16_t eeprom_default[EEPROM_SIZE] = { 88 1.3.2.2 nathanw /* -- Header ------------------------------------ */ 89 1.3.2.2 nathanw /* signature */ 90 1.3.2.2 nathanw EEP_SIGNATURE, 91 1.3.2.2 nathanw /* size, revision */ 92 1.3.2.2 nathanw EEP_WORD(EEPROM_SIZE * 2, 0x01), 93 1.3.2.2 nathanw /* -- Host Adapter Structure -------------------- */ 94 1.3.2.2 nathanw /* model */ 95 1.3.2.2 nathanw 0x0095, 96 1.3.2.2 nathanw /* model info, number of channel */ 97 1.3.2.2 nathanw EEP_WORD(0x00, 1), 98 1.3.2.2 nathanw /* BIOS config */ 99 1.3.2.2 nathanw EEP_BIOSCFG_DEFAULT, 100 1.3.2.2 nathanw /* host adapter config */ 101 1.3.2.2 nathanw 0, 102 1.3.2.2 nathanw 103 1.3.2.2 nathanw /* -- eeprom_adapter[0] ------------------------------- */ 104 1.3.2.2 nathanw /* ID, adapter config 1 */ 105 1.3.2.2 nathanw EEP_WORD(7, CFG_DEFAULT), 106 1.3.2.2 nathanw /* adapter config 2, number of targets */ 107 1.3.2.2 nathanw EEP_WORD(0x00, 8), 108 1.3.2.2 nathanw /* target flags */ 109 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 110 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 111 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 112 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 113 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 114 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 115 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 116 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 117 1.3.2.2 nathanw 118 1.3.2.2 nathanw /* -- eeprom_adapter[1] ------------------------------- */ 119 1.3.2.2 nathanw /* ID, adapter config 1 */ 120 1.3.2.2 nathanw EEP_WORD(7, CFG_DEFAULT), 121 1.3.2.2 nathanw /* adapter config 2, number of targets */ 122 1.3.2.2 nathanw EEP_WORD(0x00, 8), 123 1.3.2.2 nathanw /* target flags */ 124 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 125 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 126 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 127 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 128 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 129 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 130 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 131 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 132 1.3.2.2 nathanw /* reserved[5] */ 133 1.3.2.2 nathanw 0, 0, 0, 0, 0, 134 1.3.2.2 nathanw /* checksum */ 135 1.3.2.2 nathanw 0 136 1.3.2.2 nathanw }; 137 1.3.2.2 nathanw 138 1.3.2.2 nathanw static u_int8_t tul_data_over_run(struct iha_scsi_req_q *); 139 1.3.2.2 nathanw 140 1.3.2.2 nathanw static int tul_push_sense_request(struct iha_softc *, struct iha_scsi_req_q *); 141 1.3.2.2 nathanw static void tul_timeout(void *); 142 1.3.2.2 nathanw static int tul_alloc_sglist(struct iha_softc *); 143 1.3.2.2 nathanw 144 1.3.2.2 nathanw static void tul_read_eeprom(struct iha_softc *, struct iha_eeprom *); 145 1.3.2.2 nathanw static void tul_se2_update_all(struct iha_softc *); 146 1.3.2.2 nathanw static int tul_se2_rd_all(struct iha_softc *, u_int16_t *); 147 1.3.2.2 nathanw static void tul_se2_wr(struct iha_softc *, int, u_int16_t); 148 1.3.2.2 nathanw static void tul_se2_instr(struct iha_softc *, int); 149 1.3.2.2 nathanw static u_int16_t tul_se2_rd(struct iha_softc *, int); 150 1.3.2.2 nathanw 151 1.3.2.2 nathanw static void tul_reset_scsi_bus(struct iha_softc *); 152 1.3.2.2 nathanw static void tul_reset_chip(struct iha_softc *); 153 1.3.2.2 nathanw static void tul_reset_dma(struct iha_softc *); 154 1.3.2.2 nathanw 155 1.3.2.2 nathanw static void tul_reset_tcs(struct tcs *, u_int8_t); 156 1.3.2.2 nathanw 157 1.3.2.2 nathanw static void tul_done_scb(struct iha_softc *, struct iha_scsi_req_q *); 158 1.3.2.2 nathanw static void tul_exec_scb(struct iha_softc *, struct iha_scsi_req_q *); 159 1.3.2.2 nathanw 160 1.3.2.2 nathanw static void tul_main(struct iha_softc *); 161 1.3.2.2 nathanw static void tul_scsi(struct iha_softc *); 162 1.3.2.2 nathanw 163 1.3.2.2 nathanw static int tul_wait(struct iha_softc *, u_int8_t); 164 1.3.2.2 nathanw 165 1.3.2.2 nathanw static __inline void tul_mark_busy_scb(struct iha_scsi_req_q *); 166 1.3.2.2 nathanw 167 1.3.2.2 nathanw static void tul_append_free_scb(struct iha_softc *, struct iha_scsi_req_q *); 168 1.3.2.2 nathanw static void tul_append_done_scb(struct iha_softc *, struct iha_scsi_req_q *, 169 1.3.2.2 nathanw u_int8_t); 170 1.3.2.2 nathanw static __inline struct iha_scsi_req_q *tul_pop_done_scb(struct iha_softc *); 171 1.3.2.2 nathanw 172 1.3.2.2 nathanw static __inline void tul_append_pend_scb(struct iha_softc *, 173 1.3.2.2 nathanw struct iha_scsi_req_q *); 174 1.3.2.2 nathanw static __inline void tul_push_pend_scb(struct iha_softc *, 175 1.3.2.2 nathanw struct iha_scsi_req_q *); 176 1.3.2.2 nathanw static __inline void tul_del_pend_scb(struct iha_softc *, 177 1.3.2.2 nathanw struct iha_scsi_req_q *); 178 1.3.2.2 nathanw static struct iha_scsi_req_q *tul_find_pend_scb(struct iha_softc *); 179 1.3.2.2 nathanw 180 1.3.2.2 nathanw static void tul_sync_done(struct iha_softc *); 181 1.3.2.2 nathanw static void tul_wdtr_done(struct iha_softc *); 182 1.3.2.2 nathanw static void tul_bad_seq(struct iha_softc *); 183 1.3.2.2 nathanw 184 1.3.2.2 nathanw static int tul_next_state(struct iha_softc *); 185 1.3.2.2 nathanw static int tul_state_1(struct iha_softc *); 186 1.3.2.2 nathanw static int tul_state_2(struct iha_softc *); 187 1.3.2.2 nathanw static int tul_state_3(struct iha_softc *); 188 1.3.2.2 nathanw static int tul_state_4(struct iha_softc *); 189 1.3.2.2 nathanw static int tul_state_5(struct iha_softc *); 190 1.3.2.2 nathanw static int tul_state_6(struct iha_softc *); 191 1.3.2.2 nathanw static int tul_state_8(struct iha_softc *); 192 1.3.2.2 nathanw 193 1.3.2.2 nathanw static void tul_set_ssig(struct iha_softc *, u_int8_t, u_int8_t); 194 1.3.2.2 nathanw 195 1.3.2.2 nathanw static int tul_xpad_in(struct iha_softc *); 196 1.3.2.2 nathanw static int tul_xpad_out(struct iha_softc *); 197 1.3.2.2 nathanw 198 1.3.2.2 nathanw static int tul_xfer_data(struct iha_softc *, struct iha_scsi_req_q *, 199 1.3.2.2 nathanw int direction); 200 1.3.2.2 nathanw 201 1.3.2.2 nathanw static int tul_status_msg(struct iha_softc *); 202 1.3.2.2 nathanw 203 1.3.2.2 nathanw static int tul_msgin(struct iha_softc *); 204 1.3.2.2 nathanw static int tul_msgin_sync(struct iha_softc *); 205 1.3.2.2 nathanw static int tul_msgin_extend(struct iha_softc *); 206 1.3.2.2 nathanw static int tul_msgin_ignore_wid_resid(struct iha_softc *); 207 1.3.2.2 nathanw 208 1.3.2.2 nathanw static int tul_msgout(struct iha_softc *, u_int8_t); 209 1.3.2.2 nathanw static void tul_msgout_abort(struct iha_softc *, u_int8_t); 210 1.3.2.2 nathanw static int tul_msgout_reject(struct iha_softc *); 211 1.3.2.2 nathanw static int tul_msgout_sync(struct iha_softc *); 212 1.3.2.2 nathanw static int tul_msgout_wide(struct iha_softc *); 213 1.3.2.2 nathanw 214 1.3.2.2 nathanw static void tul_select(struct iha_softc *, struct iha_scsi_req_q *, u_int8_t); 215 1.3.2.2 nathanw 216 1.3.2.2 nathanw static void tul_busfree(struct iha_softc *); 217 1.3.2.2 nathanw static int tul_resel(struct iha_softc *); 218 1.3.2.2 nathanw 219 1.3.2.2 nathanw static void tul_abort_xs(struct iha_softc *, struct scsipi_xfer *, u_int8_t); 220 1.3.2.2 nathanw 221 1.3.2.2 nathanw static void iha_minphys(struct buf *); 222 1.3.2.2 nathanw void iha_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 223 1.3.2.2 nathanw void *arg); 224 1.3.2.2 nathanw 225 1.3.2.2 nathanw /* 226 1.3.2.2 nathanw * iha_intr - the interrupt service routine for the iha driver 227 1.3.2.2 nathanw */ 228 1.3.2.2 nathanw int 229 1.3.2.2 nathanw iha_intr(arg) 230 1.3.2.2 nathanw void *arg; 231 1.3.2.2 nathanw { 232 1.3.2.2 nathanw bus_space_tag_t iot; 233 1.3.2.2 nathanw bus_space_handle_t ioh; 234 1.3.2.2 nathanw struct iha_softc *sc; 235 1.3.2.2 nathanw int s; 236 1.3.2.2 nathanw 237 1.3.2.2 nathanw sc = (struct iha_softc *)arg; 238 1.3.2.2 nathanw iot = sc->sc_iot; 239 1.3.2.2 nathanw ioh = sc->sc_ioh; 240 1.3.2.2 nathanw 241 1.3.2.2 nathanw if ((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 242 1.3.2.2 nathanw return (0); 243 1.3.2.2 nathanw 244 1.3.2.2 nathanw s = splbio(); /* XXX - Or are interrupts off when ISR's are called? */ 245 1.3.2.2 nathanw 246 1.3.2.2 nathanw if (sc->sc_semaph != SEMAPH_IN_MAIN) { 247 1.3.2.2 nathanw /* XXX - need these inside a splbio()/splx()? */ 248 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 249 1.3.2.2 nathanw sc->sc_semaph = SEMAPH_IN_MAIN; 250 1.3.2.2 nathanw 251 1.3.2.2 nathanw tul_main(sc); 252 1.3.2.2 nathanw 253 1.3.2.2 nathanw sc->sc_semaph = ~SEMAPH_IN_MAIN; 254 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 255 1.3.2.2 nathanw } 256 1.3.2.2 nathanw 257 1.3.2.2 nathanw splx(s); 258 1.3.2.2 nathanw 259 1.3.2.2 nathanw return (1); 260 1.3.2.2 nathanw } 261 1.3.2.2 nathanw 262 1.3.2.2 nathanw void 263 1.3.2.2 nathanw iha_scsipi_request(chan, req, arg) 264 1.3.2.2 nathanw struct scsipi_channel *chan; 265 1.3.2.2 nathanw scsipi_adapter_req_t req; 266 1.3.2.2 nathanw void *arg; 267 1.3.2.2 nathanw { 268 1.3.2.2 nathanw struct scsipi_xfer *xs; 269 1.3.2.2 nathanw struct scsipi_periph *periph; 270 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 271 1.3.2.2 nathanw struct iha_softc *sc; 272 1.3.2.2 nathanw int error, flags, s; 273 1.3.2.2 nathanw 274 1.3.2.2 nathanw sc = (struct iha_softc *)chan->chan_adapter->adapt_dev; 275 1.3.2.2 nathanw 276 1.3.2.2 nathanw switch (req) { 277 1.3.2.2 nathanw case ADAPTER_REQ_RUN_XFER: 278 1.3.2.2 nathanw xs = arg; 279 1.3.2.2 nathanw periph = xs->xs_periph; 280 1.3.2.2 nathanw flags = xs->xs_control; 281 1.3.2.2 nathanw 282 1.3.2.2 nathanw if (xs->cmdlen > sizeof(struct scsi_generic) || 283 1.3.2.2 nathanw periph->periph_target >= IHA_MAX_TARGETS) { 284 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 285 1.3.2.2 nathanw return; 286 1.3.2.2 nathanw } 287 1.3.2.2 nathanw 288 1.3.2.2 nathanw s = splbio(); 289 1.3.2.2 nathanw scb = TAILQ_FIRST(&sc->sc_freescb); 290 1.3.2.2 nathanw if (scb != NULL) { 291 1.3.2.2 nathanw scb->status = STATUS_RENT; 292 1.3.2.2 nathanw TAILQ_REMOVE(&sc->sc_freescb, scb, chain); 293 1.3.2.2 nathanw } 294 1.3.2.2 nathanw #ifdef DIAGNOSTIC 295 1.3.2.2 nathanw else { 296 1.3.2.2 nathanw scsipi_printaddr(periph); 297 1.3.2.2 nathanw printf("unable to allocate scb\n"); 298 1.3.2.2 nathanw panic("iha_scsipi_request"); 299 1.3.2.2 nathanw } 300 1.3.2.2 nathanw #endif 301 1.3.2.2 nathanw splx(s); 302 1.3.2.2 nathanw 303 1.3.2.2 nathanw scb->target = periph->periph_target; 304 1.3.2.2 nathanw scb->lun = periph->periph_lun; 305 1.3.2.2 nathanw scb->tcs = &sc->sc_tcs[scb->target]; 306 1.3.2.2 nathanw scb->flags = xs->xs_control; /* XXX */ 307 1.3.2.2 nathanw scb->scb_id = MSG_IDENTIFY(periph->periph_lun, 308 1.3.2.2 nathanw (xs->xs_control & XS_CTL_REQSENSE) == 0); 309 1.3.2.2 nathanw 310 1.3.2.2 nathanw scb->xs = xs; 311 1.3.2.2 nathanw scb->timeout = xs->timeout; 312 1.3.2.2 nathanw scb->cmdlen = xs->cmdlen; 313 1.3.2.2 nathanw memcpy(&scb->cmd, xs->cmd, xs->cmdlen); 314 1.3.2.2 nathanw 315 1.3.2.2 nathanw scb->buflen = xs->datalen; 316 1.3.2.2 nathanw 317 1.3.2.2 nathanw if (scb->buflen > 0) { 318 1.3.2.2 nathanw error = bus_dmamap_load(sc->sc_dmat, scb->dmap, 319 1.3.2.2 nathanw xs->data, scb->buflen, NULL, 320 1.3.2.2 nathanw (xs->xs_control & XS_CTL_NOSLEEP) ? 321 1.3.2.2 nathanw BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 322 1.3.2.2 nathanw 323 1.3.2.2 nathanw if (error) { 324 1.3.2.2 nathanw printf("%s: error %d loading dma map\n", 325 1.3.2.2 nathanw sc->sc_dev.dv_xname, error); 326 1.3.2.2 nathanw tul_append_free_scb(sc, scb); 327 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 328 1.3.2.2 nathanw scsipi_done(xs); 329 1.3.2.2 nathanw return; 330 1.3.2.2 nathanw } 331 1.3.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, scb->dmap, 332 1.3.2.2 nathanw 0, scb->dmap->dm_mapsize, 333 1.3.2.2 nathanw (xs->xs_control & XS_CTL_DATA_IN) ? 334 1.3.2.2 nathanw BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 335 1.3.2.2 nathanw } 336 1.3.2.2 nathanw 337 1.3.2.2 nathanw tul_exec_scb(sc, scb); 338 1.3.2.2 nathanw return; 339 1.3.2.2 nathanw 340 1.3.2.2 nathanw case ADAPTER_REQ_GROW_RESOURCES: 341 1.3.2.2 nathanw return; /* XXX */ 342 1.3.2.2 nathanw 343 1.3.2.2 nathanw case ADAPTER_REQ_SET_XFER_MODE: 344 1.3.2.2 nathanw return; /* XXX */ 345 1.3.2.2 nathanw } 346 1.3.2.2 nathanw } 347 1.3.2.2 nathanw 348 1.3.2.2 nathanw void 349 1.3.2.2 nathanw iha_attach(sc) 350 1.3.2.2 nathanw struct iha_softc *sc; 351 1.3.2.2 nathanw { 352 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 353 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 354 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 355 1.3.2.2 nathanw struct iha_eeprom eeprom; 356 1.3.2.2 nathanw struct eeprom_adapter *conf; 357 1.3.2.2 nathanw int i, error, reg; 358 1.3.2.2 nathanw 359 1.3.2.2 nathanw tul_read_eeprom(sc, &eeprom); 360 1.3.2.2 nathanw 361 1.3.2.2 nathanw conf = &eeprom.adapter[0]; 362 1.3.2.2 nathanw 363 1.3.2.2 nathanw /* 364 1.3.2.2 nathanw * fill in the rest of the IHA_SOFTC fields 365 1.3.2.2 nathanw */ 366 1.3.2.2 nathanw sc->sc_id = CFG_ID(conf->config1); 367 1.3.2.2 nathanw sc->sc_semaph = ~SEMAPH_IN_MAIN; 368 1.3.2.2 nathanw sc->sc_status0 = 0; 369 1.3.2.2 nathanw sc->sc_actscb = NULL; 370 1.3.2.2 nathanw 371 1.3.2.2 nathanw TAILQ_INIT(&sc->sc_freescb); 372 1.3.2.2 nathanw TAILQ_INIT(&sc->sc_pendscb); 373 1.3.2.2 nathanw TAILQ_INIT(&sc->sc_donescb); 374 1.3.2.2 nathanw error = tul_alloc_sglist(sc); 375 1.3.2.2 nathanw if (error != 0) { 376 1.3.2.2 nathanw printf(": cannot allocate sglist\n"); 377 1.3.2.2 nathanw return; 378 1.3.2.2 nathanw } 379 1.3.2.2 nathanw 380 1.3.2.2 nathanw sc->sc_scb = malloc(sizeof(struct iha_scsi_req_q) * IHA_MAX_SCB, 381 1.3.2.2 nathanw M_DEVBUF, M_NOWAIT); 382 1.3.2.2 nathanw if (sc->sc_scb == NULL) { 383 1.3.2.2 nathanw printf(": cannot allocate SCB\n"); 384 1.3.2.2 nathanw return; 385 1.3.2.2 nathanw } 386 1.3.2.2 nathanw bzero(sc->sc_scb, sizeof(struct iha_scsi_req_q) * IHA_MAX_SCB); 387 1.3.2.2 nathanw 388 1.3.2.2 nathanw for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) { 389 1.3.2.2 nathanw scb->scb_tagid = i; 390 1.3.2.2 nathanw scb->sgoffset = IHA_SG_SIZE * i; 391 1.3.2.2 nathanw scb->sglist = &sc->sc_sglist[i].sg_element[0]; 392 1.3.2.2 nathanw scb->sg_addr = 393 1.3.2.2 nathanw sc->sc_dmamap->dm_segs[0].ds_addr + scb->sgoffset; 394 1.3.2.2 nathanw 395 1.3.2.2 nathanw error = bus_dmamap_create(sc->sc_dmat, 396 1.3.2.2 nathanw (IHA_MAX_SG_ENTRIES - 1) * PAGE_SIZE, IHA_MAX_SG_ENTRIES, 397 1.3.2.2 nathanw (IHA_MAX_SG_ENTRIES - 1) * PAGE_SIZE, 0, 398 1.3.2.2 nathanw BUS_DMA_NOWAIT, &scb->dmap); 399 1.3.2.2 nathanw 400 1.3.2.2 nathanw if (error != 0) { 401 1.3.2.2 nathanw printf(": couldn't create SCB DMA map, error = %d\n", 402 1.3.2.2 nathanw error); 403 1.3.2.2 nathanw return; 404 1.3.2.2 nathanw } 405 1.3.2.2 nathanw TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 406 1.3.2.2 nathanw } 407 1.3.2.2 nathanw 408 1.3.2.2 nathanw /* Mask all the interrupts */ 409 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 410 1.3.2.2 nathanw 411 1.3.2.2 nathanw /* Stop any I/O and reset the scsi module */ 412 1.3.2.2 nathanw tul_reset_dma(sc); 413 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSMOD); 414 1.3.2.2 nathanw 415 1.3.2.2 nathanw /* Program HBA's SCSI ID */ 416 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SID, sc->sc_id << 4); 417 1.3.2.2 nathanw 418 1.3.2.2 nathanw /* 419 1.3.2.2 nathanw * Configure the channel as requested by the NVRAM settings read 420 1.3.2.2 nathanw * by tul_read_eeprom() above. 421 1.3.2.2 nathanw */ 422 1.3.2.2 nathanw 423 1.3.2.2 nathanw sc->sc_sconf1 = SCONFIG0DEFAULT; 424 1.3.2.2 nathanw if ((conf->config1 & CFG_EN_PAR) != 0) 425 1.3.2.2 nathanw sc->sc_sconf1 |= SPCHK; 426 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, sc->sc_sconf1); 427 1.3.2.2 nathanw 428 1.3.2.2 nathanw /* set selection time out 250 ms */ 429 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_STIMO, STIMO_250MS); 430 1.3.2.2 nathanw 431 1.3.2.2 nathanw /* Enable desired SCSI termination configuration read from eeprom */ 432 1.3.2.2 nathanw reg = 0; 433 1.3.2.2 nathanw if (conf->config1 & CFG_ACT_TERM1) 434 1.3.2.2 nathanw reg |= ENTMW; 435 1.3.2.2 nathanw if (conf->config1 & CFG_ACT_TERM2) 436 1.3.2.2 nathanw reg |= ENTM; 437 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_DCTRL0, reg); 438 1.3.2.2 nathanw 439 1.3.2.2 nathanw reg = bus_space_read_1(iot, ioh, TUL_GCTRL1) & ~ATDEN; 440 1.3.2.2 nathanw if (conf->config1 & CFG_AUTO_TERM) 441 1.3.2.2 nathanw reg |= ATDEN; 442 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_GCTRL1, reg); 443 1.3.2.2 nathanw 444 1.3.2.2 nathanw for (i = 0; i < IHA_MAX_TARGETS / 2; i++) { 445 1.3.2.2 nathanw sc->sc_tcs[i * 2 ].flags = EEP_LBYTE(conf->tflags[i]); 446 1.3.2.2 nathanw sc->sc_tcs[i * 2 + 1].flags = EEP_HBYTE(conf->tflags[i]); 447 1.3.2.2 nathanw tul_reset_tcs(&sc->sc_tcs[i * 2 ], sc->sc_sconf1); 448 1.3.2.2 nathanw tul_reset_tcs(&sc->sc_tcs[i * 2 + 1], sc->sc_sconf1); 449 1.3.2.2 nathanw } 450 1.3.2.2 nathanw 451 1.3.2.2 nathanw tul_reset_chip(sc); 452 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SIEN, ALL_INTERRUPTS); 453 1.3.2.2 nathanw 454 1.3.2.2 nathanw /* 455 1.3.2.2 nathanw * fill in the adapter. 456 1.3.2.2 nathanw */ 457 1.3.2.2 nathanw sc->sc_adapter.adapt_dev = &sc->sc_dev; 458 1.3.2.2 nathanw sc->sc_adapter.adapt_nchannels = 1; 459 1.3.2.2 nathanw sc->sc_adapter.adapt_openings = IHA_MAX_SCB; 460 1.3.2.2 nathanw sc->sc_adapter.adapt_max_periph = IHA_MAX_SCB; 461 1.3.2.2 nathanw sc->sc_adapter.adapt_ioctl = NULL; 462 1.3.2.2 nathanw sc->sc_adapter.adapt_minphys = iha_minphys; 463 1.3.2.2 nathanw sc->sc_adapter.adapt_request = iha_scsipi_request; 464 1.3.2.2 nathanw 465 1.3.2.2 nathanw /* 466 1.3.2.2 nathanw * fill in the channel. 467 1.3.2.2 nathanw */ 468 1.3.2.2 nathanw sc->sc_channel.chan_adapter = &sc->sc_adapter; 469 1.3.2.2 nathanw sc->sc_channel.chan_bustype = &scsi_bustype; 470 1.3.2.2 nathanw sc->sc_channel.chan_channel = 0; 471 1.3.2.2 nathanw sc->sc_channel.chan_ntargets = CFG_TARGET(conf->config2); 472 1.3.2.2 nathanw sc->sc_channel.chan_nluns = 8; 473 1.3.2.2 nathanw sc->sc_channel.chan_id = sc->sc_id; 474 1.3.2.2 nathanw 475 1.3.2.2 nathanw /* 476 1.3.2.2 nathanw * Now try to attach all the sub devices. 477 1.3.2.2 nathanw */ 478 1.3.2.2 nathanw config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 479 1.3.2.2 nathanw } 480 1.3.2.2 nathanw 481 1.3.2.2 nathanw /* 482 1.3.2.2 nathanw * iha_minphys - reduce bp->b_bcount to something less than 483 1.3.2.2 nathanw * or equal to the largest I/O possible through 484 1.3.2.2 nathanw * the adapter. Called from higher layers 485 1.3.2.2 nathanw * via sc->sc_adapter.scsi_minphys. 486 1.3.2.2 nathanw */ 487 1.3.2.2 nathanw static void 488 1.3.2.2 nathanw iha_minphys(bp) 489 1.3.2.2 nathanw struct buf *bp; 490 1.3.2.2 nathanw { 491 1.3.2.2 nathanw if (bp->b_bcount > ((IHA_MAX_SG_ENTRIES - 1) * PAGE_SIZE)) 492 1.3.2.2 nathanw bp->b_bcount = ((IHA_MAX_SG_ENTRIES - 1) * PAGE_SIZE); 493 1.3.2.2 nathanw 494 1.3.2.2 nathanw minphys(bp); 495 1.3.2.2 nathanw } 496 1.3.2.2 nathanw 497 1.3.2.2 nathanw /* 498 1.3.2.2 nathanw * tul_reset_dma - abort any active DMA xfer, reset tulip FIFO. 499 1.3.2.2 nathanw */ 500 1.3.2.2 nathanw static void 501 1.3.2.2 nathanw tul_reset_dma(sc) 502 1.3.2.2 nathanw struct iha_softc *sc; 503 1.3.2.2 nathanw { 504 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 505 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 506 1.3.2.2 nathanw 507 1.3.2.2 nathanw if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 508 1.3.2.2 nathanw /* if DMA xfer is pending, abort DMA xfer */ 509 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 510 1.3.2.2 nathanw /* wait Abort DMA xfer done */ 511 1.3.2.2 nathanw while ((bus_space_read_1(iot, ioh, TUL_ISTUS0) & DABT) == 0) 512 1.3.2.2 nathanw ; 513 1.3.2.2 nathanw } 514 1.3.2.2 nathanw 515 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 516 1.3.2.2 nathanw } 517 1.3.2.2 nathanw 518 1.3.2.2 nathanw /* 519 1.3.2.2 nathanw * tul_append_free_scb - append the supplied SCB to the tail of the 520 1.3.2.2 nathanw * sc_freescb queue after clearing and resetting 521 1.3.2.2 nathanw * everything possible. 522 1.3.2.2 nathanw */ 523 1.3.2.2 nathanw static void 524 1.3.2.2 nathanw tul_append_free_scb(sc, scb) 525 1.3.2.2 nathanw struct iha_softc *sc; 526 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 527 1.3.2.2 nathanw { 528 1.3.2.2 nathanw int s; 529 1.3.2.2 nathanw 530 1.3.2.2 nathanw s = splbio(); 531 1.3.2.2 nathanw 532 1.3.2.2 nathanw if (scb == sc->sc_actscb) 533 1.3.2.2 nathanw sc->sc_actscb = NULL; 534 1.3.2.2 nathanw 535 1.3.2.2 nathanw scb->status = STATUS_QUEUED; 536 1.3.2.2 nathanw scb->ha_stat = HOST_OK; 537 1.3.2.2 nathanw scb->ta_stat = SCSI_OK; 538 1.3.2.2 nathanw 539 1.3.2.2 nathanw scb->nextstat = 0; 540 1.3.2.2 nathanw scb->sg_index = 0; 541 1.3.2.2 nathanw scb->sg_max = 0; 542 1.3.2.2 nathanw scb->flags = 0; 543 1.3.2.2 nathanw scb->target = 0; 544 1.3.2.2 nathanw scb->lun = 0; 545 1.3.2.2 nathanw scb->buflen = 0; 546 1.3.2.2 nathanw scb->sg_size = 0; 547 1.3.2.2 nathanw scb->cmdlen = 0; 548 1.3.2.2 nathanw scb->scb_id = 0; 549 1.3.2.2 nathanw scb->scb_tagmsg = 0; 550 1.3.2.2 nathanw scb->timeout = 0; 551 1.3.2.2 nathanw scb->bufaddr = 0; 552 1.3.2.2 nathanw 553 1.3.2.2 nathanw scb->xs = NULL; 554 1.3.2.2 nathanw scb->tcs = NULL; 555 1.3.2.2 nathanw 556 1.3.2.2 nathanw bzero(scb->cmd, sizeof(scb->cmd)); 557 1.3.2.2 nathanw bzero(scb->sglist, sizeof(scb->sglist)); 558 1.3.2.2 nathanw 559 1.3.2.2 nathanw /* 560 1.3.2.2 nathanw * scb_tagid, sg_addr, sglist 561 1.3.2.2 nathanw * SCB_SensePtr are set at initialization 562 1.3.2.2 nathanw * and never change 563 1.3.2.2 nathanw */ 564 1.3.2.2 nathanw 565 1.3.2.2 nathanw TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 566 1.3.2.2 nathanw 567 1.3.2.2 nathanw splx(s); 568 1.3.2.2 nathanw } 569 1.3.2.2 nathanw 570 1.3.2.2 nathanw static __inline void 571 1.3.2.2 nathanw tul_append_pend_scb(sc, scb) 572 1.3.2.2 nathanw struct iha_softc *sc; 573 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 574 1.3.2.2 nathanw { 575 1.3.2.2 nathanw /* ASSUMPTION: only called within a splbio()/splx() pair */ 576 1.3.2.2 nathanw 577 1.3.2.2 nathanw if (scb == sc->sc_actscb) 578 1.3.2.2 nathanw sc->sc_actscb = NULL; 579 1.3.2.2 nathanw 580 1.3.2.2 nathanw scb->status = STATUS_QUEUED; 581 1.3.2.2 nathanw 582 1.3.2.2 nathanw TAILQ_INSERT_TAIL(&sc->sc_pendscb, scb, chain); 583 1.3.2.2 nathanw } 584 1.3.2.2 nathanw 585 1.3.2.2 nathanw static __inline void 586 1.3.2.2 nathanw tul_push_pend_scb(sc, scb) 587 1.3.2.2 nathanw struct iha_softc *sc; 588 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 589 1.3.2.2 nathanw { 590 1.3.2.2 nathanw int s; 591 1.3.2.2 nathanw 592 1.3.2.2 nathanw s = splbio(); 593 1.3.2.2 nathanw 594 1.3.2.2 nathanw if (scb == sc->sc_actscb) 595 1.3.2.2 nathanw sc->sc_actscb = NULL; 596 1.3.2.2 nathanw 597 1.3.2.2 nathanw scb->status = STATUS_QUEUED; 598 1.3.2.2 nathanw 599 1.3.2.2 nathanw TAILQ_INSERT_HEAD(&sc->sc_pendscb, scb, chain); 600 1.3.2.2 nathanw 601 1.3.2.2 nathanw splx(s); 602 1.3.2.2 nathanw } 603 1.3.2.2 nathanw 604 1.3.2.2 nathanw /* 605 1.3.2.2 nathanw * tul_find_pend_scb - scan the pending queue for a SCB that can be 606 1.3.2.2 nathanw * processed immediately. Return NULL if none found 607 1.3.2.2 nathanw * and a pointer to the SCB if one is found. If there 608 1.3.2.2 nathanw * is an active SCB, return NULL! 609 1.3.2.2 nathanw */ 610 1.3.2.2 nathanw static struct iha_scsi_req_q * 611 1.3.2.2 nathanw tul_find_pend_scb(sc) 612 1.3.2.2 nathanw struct iha_softc *sc; 613 1.3.2.2 nathanw { 614 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 615 1.3.2.2 nathanw struct tcs *tcs; 616 1.3.2.2 nathanw int s; 617 1.3.2.2 nathanw 618 1.3.2.2 nathanw s = splbio(); 619 1.3.2.2 nathanw 620 1.3.2.2 nathanw if (sc->sc_actscb != NULL) 621 1.3.2.2 nathanw scb = NULL; 622 1.3.2.2 nathanw 623 1.3.2.2 nathanw else 624 1.3.2.2 nathanw TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) { 625 1.3.2.2 nathanw if ((scb->flags & XS_CTL_RESET) != 0) 626 1.3.2.2 nathanw /* ALWAYS willing to reset a device */ 627 1.3.2.2 nathanw break; 628 1.3.2.2 nathanw 629 1.3.2.2 nathanw tcs = scb->tcs; 630 1.3.2.2 nathanw 631 1.3.2.2 nathanw if ((scb->scb_tagmsg) != 0) { 632 1.3.2.2 nathanw /* 633 1.3.2.2 nathanw * A Tagged I/O. OK to start If no 634 1.3.2.2 nathanw * non-tagged I/O is active on the same 635 1.3.2.2 nathanw * target 636 1.3.2.2 nathanw */ 637 1.3.2.2 nathanw if (tcs->ntagscb == NULL) 638 1.3.2.2 nathanw break; 639 1.3.2.2 nathanw 640 1.3.2.2 nathanw } else if (scb->cmd[0] == REQUEST_SENSE) { 641 1.3.2.2 nathanw /* 642 1.3.2.2 nathanw * OK to do a non-tagged request sense 643 1.3.2.2 nathanw * even if a non-tagged I/O has been 644 1.3.2.2 nathanw * started, 'cuz we don't allow any 645 1.3.2.2 nathanw * disconnect during a request sense op 646 1.3.2.2 nathanw */ 647 1.3.2.2 nathanw break; 648 1.3.2.2 nathanw 649 1.3.2.2 nathanw } else if (tcs->tagcnt == 0) { 650 1.3.2.2 nathanw /* 651 1.3.2.2 nathanw * No tagged I/O active on this target, 652 1.3.2.2 nathanw * ok to start a non-tagged one if one 653 1.3.2.2 nathanw * is not already active 654 1.3.2.2 nathanw */ 655 1.3.2.2 nathanw if (tcs->ntagscb == NULL) 656 1.3.2.2 nathanw break; 657 1.3.2.2 nathanw } 658 1.3.2.2 nathanw } 659 1.3.2.2 nathanw 660 1.3.2.2 nathanw splx(s); 661 1.3.2.2 nathanw 662 1.3.2.2 nathanw return (scb); 663 1.3.2.2 nathanw } 664 1.3.2.2 nathanw 665 1.3.2.2 nathanw /* 666 1.3.2.2 nathanw * tul_del_pend_scb - remove scb from sc_pendscb 667 1.3.2.2 nathanw */ 668 1.3.2.2 nathanw static __inline void 669 1.3.2.2 nathanw tul_del_pend_scb(sc, scb) 670 1.3.2.2 nathanw struct iha_softc *sc; 671 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 672 1.3.2.2 nathanw { 673 1.3.2.2 nathanw int s; 674 1.3.2.2 nathanw 675 1.3.2.2 nathanw s = splbio(); 676 1.3.2.2 nathanw 677 1.3.2.2 nathanw TAILQ_REMOVE(&sc->sc_pendscb, scb, chain); 678 1.3.2.2 nathanw 679 1.3.2.2 nathanw splx(s); 680 1.3.2.2 nathanw } 681 1.3.2.2 nathanw 682 1.3.2.2 nathanw static __inline void 683 1.3.2.2 nathanw tul_mark_busy_scb(scb) 684 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 685 1.3.2.2 nathanw { 686 1.3.2.2 nathanw int s; 687 1.3.2.2 nathanw 688 1.3.2.2 nathanw s = splbio(); 689 1.3.2.2 nathanw 690 1.3.2.2 nathanw scb->status = STATUS_BUSY; 691 1.3.2.2 nathanw 692 1.3.2.2 nathanw if (scb->scb_tagmsg == 0) 693 1.3.2.2 nathanw scb->tcs->ntagscb = scb; 694 1.3.2.2 nathanw else 695 1.3.2.2 nathanw scb->tcs->tagcnt++; 696 1.3.2.2 nathanw 697 1.3.2.2 nathanw splx(s); 698 1.3.2.2 nathanw } 699 1.3.2.2 nathanw 700 1.3.2.2 nathanw static void 701 1.3.2.2 nathanw tul_append_done_scb(sc, scb, hastat) 702 1.3.2.2 nathanw struct iha_softc *sc; 703 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 704 1.3.2.2 nathanw u_int8_t hastat; 705 1.3.2.2 nathanw { 706 1.3.2.2 nathanw struct tcs *tcs; 707 1.3.2.2 nathanw int s; 708 1.3.2.2 nathanw 709 1.3.2.2 nathanw s = splbio(); 710 1.3.2.2 nathanw 711 1.3.2.2 nathanw if (scb->xs != NULL) 712 1.3.2.2 nathanw callout_stop(&scb->xs->xs_callout); 713 1.3.2.2 nathanw 714 1.3.2.2 nathanw if (scb == sc->sc_actscb) 715 1.3.2.2 nathanw sc->sc_actscb = NULL; 716 1.3.2.2 nathanw 717 1.3.2.2 nathanw tcs = scb->tcs; 718 1.3.2.2 nathanw 719 1.3.2.2 nathanw if (scb->scb_tagmsg != 0) { 720 1.3.2.2 nathanw if (tcs->tagcnt) 721 1.3.2.2 nathanw tcs->tagcnt--; 722 1.3.2.2 nathanw } else if (tcs->ntagscb == scb) 723 1.3.2.2 nathanw tcs->ntagscb = NULL; 724 1.3.2.2 nathanw 725 1.3.2.2 nathanw scb->status = STATUS_QUEUED; 726 1.3.2.2 nathanw scb->ha_stat = hastat; 727 1.3.2.2 nathanw 728 1.3.2.2 nathanw TAILQ_INSERT_TAIL(&sc->sc_donescb, scb, chain); 729 1.3.2.2 nathanw 730 1.3.2.2 nathanw splx(s); 731 1.3.2.2 nathanw } 732 1.3.2.2 nathanw 733 1.3.2.2 nathanw static __inline struct iha_scsi_req_q * 734 1.3.2.2 nathanw tul_pop_done_scb(sc) 735 1.3.2.2 nathanw struct iha_softc *sc; 736 1.3.2.2 nathanw { 737 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 738 1.3.2.2 nathanw int s; 739 1.3.2.2 nathanw 740 1.3.2.2 nathanw s = splbio(); 741 1.3.2.2 nathanw 742 1.3.2.2 nathanw scb = TAILQ_FIRST(&sc->sc_donescb); 743 1.3.2.2 nathanw 744 1.3.2.2 nathanw if (scb != NULL) { 745 1.3.2.2 nathanw scb->status = STATUS_RENT; 746 1.3.2.2 nathanw TAILQ_REMOVE(&sc->sc_donescb, scb, chain); 747 1.3.2.2 nathanw } 748 1.3.2.2 nathanw 749 1.3.2.2 nathanw splx(s); 750 1.3.2.2 nathanw 751 1.3.2.2 nathanw return (scb); 752 1.3.2.2 nathanw } 753 1.3.2.2 nathanw 754 1.3.2.2 nathanw /* 755 1.3.2.2 nathanw * tul_abort_xs - find the SCB associated with the supplied xs and 756 1.3.2.2 nathanw * stop all processing on it, moving it to the done 757 1.3.2.2 nathanw * queue with the supplied host status value. 758 1.3.2.2 nathanw */ 759 1.3.2.2 nathanw static void 760 1.3.2.2 nathanw tul_abort_xs(sc, xs, hastat) 761 1.3.2.2 nathanw struct iha_softc *sc; 762 1.3.2.2 nathanw struct scsipi_xfer *xs; 763 1.3.2.2 nathanw u_int8_t hastat; 764 1.3.2.2 nathanw { 765 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 766 1.3.2.2 nathanw int i, s; 767 1.3.2.2 nathanw 768 1.3.2.2 nathanw s = splbio(); 769 1.3.2.2 nathanw 770 1.3.2.2 nathanw /* Check the pending queue for the SCB pointing to xs */ 771 1.3.2.2 nathanw 772 1.3.2.2 nathanw TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) 773 1.3.2.2 nathanw if (scb->xs == xs) { 774 1.3.2.2 nathanw tul_del_pend_scb(sc, scb); 775 1.3.2.2 nathanw tul_append_done_scb(sc, scb, hastat); 776 1.3.2.2 nathanw splx(s); 777 1.3.2.2 nathanw return; 778 1.3.2.2 nathanw } 779 1.3.2.2 nathanw 780 1.3.2.2 nathanw /* 781 1.3.2.2 nathanw * If that didn't work, check all BUSY/SELECTING SCB's for one 782 1.3.2.2 nathanw * pointing to xs 783 1.3.2.2 nathanw */ 784 1.3.2.2 nathanw 785 1.3.2.2 nathanw for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 786 1.3.2.2 nathanw switch (scb->status) { 787 1.3.2.2 nathanw case STATUS_BUSY: 788 1.3.2.2 nathanw case STATUS_SELECT: 789 1.3.2.2 nathanw if (scb->xs == xs) { 790 1.3.2.2 nathanw tul_append_done_scb(sc, scb, hastat); 791 1.3.2.2 nathanw splx(s); 792 1.3.2.2 nathanw return; 793 1.3.2.2 nathanw } 794 1.3.2.2 nathanw break; 795 1.3.2.2 nathanw default: 796 1.3.2.2 nathanw break; 797 1.3.2.2 nathanw } 798 1.3.2.2 nathanw 799 1.3.2.2 nathanw splx(s); 800 1.3.2.2 nathanw } 801 1.3.2.2 nathanw 802 1.3.2.2 nathanw /* 803 1.3.2.2 nathanw * tul_bad_seq - a SCSI bus phase was encountered out of the 804 1.3.2.2 nathanw * correct/expected sequence. Reset the SCSI bus. 805 1.3.2.2 nathanw */ 806 1.3.2.2 nathanw static void 807 1.3.2.2 nathanw tul_bad_seq(sc) 808 1.3.2.2 nathanw struct iha_softc *sc; 809 1.3.2.2 nathanw { 810 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 811 1.3.2.2 nathanw 812 1.3.2.2 nathanw if (scb != NULL) 813 1.3.2.2 nathanw tul_append_done_scb(sc, scb, HOST_BAD_PHAS); 814 1.3.2.2 nathanw 815 1.3.2.2 nathanw tul_reset_scsi_bus(sc); 816 1.3.2.2 nathanw tul_reset_chip(sc); 817 1.3.2.2 nathanw } 818 1.3.2.2 nathanw 819 1.3.2.2 nathanw /* 820 1.3.2.2 nathanw * tul_push_sense_request - obtain auto sense data by pushing the 821 1.3.2.2 nathanw * SCB needing it back onto the pending 822 1.3.2.2 nathanw * queue with a REQUEST_SENSE CDB. 823 1.3.2.2 nathanw */ 824 1.3.2.2 nathanw static int 825 1.3.2.2 nathanw tul_push_sense_request(sc, scb) 826 1.3.2.2 nathanw struct iha_softc *sc; 827 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 828 1.3.2.2 nathanw { 829 1.3.2.2 nathanw struct scsipi_xfer *xs = scb->xs; 830 1.3.2.2 nathanw struct scsipi_periph *periph = xs->xs_periph; 831 1.3.2.2 nathanw struct scsipi_sense *ss = (struct scsipi_sense *)scb->cmd; 832 1.3.2.2 nathanw int lun = periph->periph_lun; 833 1.3.2.2 nathanw int err; 834 1.3.2.2 nathanw 835 1.3.2.2 nathanw ss->opcode = REQUEST_SENSE; 836 1.3.2.2 nathanw ss->byte2 = lun << SCSI_CMD_LUN_SHIFT; 837 1.3.2.2 nathanw ss->unused[0] = ss->unused[1] = 0; 838 1.3.2.2 nathanw ss->length = sizeof(struct scsipi_sense_data); 839 1.3.2.2 nathanw ss->control = 0; 840 1.3.2.2 nathanw 841 1.3.2.2 nathanw scb->flags &= ~(FLAG_SG | XS_CTL_DATA_OUT); 842 1.3.2.2 nathanw scb->flags |= FLAG_RSENS | XS_CTL_DATA_IN; 843 1.3.2.2 nathanw 844 1.3.2.2 nathanw scb->scb_id &= ~MSG_IDENTIFY_DISCFLAG; 845 1.3.2.2 nathanw 846 1.3.2.2 nathanw scb->scb_tagmsg = 0; 847 1.3.2.2 nathanw scb->ta_stat = SCSI_OK; 848 1.3.2.2 nathanw 849 1.3.2.2 nathanw scb->cmdlen = sizeof(struct scsipi_sense); 850 1.3.2.2 nathanw scb->buflen = ss->length; 851 1.3.2.2 nathanw 852 1.3.2.2 nathanw err = bus_dmamap_load(sc->sc_dmat, scb->dmap, 853 1.3.2.2 nathanw &xs->sense.scsi_sense, scb->buflen, NULL, BUS_DMA_NOWAIT); 854 1.3.2.2 nathanw if (err != 0) { 855 1.3.2.2 nathanw printf("iha_push_sense_request: cannot bus_dmamap_load()\n"); 856 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 857 1.3.2.2 nathanw return 1; 858 1.3.2.2 nathanw } 859 1.3.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, scb->dmap, 860 1.3.2.2 nathanw 0, scb->buflen, BUS_DMASYNC_PREREAD); 861 1.3.2.2 nathanw 862 1.3.2.2 nathanw /* XXX What about queued command? */ 863 1.3.2.2 nathanw tul_exec_scb(sc, scb); 864 1.3.2.2 nathanw 865 1.3.2.2 nathanw return 0; 866 1.3.2.2 nathanw } 867 1.3.2.2 nathanw 868 1.3.2.2 nathanw /* 869 1.3.2.2 nathanw * tul_main - process the active SCB, taking one off pending and making it 870 1.3.2.2 nathanw * active if necessary, and any done SCB's created as 871 1.3.2.2 nathanw * a result until there are no interrupts pending and no pending 872 1.3.2.2 nathanw * SCB's that can be started. 873 1.3.2.2 nathanw */ 874 1.3.2.2 nathanw static void 875 1.3.2.2 nathanw tul_main(sc) 876 1.3.2.2 nathanw struct iha_softc *sc; 877 1.3.2.2 nathanw { 878 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 879 1.3.2.2 nathanw bus_space_handle_t ioh =sc->sc_ioh; 880 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 881 1.3.2.2 nathanw 882 1.3.2.2 nathanw for (;;) { 883 1.3.2.2 nathanw tul_scsi(sc); 884 1.3.2.2 nathanw 885 1.3.2.2 nathanw while ((scb = tul_pop_done_scb(sc)) != NULL) 886 1.3.2.2 nathanw tul_done_scb(sc, scb); 887 1.3.2.2 nathanw 888 1.3.2.2 nathanw /* 889 1.3.2.2 nathanw * If there are no interrupts pending, or we can't start 890 1.3.2.2 nathanw * a pending sc, break out of the for(;;). Otherwise 891 1.3.2.2 nathanw * continue the good work with another call to 892 1.3.2.2 nathanw * tul_scsi(). 893 1.3.2.2 nathanw */ 894 1.3.2.2 nathanw if (((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 895 1.3.2.2 nathanw && (tul_find_pend_scb(sc) == NULL)) 896 1.3.2.2 nathanw break; 897 1.3.2.2 nathanw } 898 1.3.2.2 nathanw } 899 1.3.2.2 nathanw 900 1.3.2.2 nathanw /* 901 1.3.2.2 nathanw * tul_scsi - service any outstanding interrupts. If there are none, try to 902 1.3.2.2 nathanw * start another SCB currently in the pending queue. 903 1.3.2.2 nathanw */ 904 1.3.2.2 nathanw static void 905 1.3.2.2 nathanw tul_scsi(sc) 906 1.3.2.2 nathanw struct iha_softc *sc; 907 1.3.2.2 nathanw { 908 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 909 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 910 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 911 1.3.2.2 nathanw struct tcs *tcs; 912 1.3.2.2 nathanw u_int8_t stat; 913 1.3.2.2 nathanw 914 1.3.2.2 nathanw /* service pending interrupts asap */ 915 1.3.2.2 nathanw 916 1.3.2.2 nathanw stat = bus_space_read_1(iot, ioh, TUL_STAT0); 917 1.3.2.2 nathanw if ((stat & INTPD) != 0) { 918 1.3.2.2 nathanw sc->sc_status0 = stat; 919 1.3.2.2 nathanw sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 920 1.3.2.2 nathanw sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 921 1.3.2.2 nathanw 922 1.3.2.2 nathanw sc->sc_phase = sc->sc_status0 & PH_MASK; 923 1.3.2.2 nathanw 924 1.3.2.2 nathanw if ((sc->sc_sistat & SRSTD) != 0) { 925 1.3.2.2 nathanw tul_reset_scsi_bus(sc); 926 1.3.2.2 nathanw return; 927 1.3.2.2 nathanw } 928 1.3.2.2 nathanw 929 1.3.2.2 nathanw if ((sc->sc_sistat & RSELED) != 0) { 930 1.3.2.2 nathanw tul_resel(sc); 931 1.3.2.2 nathanw return; 932 1.3.2.2 nathanw } 933 1.3.2.2 nathanw 934 1.3.2.2 nathanw if ((sc->sc_sistat & (STIMEO | DISCD)) != 0) { 935 1.3.2.2 nathanw tul_busfree(sc); 936 1.3.2.2 nathanw return; 937 1.3.2.2 nathanw } 938 1.3.2.2 nathanw 939 1.3.2.2 nathanw if ((sc->sc_sistat & (SCMDN | SBSRV)) != 0) { 940 1.3.2.2 nathanw tul_next_state(sc); 941 1.3.2.2 nathanw return; 942 1.3.2.2 nathanw } 943 1.3.2.2 nathanw 944 1.3.2.2 nathanw if ((sc->sc_sistat & SELED) != 0) 945 1.3.2.2 nathanw tul_set_ssig(sc, 0, 0); 946 1.3.2.2 nathanw } 947 1.3.2.2 nathanw 948 1.3.2.2 nathanw /* 949 1.3.2.2 nathanw * There were no interrupts pending which required action elsewhere, so 950 1.3.2.2 nathanw * see if it is possible to start the selection phase on a pending SCB 951 1.3.2.2 nathanw */ 952 1.3.2.2 nathanw if ((scb = tul_find_pend_scb(sc)) == NULL) 953 1.3.2.2 nathanw return; 954 1.3.2.2 nathanw 955 1.3.2.2 nathanw tcs = scb->tcs; 956 1.3.2.2 nathanw 957 1.3.2.2 nathanw /* program HBA's SCSI ID & target SCSI ID */ 958 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SID, (sc->sc_id << 4) | scb->target); 959 1.3.2.2 nathanw 960 1.3.2.2 nathanw if ((scb->flags & XS_CTL_RESET) == 0) { 961 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 962 1.3.2.2 nathanw 963 1.3.2.2 nathanw if ((tcs->flags & FLAG_NO_NEG_SYNC) == 0 || 964 1.3.2.2 nathanw (tcs->flags & FLAG_NO_NEG_WIDE) == 0) 965 1.3.2.2 nathanw tul_select(sc, scb, SELATNSTOP); 966 1.3.2.2 nathanw 967 1.3.2.2 nathanw else if (scb->scb_tagmsg != 0) 968 1.3.2.2 nathanw tul_select(sc, scb, SEL_ATN3); 969 1.3.2.2 nathanw 970 1.3.2.2 nathanw else 971 1.3.2.2 nathanw tul_select(sc, scb, SEL_ATN); 972 1.3.2.2 nathanw 973 1.3.2.2 nathanw } else { 974 1.3.2.2 nathanw tul_select(sc, scb, SELATNSTOP); 975 1.3.2.2 nathanw scb->nextstat = 8; 976 1.3.2.2 nathanw } 977 1.3.2.2 nathanw 978 1.3.2.2 nathanw if ((scb->flags & XS_CTL_POLL) != 0) { 979 1.3.2.2 nathanw for (; scb->timeout > 0; scb->timeout--) { 980 1.3.2.2 nathanw if (tul_wait(sc, NO_OP) == -1) 981 1.3.2.2 nathanw break; 982 1.3.2.2 nathanw if (tul_next_state(sc) == -1) 983 1.3.2.2 nathanw break; 984 1.3.2.2 nathanw delay(1000); /* Only happens in boot, so it's ok */ 985 1.3.2.2 nathanw } 986 1.3.2.2 nathanw 987 1.3.2.2 nathanw /* 988 1.3.2.2 nathanw * Since done queue processing not done until AFTER this 989 1.3.2.2 nathanw * function returns, scb is on the done queue, not 990 1.3.2.2 nathanw * the free queue at this point and still has valid data 991 1.3.2.2 nathanw * 992 1.3.2.2 nathanw * Conversely, xs->error has not been set yet 993 1.3.2.2 nathanw */ 994 1.3.2.2 nathanw if (scb->timeout == 0) 995 1.3.2.2 nathanw tul_timeout(scb); 996 1.3.2.2 nathanw } 997 1.3.2.2 nathanw } 998 1.3.2.2 nathanw 999 1.3.2.2 nathanw /* 1000 1.3.2.2 nathanw * tul_data_over_run - return HOST_OK for all SCSI opcodes where BufLen 1001 1.3.2.2 nathanw * is an 'Allocation Length'. All other SCSI opcodes 1002 1.3.2.2 nathanw * get HOST_DO_DU as they SHOULD have xferred all the 1003 1.3.2.2 nathanw * data requested. 1004 1.3.2.2 nathanw * 1005 1.3.2.2 nathanw * The list of opcodes using 'Allocation Length' was 1006 1.3.2.2 nathanw * found by scanning all the SCSI-3 T10 drafts. See 1007 1.3.2.2 nathanw * www.t10.org for the curious with a .pdf reader. 1008 1.3.2.2 nathanw */ 1009 1.3.2.2 nathanw static u_int8_t 1010 1.3.2.2 nathanw tul_data_over_run(scb) 1011 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1012 1.3.2.2 nathanw { 1013 1.3.2.2 nathanw switch (scb->cmd[0]) { 1014 1.3.2.2 nathanw case 0x03: /* Request Sense SPC-2 */ 1015 1.3.2.2 nathanw case 0x12: /* Inquiry SPC-2 */ 1016 1.3.2.2 nathanw case 0x1a: /* Mode Sense (6 byte version) SPC-2 */ 1017 1.3.2.2 nathanw case 0x1c: /* Receive Diagnostic Results SPC-2 */ 1018 1.3.2.2 nathanw case 0x23: /* Read Format Capacities MMC-2 */ 1019 1.3.2.2 nathanw case 0x29: /* Read Generation SBC */ 1020 1.3.2.2 nathanw case 0x34: /* Read Position SSC-2 */ 1021 1.3.2.2 nathanw case 0x37: /* Read Defect Data SBC */ 1022 1.3.2.2 nathanw case 0x3c: /* Read Buffer SPC-2 */ 1023 1.3.2.2 nathanw case 0x42: /* Read Sub Channel MMC-2 */ 1024 1.3.2.2 nathanw case 0x43: /* Read TOC/PMA/ATIP MMC */ 1025 1.3.2.2 nathanw 1026 1.3.2.2 nathanw /* XXX - 2 with same opcode of 0x44? */ 1027 1.3.2.2 nathanw case 0x44: /* Read Header/Read Density Suprt MMC/SSC*/ 1028 1.3.2.2 nathanw 1029 1.3.2.2 nathanw case 0x46: /* Get Configuration MMC-2 */ 1030 1.3.2.2 nathanw case 0x4a: /* Get Event/Status Notification MMC-2 */ 1031 1.3.2.2 nathanw case 0x4d: /* Log Sense SPC-2 */ 1032 1.3.2.2 nathanw case 0x51: /* Read Disc Information MMC */ 1033 1.3.2.2 nathanw case 0x52: /* Read Track Information MMC */ 1034 1.3.2.2 nathanw case 0x59: /* Read Master CUE MMC */ 1035 1.3.2.2 nathanw case 0x5a: /* Mode Sense (10 byte version) SPC-2 */ 1036 1.3.2.2 nathanw case 0x5c: /* Read Buffer Capacity MMC */ 1037 1.3.2.2 nathanw case 0x5e: /* Persistant Reserve In SPC-2 */ 1038 1.3.2.2 nathanw case 0x84: /* Receive Copy Results SPC-2 */ 1039 1.3.2.2 nathanw case 0xa0: /* Report LUNs SPC-2 */ 1040 1.3.2.2 nathanw case 0xa3: /* Various Report requests SBC-2/SCC-2*/ 1041 1.3.2.2 nathanw case 0xa4: /* Report Key MMC-2 */ 1042 1.3.2.2 nathanw case 0xad: /* Read DVD Structure MMC-2 */ 1043 1.3.2.2 nathanw case 0xb4: /* Read Element Status (Attached) SMC */ 1044 1.3.2.2 nathanw case 0xb5: /* Request Volume Element Address SMC */ 1045 1.3.2.2 nathanw case 0xb7: /* Read Defect Data (12 byte ver.) SBC */ 1046 1.3.2.2 nathanw case 0xb8: /* Read Element Status (Independ.) SMC */ 1047 1.3.2.2 nathanw case 0xba: /* Report Redundancy SCC-2 */ 1048 1.3.2.2 nathanw case 0xbd: /* Mechanism Status MMC */ 1049 1.3.2.2 nathanw case 0xbe: /* Report Basic Redundancy SCC-2 */ 1050 1.3.2.2 nathanw 1051 1.3.2.2 nathanw return (HOST_OK); 1052 1.3.2.2 nathanw break; 1053 1.3.2.2 nathanw 1054 1.3.2.2 nathanw default: 1055 1.3.2.2 nathanw return (HOST_DO_DU); 1056 1.3.2.2 nathanw break; 1057 1.3.2.2 nathanw } 1058 1.3.2.2 nathanw } 1059 1.3.2.2 nathanw 1060 1.3.2.2 nathanw /* 1061 1.3.2.2 nathanw * tul_next_state - prcess the current SCB as requested in it's 1062 1.3.2.2 nathanw * nextstat member. 1063 1.3.2.2 nathanw */ 1064 1.3.2.2 nathanw static int 1065 1.3.2.2 nathanw tul_next_state(sc) 1066 1.3.2.2 nathanw struct iha_softc *sc; 1067 1.3.2.2 nathanw { 1068 1.3.2.2 nathanw 1069 1.3.2.2 nathanw if (sc->sc_actscb == NULL) 1070 1.3.2.2 nathanw return (-1); 1071 1.3.2.2 nathanw 1072 1.3.2.2 nathanw switch (sc->sc_actscb->nextstat) { 1073 1.3.2.2 nathanw case 1: 1074 1.3.2.2 nathanw if (tul_state_1(sc) == 3) 1075 1.3.2.2 nathanw goto state_3; 1076 1.3.2.2 nathanw break; 1077 1.3.2.2 nathanw 1078 1.3.2.2 nathanw case 2: 1079 1.3.2.2 nathanw switch (tul_state_2(sc)) { 1080 1.3.2.2 nathanw case 3: 1081 1.3.2.2 nathanw goto state_3; 1082 1.3.2.2 nathanw case 4: 1083 1.3.2.2 nathanw goto state_4; 1084 1.3.2.2 nathanw default: 1085 1.3.2.2 nathanw break; 1086 1.3.2.2 nathanw } 1087 1.3.2.2 nathanw break; 1088 1.3.2.2 nathanw 1089 1.3.2.2 nathanw case 3: 1090 1.3.2.2 nathanw state_3: 1091 1.3.2.2 nathanw if (tul_state_3(sc) == 4) 1092 1.3.2.2 nathanw goto state_4; 1093 1.3.2.2 nathanw break; 1094 1.3.2.2 nathanw 1095 1.3.2.2 nathanw case 4: 1096 1.3.2.2 nathanw state_4: 1097 1.3.2.2 nathanw switch (tul_state_4(sc)) { 1098 1.3.2.2 nathanw case 0: 1099 1.3.2.2 nathanw return (0); 1100 1.3.2.2 nathanw case 6: 1101 1.3.2.2 nathanw goto state_6; 1102 1.3.2.2 nathanw default: 1103 1.3.2.2 nathanw break; 1104 1.3.2.2 nathanw } 1105 1.3.2.2 nathanw break; 1106 1.3.2.2 nathanw 1107 1.3.2.2 nathanw case 5: 1108 1.3.2.2 nathanw switch (tul_state_5(sc)) { 1109 1.3.2.2 nathanw case 4: 1110 1.3.2.2 nathanw goto state_4; 1111 1.3.2.2 nathanw case 6: 1112 1.3.2.2 nathanw goto state_6; 1113 1.3.2.2 nathanw default: 1114 1.3.2.2 nathanw break; 1115 1.3.2.2 nathanw } 1116 1.3.2.2 nathanw break; 1117 1.3.2.2 nathanw 1118 1.3.2.2 nathanw case 6: 1119 1.3.2.2 nathanw state_6: 1120 1.3.2.2 nathanw tul_state_6(sc); 1121 1.3.2.2 nathanw break; 1122 1.3.2.2 nathanw 1123 1.3.2.2 nathanw case 8: 1124 1.3.2.2 nathanw tul_state_8(sc); 1125 1.3.2.2 nathanw break; 1126 1.3.2.2 nathanw 1127 1.3.2.2 nathanw default: 1128 1.3.2.2 nathanw #ifdef IHA_DEBUG_STATE 1129 1.3.2.2 nathanw printf("[debug] -unknown state: %i-\n", 1130 1.3.2.2 nathanw sc->sc_actscb->nextstat); 1131 1.3.2.2 nathanw #endif 1132 1.3.2.2 nathanw tul_bad_seq(sc); 1133 1.3.2.2 nathanw break; 1134 1.3.2.2 nathanw } 1135 1.3.2.2 nathanw 1136 1.3.2.2 nathanw return (-1); 1137 1.3.2.2 nathanw } 1138 1.3.2.2 nathanw 1139 1.3.2.2 nathanw /* 1140 1.3.2.2 nathanw * tul_state_1 - selection is complete after a SELATNSTOP. If the target 1141 1.3.2.2 nathanw * has put the bus into MSG_OUT phase start wide/sync 1142 1.3.2.2 nathanw * negotiation. Otherwise clear the FIFO and go to state 3, 1143 1.3.2.2 nathanw * which will send the SCSI CDB to the target. 1144 1.3.2.2 nathanw */ 1145 1.3.2.2 nathanw static int 1146 1.3.2.2 nathanw tul_state_1(sc) 1147 1.3.2.2 nathanw struct iha_softc *sc; 1148 1.3.2.2 nathanw { 1149 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1150 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1151 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1152 1.3.2.2 nathanw struct tcs *tcs; 1153 1.3.2.2 nathanw int flags; 1154 1.3.2.2 nathanw 1155 1.3.2.2 nathanw tul_mark_busy_scb(scb); 1156 1.3.2.2 nathanw 1157 1.3.2.2 nathanw tcs = scb->tcs; 1158 1.3.2.2 nathanw 1159 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 1160 1.3.2.2 nathanw 1161 1.3.2.2 nathanw /* 1162 1.3.2.2 nathanw * If we are in PHASE_MSG_OUT, send 1163 1.3.2.2 nathanw * a) IDENT message (with tags if appropriate) 1164 1.3.2.2 nathanw * b) WDTR if the target is configured to negotiate wide xfers 1165 1.3.2.2 nathanw * ** OR ** 1166 1.3.2.2 nathanw * c) SDTR if the target is configured to negotiate sync xfers 1167 1.3.2.2 nathanw * but not wide ones 1168 1.3.2.2 nathanw * 1169 1.3.2.2 nathanw * If we are NOT, then the target is not asking for anything but 1170 1.3.2.2 nathanw * the data/command, so go straight to state 3. 1171 1.3.2.2 nathanw */ 1172 1.3.2.2 nathanw if (sc->sc_phase == PHASE_MSG_OUT) { 1173 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL1, (ESBUSIN | EHRSL)); 1174 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1175 1.3.2.2 nathanw 1176 1.3.2.2 nathanw if (scb->scb_tagmsg != 0) { 1177 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, 1178 1.3.2.2 nathanw scb->scb_tagmsg); 1179 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, 1180 1.3.2.2 nathanw scb->scb_tagid); 1181 1.3.2.2 nathanw } 1182 1.3.2.2 nathanw 1183 1.3.2.2 nathanw flags = tcs->flags; 1184 1.3.2.2 nathanw if ((flags & FLAG_NO_NEG_WIDE) == 0) { 1185 1.3.2.2 nathanw if (tul_msgout_wide(sc) == -1) 1186 1.3.2.2 nathanw return (-1); 1187 1.3.2.2 nathanw } else if ((flags & FLAG_NO_NEG_SYNC) == 0) { 1188 1.3.2.2 nathanw if (tul_msgout_sync(sc) == -1) 1189 1.3.2.2 nathanw return (-1); 1190 1.3.2.2 nathanw } 1191 1.3.2.2 nathanw 1192 1.3.2.2 nathanw } else { 1193 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1194 1.3.2.2 nathanw tul_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1195 1.3.2.2 nathanw } 1196 1.3.2.2 nathanw 1197 1.3.2.2 nathanw return (3); 1198 1.3.2.2 nathanw } 1199 1.3.2.2 nathanw 1200 1.3.2.2 nathanw /* 1201 1.3.2.2 nathanw * tul_state_2 - selection is complete after a SEL_ATN or SEL_ATN3. If the SCSI 1202 1.3.2.2 nathanw * CDB has already been send, go to state 4 to start the data 1203 1.3.2.2 nathanw * xfer. Otherwise reset the FIFO and go to state 3, sending 1204 1.3.2.2 nathanw * the SCSI CDB. 1205 1.3.2.2 nathanw */ 1206 1.3.2.2 nathanw static int 1207 1.3.2.2 nathanw tul_state_2(sc) 1208 1.3.2.2 nathanw struct iha_softc *sc; 1209 1.3.2.2 nathanw { 1210 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1211 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1212 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1213 1.3.2.2 nathanw 1214 1.3.2.2 nathanw tul_mark_busy_scb(scb); 1215 1.3.2.2 nathanw 1216 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, scb->tcs->sconfig0); 1217 1.3.2.2 nathanw 1218 1.3.2.2 nathanw if ((sc->sc_status1 & CPDNE) != 0) 1219 1.3.2.2 nathanw return (4); 1220 1.3.2.2 nathanw 1221 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1222 1.3.2.2 nathanw 1223 1.3.2.2 nathanw tul_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1224 1.3.2.2 nathanw 1225 1.3.2.2 nathanw return (3); 1226 1.3.2.2 nathanw } 1227 1.3.2.2 nathanw 1228 1.3.2.2 nathanw /* 1229 1.3.2.2 nathanw * tul_state_3 - send the SCSI CDB to the target, processing any status 1230 1.3.2.2 nathanw * or other messages received until that is done or 1231 1.3.2.2 nathanw * abandoned. 1232 1.3.2.2 nathanw */ 1233 1.3.2.2 nathanw static int 1234 1.3.2.2 nathanw tul_state_3(sc) 1235 1.3.2.2 nathanw struct iha_softc *sc; 1236 1.3.2.2 nathanw { 1237 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1238 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1239 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1240 1.3.2.2 nathanw int flags; 1241 1.3.2.2 nathanw 1242 1.3.2.2 nathanw for (;;) { 1243 1.3.2.2 nathanw switch (sc->sc_phase) { 1244 1.3.2.2 nathanw case PHASE_CMD_OUT: 1245 1.3.2.2 nathanw bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1246 1.3.2.2 nathanw scb->cmd, scb->cmdlen); 1247 1.3.2.2 nathanw if (tul_wait(sc, XF_FIFO_OUT) == -1) 1248 1.3.2.2 nathanw return (-1); 1249 1.3.2.2 nathanw else if (sc->sc_phase == PHASE_CMD_OUT) { 1250 1.3.2.2 nathanw tul_bad_seq(sc); 1251 1.3.2.2 nathanw return (-1); 1252 1.3.2.2 nathanw } else 1253 1.3.2.2 nathanw return (4); 1254 1.3.2.2 nathanw 1255 1.3.2.2 nathanw case PHASE_MSG_IN: 1256 1.3.2.2 nathanw scb->nextstat = 3; 1257 1.3.2.2 nathanw if (tul_msgin(sc) == -1) 1258 1.3.2.2 nathanw return (-1); 1259 1.3.2.2 nathanw break; 1260 1.3.2.2 nathanw 1261 1.3.2.2 nathanw case PHASE_STATUS_IN: 1262 1.3.2.2 nathanw if (tul_status_msg(sc) == -1) 1263 1.3.2.2 nathanw return (-1); 1264 1.3.2.2 nathanw break; 1265 1.3.2.2 nathanw 1266 1.3.2.2 nathanw case PHASE_MSG_OUT: 1267 1.3.2.2 nathanw flags = scb->tcs->flags; 1268 1.3.2.2 nathanw if ((flags & FLAG_NO_NEG_SYNC) != 0) { 1269 1.3.2.2 nathanw if (tul_msgout(sc, MSG_NOOP) == -1) 1270 1.3.2.2 nathanw return (-1); 1271 1.3.2.2 nathanw } else if (tul_msgout_sync(sc) == -1) 1272 1.3.2.2 nathanw return (-1); 1273 1.3.2.2 nathanw break; 1274 1.3.2.2 nathanw 1275 1.3.2.2 nathanw default: 1276 1.3.2.2 nathanw printf("[debug] -s3- bad phase = %d\n", sc->sc_phase); 1277 1.3.2.2 nathanw tul_bad_seq(sc); 1278 1.3.2.2 nathanw return (-1); 1279 1.3.2.2 nathanw } 1280 1.3.2.2 nathanw } 1281 1.3.2.2 nathanw } 1282 1.3.2.2 nathanw 1283 1.3.2.2 nathanw /* 1284 1.3.2.2 nathanw * tul_state_4 - start a data xfer. Handle any bus state 1285 1.3.2.2 nathanw * transitions until PHASE_DATA_IN/_OUT 1286 1.3.2.2 nathanw * or the attempt is abandoned. If there is 1287 1.3.2.2 nathanw * no data to xfer, go to state 6 and finish 1288 1.3.2.2 nathanw * processing the current SCB. 1289 1.3.2.2 nathanw */ 1290 1.3.2.2 nathanw static int 1291 1.3.2.2 nathanw tul_state_4(sc) 1292 1.3.2.2 nathanw struct iha_softc *sc; 1293 1.3.2.2 nathanw { 1294 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1295 1.3.2.2 nathanw 1296 1.3.2.2 nathanw if ((scb->flags & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) == 1297 1.3.2.2 nathanw (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) 1298 1.3.2.2 nathanw return (6); /* Both dir flags set => NO xfer was requested */ 1299 1.3.2.2 nathanw 1300 1.3.2.2 nathanw for (;;) { 1301 1.3.2.2 nathanw if (scb->buflen == 0) 1302 1.3.2.2 nathanw return (6); 1303 1.3.2.2 nathanw 1304 1.3.2.2 nathanw switch (sc->sc_phase) { 1305 1.3.2.2 nathanw case PHASE_STATUS_IN: 1306 1.3.2.2 nathanw if ((scb->flags & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) 1307 1.3.2.2 nathanw != 0) 1308 1.3.2.2 nathanw scb->ha_stat = tul_data_over_run(scb); 1309 1.3.2.2 nathanw if ((tul_status_msg(sc)) == -1) 1310 1.3.2.2 nathanw return (-1); 1311 1.3.2.2 nathanw break; 1312 1.3.2.2 nathanw 1313 1.3.2.2 nathanw case PHASE_MSG_IN: 1314 1.3.2.2 nathanw scb->nextstat = 4; 1315 1.3.2.2 nathanw if (tul_msgin(sc) == -1) 1316 1.3.2.2 nathanw return (-1); 1317 1.3.2.2 nathanw break; 1318 1.3.2.2 nathanw 1319 1.3.2.2 nathanw case PHASE_MSG_OUT: 1320 1.3.2.2 nathanw if ((sc->sc_status0 & SPERR) != 0) { 1321 1.3.2.2 nathanw scb->buflen = 0; 1322 1.3.2.2 nathanw scb->ha_stat = HOST_SPERR; 1323 1.3.2.2 nathanw if (tul_msgout(sc, MSG_INITIATOR_DET_ERR) == -1) 1324 1.3.2.2 nathanw return (-1); 1325 1.3.2.2 nathanw else 1326 1.3.2.2 nathanw return (6); 1327 1.3.2.2 nathanw } else { 1328 1.3.2.2 nathanw if (tul_msgout(sc, MSG_NOOP) == -1) 1329 1.3.2.2 nathanw return (-1); 1330 1.3.2.2 nathanw } 1331 1.3.2.2 nathanw break; 1332 1.3.2.2 nathanw 1333 1.3.2.2 nathanw case PHASE_DATA_IN: 1334 1.3.2.2 nathanw return (tul_xfer_data(sc, scb, XS_CTL_DATA_IN)); 1335 1.3.2.2 nathanw 1336 1.3.2.2 nathanw case PHASE_DATA_OUT: 1337 1.3.2.2 nathanw return (tul_xfer_data(sc, scb, XS_CTL_DATA_OUT)); 1338 1.3.2.2 nathanw 1339 1.3.2.2 nathanw default: 1340 1.3.2.2 nathanw tul_bad_seq(sc); 1341 1.3.2.2 nathanw return (-1); 1342 1.3.2.2 nathanw } 1343 1.3.2.2 nathanw } 1344 1.3.2.2 nathanw } 1345 1.3.2.2 nathanw 1346 1.3.2.2 nathanw /* 1347 1.3.2.2 nathanw * tul_state_5 - handle the partial or final completion of the current 1348 1.3.2.2 nathanw * data xfer. If DMA is still active stop it. If there is 1349 1.3.2.2 nathanw * more data to xfer, go to state 4 and start the xfer. 1350 1.3.2.2 nathanw * If not go to state 6 and finish the SCB. 1351 1.3.2.2 nathanw */ 1352 1.3.2.2 nathanw static int 1353 1.3.2.2 nathanw tul_state_5(sc) 1354 1.3.2.2 nathanw struct iha_softc *sc; 1355 1.3.2.2 nathanw { 1356 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1357 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1358 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1359 1.3.2.2 nathanw struct iha_sg_element *sg; 1360 1.3.2.2 nathanw u_int32_t cnt; 1361 1.3.2.2 nathanw u_int8_t period, stat; 1362 1.3.2.2 nathanw long xcnt; /* cannot use unsigned!! see code: if (xcnt < 0) */ 1363 1.3.2.2 nathanw int i; 1364 1.3.2.2 nathanw 1365 1.3.2.2 nathanw cnt = bus_space_read_4(iot, ioh, TUL_STCNT0) & TCNT; 1366 1.3.2.2 nathanw 1367 1.3.2.2 nathanw /* 1368 1.3.2.2 nathanw * Stop any pending DMA activity and check for parity error. 1369 1.3.2.2 nathanw */ 1370 1.3.2.2 nathanw 1371 1.3.2.2 nathanw if ((bus_space_read_1(iot, ioh, TUL_DCMD) & XDIR) != 0) { 1372 1.3.2.2 nathanw /* Input Operation */ 1373 1.3.2.2 nathanw if ((sc->sc_status0 & SPERR) != 0) 1374 1.3.2.2 nathanw scb->ha_stat = HOST_SPERR; 1375 1.3.2.2 nathanw 1376 1.3.2.2 nathanw if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1377 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_DCTRL0, 1378 1.3.2.2 nathanw bus_space_read_1(iot, ioh, TUL_DCTRL0) | SXSTP); 1379 1.3.2.2 nathanw while (bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) 1380 1.3.2.2 nathanw ; 1381 1.3.2.2 nathanw } 1382 1.3.2.2 nathanw 1383 1.3.2.2 nathanw } else { 1384 1.3.2.2 nathanw /* Output Operation */ 1385 1.3.2.2 nathanw if ((sc->sc_status1 & SXCMP) == 0) { 1386 1.3.2.2 nathanw period = scb->tcs->syncm; 1387 1.3.2.2 nathanw if ((period & PERIOD_WIDE_SCSI) != 0) 1388 1.3.2.2 nathanw cnt += (bus_space_read_1(iot, ioh, 1389 1.3.2.2 nathanw TUL_SFIFOCNT) & FIFOC) * 2; 1390 1.3.2.2 nathanw else 1391 1.3.2.2 nathanw cnt += bus_space_read_1(iot, ioh, 1392 1.3.2.2 nathanw TUL_SFIFOCNT) & FIFOC; 1393 1.3.2.2 nathanw } 1394 1.3.2.2 nathanw 1395 1.3.2.2 nathanw if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1396 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 1397 1.3.2.2 nathanw do 1398 1.3.2.2 nathanw stat = bus_space_read_1(iot, ioh, TUL_ISTUS0); 1399 1.3.2.2 nathanw while ((stat & DABT) == 0); 1400 1.3.2.2 nathanw } 1401 1.3.2.2 nathanw 1402 1.3.2.2 nathanw if ((cnt == 1) && (sc->sc_phase == PHASE_DATA_OUT)) { 1403 1.3.2.2 nathanw if (tul_wait(sc, XF_FIFO_OUT) == -1) 1404 1.3.2.2 nathanw return (-1); 1405 1.3.2.2 nathanw cnt = 0; 1406 1.3.2.2 nathanw 1407 1.3.2.2 nathanw } else if ((sc->sc_status1 & SXCMP) == 0) 1408 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1409 1.3.2.2 nathanw } 1410 1.3.2.2 nathanw 1411 1.3.2.2 nathanw if (cnt == 0) { 1412 1.3.2.2 nathanw scb->buflen = 0; 1413 1.3.2.2 nathanw return (6); 1414 1.3.2.2 nathanw } 1415 1.3.2.2 nathanw 1416 1.3.2.2 nathanw /* Update active data pointer and restart the I/O at the new point */ 1417 1.3.2.2 nathanw 1418 1.3.2.2 nathanw xcnt = scb->buflen - cnt; /* xcnt == bytes xferred */ 1419 1.3.2.2 nathanw scb->buflen = cnt; /* cnt == bytes left */ 1420 1.3.2.2 nathanw 1421 1.3.2.2 nathanw if ((scb->flags & FLAG_SG) != 0) { 1422 1.3.2.2 nathanw sg = &scb->sglist[scb->sg_index]; 1423 1.3.2.2 nathanw for (i = scb->sg_index; i < scb->sg_max; sg++, i++) { 1424 1.3.2.2 nathanw xcnt -= le32toh(sg->sg_len); 1425 1.3.2.2 nathanw if (xcnt < 0) { 1426 1.3.2.2 nathanw xcnt += le32toh(sg->sg_len); 1427 1.3.2.2 nathanw 1428 1.3.2.2 nathanw sg->sg_addr = 1429 1.3.2.2 nathanw htole32(le32toh(sg->sg_addr) + xcnt); 1430 1.3.2.2 nathanw sg->sg_len = 1431 1.3.2.2 nathanw htole32(le32toh(sg->sg_len) - xcnt); 1432 1.3.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1433 1.3.2.2 nathanw scb->sgoffset, IHA_SG_SIZE, 1434 1.3.2.2 nathanw BUS_DMASYNC_PREWRITE); 1435 1.3.2.2 nathanw 1436 1.3.2.2 nathanw scb->bufaddr += (i - scb->sg_index) * 1437 1.3.2.2 nathanw sizeof(struct iha_sg_element); 1438 1.3.2.2 nathanw scb->sg_size = scb->sg_max - i; 1439 1.3.2.2 nathanw scb->sg_index = i; 1440 1.3.2.2 nathanw 1441 1.3.2.2 nathanw return (4); 1442 1.3.2.2 nathanw } 1443 1.3.2.2 nathanw } 1444 1.3.2.2 nathanw return (6); 1445 1.3.2.2 nathanw 1446 1.3.2.2 nathanw } else 1447 1.3.2.2 nathanw scb->bufaddr += xcnt; 1448 1.3.2.2 nathanw 1449 1.3.2.2 nathanw return (4); 1450 1.3.2.2 nathanw } 1451 1.3.2.2 nathanw 1452 1.3.2.2 nathanw /* 1453 1.3.2.2 nathanw * tul_state_6 - finish off the active scb (may require several 1454 1.3.2.2 nathanw * iterations if PHASE_MSG_IN) and return -1 to indicate 1455 1.3.2.2 nathanw * the bus is free. 1456 1.3.2.2 nathanw */ 1457 1.3.2.2 nathanw static int 1458 1.3.2.2 nathanw tul_state_6(sc) 1459 1.3.2.2 nathanw struct iha_softc *sc; 1460 1.3.2.2 nathanw { 1461 1.3.2.2 nathanw 1462 1.3.2.2 nathanw for (;;) { 1463 1.3.2.2 nathanw switch (sc->sc_phase) { 1464 1.3.2.2 nathanw case PHASE_STATUS_IN: 1465 1.3.2.2 nathanw if (tul_status_msg(sc) == -1) 1466 1.3.2.2 nathanw return (-1); 1467 1.3.2.2 nathanw break; 1468 1.3.2.2 nathanw 1469 1.3.2.2 nathanw case PHASE_MSG_IN: 1470 1.3.2.2 nathanw sc->sc_actscb->nextstat = 6; 1471 1.3.2.2 nathanw if ((tul_msgin(sc)) == -1) 1472 1.3.2.2 nathanw return (-1); 1473 1.3.2.2 nathanw break; 1474 1.3.2.2 nathanw 1475 1.3.2.2 nathanw case PHASE_MSG_OUT: 1476 1.3.2.2 nathanw if ((tul_msgout(sc, MSG_NOOP)) == -1) 1477 1.3.2.2 nathanw return (-1); 1478 1.3.2.2 nathanw break; 1479 1.3.2.2 nathanw 1480 1.3.2.2 nathanw case PHASE_DATA_IN: 1481 1.3.2.2 nathanw if (tul_xpad_in(sc) == -1) 1482 1.3.2.2 nathanw return (-1); 1483 1.3.2.2 nathanw break; 1484 1.3.2.2 nathanw 1485 1.3.2.2 nathanw case PHASE_DATA_OUT: 1486 1.3.2.2 nathanw if (tul_xpad_out(sc) == -1) 1487 1.3.2.2 nathanw return (-1); 1488 1.3.2.2 nathanw break; 1489 1.3.2.2 nathanw 1490 1.3.2.2 nathanw default: 1491 1.3.2.2 nathanw tul_bad_seq(sc); 1492 1.3.2.2 nathanw return (-1); 1493 1.3.2.2 nathanw } 1494 1.3.2.2 nathanw } 1495 1.3.2.2 nathanw } 1496 1.3.2.2 nathanw 1497 1.3.2.2 nathanw /* 1498 1.3.2.2 nathanw * tul_state_8 - reset the active device and all busy SCBs using it 1499 1.3.2.2 nathanw */ 1500 1.3.2.2 nathanw static int 1501 1.3.2.2 nathanw tul_state_8(sc) 1502 1.3.2.2 nathanw struct iha_softc *sc; 1503 1.3.2.2 nathanw { 1504 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1505 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1506 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1507 1.3.2.2 nathanw int i; 1508 1.3.2.2 nathanw u_int8_t tar; 1509 1.3.2.2 nathanw 1510 1.3.2.2 nathanw if (sc->sc_phase == PHASE_MSG_OUT) { 1511 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_BUS_DEV_RESET); 1512 1.3.2.2 nathanw 1513 1.3.2.2 nathanw scb = sc->sc_actscb; 1514 1.3.2.2 nathanw 1515 1.3.2.2 nathanw /* This SCB finished correctly -- resetting the device */ 1516 1.3.2.2 nathanw tul_append_done_scb(sc, scb, HOST_OK); 1517 1.3.2.2 nathanw 1518 1.3.2.2 nathanw tul_reset_tcs(scb->tcs, sc->sc_sconf1); 1519 1.3.2.2 nathanw 1520 1.3.2.2 nathanw tar = scb->target; 1521 1.3.2.2 nathanw for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1522 1.3.2.2 nathanw if (scb->target == tar) 1523 1.3.2.2 nathanw switch (scb->status) { 1524 1.3.2.2 nathanw case STATUS_BUSY: 1525 1.3.2.2 nathanw tul_append_done_scb(sc, 1526 1.3.2.2 nathanw scb, HOST_DEV_RST); 1527 1.3.2.2 nathanw break; 1528 1.3.2.2 nathanw 1529 1.3.2.2 nathanw case STATUS_SELECT: 1530 1.3.2.2 nathanw tul_push_pend_scb(sc, scb); 1531 1.3.2.2 nathanw break; 1532 1.3.2.2 nathanw 1533 1.3.2.2 nathanw default: 1534 1.3.2.2 nathanw break; 1535 1.3.2.2 nathanw } 1536 1.3.2.2 nathanw 1537 1.3.2.2 nathanw sc->sc_flags |= FLAG_EXPECT_DISC; 1538 1.3.2.2 nathanw 1539 1.3.2.2 nathanw if (tul_wait(sc, XF_FIFO_OUT) == -1) 1540 1.3.2.2 nathanw return (-1); 1541 1.3.2.2 nathanw } 1542 1.3.2.2 nathanw 1543 1.3.2.2 nathanw tul_bad_seq(sc); 1544 1.3.2.2 nathanw return (-1); 1545 1.3.2.2 nathanw } 1546 1.3.2.2 nathanw 1547 1.3.2.2 nathanw /* 1548 1.3.2.2 nathanw * tul_xfer_data - initiate the DMA xfer of the data 1549 1.3.2.2 nathanw */ 1550 1.3.2.2 nathanw static int 1551 1.3.2.2 nathanw tul_xfer_data(sc, scb, direction) 1552 1.3.2.2 nathanw struct iha_softc *sc; 1553 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1554 1.3.2.2 nathanw int direction; 1555 1.3.2.2 nathanw { 1556 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1557 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1558 1.3.2.2 nathanw u_int32_t xferlen; 1559 1.3.2.2 nathanw u_int8_t xfertype; 1560 1.3.2.2 nathanw 1561 1.3.2.2 nathanw if ((scb->flags & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) != direction) 1562 1.3.2.2 nathanw return (6); /* wrong direction, abandon I/O */ 1563 1.3.2.2 nathanw 1564 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, scb->buflen); 1565 1.3.2.2 nathanw 1566 1.3.2.2 nathanw if ((scb->flags & FLAG_SG) == 0) { 1567 1.3.2.2 nathanw xferlen = scb->buflen; 1568 1.3.2.2 nathanw xfertype = (direction == XS_CTL_DATA_IN) ? ST_X_IN : ST_X_OUT; 1569 1.3.2.2 nathanw 1570 1.3.2.2 nathanw } else { 1571 1.3.2.2 nathanw xferlen = scb->sg_size * sizeof(struct iha_sg_element); 1572 1.3.2.2 nathanw xfertype = (direction == XS_CTL_DATA_IN) ? ST_SG_IN : ST_SG_OUT; 1573 1.3.2.2 nathanw } 1574 1.3.2.2 nathanw 1575 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_DXC, xferlen); 1576 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_DXPA, scb->bufaddr); 1577 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_DCMD, xfertype); 1578 1.3.2.2 nathanw 1579 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCMD, 1580 1.3.2.2 nathanw (direction == XS_CTL_DATA_IN) ? XF_DMA_IN : XF_DMA_OUT); 1581 1.3.2.2 nathanw 1582 1.3.2.2 nathanw scb->nextstat = 5; 1583 1.3.2.2 nathanw 1584 1.3.2.2 nathanw return (0); 1585 1.3.2.2 nathanw } 1586 1.3.2.2 nathanw 1587 1.3.2.2 nathanw static int 1588 1.3.2.2 nathanw tul_xpad_in(sc) 1589 1.3.2.2 nathanw struct iha_softc *sc; 1590 1.3.2.2 nathanw { 1591 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1592 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1593 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1594 1.3.2.2 nathanw 1595 1.3.2.2 nathanw if ((scb->flags & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) != 0) 1596 1.3.2.2 nathanw scb->ha_stat = HOST_DO_DU; 1597 1.3.2.2 nathanw 1598 1.3.2.2 nathanw for (;;) { 1599 1.3.2.2 nathanw if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 1600 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 1601 1.3.2.2 nathanw else 1602 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1603 1.3.2.2 nathanw 1604 1.3.2.2 nathanw switch (tul_wait(sc, XF_FIFO_IN)) { 1605 1.3.2.2 nathanw case -1: 1606 1.3.2.2 nathanw return (-1); 1607 1.3.2.2 nathanw 1608 1.3.2.2 nathanw case PHASE_DATA_IN: 1609 1.3.2.2 nathanw bus_space_read_1(iot, ioh, TUL_SFIFO); 1610 1.3.2.2 nathanw break; 1611 1.3.2.2 nathanw 1612 1.3.2.2 nathanw default: 1613 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1614 1.3.2.2 nathanw return (6); 1615 1.3.2.2 nathanw } 1616 1.3.2.2 nathanw } 1617 1.3.2.2 nathanw } 1618 1.3.2.2 nathanw 1619 1.3.2.2 nathanw static int 1620 1.3.2.2 nathanw tul_xpad_out(sc) 1621 1.3.2.2 nathanw struct iha_softc *sc; 1622 1.3.2.2 nathanw { 1623 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1624 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1625 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1626 1.3.2.2 nathanw 1627 1.3.2.2 nathanw if ((scb->flags & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) != 0) 1628 1.3.2.2 nathanw scb->ha_stat = HOST_DO_DU; 1629 1.3.2.2 nathanw 1630 1.3.2.2 nathanw for (;;) { 1631 1.3.2.2 nathanw if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 1632 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 1633 1.3.2.2 nathanw else 1634 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1635 1.3.2.2 nathanw 1636 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 1637 1.3.2.2 nathanw 1638 1.3.2.2 nathanw switch (tul_wait(sc, XF_FIFO_OUT)) { 1639 1.3.2.2 nathanw case -1: 1640 1.3.2.2 nathanw return (-1); 1641 1.3.2.2 nathanw 1642 1.3.2.2 nathanw case PHASE_DATA_OUT: 1643 1.3.2.2 nathanw break; 1644 1.3.2.2 nathanw 1645 1.3.2.2 nathanw default: 1646 1.3.2.2 nathanw /* Disable wide CPU to allow read 16 bits */ 1647 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1648 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1649 1.3.2.2 nathanw return (6); 1650 1.3.2.2 nathanw } 1651 1.3.2.2 nathanw } 1652 1.3.2.2 nathanw } 1653 1.3.2.2 nathanw 1654 1.3.2.2 nathanw static int 1655 1.3.2.2 nathanw tul_status_msg(sc) 1656 1.3.2.2 nathanw struct iha_softc *sc; 1657 1.3.2.2 nathanw { 1658 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1659 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1660 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1661 1.3.2.2 nathanw u_int8_t msg; 1662 1.3.2.2 nathanw int phase; 1663 1.3.2.2 nathanw 1664 1.3.2.2 nathanw if ((phase = tul_wait(sc, CMD_COMP)) == -1) 1665 1.3.2.2 nathanw return (-1); 1666 1.3.2.2 nathanw 1667 1.3.2.2 nathanw scb = sc->sc_actscb; 1668 1.3.2.2 nathanw 1669 1.3.2.2 nathanw scb->ta_stat = bus_space_read_1(iot, ioh, TUL_SFIFO); 1670 1.3.2.2 nathanw 1671 1.3.2.2 nathanw if (phase == PHASE_MSG_OUT) { 1672 1.3.2.2 nathanw if ((sc->sc_status0 & SPERR) == 0) 1673 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_NOOP); 1674 1.3.2.2 nathanw else 1675 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, 1676 1.3.2.2 nathanw MSG_PARITY_ERROR); 1677 1.3.2.2 nathanw 1678 1.3.2.2 nathanw return (tul_wait(sc, XF_FIFO_OUT)); 1679 1.3.2.2 nathanw 1680 1.3.2.2 nathanw } else if (phase == PHASE_MSG_IN) { 1681 1.3.2.2 nathanw msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 1682 1.3.2.2 nathanw 1683 1.3.2.2 nathanw if ((sc->sc_status0 & SPERR) != 0) 1684 1.3.2.2 nathanw switch (tul_wait(sc, MSG_ACCEPT)) { 1685 1.3.2.2 nathanw case -1: 1686 1.3.2.2 nathanw return (-1); 1687 1.3.2.2 nathanw case PHASE_MSG_OUT: 1688 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, 1689 1.3.2.2 nathanw MSG_PARITY_ERROR); 1690 1.3.2.2 nathanw return (tul_wait(sc, XF_FIFO_OUT)); 1691 1.3.2.2 nathanw default: 1692 1.3.2.2 nathanw tul_bad_seq(sc); 1693 1.3.2.2 nathanw return (-1); 1694 1.3.2.2 nathanw } 1695 1.3.2.2 nathanw 1696 1.3.2.2 nathanw if (msg == MSG_CMDCOMPLETE) { 1697 1.3.2.2 nathanw if ((scb->ta_stat & 1698 1.3.2.2 nathanw (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) { 1699 1.3.2.2 nathanw tul_bad_seq(sc); 1700 1.3.2.2 nathanw return (-1); 1701 1.3.2.2 nathanw } 1702 1.3.2.2 nathanw sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 1703 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1704 1.3.2.2 nathanw return (tul_wait(sc, MSG_ACCEPT)); 1705 1.3.2.2 nathanw } 1706 1.3.2.2 nathanw 1707 1.3.2.2 nathanw if ((msg == MSG_LINK_CMD_COMPLETE) 1708 1.3.2.2 nathanw || (msg == MSG_LINK_CMD_COMPLETEF)) { 1709 1.3.2.2 nathanw if ((scb->ta_stat & 1710 1.3.2.2 nathanw (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) 1711 1.3.2.2 nathanw return (tul_wait(sc, MSG_ACCEPT)); 1712 1.3.2.2 nathanw } 1713 1.3.2.2 nathanw } 1714 1.3.2.2 nathanw 1715 1.3.2.2 nathanw tul_bad_seq(sc); 1716 1.3.2.2 nathanw return (-1); 1717 1.3.2.2 nathanw } 1718 1.3.2.2 nathanw 1719 1.3.2.2 nathanw /* 1720 1.3.2.2 nathanw * tul_busfree - SCSI bus free detected as a result of a TIMEOUT or 1721 1.3.2.2 nathanw * DISCONNECT interrupt. Reset the tulip FIFO and 1722 1.3.2.2 nathanw * SCONFIG0 and enable hardware reselect. Move any active 1723 1.3.2.2 nathanw * SCB to sc_donescb list. Return an appropriate host status 1724 1.3.2.2 nathanw * if an I/O was active. 1725 1.3.2.2 nathanw */ 1726 1.3.2.2 nathanw static void 1727 1.3.2.2 nathanw tul_busfree(sc) 1728 1.3.2.2 nathanw struct iha_softc *sc; 1729 1.3.2.2 nathanw { 1730 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1731 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1732 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1733 1.3.2.2 nathanw 1734 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1735 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, SCONFIG0DEFAULT); 1736 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1737 1.3.2.2 nathanw 1738 1.3.2.2 nathanw scb = sc->sc_actscb; 1739 1.3.2.2 nathanw 1740 1.3.2.2 nathanw if (scb != NULL) { 1741 1.3.2.2 nathanw if (scb->status == STATUS_SELECT) 1742 1.3.2.2 nathanw /* selection timeout */ 1743 1.3.2.2 nathanw tul_append_done_scb(sc, scb, HOST_SEL_TOUT); 1744 1.3.2.2 nathanw else 1745 1.3.2.2 nathanw /* Unexpected bus free */ 1746 1.3.2.2 nathanw tul_append_done_scb(sc, scb, HOST_BAD_PHAS); 1747 1.3.2.2 nathanw } 1748 1.3.2.2 nathanw } 1749 1.3.2.2 nathanw 1750 1.3.2.2 nathanw static void 1751 1.3.2.2 nathanw tul_reset_scsi_bus(sc) 1752 1.3.2.2 nathanw struct iha_softc *sc; 1753 1.3.2.2 nathanw { 1754 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1755 1.3.2.2 nathanw struct tcs *tcs; 1756 1.3.2.2 nathanw int i, s; 1757 1.3.2.2 nathanw 1758 1.3.2.2 nathanw s = splbio(); 1759 1.3.2.2 nathanw 1760 1.3.2.2 nathanw tul_reset_dma(sc); 1761 1.3.2.2 nathanw 1762 1.3.2.2 nathanw for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1763 1.3.2.2 nathanw switch (scb->status) { 1764 1.3.2.2 nathanw case STATUS_BUSY: 1765 1.3.2.2 nathanw tul_append_done_scb(sc, scb, HOST_SCSI_RST); 1766 1.3.2.2 nathanw break; 1767 1.3.2.2 nathanw 1768 1.3.2.2 nathanw case STATUS_SELECT: 1769 1.3.2.2 nathanw tul_push_pend_scb(sc, scb); 1770 1.3.2.2 nathanw break; 1771 1.3.2.2 nathanw 1772 1.3.2.2 nathanw default: 1773 1.3.2.2 nathanw break; 1774 1.3.2.2 nathanw } 1775 1.3.2.2 nathanw 1776 1.3.2.2 nathanw for (i = 0, tcs = sc->sc_tcs; i < IHA_MAX_TARGETS; i++, tcs++) 1777 1.3.2.2 nathanw tul_reset_tcs(tcs, sc->sc_sconf1); 1778 1.3.2.2 nathanw 1779 1.3.2.2 nathanw splx(s); 1780 1.3.2.2 nathanw } 1781 1.3.2.2 nathanw 1782 1.3.2.2 nathanw /* 1783 1.3.2.2 nathanw * tul_resel - handle a detected SCSI bus reselection request. 1784 1.3.2.2 nathanw */ 1785 1.3.2.2 nathanw static int 1786 1.3.2.2 nathanw tul_resel(sc) 1787 1.3.2.2 nathanw struct iha_softc *sc; 1788 1.3.2.2 nathanw { 1789 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1790 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1791 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1792 1.3.2.2 nathanw struct tcs *tcs; 1793 1.3.2.2 nathanw u_int8_t tag, target, lun, msg, abortmsg; 1794 1.3.2.2 nathanw 1795 1.3.2.2 nathanw if (sc->sc_actscb != NULL) { 1796 1.3.2.2 nathanw if ((sc->sc_actscb->status == STATUS_SELECT)) 1797 1.3.2.2 nathanw /* sets ActScb to NULL */ 1798 1.3.2.2 nathanw tul_push_pend_scb(sc, sc->sc_actscb); 1799 1.3.2.2 nathanw else 1800 1.3.2.2 nathanw sc->sc_actscb = NULL; 1801 1.3.2.2 nathanw } 1802 1.3.2.2 nathanw 1803 1.3.2.2 nathanw target = bus_space_read_1(iot, ioh, TUL_SBID); 1804 1.3.2.2 nathanw lun = bus_space_read_1(iot, ioh, TUL_SALVC) & MSG_IDENTIFY_LUNMASK; 1805 1.3.2.2 nathanw 1806 1.3.2.2 nathanw tcs = &sc->sc_tcs[target]; 1807 1.3.2.2 nathanw 1808 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 1809 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 1810 1.3.2.2 nathanw 1811 1.3.2.2 nathanw abortmsg = MSG_ABORT; /* until a valid tag has been obtained */ 1812 1.3.2.2 nathanw 1813 1.3.2.2 nathanw if (tcs->ntagscb != NULL) 1814 1.3.2.2 nathanw /* There is a non-tagged I/O active on the target */ 1815 1.3.2.2 nathanw scb = tcs->ntagscb; 1816 1.3.2.2 nathanw 1817 1.3.2.2 nathanw else { 1818 1.3.2.2 nathanw /* 1819 1.3.2.2 nathanw * Since there is no active non-tagged operation 1820 1.3.2.2 nathanw * read the tag type, the tag itself, and find 1821 1.3.2.2 nathanw * the appropriate scb by indexing sc_scb with 1822 1.3.2.2 nathanw * the tag. 1823 1.3.2.2 nathanw */ 1824 1.3.2.2 nathanw 1825 1.3.2.2 nathanw switch (tul_wait(sc, MSG_ACCEPT)) { 1826 1.3.2.2 nathanw case -1: 1827 1.3.2.2 nathanw return (-1); 1828 1.3.2.2 nathanw case PHASE_MSG_IN: 1829 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1830 1.3.2.2 nathanw if ((tul_wait(sc, XF_FIFO_IN)) == -1) 1831 1.3.2.2 nathanw return (-1); 1832 1.3.2.2 nathanw break; 1833 1.3.2.2 nathanw default: 1834 1.3.2.2 nathanw goto abort; 1835 1.3.2.2 nathanw } 1836 1.3.2.2 nathanw 1837 1.3.2.2 nathanw msg = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag Msg */ 1838 1.3.2.2 nathanw 1839 1.3.2.2 nathanw if ((msg < MSG_SIMPLE_Q_TAG) || (msg > MSG_ORDERED_Q_TAG)) 1840 1.3.2.2 nathanw goto abort; 1841 1.3.2.2 nathanw 1842 1.3.2.2 nathanw switch (tul_wait(sc, MSG_ACCEPT)) { 1843 1.3.2.2 nathanw case -1: 1844 1.3.2.2 nathanw return (-1); 1845 1.3.2.2 nathanw case PHASE_MSG_IN: 1846 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1847 1.3.2.2 nathanw if ((tul_wait(sc, XF_FIFO_IN)) == -1) 1848 1.3.2.2 nathanw return (-1); 1849 1.3.2.2 nathanw break; 1850 1.3.2.2 nathanw default: 1851 1.3.2.2 nathanw goto abort; 1852 1.3.2.2 nathanw } 1853 1.3.2.2 nathanw 1854 1.3.2.2 nathanw tag = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag ID */ 1855 1.3.2.2 nathanw scb = &sc->sc_scb[tag]; 1856 1.3.2.2 nathanw 1857 1.3.2.2 nathanw abortmsg = MSG_ABORT_TAG; /* Now that we have valdid tag! */ 1858 1.3.2.2 nathanw } 1859 1.3.2.2 nathanw 1860 1.3.2.2 nathanw if ((scb->target != target) 1861 1.3.2.2 nathanw || (scb->lun != lun) 1862 1.3.2.2 nathanw || (scb->status != STATUS_BUSY)) { 1863 1.3.2.2 nathanw abort: 1864 1.3.2.2 nathanw tul_msgout_abort(sc, abortmsg); 1865 1.3.2.2 nathanw return (-1); 1866 1.3.2.2 nathanw } 1867 1.3.2.2 nathanw 1868 1.3.2.2 nathanw sc->sc_actscb = scb; 1869 1.3.2.2 nathanw 1870 1.3.2.2 nathanw if (tul_wait(sc, MSG_ACCEPT) == -1) 1871 1.3.2.2 nathanw return (-1); 1872 1.3.2.2 nathanw 1873 1.3.2.2 nathanw return (tul_next_state(sc)); 1874 1.3.2.2 nathanw } 1875 1.3.2.2 nathanw 1876 1.3.2.2 nathanw static int 1877 1.3.2.2 nathanw tul_msgin(sc) 1878 1.3.2.2 nathanw struct iha_softc *sc; 1879 1.3.2.2 nathanw { 1880 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1881 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1882 1.3.2.2 nathanw int flags; 1883 1.3.2.2 nathanw int phase; 1884 1.3.2.2 nathanw u_int8_t msg; 1885 1.3.2.2 nathanw 1886 1.3.2.2 nathanw for (;;) { 1887 1.3.2.2 nathanw if ((bus_space_read_1(iot, ioh, TUL_SFIFOCNT) & FIFOC) > 0) 1888 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1889 1.3.2.2 nathanw 1890 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1891 1.3.2.2 nathanw 1892 1.3.2.2 nathanw phase = tul_wait(sc, XF_FIFO_IN); 1893 1.3.2.2 nathanw msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 1894 1.3.2.2 nathanw 1895 1.3.2.2 nathanw switch (msg) { 1896 1.3.2.2 nathanw case MSG_DISCONNECT: 1897 1.3.2.2 nathanw sc->sc_flags |= FLAG_EXPECT_DISC; 1898 1.3.2.2 nathanw if (tul_wait(sc, MSG_ACCEPT) != -1) 1899 1.3.2.2 nathanw tul_bad_seq(sc); 1900 1.3.2.2 nathanw phase = -1; 1901 1.3.2.2 nathanw break; 1902 1.3.2.2 nathanw case MSG_SAVEDATAPOINTER: 1903 1.3.2.2 nathanw case MSG_RESTOREPOINTERS: 1904 1.3.2.2 nathanw case MSG_NOOP: 1905 1.3.2.2 nathanw phase = tul_wait(sc, MSG_ACCEPT); 1906 1.3.2.2 nathanw break; 1907 1.3.2.2 nathanw case MSG_MESSAGE_REJECT: 1908 1.3.2.2 nathanw /* XXX - need to clear FIFO like other 'Clear ATN'?*/ 1909 1.3.2.2 nathanw tul_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1910 1.3.2.2 nathanw flags = sc->sc_actscb->tcs->flags; 1911 1.3.2.2 nathanw if ((flags & FLAG_NO_NEG_SYNC) == 0) 1912 1.3.2.2 nathanw tul_set_ssig(sc, REQ | BSY | SEL, ATN); 1913 1.3.2.2 nathanw phase = tul_wait(sc, MSG_ACCEPT); 1914 1.3.2.2 nathanw break; 1915 1.3.2.2 nathanw case MSG_EXTENDED: 1916 1.3.2.2 nathanw phase = tul_msgin_extend(sc); 1917 1.3.2.2 nathanw break; 1918 1.3.2.2 nathanw case MSG_IGN_WIDE_RESIDUE: 1919 1.3.2.2 nathanw phase = tul_msgin_ignore_wid_resid(sc); 1920 1.3.2.2 nathanw break; 1921 1.3.2.2 nathanw case MSG_CMDCOMPLETE: 1922 1.3.2.2 nathanw sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 1923 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1924 1.3.2.2 nathanw phase = tul_wait(sc, MSG_ACCEPT); 1925 1.3.2.2 nathanw if (phase != -1) { 1926 1.3.2.2 nathanw tul_bad_seq(sc); 1927 1.3.2.2 nathanw return (-1); 1928 1.3.2.2 nathanw } 1929 1.3.2.2 nathanw break; 1930 1.3.2.2 nathanw default: 1931 1.3.2.2 nathanw printf("[debug] tul_msgin: bad msg type: %d\n", msg); 1932 1.3.2.2 nathanw phase = tul_msgout_reject(sc); 1933 1.3.2.2 nathanw break; 1934 1.3.2.2 nathanw } 1935 1.3.2.2 nathanw 1936 1.3.2.2 nathanw if (phase != PHASE_MSG_IN) 1937 1.3.2.2 nathanw return (phase); 1938 1.3.2.2 nathanw } 1939 1.3.2.2 nathanw /* NOTREACHED */ 1940 1.3.2.2 nathanw } 1941 1.3.2.2 nathanw 1942 1.3.2.2 nathanw static int 1943 1.3.2.2 nathanw tul_msgin_ignore_wid_resid(sc) 1944 1.3.2.2 nathanw struct iha_softc *sc; 1945 1.3.2.2 nathanw { 1946 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1947 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1948 1.3.2.2 nathanw int phase; 1949 1.3.2.2 nathanw 1950 1.3.2.2 nathanw phase = tul_wait(sc, MSG_ACCEPT); 1951 1.3.2.2 nathanw 1952 1.3.2.2 nathanw if (phase == PHASE_MSG_IN) { 1953 1.3.2.2 nathanw if (tul_wait(sc, XF_FIFO_IN) == -1) 1954 1.3.2.2 nathanw return (-1); 1955 1.3.2.2 nathanw 1956 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, 0); /* put pad */ 1957 1.3.2.2 nathanw bus_space_read_1(iot, ioh, TUL_SFIFO); /* get IGNORE */ 1958 1.3.2.2 nathanw bus_space_read_1(iot, ioh, TUL_SFIFO); /* get pad */ 1959 1.3.2.2 nathanw 1960 1.3.2.2 nathanw return (tul_wait(sc, MSG_ACCEPT)); 1961 1.3.2.2 nathanw } 1962 1.3.2.2 nathanw else 1963 1.3.2.2 nathanw return (phase); 1964 1.3.2.2 nathanw } 1965 1.3.2.2 nathanw 1966 1.3.2.2 nathanw static int 1967 1.3.2.2 nathanw tul_msgin_extend(sc) 1968 1.3.2.2 nathanw struct iha_softc *sc; 1969 1.3.2.2 nathanw { 1970 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1971 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1972 1.3.2.2 nathanw int flags, i, phase, msglen, msgcode; 1973 1.3.2.2 nathanw 1974 1.3.2.2 nathanw /* 1975 1.3.2.2 nathanw * XXX - can we just stop reading and reject, or do we have to 1976 1.3.2.2 nathanw * read all input, discarding the excess, and then reject 1977 1.3.2.2 nathanw */ 1978 1.3.2.2 nathanw for (i = 0; i < IHA_MAX_EXTENDED_MSG; i++) { 1979 1.3.2.2 nathanw phase = tul_wait(sc, MSG_ACCEPT); 1980 1.3.2.2 nathanw 1981 1.3.2.2 nathanw if (phase != PHASE_MSG_IN) 1982 1.3.2.2 nathanw return (phase); 1983 1.3.2.2 nathanw 1984 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1985 1.3.2.2 nathanw 1986 1.3.2.2 nathanw if (tul_wait(sc, XF_FIFO_IN) == -1) 1987 1.3.2.2 nathanw return (-1); 1988 1.3.2.2 nathanw 1989 1.3.2.2 nathanw sc->sc_msg[i] = bus_space_read_1(iot, ioh, TUL_SFIFO); 1990 1.3.2.2 nathanw 1991 1.3.2.2 nathanw if (sc->sc_msg[0] == i) 1992 1.3.2.2 nathanw break; 1993 1.3.2.2 nathanw } 1994 1.3.2.2 nathanw 1995 1.3.2.2 nathanw msglen = sc->sc_msg[0]; 1996 1.3.2.2 nathanw msgcode = sc->sc_msg[1]; 1997 1.3.2.2 nathanw 1998 1.3.2.2 nathanw if ((msglen == MSG_EXT_SDTR_LEN) && (msgcode == MSG_EXT_SDTR)) { 1999 1.3.2.2 nathanw if (tul_msgin_sync(sc) == 0) { 2000 1.3.2.2 nathanw tul_sync_done(sc); 2001 1.3.2.2 nathanw return (tul_wait(sc, MSG_ACCEPT)); 2002 1.3.2.2 nathanw } 2003 1.3.2.2 nathanw 2004 1.3.2.2 nathanw tul_set_ssig(sc, REQ | BSY | SEL, ATN); 2005 1.3.2.2 nathanw 2006 1.3.2.2 nathanw phase = tul_wait(sc, MSG_ACCEPT); 2007 1.3.2.2 nathanw if (phase != PHASE_MSG_OUT) 2008 1.3.2.2 nathanw return (phase); 2009 1.3.2.2 nathanw 2010 1.3.2.2 nathanw /* Clear FIFO for important message - final SYNC offer */ 2011 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2012 1.3.2.2 nathanw 2013 1.3.2.2 nathanw tul_sync_done(sc); /* This is our final offer */ 2014 1.3.2.2 nathanw 2015 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXTENDED); 2016 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXT_SDTR_LEN); 2017 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXT_SDTR); 2018 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, sc->sc_msg[2]); 2019 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, sc->sc_msg[3]); 2020 1.3.2.2 nathanw 2021 1.3.2.2 nathanw } else if ((msglen == MSG_EXT_WDTR_LEN) && (msgcode == MSG_EXT_WDTR)) { 2022 1.3.2.2 nathanw 2023 1.3.2.2 nathanw flags = sc->sc_actscb->tcs->flags; 2024 1.3.2.2 nathanw 2025 1.3.2.2 nathanw if ((flags & FLAG_NO_WIDE) != 0) 2026 1.3.2.2 nathanw sc->sc_msg[2] = 0; /* Offer async xfers only */ 2027 1.3.2.2 nathanw 2028 1.3.2.2 nathanw else if (sc->sc_msg[2] > 2) /* BAD MSG: 2 is max value */ 2029 1.3.2.2 nathanw return (tul_msgout_reject(sc)); 2030 1.3.2.2 nathanw 2031 1.3.2.2 nathanw else if (sc->sc_msg[2] == 2) /* a request for 32 bit xfers*/ 2032 1.3.2.2 nathanw sc->sc_msg[2] = 1; /* Offer 16 instead */ 2033 1.3.2.2 nathanw 2034 1.3.2.2 nathanw else { 2035 1.3.2.2 nathanw tul_wdtr_done(sc); 2036 1.3.2.2 nathanw if ((flags & FLAG_NO_NEG_SYNC) == 0) 2037 1.3.2.2 nathanw tul_set_ssig(sc, REQ | BSY | SEL, ATN); 2038 1.3.2.2 nathanw return (tul_wait(sc, MSG_ACCEPT)); 2039 1.3.2.2 nathanw } 2040 1.3.2.2 nathanw 2041 1.3.2.2 nathanw tul_set_ssig(sc, REQ | BSY | SEL, ATN); 2042 1.3.2.2 nathanw 2043 1.3.2.2 nathanw phase = tul_wait(sc, MSG_ACCEPT); 2044 1.3.2.2 nathanw if (phase != PHASE_MSG_OUT) 2045 1.3.2.2 nathanw return (phase); 2046 1.3.2.2 nathanw 2047 1.3.2.2 nathanw /* WDTR msg out */ 2048 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXTENDED); 2049 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXT_WDTR_LEN); 2050 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXT_WDTR); 2051 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, sc->sc_msg[2]); 2052 1.3.2.2 nathanw 2053 1.3.2.2 nathanw } else 2054 1.3.2.2 nathanw return (tul_msgout_reject(sc)); 2055 1.3.2.2 nathanw 2056 1.3.2.2 nathanw return (tul_wait(sc, XF_FIFO_OUT)); 2057 1.3.2.2 nathanw } 2058 1.3.2.2 nathanw 2059 1.3.2.2 nathanw /* 2060 1.3.2.2 nathanw * tul_msgin_sync - check SDTR msg in sc_msg. If the offer is 2061 1.3.2.2 nathanw * acceptable leave sc_msg as is and return 0. 2062 1.3.2.2 nathanw * If the negotiation must continue, modify sc_msg 2063 1.3.2.2 nathanw * as needed and return 1. Else return 0. 2064 1.3.2.2 nathanw */ 2065 1.3.2.2 nathanw static int 2066 1.3.2.2 nathanw tul_msgin_sync(sc) 2067 1.3.2.2 nathanw struct iha_softc *sc; 2068 1.3.2.2 nathanw { 2069 1.3.2.2 nathanw int flags; 2070 1.3.2.2 nathanw int newoffer; 2071 1.3.2.2 nathanw u_int8_t default_period; 2072 1.3.2.2 nathanw 2073 1.3.2.2 nathanw flags = sc->sc_actscb->tcs->flags; 2074 1.3.2.2 nathanw 2075 1.3.2.2 nathanw default_period = tul_rate_tbl[flags & FLAG_SCSI_RATE]; 2076 1.3.2.2 nathanw 2077 1.3.2.2 nathanw if (sc->sc_msg[3] == 0) /* target offered async only. Accept it. */ 2078 1.3.2.2 nathanw return (0); 2079 1.3.2.2 nathanw 2080 1.3.2.2 nathanw newoffer = 0; 2081 1.3.2.2 nathanw 2082 1.3.2.2 nathanw if ((flags & FLAG_NO_SYNC) != 0) { 2083 1.3.2.2 nathanw sc->sc_msg[3] = 0; 2084 1.3.2.2 nathanw newoffer = 1; 2085 1.3.2.2 nathanw } 2086 1.3.2.2 nathanw 2087 1.3.2.2 nathanw if (sc->sc_msg[3] > IHA_MAX_OFFSET) { 2088 1.3.2.2 nathanw sc->sc_msg[3] = IHA_MAX_OFFSET; 2089 1.3.2.2 nathanw newoffer = 1; 2090 1.3.2.2 nathanw } 2091 1.3.2.2 nathanw 2092 1.3.2.2 nathanw if (sc->sc_msg[2] < default_period) { 2093 1.3.2.2 nathanw sc->sc_msg[2] = default_period; 2094 1.3.2.2 nathanw newoffer = 1; 2095 1.3.2.2 nathanw } 2096 1.3.2.2 nathanw 2097 1.3.2.2 nathanw if (sc->sc_msg[2] >= 59) { /* XXX magic */ 2098 1.3.2.2 nathanw sc->sc_msg[3] = 0; 2099 1.3.2.2 nathanw newoffer = 1; 2100 1.3.2.2 nathanw } 2101 1.3.2.2 nathanw 2102 1.3.2.2 nathanw return (newoffer); 2103 1.3.2.2 nathanw } 2104 1.3.2.2 nathanw 2105 1.3.2.2 nathanw static int 2106 1.3.2.2 nathanw tul_msgout(sc, msg) 2107 1.3.2.2 nathanw struct iha_softc *sc; 2108 1.3.2.2 nathanw u_int8_t msg; 2109 1.3.2.2 nathanw { 2110 1.3.2.2 nathanw 2111 1.3.2.2 nathanw bus_space_write_1(sc->sc_iot, sc->sc_ioh, TUL_SFIFO, msg); 2112 1.3.2.2 nathanw 2113 1.3.2.2 nathanw return (tul_wait(sc, XF_FIFO_OUT)); 2114 1.3.2.2 nathanw } 2115 1.3.2.2 nathanw 2116 1.3.2.2 nathanw static void 2117 1.3.2.2 nathanw tul_msgout_abort(sc, aborttype) 2118 1.3.2.2 nathanw struct iha_softc *sc; 2119 1.3.2.2 nathanw u_int8_t aborttype; 2120 1.3.2.2 nathanw { 2121 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2122 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2123 1.3.2.2 nathanw 2124 1.3.2.2 nathanw tul_set_ssig(sc, REQ | BSY | SEL, ATN); 2125 1.3.2.2 nathanw 2126 1.3.2.2 nathanw switch (tul_wait(sc, MSG_ACCEPT)) { 2127 1.3.2.2 nathanw case -1: 2128 1.3.2.2 nathanw break; 2129 1.3.2.2 nathanw 2130 1.3.2.2 nathanw case PHASE_MSG_OUT: 2131 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, aborttype); 2132 1.3.2.2 nathanw 2133 1.3.2.2 nathanw sc->sc_flags |= FLAG_EXPECT_DISC; 2134 1.3.2.2 nathanw 2135 1.3.2.2 nathanw if (tul_wait(sc, XF_FIFO_OUT) != -1) 2136 1.3.2.2 nathanw tul_bad_seq(sc); 2137 1.3.2.2 nathanw break; 2138 1.3.2.2 nathanw 2139 1.3.2.2 nathanw default: 2140 1.3.2.2 nathanw tul_bad_seq(sc); 2141 1.3.2.2 nathanw break; 2142 1.3.2.2 nathanw } 2143 1.3.2.2 nathanw } 2144 1.3.2.2 nathanw 2145 1.3.2.2 nathanw static int 2146 1.3.2.2 nathanw tul_msgout_reject(sc) 2147 1.3.2.2 nathanw struct iha_softc *sc; 2148 1.3.2.2 nathanw { 2149 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2150 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2151 1.3.2.2 nathanw int phase; 2152 1.3.2.2 nathanw 2153 1.3.2.2 nathanw tul_set_ssig(sc, REQ | BSY | SEL, ATN); 2154 1.3.2.2 nathanw 2155 1.3.2.2 nathanw if ((phase = tul_wait(sc, MSG_ACCEPT)) == -1) 2156 1.3.2.2 nathanw return (-1); 2157 1.3.2.2 nathanw 2158 1.3.2.2 nathanw if (phase == PHASE_MSG_OUT) { 2159 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_MESSAGE_REJECT); 2160 1.3.2.2 nathanw return (tul_wait(sc, XF_FIFO_OUT)); 2161 1.3.2.2 nathanw } 2162 1.3.2.2 nathanw 2163 1.3.2.2 nathanw return (phase); 2164 1.3.2.2 nathanw } 2165 1.3.2.2 nathanw 2166 1.3.2.2 nathanw static int 2167 1.3.2.2 nathanw tul_msgout_wide(sc) 2168 1.3.2.2 nathanw struct iha_softc *sc; 2169 1.3.2.2 nathanw { 2170 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2171 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2172 1.3.2.2 nathanw int phase; 2173 1.3.2.2 nathanw 2174 1.3.2.2 nathanw sc->sc_actscb->tcs->flags |= FLAG_WIDE_DONE; 2175 1.3.2.2 nathanw 2176 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXTENDED); 2177 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXT_WDTR_LEN); 2178 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXT_WDTR); 2179 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXT_WDTR_BUS_16_BIT); 2180 1.3.2.2 nathanw 2181 1.3.2.2 nathanw phase = tul_wait(sc, XF_FIFO_OUT); 2182 1.3.2.2 nathanw 2183 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2184 1.3.2.2 nathanw tul_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2185 1.3.2.2 nathanw 2186 1.3.2.2 nathanw return (phase); 2187 1.3.2.2 nathanw } 2188 1.3.2.2 nathanw 2189 1.3.2.2 nathanw static int 2190 1.3.2.2 nathanw tul_msgout_sync(sc) 2191 1.3.2.2 nathanw struct iha_softc *sc; 2192 1.3.2.2 nathanw { 2193 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2194 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2195 1.3.2.2 nathanw int rateindex; 2196 1.3.2.2 nathanw int phase; 2197 1.3.2.2 nathanw u_int8_t sync_rate; 2198 1.3.2.2 nathanw 2199 1.3.2.2 nathanw rateindex = sc->sc_actscb->tcs->flags & FLAG_SCSI_RATE; 2200 1.3.2.2 nathanw 2201 1.3.2.2 nathanw sync_rate = tul_rate_tbl[rateindex]; 2202 1.3.2.2 nathanw 2203 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXTENDED); 2204 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXT_SDTR_LEN); 2205 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXT_SDTR); 2206 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, sync_rate); 2207 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, IHA_MAX_OFFSET);/* REQ/ACK*/ 2208 1.3.2.2 nathanw 2209 1.3.2.2 nathanw phase = tul_wait(sc, XF_FIFO_OUT); 2210 1.3.2.2 nathanw 2211 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2212 1.3.2.2 nathanw tul_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2213 1.3.2.2 nathanw 2214 1.3.2.2 nathanw return (phase); 2215 1.3.2.2 nathanw } 2216 1.3.2.2 nathanw 2217 1.3.2.2 nathanw static void 2218 1.3.2.2 nathanw tul_wdtr_done(sc) 2219 1.3.2.2 nathanw struct iha_softc *sc; 2220 1.3.2.2 nathanw { 2221 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2222 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2223 1.3.2.2 nathanw struct tcs *tcs = sc->sc_actscb->tcs; 2224 1.3.2.2 nathanw 2225 1.3.2.2 nathanw tcs->syncm = 0; 2226 1.3.2.2 nathanw tcs->period = 0; 2227 1.3.2.2 nathanw tcs->offset = 0; 2228 1.3.2.2 nathanw 2229 1.3.2.2 nathanw if (sc->sc_msg[2] != 0) 2230 1.3.2.2 nathanw tcs->syncm |= PERIOD_WIDE_SCSI; 2231 1.3.2.2 nathanw 2232 1.3.2.2 nathanw tcs->sconfig0 &= ~ALTPD; 2233 1.3.2.2 nathanw tcs->flags &= ~FLAG_SYNC_DONE; 2234 1.3.2.2 nathanw tcs->flags |= FLAG_WIDE_DONE; 2235 1.3.2.2 nathanw 2236 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2237 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2238 1.3.2.2 nathanw } 2239 1.3.2.2 nathanw 2240 1.3.2.2 nathanw static void 2241 1.3.2.2 nathanw tul_sync_done(sc) 2242 1.3.2.2 nathanw struct iha_softc *sc; 2243 1.3.2.2 nathanw { 2244 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2245 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2246 1.3.2.2 nathanw struct tcs *tcs = sc->sc_actscb->tcs; 2247 1.3.2.2 nathanw int i; 2248 1.3.2.2 nathanw 2249 1.3.2.2 nathanw if ((tcs->flags & FLAG_SYNC_DONE) == 0) { 2250 1.3.2.2 nathanw tcs->period = sc->sc_msg[2]; 2251 1.3.2.2 nathanw tcs->offset = sc->sc_msg[3]; 2252 1.3.2.2 nathanw if (tcs->offset != 0) { 2253 1.3.2.2 nathanw tcs->syncm |= tcs->offset; 2254 1.3.2.2 nathanw 2255 1.3.2.2 nathanw /* pick the highest possible rate */ 2256 1.3.2.2 nathanw for (i = 0; i < 8; i++) 2257 1.3.2.2 nathanw if (tul_rate_tbl[i] >= tcs->period) 2258 1.3.2.2 nathanw break; 2259 1.3.2.2 nathanw 2260 1.3.2.2 nathanw tcs->syncm |= (i << 4); 2261 1.3.2.2 nathanw tcs->sconfig0 |= ALTPD; 2262 1.3.2.2 nathanw } 2263 1.3.2.2 nathanw 2264 1.3.2.2 nathanw tcs->flags |= FLAG_SYNC_DONE; 2265 1.3.2.2 nathanw 2266 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2267 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2268 1.3.2.2 nathanw } 2269 1.3.2.2 nathanw } 2270 1.3.2.2 nathanw 2271 1.3.2.2 nathanw void 2272 1.3.2.2 nathanw tul_reset_chip(sc) 2273 1.3.2.2 nathanw struct iha_softc *sc; 2274 1.3.2.2 nathanw { 2275 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2276 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2277 1.3.2.2 nathanw 2278 1.3.2.2 nathanw /* reset tulip chip */ 2279 1.3.2.2 nathanw 2280 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSCSI); 2281 1.3.2.2 nathanw 2282 1.3.2.2 nathanw do { 2283 1.3.2.2 nathanw sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 2284 1.3.2.2 nathanw } while ((sc->sc_sistat & SRSTD) == 0); 2285 1.3.2.2 nathanw 2286 1.3.2.2 nathanw tul_set_ssig(sc, 0, 0); 2287 1.3.2.2 nathanw 2288 1.3.2.2 nathanw bus_space_read_1(iot, ioh, TUL_SISTAT); /* Clear any active interrupt*/ 2289 1.3.2.2 nathanw } 2290 1.3.2.2 nathanw 2291 1.3.2.2 nathanw static void 2292 1.3.2.2 nathanw tul_select(sc, scb, select_type) 2293 1.3.2.2 nathanw struct iha_softc *sc; 2294 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 2295 1.3.2.2 nathanw u_int8_t select_type; 2296 1.3.2.2 nathanw { 2297 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2298 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2299 1.3.2.2 nathanw 2300 1.3.2.2 nathanw switch (select_type) { 2301 1.3.2.2 nathanw case SEL_ATN: 2302 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 2303 1.3.2.2 nathanw bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 2304 1.3.2.2 nathanw scb->cmd, scb->cmdlen); 2305 1.3.2.2 nathanw 2306 1.3.2.2 nathanw scb->nextstat = 2; 2307 1.3.2.2 nathanw break; 2308 1.3.2.2 nathanw 2309 1.3.2.2 nathanw case SELATNSTOP: 2310 1.3.2.2 nathanw scb->nextstat = 1; 2311 1.3.2.2 nathanw break; 2312 1.3.2.2 nathanw 2313 1.3.2.2 nathanw case SEL_ATN3: 2314 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 2315 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagmsg); 2316 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagid); 2317 1.3.2.2 nathanw 2318 1.3.2.2 nathanw bus_space_write_multi_1(iot, ioh, TUL_SFIFO, scb->cmd, 2319 1.3.2.2 nathanw scb->cmdlen); 2320 1.3.2.2 nathanw 2321 1.3.2.2 nathanw scb->nextstat = 2; 2322 1.3.2.2 nathanw break; 2323 1.3.2.2 nathanw 2324 1.3.2.2 nathanw default: 2325 1.3.2.2 nathanw printf("[debug] tul_select() - unknown select type = 0x%02x\n", 2326 1.3.2.2 nathanw select_type); 2327 1.3.2.2 nathanw return; 2328 1.3.2.2 nathanw } 2329 1.3.2.2 nathanw 2330 1.3.2.2 nathanw tul_del_pend_scb(sc, scb); 2331 1.3.2.2 nathanw scb->status = STATUS_SELECT; 2332 1.3.2.2 nathanw 2333 1.3.2.2 nathanw sc->sc_actscb = scb; 2334 1.3.2.2 nathanw 2335 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCMD, select_type); 2336 1.3.2.2 nathanw } 2337 1.3.2.2 nathanw 2338 1.3.2.2 nathanw /* 2339 1.3.2.2 nathanw * tul_wait - wait for an interrupt to service or a SCSI bus phase change 2340 1.3.2.2 nathanw * after writing the supplied command to the tulip chip. If 2341 1.3.2.2 nathanw * the command is NO_OP, skip the command writing. 2342 1.3.2.2 nathanw */ 2343 1.3.2.2 nathanw static int 2344 1.3.2.2 nathanw tul_wait(sc, cmd) 2345 1.3.2.2 nathanw struct iha_softc *sc; 2346 1.3.2.2 nathanw u_int8_t cmd; 2347 1.3.2.2 nathanw { 2348 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2349 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2350 1.3.2.2 nathanw 2351 1.3.2.2 nathanw if (cmd != NO_OP) 2352 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCMD, cmd); 2353 1.3.2.2 nathanw 2354 1.3.2.2 nathanw /* 2355 1.3.2.2 nathanw * Have to do this here, in addition to in iha_isr, because 2356 1.3.2.2 nathanw * interrupts might be turned off when we get here. 2357 1.3.2.2 nathanw */ 2358 1.3.2.2 nathanw do { 2359 1.3.2.2 nathanw sc->sc_status0 = bus_space_read_1(iot, ioh, TUL_STAT0); 2360 1.3.2.2 nathanw } while ((sc->sc_status0 & INTPD) == 0); 2361 1.3.2.2 nathanw 2362 1.3.2.2 nathanw sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 2363 1.3.2.2 nathanw sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 2364 1.3.2.2 nathanw 2365 1.3.2.2 nathanw sc->sc_phase = sc->sc_status0 & PH_MASK; 2366 1.3.2.2 nathanw 2367 1.3.2.2 nathanw if ((sc->sc_sistat & SRSTD) != 0) { 2368 1.3.2.2 nathanw /* SCSI bus reset interrupt */ 2369 1.3.2.2 nathanw tul_reset_scsi_bus(sc); 2370 1.3.2.2 nathanw return (-1); 2371 1.3.2.2 nathanw } 2372 1.3.2.2 nathanw 2373 1.3.2.2 nathanw if ((sc->sc_sistat & RSELED) != 0) 2374 1.3.2.2 nathanw /* Reselection interrupt */ 2375 1.3.2.2 nathanw return (tul_resel(sc)); 2376 1.3.2.2 nathanw 2377 1.3.2.2 nathanw if ((sc->sc_sistat & STIMEO) != 0) { 2378 1.3.2.2 nathanw /* selected/reselected timeout interrupt */ 2379 1.3.2.2 nathanw tul_busfree(sc); 2380 1.3.2.2 nathanw return (-1); 2381 1.3.2.2 nathanw } 2382 1.3.2.2 nathanw 2383 1.3.2.2 nathanw if ((sc->sc_sistat & DISCD) != 0) { 2384 1.3.2.2 nathanw /* BUS disconnection interrupt */ 2385 1.3.2.2 nathanw if ((sc->sc_flags & FLAG_EXPECT_DONE_DISC) != 0) { 2386 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2387 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, 2388 1.3.2.2 nathanw SCONFIG0DEFAULT); 2389 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2390 1.3.2.2 nathanw tul_append_done_scb(sc, sc->sc_actscb, HOST_OK); 2391 1.3.2.2 nathanw sc->sc_flags &= ~FLAG_EXPECT_DONE_DISC; 2392 1.3.2.2 nathanw 2393 1.3.2.2 nathanw } else if ((sc->sc_flags & FLAG_EXPECT_DISC) != 0) { 2394 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2395 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, 2396 1.3.2.2 nathanw SCONFIG0DEFAULT); 2397 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2398 1.3.2.2 nathanw sc->sc_actscb = NULL; 2399 1.3.2.2 nathanw sc->sc_flags &= ~FLAG_EXPECT_DISC; 2400 1.3.2.2 nathanw 2401 1.3.2.2 nathanw } else 2402 1.3.2.2 nathanw tul_busfree(sc); 2403 1.3.2.2 nathanw 2404 1.3.2.2 nathanw return (-1); 2405 1.3.2.2 nathanw } 2406 1.3.2.2 nathanw 2407 1.3.2.2 nathanw return (sc->sc_phase); 2408 1.3.2.2 nathanw } 2409 1.3.2.2 nathanw 2410 1.3.2.2 nathanw /* 2411 1.3.2.2 nathanw * tul_done_scb - We have a scb which has been processed by the 2412 1.3.2.2 nathanw * adaptor, now we look to see how the operation went. 2413 1.3.2.2 nathanw */ 2414 1.3.2.2 nathanw static void 2415 1.3.2.2 nathanw tul_done_scb(sc, scb) 2416 1.3.2.2 nathanw struct iha_softc *sc; 2417 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 2418 1.3.2.2 nathanw { 2419 1.3.2.2 nathanw struct scsipi_xfer *xs = scb->xs; 2420 1.3.2.2 nathanw 2421 1.3.2.2 nathanw if (xs != NULL) { 2422 1.3.2.2 nathanw /* Cancel the timeout. */ 2423 1.3.2.2 nathanw callout_stop(&xs->xs_callout); 2424 1.3.2.2 nathanw 2425 1.3.2.2 nathanw if (xs->datalen > 0) { 2426 1.3.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, scb->dmap, 2427 1.3.2.2 nathanw 0, scb->dmap->dm_mapsize, 2428 1.3.2.2 nathanw (xs->xs_control & XS_CTL_DATA_IN) ? 2429 1.3.2.2 nathanw BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2430 1.3.2.2 nathanw bus_dmamap_unload(sc->sc_dmat, scb->dmap); 2431 1.3.2.2 nathanw } 2432 1.3.2.2 nathanw 2433 1.3.2.2 nathanw xs->status = scb->ta_stat; 2434 1.3.2.2 nathanw 2435 1.3.2.2 nathanw switch (scb->ha_stat) { 2436 1.3.2.2 nathanw case HOST_OK: 2437 1.3.2.2 nathanw switch (scb->ta_stat) { 2438 1.3.2.2 nathanw case SCSI_OK: 2439 1.3.2.2 nathanw case SCSI_CONDITION_MET: 2440 1.3.2.2 nathanw case SCSI_INTERM: 2441 1.3.2.2 nathanw case SCSI_INTERM_COND_MET: 2442 1.3.2.2 nathanw xs->resid = scb->buflen; 2443 1.3.2.2 nathanw xs->error = XS_NOERROR; 2444 1.3.2.2 nathanw if ((scb->flags & FLAG_RSENS) != 0) 2445 1.3.2.2 nathanw xs->error = XS_SENSE; 2446 1.3.2.2 nathanw break; 2447 1.3.2.2 nathanw 2448 1.3.2.2 nathanw case SCSI_RESV_CONFLICT: 2449 1.3.2.2 nathanw case SCSI_BUSY: 2450 1.3.2.2 nathanw case SCSI_QUEUE_FULL: 2451 1.3.2.2 nathanw xs->error = XS_BUSY; 2452 1.3.2.2 nathanw break; 2453 1.3.2.2 nathanw 2454 1.3.2.2 nathanw case SCSI_TERMINATED: 2455 1.3.2.2 nathanw case SCSI_ACA_ACTIVE: 2456 1.3.2.2 nathanw case SCSI_CHECK: 2457 1.3.2.2 nathanw scb->tcs->flags &= 2458 1.3.2.2 nathanw ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 2459 1.3.2.2 nathanw 2460 1.3.2.2 nathanw if ((scb->flags & FLAG_RSENS) != 0 || 2461 1.3.2.2 nathanw tul_push_sense_request(sc, scb) != 0) { 2462 1.3.2.2 nathanw scb->flags &= FLAG_RSENS; 2463 1.3.2.2 nathanw printf("%s: request sense failed\n", 2464 1.3.2.2 nathanw sc->sc_dev.dv_xname); 2465 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 2466 1.3.2.2 nathanw break; 2467 1.3.2.2 nathanw } 2468 1.3.2.2 nathanw 2469 1.3.2.2 nathanw xs->error = XS_SENSE; 2470 1.3.2.2 nathanw return; 2471 1.3.2.2 nathanw 2472 1.3.2.2 nathanw default: 2473 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 2474 1.3.2.2 nathanw break; 2475 1.3.2.2 nathanw } 2476 1.3.2.2 nathanw break; 2477 1.3.2.2 nathanw 2478 1.3.2.2 nathanw case HOST_SEL_TOUT: 2479 1.3.2.2 nathanw xs->error = XS_SELTIMEOUT; 2480 1.3.2.2 nathanw break; 2481 1.3.2.2 nathanw 2482 1.3.2.2 nathanw case HOST_SCSI_RST: 2483 1.3.2.2 nathanw case HOST_DEV_RST: 2484 1.3.2.2 nathanw xs->error = XS_RESET; 2485 1.3.2.2 nathanw break; 2486 1.3.2.2 nathanw 2487 1.3.2.2 nathanw case HOST_SPERR: 2488 1.3.2.2 nathanw printf("%s: SCSI Parity error detected\n", 2489 1.3.2.2 nathanw sc->sc_dev.dv_xname); 2490 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 2491 1.3.2.2 nathanw break; 2492 1.3.2.2 nathanw 2493 1.3.2.2 nathanw case HOST_TIMED_OUT: 2494 1.3.2.2 nathanw xs->error = XS_TIMEOUT; 2495 1.3.2.2 nathanw break; 2496 1.3.2.2 nathanw 2497 1.3.2.2 nathanw case HOST_DO_DU: 2498 1.3.2.2 nathanw case HOST_BAD_PHAS: 2499 1.3.2.2 nathanw default: 2500 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 2501 1.3.2.2 nathanw break; 2502 1.3.2.2 nathanw } 2503 1.3.2.2 nathanw 2504 1.3.2.2 nathanw scsipi_done(xs); 2505 1.3.2.2 nathanw } 2506 1.3.2.2 nathanw 2507 1.3.2.2 nathanw tul_append_free_scb(sc, scb); 2508 1.3.2.2 nathanw } 2509 1.3.2.2 nathanw 2510 1.3.2.2 nathanw static void 2511 1.3.2.2 nathanw tul_timeout(arg) 2512 1.3.2.2 nathanw void *arg; 2513 1.3.2.2 nathanw { 2514 1.3.2.2 nathanw struct iha_scsi_req_q *scb = (struct iha_scsi_req_q *)arg; 2515 1.3.2.2 nathanw struct scsipi_xfer *xs = scb->xs; 2516 1.3.2.2 nathanw struct scsipi_periph *periph = xs->xs_periph; 2517 1.3.2.2 nathanw struct iha_softc *sc; 2518 1.3.2.2 nathanw 2519 1.3.2.2 nathanw sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 2520 1.3.2.2 nathanw 2521 1.3.2.2 nathanw if (xs == NULL) 2522 1.3.2.2 nathanw printf("[debug] tul_timeout called with xs == NULL\n"); 2523 1.3.2.2 nathanw 2524 1.3.2.2 nathanw else { 2525 1.3.2.2 nathanw scsipi_printaddr(periph); 2526 1.3.2.2 nathanw printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 2527 1.3.2.2 nathanw 2528 1.3.2.2 nathanw tul_abort_xs(sc, xs, HOST_TIMED_OUT); 2529 1.3.2.2 nathanw } 2530 1.3.2.2 nathanw } 2531 1.3.2.2 nathanw 2532 1.3.2.2 nathanw static void 2533 1.3.2.2 nathanw tul_exec_scb(sc, scb) 2534 1.3.2.2 nathanw struct iha_softc *sc; 2535 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 2536 1.3.2.2 nathanw { 2537 1.3.2.2 nathanw bus_space_tag_t iot; 2538 1.3.2.2 nathanw bus_space_handle_t ioh; 2539 1.3.2.2 nathanw bus_dmamap_t dm; 2540 1.3.2.2 nathanw struct scsipi_xfer *xs = scb->xs; 2541 1.3.2.2 nathanw int nseg, s; 2542 1.3.2.2 nathanw 2543 1.3.2.2 nathanw dm = scb->dmap; 2544 1.3.2.2 nathanw nseg = dm->dm_nsegs; 2545 1.3.2.2 nathanw 2546 1.3.2.2 nathanw if (nseg > 1) { 2547 1.3.2.2 nathanw struct iha_sg_element *sg = scb->sglist; 2548 1.3.2.2 nathanw int i; 2549 1.3.2.2 nathanw 2550 1.3.2.2 nathanw for (i = 0; i < nseg; i++) { 2551 1.3.2.2 nathanw sg[i].sg_len = htole32(dm->dm_segs[i].ds_len); 2552 1.3.2.2 nathanw sg[i].sg_addr = htole32(dm->dm_segs[i].ds_addr); 2553 1.3.2.2 nathanw } 2554 1.3.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2555 1.3.2.2 nathanw scb->sgoffset, IHA_SG_SIZE, 2556 1.3.2.2 nathanw BUS_DMASYNC_PREWRITE); 2557 1.3.2.2 nathanw 2558 1.3.2.2 nathanw scb->flags |= FLAG_SG; /* XXX */ 2559 1.3.2.2 nathanw scb->sg_size = scb->sg_max = nseg; 2560 1.3.2.2 nathanw 2561 1.3.2.2 nathanw scb->bufaddr = scb->sg_addr; 2562 1.3.2.2 nathanw } else 2563 1.3.2.2 nathanw scb->bufaddr = dm->dm_segs[0].ds_addr; 2564 1.3.2.2 nathanw 2565 1.3.2.2 nathanw if ((xs->xs_control & XS_CTL_POLL) == 0) { 2566 1.3.2.2 nathanw int timeout = xs->timeout; 2567 1.3.2.2 nathanw timeout = (timeout > 100000) ? 2568 1.3.2.2 nathanw timeout / 1000 * hz : timeout * hz / 1000; 2569 1.3.2.2 nathanw if (timeout == 0) 2570 1.3.2.2 nathanw timeout = 1; 2571 1.3.2.2 nathanw callout_reset(&xs->xs_callout, timeout, tul_timeout, scb); 2572 1.3.2.2 nathanw } 2573 1.3.2.2 nathanw 2574 1.3.2.2 nathanw s = splbio(); 2575 1.3.2.2 nathanw 2576 1.3.2.2 nathanw if (((scb->flags & XS_RESET) != 0) || (scb->cmd[0] == REQUEST_SENSE)) 2577 1.3.2.2 nathanw tul_push_pend_scb(sc, scb); /* Insert SCB at head of Pend */ 2578 1.3.2.2 nathanw else 2579 1.3.2.2 nathanw tul_append_pend_scb(sc, scb); /* Append SCB to tail of Pend */ 2580 1.3.2.2 nathanw 2581 1.3.2.2 nathanw /* 2582 1.3.2.2 nathanw * Run through tul_main() to ensure something is active, if 2583 1.3.2.2 nathanw * only this new SCB. 2584 1.3.2.2 nathanw */ 2585 1.3.2.2 nathanw if (sc->sc_semaph != SEMAPH_IN_MAIN) { 2586 1.3.2.2 nathanw iot = sc->sc_iot; 2587 1.3.2.2 nathanw ioh = sc->sc_ioh; 2588 1.3.2.2 nathanw 2589 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 2590 1.3.2.2 nathanw sc->sc_semaph = SEMAPH_IN_MAIN;; 2591 1.3.2.2 nathanw 2592 1.3.2.2 nathanw splx(s); 2593 1.3.2.2 nathanw tul_main(sc); 2594 1.3.2.2 nathanw s = splbio(); 2595 1.3.2.2 nathanw 2596 1.3.2.2 nathanw sc->sc_semaph = ~SEMAPH_IN_MAIN;; 2597 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 2598 1.3.2.2 nathanw } 2599 1.3.2.2 nathanw 2600 1.3.2.2 nathanw splx(s); 2601 1.3.2.2 nathanw } 2602 1.3.2.2 nathanw 2603 1.3.2.2 nathanw 2604 1.3.2.2 nathanw /* 2605 1.3.2.2 nathanw * tul_set_ssig - read the current scsi signal mask, then write a new 2606 1.3.2.2 nathanw * one which turns off/on the specified signals. 2607 1.3.2.2 nathanw */ 2608 1.3.2.2 nathanw static void 2609 1.3.2.2 nathanw tul_set_ssig(sc, offsigs, onsigs) 2610 1.3.2.2 nathanw struct iha_softc *sc; 2611 1.3.2.2 nathanw u_int8_t offsigs, onsigs; 2612 1.3.2.2 nathanw { 2613 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2614 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2615 1.3.2.2 nathanw u_int8_t currsigs; 2616 1.3.2.2 nathanw 2617 1.3.2.2 nathanw currsigs = bus_space_read_1(iot, ioh, TUL_SSIGI); 2618 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SSIGO, (currsigs & ~offsigs) | onsigs); 2619 1.3.2.2 nathanw } 2620 1.3.2.2 nathanw 2621 1.3.2.2 nathanw /* 2622 1.3.2.2 nathanw * tul_alloc_sglist - allocate and map sglist for SCB's 2623 1.3.2.2 nathanw */ 2624 1.3.2.2 nathanw static int 2625 1.3.2.2 nathanw tul_alloc_sglist(sc) 2626 1.3.2.2 nathanw struct iha_softc *sc; 2627 1.3.2.2 nathanw { 2628 1.3.2.2 nathanw bus_dma_segment_t seg; 2629 1.3.2.2 nathanw int error, rseg; 2630 1.3.2.2 nathanw 2631 1.3.2.2 nathanw /* 2632 1.3.2.2 nathanw * Allocate dma-safe memory for the SCB's sglist 2633 1.3.2.2 nathanw */ 2634 1.3.2.2 nathanw if ((error = bus_dmamem_alloc(sc->sc_dmat, 2635 1.3.2.2 nathanw IHA_SG_SIZE * IHA_MAX_SCB, 2636 1.3.2.2 nathanw PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 2637 1.3.2.2 nathanw printf(": unable to allocate sglist, error = %d\n", error); 2638 1.3.2.2 nathanw return (error); 2639 1.3.2.2 nathanw } 2640 1.3.2.2 nathanw if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 2641 1.3.2.2 nathanw IHA_SG_SIZE * IHA_MAX_SCB, (caddr_t *)&sc->sc_sglist, 2642 1.3.2.2 nathanw BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 2643 1.3.2.2 nathanw printf(": unable to map sglist, error = %d\n", error); 2644 1.3.2.2 nathanw return (error); 2645 1.3.2.2 nathanw } 2646 1.3.2.2 nathanw 2647 1.3.2.2 nathanw /* 2648 1.3.2.2 nathanw * Create and load the DMA map used for the SCBs 2649 1.3.2.2 nathanw */ 2650 1.3.2.2 nathanw if ((error = bus_dmamap_create(sc->sc_dmat, 2651 1.3.2.2 nathanw IHA_SG_SIZE * IHA_MAX_SCB, 1, IHA_SG_SIZE * IHA_MAX_SCB, 2652 1.3.2.2 nathanw 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 2653 1.3.2.2 nathanw printf(": unable to create control DMA map, error = %d\n", 2654 1.3.2.2 nathanw error); 2655 1.3.2.2 nathanw return (error); 2656 1.3.2.2 nathanw } 2657 1.3.2.2 nathanw if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 2658 1.3.2.2 nathanw sc->sc_sglist, IHA_SG_SIZE * IHA_MAX_SCB, 2659 1.3.2.2 nathanw NULL, BUS_DMA_NOWAIT)) != 0) { 2660 1.3.2.2 nathanw printf(": unable to load control DMA map, error = %d\n", error); 2661 1.3.2.2 nathanw return (error); 2662 1.3.2.2 nathanw } 2663 1.3.2.2 nathanw 2664 1.3.2.2 nathanw bzero(sc->sc_sglist, IHA_SG_SIZE * IHA_MAX_SCB); 2665 1.3.2.2 nathanw 2666 1.3.2.2 nathanw return (0); 2667 1.3.2.2 nathanw } 2668 1.3.2.2 nathanw 2669 1.3.2.2 nathanw /* 2670 1.3.2.2 nathanw * tul_read_eeprom - read Serial EEPROM value & set to defaults 2671 1.3.2.2 nathanw * if required. XXX - Writing does NOT work! 2672 1.3.2.2 nathanw */ 2673 1.3.2.2 nathanw void 2674 1.3.2.2 nathanw tul_read_eeprom(sc, eeprom) 2675 1.3.2.2 nathanw struct iha_softc *sc; 2676 1.3.2.2 nathanw struct iha_eeprom *eeprom; 2677 1.3.2.2 nathanw { 2678 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2679 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2680 1.3.2.2 nathanw u_int16_t *buf = (u_int16_t *)eeprom; 2681 1.3.2.2 nathanw u_int8_t gctrl; 2682 1.3.2.2 nathanw 2683 1.3.2.2 nathanw /*------Enable EEProm programming ---*/ 2684 1.3.2.2 nathanw gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) | EEPRG; 2685 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2686 1.3.2.2 nathanw 2687 1.3.2.2 nathanw /*------ Program default pattern ----*/ 2688 1.3.2.2 nathanw if (tul_se2_rd_all(sc, buf) == 0) { 2689 1.3.2.2 nathanw tul_se2_update_all(sc); 2690 1.3.2.2 nathanw if(tul_se2_rd_all(sc, buf) == 0) 2691 1.3.2.2 nathanw panic("could not program iha Tulip EEPROM\n"); 2692 1.3.2.2 nathanw } 2693 1.3.2.2 nathanw 2694 1.3.2.2 nathanw /*------ Disable EEProm programming ---*/ 2695 1.3.2.2 nathanw gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) & ~EEPRG; 2696 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2697 1.3.2.2 nathanw } 2698 1.3.2.2 nathanw 2699 1.3.2.2 nathanw /* 2700 1.3.2.2 nathanw * tul_se2_update_all - Update SCSI H/A configuration parameters from 2701 1.3.2.2 nathanw * serial EEPROM Setup default pattern. Only 2702 1.3.2.2 nathanw * change those values different from the values 2703 1.3.2.2 nathanw * in tul_nvram. 2704 1.3.2.2 nathanw */ 2705 1.3.2.2 nathanw void 2706 1.3.2.2 nathanw tul_se2_update_all(sc) 2707 1.3.2.2 nathanw struct iha_softc *sc; 2708 1.3.2.2 nathanw { 2709 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2710 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2711 1.3.2.2 nathanw u_int16_t *np; 2712 1.3.2.2 nathanw u_int32_t chksum; 2713 1.3.2.2 nathanw int i; 2714 1.3.2.2 nathanw 2715 1.3.2.2 nathanw /* Enable erase/write state of EEPROM */ 2716 1.3.2.2 nathanw tul_se2_instr(sc, ENABLE_ERASE); 2717 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2718 1.3.2.2 nathanw EEP_WAIT(); 2719 1.3.2.2 nathanw 2720 1.3.2.2 nathanw np = (u_int16_t *)&eeprom_default; 2721 1.3.2.2 nathanw 2722 1.3.2.2 nathanw for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2723 1.3.2.2 nathanw tul_se2_wr(sc, i, *np); 2724 1.3.2.2 nathanw chksum += *np++; 2725 1.3.2.2 nathanw } 2726 1.3.2.2 nathanw 2727 1.3.2.2 nathanw chksum &= 0x0000ffff; 2728 1.3.2.2 nathanw tul_se2_wr(sc, 31, chksum); 2729 1.3.2.2 nathanw 2730 1.3.2.2 nathanw /* Disable erase/write state of EEPROM */ 2731 1.3.2.2 nathanw tul_se2_instr(sc, 0); 2732 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2733 1.3.2.2 nathanw EEP_WAIT(); 2734 1.3.2.2 nathanw } 2735 1.3.2.2 nathanw 2736 1.3.2.2 nathanw /* 2737 1.3.2.2 nathanw * tul_se2_wr - write the given 16 bit value into the Serial EEPROM 2738 1.3.2.2 nathanw * at the specified offset 2739 1.3.2.2 nathanw */ 2740 1.3.2.2 nathanw void 2741 1.3.2.2 nathanw tul_se2_wr(sc, addr, writeword) 2742 1.3.2.2 nathanw struct iha_softc *sc; 2743 1.3.2.2 nathanw int addr; 2744 1.3.2.2 nathanw u_int16_t writeword; 2745 1.3.2.2 nathanw { 2746 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2747 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2748 1.3.2.2 nathanw int i, bit; 2749 1.3.2.2 nathanw 2750 1.3.2.2 nathanw /* send 'WRITE' Instruction == address | WRITE bit */ 2751 1.3.2.2 nathanw tul_se2_instr(sc, addr | WRITE); 2752 1.3.2.2 nathanw 2753 1.3.2.2 nathanw for (i = 16; i > 0; i--) { 2754 1.3.2.2 nathanw if (writeword & (1 << (i - 1))) 2755 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRDO); 2756 1.3.2.2 nathanw else 2757 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2758 1.3.2.2 nathanw EEP_WAIT(); 2759 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2760 1.3.2.2 nathanw EEP_WAIT(); 2761 1.3.2.2 nathanw } 2762 1.3.2.2 nathanw 2763 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2764 1.3.2.2 nathanw EEP_WAIT(); 2765 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2766 1.3.2.2 nathanw EEP_WAIT(); 2767 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2768 1.3.2.2 nathanw EEP_WAIT(); 2769 1.3.2.2 nathanw 2770 1.3.2.2 nathanw for (;;) { 2771 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2772 1.3.2.2 nathanw EEP_WAIT(); 2773 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2774 1.3.2.2 nathanw EEP_WAIT(); 2775 1.3.2.2 nathanw bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI; 2776 1.3.2.2 nathanw EEP_WAIT(); 2777 1.3.2.2 nathanw if (bit != 0) 2778 1.3.2.2 nathanw break; /* write complete */ 2779 1.3.2.2 nathanw } 2780 1.3.2.2 nathanw 2781 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2782 1.3.2.2 nathanw } 2783 1.3.2.2 nathanw 2784 1.3.2.2 nathanw /* 2785 1.3.2.2 nathanw * tul_se2_rd - read & return the 16 bit value at the specified 2786 1.3.2.2 nathanw * offset in the Serial E2PROM 2787 1.3.2.2 nathanw * 2788 1.3.2.2 nathanw */ 2789 1.3.2.2 nathanw u_int16_t 2790 1.3.2.2 nathanw tul_se2_rd(sc, addr) 2791 1.3.2.2 nathanw struct iha_softc *sc; 2792 1.3.2.2 nathanw int addr; 2793 1.3.2.2 nathanw { 2794 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2795 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2796 1.3.2.2 nathanw int i, bit; 2797 1.3.2.2 nathanw u_int16_t readword; 2798 1.3.2.2 nathanw 2799 1.3.2.2 nathanw /* Send 'READ' instruction == address | READ bit */ 2800 1.3.2.2 nathanw tul_se2_instr(sc, addr | READ); 2801 1.3.2.2 nathanw 2802 1.3.2.2 nathanw readword = 0; 2803 1.3.2.2 nathanw for (i = 16; i > 0; i--) { 2804 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2805 1.3.2.2 nathanw EEP_WAIT(); 2806 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2807 1.3.2.2 nathanw EEP_WAIT(); 2808 1.3.2.2 nathanw /* sample data after the following edge of clock */ 2809 1.3.2.2 nathanw bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI ? 1 : 0; 2810 1.3.2.2 nathanw EEP_WAIT(); 2811 1.3.2.2 nathanw 2812 1.3.2.2 nathanw readword |= bit << (i - 1); 2813 1.3.2.2 nathanw } 2814 1.3.2.2 nathanw 2815 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2816 1.3.2.2 nathanw 2817 1.3.2.2 nathanw return (readword); 2818 1.3.2.2 nathanw } 2819 1.3.2.2 nathanw 2820 1.3.2.2 nathanw /* 2821 1.3.2.2 nathanw * tul_se2_rd_all - Read SCSI H/A config parameters from serial EEPROM 2822 1.3.2.2 nathanw */ 2823 1.3.2.2 nathanw int 2824 1.3.2.2 nathanw tul_se2_rd_all(sc, buf) 2825 1.3.2.2 nathanw struct iha_softc *sc; 2826 1.3.2.2 nathanw u_int16_t *buf; 2827 1.3.2.2 nathanw { 2828 1.3.2.2 nathanw struct iha_eeprom *eeprom = (struct iha_eeprom *)buf; 2829 1.3.2.2 nathanw u_int32_t chksum; 2830 1.3.2.2 nathanw int i; 2831 1.3.2.2 nathanw 2832 1.3.2.2 nathanw for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2833 1.3.2.2 nathanw *buf = tul_se2_rd(sc, i); 2834 1.3.2.2 nathanw chksum += *buf++; 2835 1.3.2.2 nathanw } 2836 1.3.2.2 nathanw *buf = tul_se2_rd(sc, 31); /* just read checksum */ 2837 1.3.2.2 nathanw 2838 1.3.2.2 nathanw chksum &= 0x0000ffff; /* checksum is lower 16 bits of sum */ 2839 1.3.2.2 nathanw 2840 1.3.2.2 nathanw return (eeprom->signature == EEP_SIGNATURE) && 2841 1.3.2.2 nathanw (eeprom->checksum == chksum); 2842 1.3.2.2 nathanw } 2843 1.3.2.2 nathanw 2844 1.3.2.2 nathanw /* 2845 1.3.2.2 nathanw * tul_se2_instr - write an octet to serial E2PROM one bit at a time 2846 1.3.2.2 nathanw */ 2847 1.3.2.2 nathanw void 2848 1.3.2.2 nathanw tul_se2_instr(sc, instr) 2849 1.3.2.2 nathanw struct iha_softc *sc; 2850 1.3.2.2 nathanw int instr; 2851 1.3.2.2 nathanw { 2852 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2853 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2854 1.3.2.2 nathanw int b, i; 2855 1.3.2.2 nathanw 2856 1.3.2.2 nathanw b = NVRCS | NVRDO; /* Write the start bit (== 1) */ 2857 1.3.2.2 nathanw 2858 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2859 1.3.2.2 nathanw EEP_WAIT(); 2860 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2861 1.3.2.2 nathanw EEP_WAIT(); 2862 1.3.2.2 nathanw 2863 1.3.2.2 nathanw for (i = 8; i > 0; i--) { 2864 1.3.2.2 nathanw if (instr & (1 << (i - 1))) 2865 1.3.2.2 nathanw b = NVRCS | NVRDO; /* Write a 1 bit */ 2866 1.3.2.2 nathanw else 2867 1.3.2.2 nathanw b = NVRCS; /* Write a 0 bit */ 2868 1.3.2.2 nathanw 2869 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2870 1.3.2.2 nathanw EEP_WAIT(); 2871 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2872 1.3.2.2 nathanw EEP_WAIT(); 2873 1.3.2.2 nathanw } 2874 1.3.2.2 nathanw 2875 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2876 1.3.2.2 nathanw } 2877 1.3.2.2 nathanw 2878 1.3.2.2 nathanw /* 2879 1.3.2.2 nathanw * tul_reset_tcs - reset the target control structure pointed 2880 1.3.2.2 nathanw * to by tcs to default values. tcs flags 2881 1.3.2.2 nathanw * only has the negotiation done bits reset as 2882 1.3.2.2 nathanw * the other bits are fixed at initialization. 2883 1.3.2.2 nathanw */ 2884 1.3.2.2 nathanw void 2885 1.3.2.2 nathanw tul_reset_tcs(tcs, config0) 2886 1.3.2.2 nathanw struct tcs *tcs; 2887 1.3.2.2 nathanw u_int8_t config0; 2888 1.3.2.2 nathanw { 2889 1.3.2.2 nathanw 2890 1.3.2.2 nathanw tcs->flags &= ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 2891 1.3.2.2 nathanw tcs->period = 0; 2892 1.3.2.2 nathanw tcs->offset = 0; 2893 1.3.2.2 nathanw tcs->tagcnt = 0; 2894 1.3.2.2 nathanw tcs->ntagscb = NULL; 2895 1.3.2.2 nathanw tcs->syncm = 0; 2896 1.3.2.2 nathanw tcs->sconfig0 = config0; 2897 1.3.2.2 nathanw } 2898
Indexes created Thu Oct 23 22:10:10 GMT 2025