iha.c revision 1.3.2.6
1 1.3.2.6 nathanw /* $NetBSD: iha.c,v 1.3.2.6 2002/01/08 00:29:48 nathanw Exp $ */ 2 1.3.2.2 nathanw /* 3 1.3.2.2 nathanw * Initio INI-9xxxU/UW SCSI Device Driver 4 1.3.2.2 nathanw * 5 1.3.2.2 nathanw * Copyright (c) 2000 Ken Westerback 6 1.3.2.2 nathanw * All rights reserved. 7 1.3.2.2 nathanw * 8 1.3.2.2 nathanw * Redistribution and use in source and binary forms, with or without 9 1.3.2.2 nathanw * modification, are permitted provided that the following conditions 10 1.3.2.2 nathanw * are met: 11 1.3.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 12 1.3.2.2 nathanw * notice, this list of conditions and the following disclaimer, 13 1.3.2.2 nathanw * without modification, immediately at the beginning of the file. 14 1.3.2.2 nathanw * 2. The name of the author may not be used to endorse or promote products 15 1.3.2.2 nathanw * derived from this software without specific prior written permission. 16 1.3.2.2 nathanw * 17 1.3.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 1.3.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 1.3.2.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 1.3.2.2 nathanw * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 21 1.3.2.2 nathanw * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 1.3.2.2 nathanw * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 1.3.2.2 nathanw * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 1.3.2.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 1.3.2.2 nathanw * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 1.3.2.2 nathanw * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 1.3.2.2 nathanw * THE POSSIBILITY OF SUCH DAMAGE. 28 1.3.2.2 nathanw * 29 1.3.2.2 nathanw *------------------------------------------------------------------------- 30 1.3.2.2 nathanw * 31 1.3.2.2 nathanw * Ported from i91u.c, provided by Initio Corporation, which credits: 32 1.3.2.2 nathanw * 33 1.3.2.3 nathanw * Device driver for the INI-9XXXU/UW or INIC-940/950 PCI SCSI Controller. 34 1.3.2.2 nathanw * 35 1.3.2.2 nathanw * FreeBSD 36 1.3.2.2 nathanw * 37 1.3.2.2 nathanw * Written for 386bsd and FreeBSD by 38 1.3.2.2 nathanw * Winston Hung <winstonh (at) initio.com> 39 1.3.2.2 nathanw * 40 1.3.2.2 nathanw * Copyright (c) 1997-99 Initio Corp. All rights reserved. 41 1.3.2.2 nathanw * 42 1.3.2.2 nathanw *------------------------------------------------------------------------- 43 1.3.2.2 nathanw */ 44 1.3.2.2 nathanw 45 1.3.2.2 nathanw /* 46 1.3.2.2 nathanw * Ported to NetBSD by Izumi Tsutsui <tsutsui (at) ceres.dti.ne.jp> from OpenBSD: 47 1.3.2.2 nathanw * $OpenBSD: iha.c,v 1.3 2001/02/20 00:47:33 krw Exp $ 48 1.3.2.2 nathanw */ 49 1.3.2.2 nathanw 50 1.3.2.5 nathanw #include <sys/cdefs.h> 51 1.3.2.6 nathanw __KERNEL_RCSID(0, "$NetBSD: iha.c,v 1.3.2.6 2002/01/08 00:29:48 nathanw Exp $"); 52 1.3.2.5 nathanw 53 1.3.2.2 nathanw #include <sys/param.h> 54 1.3.2.2 nathanw #include <sys/systm.h> 55 1.3.2.2 nathanw #include <sys/kernel.h> 56 1.3.2.2 nathanw #include <sys/buf.h> 57 1.3.2.2 nathanw #include <sys/device.h> 58 1.3.2.2 nathanw #include <sys/malloc.h> 59 1.3.2.2 nathanw 60 1.3.2.2 nathanw #include <uvm/uvm_extern.h> 61 1.3.2.2 nathanw 62 1.3.2.2 nathanw #include <machine/bus.h> 63 1.3.2.2 nathanw #include <machine/intr.h> 64 1.3.2.2 nathanw 65 1.3.2.2 nathanw #include <dev/scsipi/scsi_all.h> 66 1.3.2.2 nathanw #include <dev/scsipi/scsipi_all.h> 67 1.3.2.2 nathanw #include <dev/scsipi/scsiconf.h> 68 1.3.2.2 nathanw #include <dev/scsipi/scsi_message.h> 69 1.3.2.2 nathanw 70 1.3.2.2 nathanw #include <dev/ic/ihareg.h> 71 1.3.2.2 nathanw #include <dev/ic/ihavar.h> 72 1.3.2.2 nathanw 73 1.3.2.2 nathanw /* 74 1.3.2.2 nathanw * SCSI Rate Table, indexed by FLAG_SCSI_RATE field of 75 1.3.2.2 nathanw * tcs flags. 76 1.3.2.2 nathanw */ 77 1.3.2.6 nathanw static const u_int8_t iha_rate_tbl[] = { 78 1.3.2.2 nathanw /* fast 20 */ 79 1.3.2.2 nathanw /* nanosecond divide by 4 */ 80 1.3.2.2 nathanw 12, /* 50ns, 20M */ 81 1.3.2.2 nathanw 18, /* 75ns, 13.3M */ 82 1.3.2.2 nathanw 25, /* 100ns, 10M */ 83 1.3.2.2 nathanw 31, /* 125ns, 8M */ 84 1.3.2.2 nathanw 37, /* 150ns, 6.6M */ 85 1.3.2.2 nathanw 43, /* 175ns, 5.7M */ 86 1.3.2.2 nathanw 50, /* 200ns, 5M */ 87 1.3.2.2 nathanw 62 /* 250ns, 4M */ 88 1.3.2.2 nathanw }; 89 1.3.2.6 nathanw #define IHA_MAX_PERIOD 62 90 1.3.2.2 nathanw 91 1.3.2.3 nathanw #ifdef notused 92 1.3.2.2 nathanw static u_int16_t eeprom_default[EEPROM_SIZE] = { 93 1.3.2.2 nathanw /* -- Header ------------------------------------ */ 94 1.3.2.2 nathanw /* signature */ 95 1.3.2.2 nathanw EEP_SIGNATURE, 96 1.3.2.2 nathanw /* size, revision */ 97 1.3.2.2 nathanw EEP_WORD(EEPROM_SIZE * 2, 0x01), 98 1.3.2.2 nathanw /* -- Host Adapter Structure -------------------- */ 99 1.3.2.2 nathanw /* model */ 100 1.3.2.2 nathanw 0x0095, 101 1.3.2.2 nathanw /* model info, number of channel */ 102 1.3.2.2 nathanw EEP_WORD(0x00, 1), 103 1.3.2.2 nathanw /* BIOS config */ 104 1.3.2.2 nathanw EEP_BIOSCFG_DEFAULT, 105 1.3.2.2 nathanw /* host adapter config */ 106 1.3.2.2 nathanw 0, 107 1.3.2.2 nathanw 108 1.3.2.2 nathanw /* -- eeprom_adapter[0] ------------------------------- */ 109 1.3.2.2 nathanw /* ID, adapter config 1 */ 110 1.3.2.2 nathanw EEP_WORD(7, CFG_DEFAULT), 111 1.3.2.2 nathanw /* adapter config 2, number of targets */ 112 1.3.2.2 nathanw EEP_WORD(0x00, 8), 113 1.3.2.2 nathanw /* target flags */ 114 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 115 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 116 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 117 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 118 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 119 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 120 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 121 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 122 1.3.2.2 nathanw 123 1.3.2.2 nathanw /* -- eeprom_adapter[1] ------------------------------- */ 124 1.3.2.2 nathanw /* ID, adapter config 1 */ 125 1.3.2.2 nathanw EEP_WORD(7, CFG_DEFAULT), 126 1.3.2.2 nathanw /* adapter config 2, number of targets */ 127 1.3.2.2 nathanw EEP_WORD(0x00, 8), 128 1.3.2.2 nathanw /* target flags */ 129 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 130 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 131 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 132 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 133 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 134 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 135 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 136 1.3.2.2 nathanw EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 137 1.3.2.2 nathanw /* reserved[5] */ 138 1.3.2.2 nathanw 0, 0, 0, 0, 0, 139 1.3.2.2 nathanw /* checksum */ 140 1.3.2.2 nathanw 0 141 1.3.2.2 nathanw }; 142 1.3.2.3 nathanw #endif 143 1.3.2.2 nathanw 144 1.3.2.3 nathanw static u_int8_t iha_data_over_run(struct iha_scsi_req_q *); 145 1.3.2.2 nathanw 146 1.3.2.3 nathanw static int iha_push_sense_request(struct iha_softc *, struct iha_scsi_req_q *); 147 1.3.2.3 nathanw static void iha_timeout(void *); 148 1.3.2.3 nathanw static int iha_alloc_sglist(struct iha_softc *); 149 1.3.2.3 nathanw 150 1.3.2.3 nathanw static void iha_read_eeprom(struct iha_softc *, struct iha_eeprom *); 151 1.3.2.3 nathanw static int iha_se2_rd_all(struct iha_softc *, u_int16_t *); 152 1.3.2.3 nathanw static void iha_se2_instr(struct iha_softc *, int); 153 1.3.2.3 nathanw static u_int16_t iha_se2_rd(struct iha_softc *, int); 154 1.3.2.3 nathanw #ifdef notused 155 1.3.2.3 nathanw static void iha_se2_update_all(struct iha_softc *); 156 1.3.2.3 nathanw static void iha_se2_wr(struct iha_softc *, int, u_int16_t); 157 1.3.2.3 nathanw #endif 158 1.3.2.2 nathanw 159 1.3.2.3 nathanw static void iha_reset_scsi_bus(struct iha_softc *); 160 1.3.2.3 nathanw static void iha_reset_chip(struct iha_softc *); 161 1.3.2.3 nathanw static void iha_reset_dma(struct iha_softc *); 162 1.3.2.2 nathanw 163 1.3.2.3 nathanw static void iha_reset_tcs(struct tcs *, u_int8_t); 164 1.3.2.2 nathanw 165 1.3.2.3 nathanw static void iha_done_scb(struct iha_softc *, struct iha_scsi_req_q *); 166 1.3.2.3 nathanw static void iha_exec_scb(struct iha_softc *, struct iha_scsi_req_q *); 167 1.3.2.2 nathanw 168 1.3.2.3 nathanw static void iha_main(struct iha_softc *); 169 1.3.2.3 nathanw static void iha_scsi(struct iha_softc *); 170 1.3.2.2 nathanw 171 1.3.2.3 nathanw static int iha_wait(struct iha_softc *, u_int8_t); 172 1.3.2.2 nathanw 173 1.3.2.3 nathanw static __inline void iha_mark_busy_scb(struct iha_scsi_req_q *); 174 1.3.2.2 nathanw 175 1.3.2.3 nathanw static void iha_append_free_scb(struct iha_softc *, struct iha_scsi_req_q *); 176 1.3.2.3 nathanw static void iha_append_done_scb(struct iha_softc *, struct iha_scsi_req_q *, 177 1.3.2.2 nathanw u_int8_t); 178 1.3.2.3 nathanw static __inline struct iha_scsi_req_q *iha_pop_done_scb(struct iha_softc *); 179 1.3.2.2 nathanw 180 1.3.2.3 nathanw static __inline void iha_append_pend_scb(struct iha_softc *, 181 1.3.2.2 nathanw struct iha_scsi_req_q *); 182 1.3.2.3 nathanw static __inline void iha_push_pend_scb(struct iha_softc *, 183 1.3.2.2 nathanw struct iha_scsi_req_q *); 184 1.3.2.3 nathanw static __inline void iha_del_pend_scb(struct iha_softc *, 185 1.3.2.2 nathanw struct iha_scsi_req_q *); 186 1.3.2.3 nathanw static struct iha_scsi_req_q *iha_find_pend_scb(struct iha_softc *); 187 1.3.2.2 nathanw 188 1.3.2.3 nathanw static void iha_sync_done(struct iha_softc *); 189 1.3.2.3 nathanw static void iha_wide_done(struct iha_softc *); 190 1.3.2.3 nathanw static void iha_bad_seq(struct iha_softc *); 191 1.3.2.3 nathanw 192 1.3.2.3 nathanw static int iha_next_state(struct iha_softc *); 193 1.3.2.3 nathanw static int iha_state_1(struct iha_softc *); 194 1.3.2.3 nathanw static int iha_state_2(struct iha_softc *); 195 1.3.2.3 nathanw static int iha_state_3(struct iha_softc *); 196 1.3.2.3 nathanw static int iha_state_4(struct iha_softc *); 197 1.3.2.3 nathanw static int iha_state_5(struct iha_softc *); 198 1.3.2.3 nathanw static int iha_state_6(struct iha_softc *); 199 1.3.2.3 nathanw static int iha_state_8(struct iha_softc *); 200 1.3.2.2 nathanw 201 1.3.2.3 nathanw static void iha_set_ssig(struct iha_softc *, u_int8_t, u_int8_t); 202 1.3.2.2 nathanw 203 1.3.2.3 nathanw static int iha_xpad_in(struct iha_softc *); 204 1.3.2.3 nathanw static int iha_xpad_out(struct iha_softc *); 205 1.3.2.2 nathanw 206 1.3.2.3 nathanw static int iha_xfer_data(struct iha_softc *, struct iha_scsi_req_q *, 207 1.3.2.2 nathanw int direction); 208 1.3.2.2 nathanw 209 1.3.2.3 nathanw static int iha_status_msg(struct iha_softc *); 210 1.3.2.2 nathanw 211 1.3.2.3 nathanw static int iha_msgin(struct iha_softc *); 212 1.3.2.3 nathanw static int iha_msgin_sdtr(struct iha_softc *); 213 1.3.2.3 nathanw static int iha_msgin_extended(struct iha_softc *); 214 1.3.2.3 nathanw static int iha_msgin_ignore_wid_resid(struct iha_softc *); 215 1.3.2.3 nathanw 216 1.3.2.3 nathanw static int iha_msgout(struct iha_softc *, u_int8_t); 217 1.3.2.3 nathanw static int iha_msgout_extended(struct iha_softc *); 218 1.3.2.3 nathanw static void iha_msgout_abort(struct iha_softc *, u_int8_t); 219 1.3.2.3 nathanw static int iha_msgout_reject(struct iha_softc *); 220 1.3.2.3 nathanw static int iha_msgout_sdtr(struct iha_softc *); 221 1.3.2.3 nathanw static int iha_msgout_wdtr(struct iha_softc *); 222 1.3.2.2 nathanw 223 1.3.2.3 nathanw static void iha_select(struct iha_softc *, struct iha_scsi_req_q *, u_int8_t); 224 1.3.2.2 nathanw 225 1.3.2.3 nathanw static void iha_busfree(struct iha_softc *); 226 1.3.2.3 nathanw static int iha_resel(struct iha_softc *); 227 1.3.2.2 nathanw 228 1.3.2.3 nathanw static void iha_abort_xs(struct iha_softc *, struct scsipi_xfer *, u_int8_t); 229 1.3.2.2 nathanw 230 1.3.2.2 nathanw void iha_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 231 1.3.2.2 nathanw void *arg); 232 1.3.2.6 nathanw void iha_update_xfer_mode(struct iha_softc *, int); 233 1.3.2.2 nathanw 234 1.3.2.2 nathanw /* 235 1.3.2.2 nathanw * iha_intr - the interrupt service routine for the iha driver 236 1.3.2.2 nathanw */ 237 1.3.2.2 nathanw int 238 1.3.2.2 nathanw iha_intr(arg) 239 1.3.2.2 nathanw void *arg; 240 1.3.2.2 nathanw { 241 1.3.2.2 nathanw bus_space_tag_t iot; 242 1.3.2.2 nathanw bus_space_handle_t ioh; 243 1.3.2.2 nathanw struct iha_softc *sc; 244 1.3.2.2 nathanw int s; 245 1.3.2.2 nathanw 246 1.3.2.2 nathanw sc = (struct iha_softc *)arg; 247 1.3.2.2 nathanw iot = sc->sc_iot; 248 1.3.2.2 nathanw ioh = sc->sc_ioh; 249 1.3.2.2 nathanw 250 1.3.2.2 nathanw if ((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 251 1.3.2.2 nathanw return (0); 252 1.3.2.2 nathanw 253 1.3.2.2 nathanw s = splbio(); /* XXX - Or are interrupts off when ISR's are called? */ 254 1.3.2.2 nathanw 255 1.3.2.2 nathanw if (sc->sc_semaph != SEMAPH_IN_MAIN) { 256 1.3.2.2 nathanw /* XXX - need these inside a splbio()/splx()? */ 257 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 258 1.3.2.2 nathanw sc->sc_semaph = SEMAPH_IN_MAIN; 259 1.3.2.2 nathanw 260 1.3.2.3 nathanw iha_main(sc); 261 1.3.2.2 nathanw 262 1.3.2.2 nathanw sc->sc_semaph = ~SEMAPH_IN_MAIN; 263 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 264 1.3.2.2 nathanw } 265 1.3.2.2 nathanw 266 1.3.2.2 nathanw splx(s); 267 1.3.2.2 nathanw 268 1.3.2.2 nathanw return (1); 269 1.3.2.2 nathanw } 270 1.3.2.2 nathanw 271 1.3.2.2 nathanw void 272 1.3.2.2 nathanw iha_scsipi_request(chan, req, arg) 273 1.3.2.2 nathanw struct scsipi_channel *chan; 274 1.3.2.2 nathanw scsipi_adapter_req_t req; 275 1.3.2.2 nathanw void *arg; 276 1.3.2.2 nathanw { 277 1.3.2.2 nathanw struct scsipi_xfer *xs; 278 1.3.2.2 nathanw struct scsipi_periph *periph; 279 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 280 1.3.2.2 nathanw struct iha_softc *sc; 281 1.3.2.6 nathanw int error, s; 282 1.3.2.2 nathanw 283 1.3.2.2 nathanw sc = (struct iha_softc *)chan->chan_adapter->adapt_dev; 284 1.3.2.2 nathanw 285 1.3.2.2 nathanw switch (req) { 286 1.3.2.2 nathanw case ADAPTER_REQ_RUN_XFER: 287 1.3.2.2 nathanw xs = arg; 288 1.3.2.2 nathanw periph = xs->xs_periph; 289 1.3.2.2 nathanw 290 1.3.2.2 nathanw if (xs->cmdlen > sizeof(struct scsi_generic) || 291 1.3.2.2 nathanw periph->periph_target >= IHA_MAX_TARGETS) { 292 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 293 1.3.2.2 nathanw return; 294 1.3.2.2 nathanw } 295 1.3.2.2 nathanw 296 1.3.2.2 nathanw s = splbio(); 297 1.3.2.2 nathanw scb = TAILQ_FIRST(&sc->sc_freescb); 298 1.3.2.2 nathanw if (scb != NULL) { 299 1.3.2.2 nathanw scb->status = STATUS_RENT; 300 1.3.2.2 nathanw TAILQ_REMOVE(&sc->sc_freescb, scb, chain); 301 1.3.2.2 nathanw } 302 1.3.2.2 nathanw #ifdef DIAGNOSTIC 303 1.3.2.2 nathanw else { 304 1.3.2.2 nathanw scsipi_printaddr(periph); 305 1.3.2.2 nathanw printf("unable to allocate scb\n"); 306 1.3.2.2 nathanw panic("iha_scsipi_request"); 307 1.3.2.2 nathanw } 308 1.3.2.2 nathanw #endif 309 1.3.2.2 nathanw splx(s); 310 1.3.2.2 nathanw 311 1.3.2.2 nathanw scb->target = periph->periph_target; 312 1.3.2.2 nathanw scb->lun = periph->periph_lun; 313 1.3.2.2 nathanw scb->tcs = &sc->sc_tcs[scb->target]; 314 1.3.2.2 nathanw scb->scb_id = MSG_IDENTIFY(periph->periph_lun, 315 1.3.2.2 nathanw (xs->xs_control & XS_CTL_REQSENSE) == 0); 316 1.3.2.2 nathanw 317 1.3.2.2 nathanw scb->xs = xs; 318 1.3.2.2 nathanw scb->cmdlen = xs->cmdlen; 319 1.3.2.2 nathanw memcpy(&scb->cmd, xs->cmd, xs->cmdlen); 320 1.3.2.2 nathanw scb->buflen = xs->datalen; 321 1.3.2.6 nathanw scb->flags = 0; 322 1.3.2.6 nathanw if (xs->xs_control & XS_CTL_DATA_OUT) 323 1.3.2.6 nathanw scb->flags |= FLAG_DATAOUT; 324 1.3.2.6 nathanw if (xs->xs_control & XS_CTL_DATA_IN) 325 1.3.2.6 nathanw scb->flags |= FLAG_DATAIN; 326 1.3.2.2 nathanw 327 1.3.2.6 nathanw if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 328 1.3.2.2 nathanw error = bus_dmamap_load(sc->sc_dmat, scb->dmap, 329 1.3.2.2 nathanw xs->data, scb->buflen, NULL, 330 1.3.2.3 nathanw ((xs->xs_control & XS_CTL_NOSLEEP) ? 331 1.3.2.3 nathanw BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 332 1.3.2.3 nathanw BUS_DMA_STREAMING | 333 1.3.2.6 nathanw ((scb->flags & FLAG_DATAIN) ? 334 1.3.2.3 nathanw BUS_DMA_READ : BUS_DMA_WRITE)); 335 1.3.2.2 nathanw 336 1.3.2.2 nathanw if (error) { 337 1.3.2.2 nathanw printf("%s: error %d loading dma map\n", 338 1.3.2.2 nathanw sc->sc_dev.dv_xname, error); 339 1.3.2.3 nathanw iha_append_free_scb(sc, scb); 340 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 341 1.3.2.2 nathanw scsipi_done(xs); 342 1.3.2.2 nathanw return; 343 1.3.2.2 nathanw } 344 1.3.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, scb->dmap, 345 1.3.2.2 nathanw 0, scb->dmap->dm_mapsize, 346 1.3.2.6 nathanw (scb->flags & FLAG_DATAIN) ? 347 1.3.2.2 nathanw BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 348 1.3.2.2 nathanw } 349 1.3.2.2 nathanw 350 1.3.2.3 nathanw iha_exec_scb(sc, scb); 351 1.3.2.2 nathanw return; 352 1.3.2.2 nathanw 353 1.3.2.2 nathanw case ADAPTER_REQ_GROW_RESOURCES: 354 1.3.2.2 nathanw return; /* XXX */ 355 1.3.2.2 nathanw 356 1.3.2.2 nathanw case ADAPTER_REQ_SET_XFER_MODE: 357 1.3.2.6 nathanw { 358 1.3.2.6 nathanw struct tcs *tcs; 359 1.3.2.6 nathanw struct scsipi_xfer_mode *xm = arg; 360 1.3.2.6 nathanw 361 1.3.2.6 nathanw tcs = &sc->sc_tcs[xm->xm_target]; 362 1.3.2.6 nathanw 363 1.3.2.6 nathanw if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 364 1.3.2.6 nathanw (tcs->flags & FLAG_NO_WIDE) == 0) 365 1.3.2.6 nathanw tcs->flags &= ~(FLAG_WIDE_DONE|FLAG_SYNC_DONE); 366 1.3.2.6 nathanw 367 1.3.2.6 nathanw if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 368 1.3.2.6 nathanw (tcs->flags & FLAG_NO_SYNC) == 0) 369 1.3.2.6 nathanw tcs->flags &= ~FLAG_SYNC_DONE; 370 1.3.2.6 nathanw 371 1.3.2.6 nathanw /* 372 1.3.2.6 nathanw * If we're not going to negotiate, send the 373 1.3.2.6 nathanw * notification now, since it won't happen later. 374 1.3.2.6 nathanw */ 375 1.3.2.6 nathanw if ((tcs->flags & (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) == 376 1.3.2.6 nathanw (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) 377 1.3.2.6 nathanw iha_update_xfer_mode(sc, xm->xm_target); 378 1.3.2.6 nathanw 379 1.3.2.6 nathanw return; 380 1.3.2.6 nathanw } 381 1.3.2.2 nathanw } 382 1.3.2.2 nathanw } 383 1.3.2.2 nathanw 384 1.3.2.2 nathanw void 385 1.3.2.2 nathanw iha_attach(sc) 386 1.3.2.2 nathanw struct iha_softc *sc; 387 1.3.2.2 nathanw { 388 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 389 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 390 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 391 1.3.2.2 nathanw struct iha_eeprom eeprom; 392 1.3.2.2 nathanw struct eeprom_adapter *conf; 393 1.3.2.2 nathanw int i, error, reg; 394 1.3.2.2 nathanw 395 1.3.2.3 nathanw iha_read_eeprom(sc, &eeprom); 396 1.3.2.2 nathanw 397 1.3.2.2 nathanw conf = &eeprom.adapter[0]; 398 1.3.2.2 nathanw 399 1.3.2.2 nathanw /* 400 1.3.2.3 nathanw * fill in the rest of the iha_softc fields 401 1.3.2.2 nathanw */ 402 1.3.2.2 nathanw sc->sc_id = CFG_ID(conf->config1); 403 1.3.2.2 nathanw sc->sc_semaph = ~SEMAPH_IN_MAIN; 404 1.3.2.2 nathanw sc->sc_status0 = 0; 405 1.3.2.2 nathanw sc->sc_actscb = NULL; 406 1.3.2.2 nathanw 407 1.3.2.2 nathanw TAILQ_INIT(&sc->sc_freescb); 408 1.3.2.2 nathanw TAILQ_INIT(&sc->sc_pendscb); 409 1.3.2.2 nathanw TAILQ_INIT(&sc->sc_donescb); 410 1.3.2.3 nathanw error = iha_alloc_sglist(sc); 411 1.3.2.2 nathanw if (error != 0) { 412 1.3.2.2 nathanw printf(": cannot allocate sglist\n"); 413 1.3.2.2 nathanw return; 414 1.3.2.2 nathanw } 415 1.3.2.2 nathanw 416 1.3.2.2 nathanw sc->sc_scb = malloc(sizeof(struct iha_scsi_req_q) * IHA_MAX_SCB, 417 1.3.2.6 nathanw M_DEVBUF, M_NOWAIT|M_ZERO); 418 1.3.2.2 nathanw if (sc->sc_scb == NULL) { 419 1.3.2.2 nathanw printf(": cannot allocate SCB\n"); 420 1.3.2.2 nathanw return; 421 1.3.2.2 nathanw } 422 1.3.2.2 nathanw 423 1.3.2.2 nathanw for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) { 424 1.3.2.2 nathanw scb->scb_tagid = i; 425 1.3.2.2 nathanw scb->sgoffset = IHA_SG_SIZE * i; 426 1.3.2.4 nathanw scb->sglist = sc->sc_sglist + IHA_MAX_SG_ENTRIES * i; 427 1.3.2.2 nathanw scb->sg_addr = 428 1.3.2.2 nathanw sc->sc_dmamap->dm_segs[0].ds_addr + scb->sgoffset; 429 1.3.2.2 nathanw 430 1.3.2.2 nathanw error = bus_dmamap_create(sc->sc_dmat, 431 1.3.2.4 nathanw MAXPHYS, IHA_MAX_SG_ENTRIES, MAXPHYS, 0, 432 1.3.2.2 nathanw BUS_DMA_NOWAIT, &scb->dmap); 433 1.3.2.2 nathanw 434 1.3.2.2 nathanw if (error != 0) { 435 1.3.2.2 nathanw printf(": couldn't create SCB DMA map, error = %d\n", 436 1.3.2.2 nathanw error); 437 1.3.2.2 nathanw return; 438 1.3.2.2 nathanw } 439 1.3.2.2 nathanw TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 440 1.3.2.2 nathanw } 441 1.3.2.2 nathanw 442 1.3.2.2 nathanw /* Mask all the interrupts */ 443 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 444 1.3.2.2 nathanw 445 1.3.2.2 nathanw /* Stop any I/O and reset the scsi module */ 446 1.3.2.3 nathanw iha_reset_dma(sc); 447 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSMOD); 448 1.3.2.2 nathanw 449 1.3.2.2 nathanw /* Program HBA's SCSI ID */ 450 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SID, sc->sc_id << 4); 451 1.3.2.2 nathanw 452 1.3.2.2 nathanw /* 453 1.3.2.2 nathanw * Configure the channel as requested by the NVRAM settings read 454 1.3.2.3 nathanw * by iha_read_eeprom() above. 455 1.3.2.2 nathanw */ 456 1.3.2.2 nathanw 457 1.3.2.2 nathanw sc->sc_sconf1 = SCONFIG0DEFAULT; 458 1.3.2.2 nathanw if ((conf->config1 & CFG_EN_PAR) != 0) 459 1.3.2.2 nathanw sc->sc_sconf1 |= SPCHK; 460 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, sc->sc_sconf1); 461 1.3.2.2 nathanw 462 1.3.2.2 nathanw /* set selection time out 250 ms */ 463 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_STIMO, STIMO_250MS); 464 1.3.2.2 nathanw 465 1.3.2.2 nathanw /* Enable desired SCSI termination configuration read from eeprom */ 466 1.3.2.2 nathanw reg = 0; 467 1.3.2.2 nathanw if (conf->config1 & CFG_ACT_TERM1) 468 1.3.2.2 nathanw reg |= ENTMW; 469 1.3.2.2 nathanw if (conf->config1 & CFG_ACT_TERM2) 470 1.3.2.2 nathanw reg |= ENTM; 471 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_DCTRL0, reg); 472 1.3.2.2 nathanw 473 1.3.2.2 nathanw reg = bus_space_read_1(iot, ioh, TUL_GCTRL1) & ~ATDEN; 474 1.3.2.2 nathanw if (conf->config1 & CFG_AUTO_TERM) 475 1.3.2.2 nathanw reg |= ATDEN; 476 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_GCTRL1, reg); 477 1.3.2.2 nathanw 478 1.3.2.2 nathanw for (i = 0; i < IHA_MAX_TARGETS / 2; i++) { 479 1.3.2.2 nathanw sc->sc_tcs[i * 2 ].flags = EEP_LBYTE(conf->tflags[i]); 480 1.3.2.2 nathanw sc->sc_tcs[i * 2 + 1].flags = EEP_HBYTE(conf->tflags[i]); 481 1.3.2.3 nathanw iha_reset_tcs(&sc->sc_tcs[i * 2 ], sc->sc_sconf1); 482 1.3.2.3 nathanw iha_reset_tcs(&sc->sc_tcs[i * 2 + 1], sc->sc_sconf1); 483 1.3.2.2 nathanw } 484 1.3.2.2 nathanw 485 1.3.2.3 nathanw iha_reset_chip(sc); 486 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SIEN, ALL_INTERRUPTS); 487 1.3.2.2 nathanw 488 1.3.2.2 nathanw /* 489 1.3.2.2 nathanw * fill in the adapter. 490 1.3.2.2 nathanw */ 491 1.3.2.2 nathanw sc->sc_adapter.adapt_dev = &sc->sc_dev; 492 1.3.2.2 nathanw sc->sc_adapter.adapt_nchannels = 1; 493 1.3.2.2 nathanw sc->sc_adapter.adapt_openings = IHA_MAX_SCB; 494 1.3.2.2 nathanw sc->sc_adapter.adapt_max_periph = IHA_MAX_SCB; 495 1.3.2.2 nathanw sc->sc_adapter.adapt_ioctl = NULL; 496 1.3.2.4 nathanw sc->sc_adapter.adapt_minphys = minphys; 497 1.3.2.2 nathanw sc->sc_adapter.adapt_request = iha_scsipi_request; 498 1.3.2.2 nathanw 499 1.3.2.2 nathanw /* 500 1.3.2.2 nathanw * fill in the channel. 501 1.3.2.2 nathanw */ 502 1.3.2.2 nathanw sc->sc_channel.chan_adapter = &sc->sc_adapter; 503 1.3.2.2 nathanw sc->sc_channel.chan_bustype = &scsi_bustype; 504 1.3.2.2 nathanw sc->sc_channel.chan_channel = 0; 505 1.3.2.2 nathanw sc->sc_channel.chan_ntargets = CFG_TARGET(conf->config2); 506 1.3.2.2 nathanw sc->sc_channel.chan_nluns = 8; 507 1.3.2.2 nathanw sc->sc_channel.chan_id = sc->sc_id; 508 1.3.2.2 nathanw 509 1.3.2.2 nathanw /* 510 1.3.2.2 nathanw * Now try to attach all the sub devices. 511 1.3.2.2 nathanw */ 512 1.3.2.2 nathanw config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 513 1.3.2.2 nathanw } 514 1.3.2.2 nathanw 515 1.3.2.2 nathanw /* 516 1.3.2.3 nathanw * iha_reset_dma - abort any active DMA xfer, reset tulip FIFO. 517 1.3.2.2 nathanw */ 518 1.3.2.2 nathanw static void 519 1.3.2.3 nathanw iha_reset_dma(sc) 520 1.3.2.2 nathanw struct iha_softc *sc; 521 1.3.2.2 nathanw { 522 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 523 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 524 1.3.2.2 nathanw 525 1.3.2.2 nathanw if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 526 1.3.2.2 nathanw /* if DMA xfer is pending, abort DMA xfer */ 527 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 528 1.3.2.2 nathanw /* wait Abort DMA xfer done */ 529 1.3.2.2 nathanw while ((bus_space_read_1(iot, ioh, TUL_ISTUS0) & DABT) == 0) 530 1.3.2.2 nathanw ; 531 1.3.2.2 nathanw } 532 1.3.2.2 nathanw 533 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 534 1.3.2.2 nathanw } 535 1.3.2.2 nathanw 536 1.3.2.2 nathanw /* 537 1.3.2.3 nathanw * iha_append_free_scb - append the supplied SCB to the tail of the 538 1.3.2.2 nathanw * sc_freescb queue after clearing and resetting 539 1.3.2.2 nathanw * everything possible. 540 1.3.2.2 nathanw */ 541 1.3.2.2 nathanw static void 542 1.3.2.3 nathanw iha_append_free_scb(sc, scb) 543 1.3.2.2 nathanw struct iha_softc *sc; 544 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 545 1.3.2.2 nathanw { 546 1.3.2.2 nathanw int s; 547 1.3.2.2 nathanw 548 1.3.2.2 nathanw s = splbio(); 549 1.3.2.2 nathanw 550 1.3.2.2 nathanw if (scb == sc->sc_actscb) 551 1.3.2.2 nathanw sc->sc_actscb = NULL; 552 1.3.2.2 nathanw 553 1.3.2.2 nathanw scb->status = STATUS_QUEUED; 554 1.3.2.2 nathanw scb->ha_stat = HOST_OK; 555 1.3.2.2 nathanw scb->ta_stat = SCSI_OK; 556 1.3.2.2 nathanw 557 1.3.2.2 nathanw scb->nextstat = 0; 558 1.3.2.2 nathanw scb->scb_tagmsg = 0; 559 1.3.2.2 nathanw 560 1.3.2.2 nathanw scb->xs = NULL; 561 1.3.2.2 nathanw scb->tcs = NULL; 562 1.3.2.2 nathanw 563 1.3.2.2 nathanw /* 564 1.3.2.2 nathanw * scb_tagid, sg_addr, sglist 565 1.3.2.2 nathanw * SCB_SensePtr are set at initialization 566 1.3.2.2 nathanw * and never change 567 1.3.2.2 nathanw */ 568 1.3.2.2 nathanw 569 1.3.2.2 nathanw TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 570 1.3.2.2 nathanw 571 1.3.2.2 nathanw splx(s); 572 1.3.2.2 nathanw } 573 1.3.2.2 nathanw 574 1.3.2.2 nathanw static __inline void 575 1.3.2.3 nathanw iha_append_pend_scb(sc, scb) 576 1.3.2.2 nathanw struct iha_softc *sc; 577 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 578 1.3.2.2 nathanw { 579 1.3.2.2 nathanw /* ASSUMPTION: only called within a splbio()/splx() pair */ 580 1.3.2.2 nathanw 581 1.3.2.2 nathanw if (scb == sc->sc_actscb) 582 1.3.2.2 nathanw sc->sc_actscb = NULL; 583 1.3.2.2 nathanw 584 1.3.2.2 nathanw scb->status = STATUS_QUEUED; 585 1.3.2.2 nathanw 586 1.3.2.2 nathanw TAILQ_INSERT_TAIL(&sc->sc_pendscb, scb, chain); 587 1.3.2.2 nathanw } 588 1.3.2.2 nathanw 589 1.3.2.2 nathanw static __inline void 590 1.3.2.3 nathanw iha_push_pend_scb(sc, scb) 591 1.3.2.2 nathanw struct iha_softc *sc; 592 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 593 1.3.2.2 nathanw { 594 1.3.2.2 nathanw int s; 595 1.3.2.2 nathanw 596 1.3.2.2 nathanw s = splbio(); 597 1.3.2.2 nathanw 598 1.3.2.2 nathanw if (scb == sc->sc_actscb) 599 1.3.2.2 nathanw sc->sc_actscb = NULL; 600 1.3.2.2 nathanw 601 1.3.2.2 nathanw scb->status = STATUS_QUEUED; 602 1.3.2.2 nathanw 603 1.3.2.2 nathanw TAILQ_INSERT_HEAD(&sc->sc_pendscb, scb, chain); 604 1.3.2.2 nathanw 605 1.3.2.2 nathanw splx(s); 606 1.3.2.2 nathanw } 607 1.3.2.2 nathanw 608 1.3.2.2 nathanw /* 609 1.3.2.3 nathanw * iha_find_pend_scb - scan the pending queue for a SCB that can be 610 1.3.2.2 nathanw * processed immediately. Return NULL if none found 611 1.3.2.2 nathanw * and a pointer to the SCB if one is found. If there 612 1.3.2.2 nathanw * is an active SCB, return NULL! 613 1.3.2.2 nathanw */ 614 1.3.2.2 nathanw static struct iha_scsi_req_q * 615 1.3.2.3 nathanw iha_find_pend_scb(sc) 616 1.3.2.2 nathanw struct iha_softc *sc; 617 1.3.2.2 nathanw { 618 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 619 1.3.2.2 nathanw struct tcs *tcs; 620 1.3.2.2 nathanw int s; 621 1.3.2.2 nathanw 622 1.3.2.2 nathanw s = splbio(); 623 1.3.2.2 nathanw 624 1.3.2.2 nathanw if (sc->sc_actscb != NULL) 625 1.3.2.2 nathanw scb = NULL; 626 1.3.2.2 nathanw 627 1.3.2.2 nathanw else 628 1.3.2.2 nathanw TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) { 629 1.3.2.6 nathanw if ((scb->xs->xs_control & XS_CTL_RESET) != 0) 630 1.3.2.2 nathanw /* ALWAYS willing to reset a device */ 631 1.3.2.2 nathanw break; 632 1.3.2.2 nathanw 633 1.3.2.2 nathanw tcs = scb->tcs; 634 1.3.2.2 nathanw 635 1.3.2.2 nathanw if ((scb->scb_tagmsg) != 0) { 636 1.3.2.2 nathanw /* 637 1.3.2.2 nathanw * A Tagged I/O. OK to start If no 638 1.3.2.2 nathanw * non-tagged I/O is active on the same 639 1.3.2.2 nathanw * target 640 1.3.2.2 nathanw */ 641 1.3.2.2 nathanw if (tcs->ntagscb == NULL) 642 1.3.2.2 nathanw break; 643 1.3.2.2 nathanw 644 1.3.2.2 nathanw } else if (scb->cmd[0] == REQUEST_SENSE) { 645 1.3.2.2 nathanw /* 646 1.3.2.2 nathanw * OK to do a non-tagged request sense 647 1.3.2.2 nathanw * even if a non-tagged I/O has been 648 1.3.2.2 nathanw * started, 'cuz we don't allow any 649 1.3.2.2 nathanw * disconnect during a request sense op 650 1.3.2.2 nathanw */ 651 1.3.2.2 nathanw break; 652 1.3.2.2 nathanw 653 1.3.2.2 nathanw } else if (tcs->tagcnt == 0) { 654 1.3.2.2 nathanw /* 655 1.3.2.2 nathanw * No tagged I/O active on this target, 656 1.3.2.2 nathanw * ok to start a non-tagged one if one 657 1.3.2.2 nathanw * is not already active 658 1.3.2.2 nathanw */ 659 1.3.2.2 nathanw if (tcs->ntagscb == NULL) 660 1.3.2.2 nathanw break; 661 1.3.2.2 nathanw } 662 1.3.2.2 nathanw } 663 1.3.2.2 nathanw 664 1.3.2.2 nathanw splx(s); 665 1.3.2.2 nathanw 666 1.3.2.2 nathanw return (scb); 667 1.3.2.2 nathanw } 668 1.3.2.2 nathanw 669 1.3.2.2 nathanw /* 670 1.3.2.3 nathanw * iha_del_pend_scb - remove scb from sc_pendscb 671 1.3.2.2 nathanw */ 672 1.3.2.2 nathanw static __inline void 673 1.3.2.3 nathanw iha_del_pend_scb(sc, scb) 674 1.3.2.2 nathanw struct iha_softc *sc; 675 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 676 1.3.2.2 nathanw { 677 1.3.2.2 nathanw int s; 678 1.3.2.2 nathanw 679 1.3.2.2 nathanw s = splbio(); 680 1.3.2.2 nathanw 681 1.3.2.2 nathanw TAILQ_REMOVE(&sc->sc_pendscb, scb, chain); 682 1.3.2.2 nathanw 683 1.3.2.2 nathanw splx(s); 684 1.3.2.2 nathanw } 685 1.3.2.2 nathanw 686 1.3.2.2 nathanw static __inline void 687 1.3.2.3 nathanw iha_mark_busy_scb(scb) 688 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 689 1.3.2.2 nathanw { 690 1.3.2.2 nathanw int s; 691 1.3.2.2 nathanw 692 1.3.2.2 nathanw s = splbio(); 693 1.3.2.2 nathanw 694 1.3.2.2 nathanw scb->status = STATUS_BUSY; 695 1.3.2.2 nathanw 696 1.3.2.2 nathanw if (scb->scb_tagmsg == 0) 697 1.3.2.2 nathanw scb->tcs->ntagscb = scb; 698 1.3.2.2 nathanw else 699 1.3.2.2 nathanw scb->tcs->tagcnt++; 700 1.3.2.2 nathanw 701 1.3.2.2 nathanw splx(s); 702 1.3.2.2 nathanw } 703 1.3.2.2 nathanw 704 1.3.2.2 nathanw static void 705 1.3.2.3 nathanw iha_append_done_scb(sc, scb, hastat) 706 1.3.2.2 nathanw struct iha_softc *sc; 707 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 708 1.3.2.2 nathanw u_int8_t hastat; 709 1.3.2.2 nathanw { 710 1.3.2.2 nathanw struct tcs *tcs; 711 1.3.2.2 nathanw int s; 712 1.3.2.2 nathanw 713 1.3.2.2 nathanw s = splbio(); 714 1.3.2.2 nathanw 715 1.3.2.2 nathanw if (scb->xs != NULL) 716 1.3.2.2 nathanw callout_stop(&scb->xs->xs_callout); 717 1.3.2.2 nathanw 718 1.3.2.2 nathanw if (scb == sc->sc_actscb) 719 1.3.2.2 nathanw sc->sc_actscb = NULL; 720 1.3.2.2 nathanw 721 1.3.2.2 nathanw tcs = scb->tcs; 722 1.3.2.2 nathanw 723 1.3.2.2 nathanw if (scb->scb_tagmsg != 0) { 724 1.3.2.2 nathanw if (tcs->tagcnt) 725 1.3.2.2 nathanw tcs->tagcnt--; 726 1.3.2.2 nathanw } else if (tcs->ntagscb == scb) 727 1.3.2.2 nathanw tcs->ntagscb = NULL; 728 1.3.2.2 nathanw 729 1.3.2.2 nathanw scb->status = STATUS_QUEUED; 730 1.3.2.2 nathanw scb->ha_stat = hastat; 731 1.3.2.2 nathanw 732 1.3.2.2 nathanw TAILQ_INSERT_TAIL(&sc->sc_donescb, scb, chain); 733 1.3.2.2 nathanw 734 1.3.2.2 nathanw splx(s); 735 1.3.2.2 nathanw } 736 1.3.2.2 nathanw 737 1.3.2.2 nathanw static __inline struct iha_scsi_req_q * 738 1.3.2.3 nathanw iha_pop_done_scb(sc) 739 1.3.2.2 nathanw struct iha_softc *sc; 740 1.3.2.2 nathanw { 741 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 742 1.3.2.2 nathanw int s; 743 1.3.2.2 nathanw 744 1.3.2.2 nathanw s = splbio(); 745 1.3.2.2 nathanw 746 1.3.2.2 nathanw scb = TAILQ_FIRST(&sc->sc_donescb); 747 1.3.2.2 nathanw 748 1.3.2.2 nathanw if (scb != NULL) { 749 1.3.2.2 nathanw scb->status = STATUS_RENT; 750 1.3.2.2 nathanw TAILQ_REMOVE(&sc->sc_donescb, scb, chain); 751 1.3.2.2 nathanw } 752 1.3.2.2 nathanw 753 1.3.2.2 nathanw splx(s); 754 1.3.2.2 nathanw 755 1.3.2.2 nathanw return (scb); 756 1.3.2.2 nathanw } 757 1.3.2.2 nathanw 758 1.3.2.2 nathanw /* 759 1.3.2.3 nathanw * iha_abort_xs - find the SCB associated with the supplied xs and 760 1.3.2.2 nathanw * stop all processing on it, moving it to the done 761 1.3.2.2 nathanw * queue with the supplied host status value. 762 1.3.2.2 nathanw */ 763 1.3.2.2 nathanw static void 764 1.3.2.3 nathanw iha_abort_xs(sc, xs, hastat) 765 1.3.2.2 nathanw struct iha_softc *sc; 766 1.3.2.2 nathanw struct scsipi_xfer *xs; 767 1.3.2.2 nathanw u_int8_t hastat; 768 1.3.2.2 nathanw { 769 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 770 1.3.2.2 nathanw int i, s; 771 1.3.2.2 nathanw 772 1.3.2.2 nathanw s = splbio(); 773 1.3.2.2 nathanw 774 1.3.2.2 nathanw /* Check the pending queue for the SCB pointing to xs */ 775 1.3.2.2 nathanw 776 1.3.2.2 nathanw TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) 777 1.3.2.2 nathanw if (scb->xs == xs) { 778 1.3.2.3 nathanw iha_del_pend_scb(sc, scb); 779 1.3.2.3 nathanw iha_append_done_scb(sc, scb, hastat); 780 1.3.2.2 nathanw splx(s); 781 1.3.2.2 nathanw return; 782 1.3.2.2 nathanw } 783 1.3.2.2 nathanw 784 1.3.2.2 nathanw /* 785 1.3.2.2 nathanw * If that didn't work, check all BUSY/SELECTING SCB's for one 786 1.3.2.2 nathanw * pointing to xs 787 1.3.2.2 nathanw */ 788 1.3.2.2 nathanw 789 1.3.2.2 nathanw for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 790 1.3.2.2 nathanw switch (scb->status) { 791 1.3.2.2 nathanw case STATUS_BUSY: 792 1.3.2.2 nathanw case STATUS_SELECT: 793 1.3.2.2 nathanw if (scb->xs == xs) { 794 1.3.2.3 nathanw iha_append_done_scb(sc, scb, hastat); 795 1.3.2.2 nathanw splx(s); 796 1.3.2.2 nathanw return; 797 1.3.2.2 nathanw } 798 1.3.2.2 nathanw break; 799 1.3.2.2 nathanw default: 800 1.3.2.2 nathanw break; 801 1.3.2.2 nathanw } 802 1.3.2.2 nathanw 803 1.3.2.2 nathanw splx(s); 804 1.3.2.2 nathanw } 805 1.3.2.2 nathanw 806 1.3.2.2 nathanw /* 807 1.3.2.3 nathanw * iha_bad_seq - a SCSI bus phase was encountered out of the 808 1.3.2.2 nathanw * correct/expected sequence. Reset the SCSI bus. 809 1.3.2.2 nathanw */ 810 1.3.2.2 nathanw static void 811 1.3.2.3 nathanw iha_bad_seq(sc) 812 1.3.2.2 nathanw struct iha_softc *sc; 813 1.3.2.2 nathanw { 814 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 815 1.3.2.2 nathanw 816 1.3.2.2 nathanw if (scb != NULL) 817 1.3.2.3 nathanw iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 818 1.3.2.2 nathanw 819 1.3.2.3 nathanw iha_reset_scsi_bus(sc); 820 1.3.2.3 nathanw iha_reset_chip(sc); 821 1.3.2.2 nathanw } 822 1.3.2.2 nathanw 823 1.3.2.2 nathanw /* 824 1.3.2.3 nathanw * iha_push_sense_request - obtain auto sense data by pushing the 825 1.3.2.2 nathanw * SCB needing it back onto the pending 826 1.3.2.2 nathanw * queue with a REQUEST_SENSE CDB. 827 1.3.2.2 nathanw */ 828 1.3.2.2 nathanw static int 829 1.3.2.3 nathanw iha_push_sense_request(sc, scb) 830 1.3.2.2 nathanw struct iha_softc *sc; 831 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 832 1.3.2.2 nathanw { 833 1.3.2.2 nathanw struct scsipi_xfer *xs = scb->xs; 834 1.3.2.2 nathanw struct scsipi_periph *periph = xs->xs_periph; 835 1.3.2.2 nathanw struct scsipi_sense *ss = (struct scsipi_sense *)scb->cmd; 836 1.3.2.2 nathanw int lun = periph->periph_lun; 837 1.3.2.2 nathanw int err; 838 1.3.2.2 nathanw 839 1.3.2.2 nathanw ss->opcode = REQUEST_SENSE; 840 1.3.2.2 nathanw ss->byte2 = lun << SCSI_CMD_LUN_SHIFT; 841 1.3.2.2 nathanw ss->unused[0] = ss->unused[1] = 0; 842 1.3.2.2 nathanw ss->length = sizeof(struct scsipi_sense_data); 843 1.3.2.2 nathanw ss->control = 0; 844 1.3.2.2 nathanw 845 1.3.2.6 nathanw scb->flags = FLAG_RSENS | FLAG_DATAIN; 846 1.3.2.2 nathanw 847 1.3.2.2 nathanw scb->scb_id &= ~MSG_IDENTIFY_DISCFLAG; 848 1.3.2.2 nathanw 849 1.3.2.2 nathanw scb->scb_tagmsg = 0; 850 1.3.2.2 nathanw scb->ta_stat = SCSI_OK; 851 1.3.2.2 nathanw 852 1.3.2.2 nathanw scb->cmdlen = sizeof(struct scsipi_sense); 853 1.3.2.2 nathanw scb->buflen = ss->length; 854 1.3.2.2 nathanw 855 1.3.2.2 nathanw err = bus_dmamap_load(sc->sc_dmat, scb->dmap, 856 1.3.2.3 nathanw &xs->sense.scsi_sense, scb->buflen, NULL, 857 1.3.2.3 nathanw BUS_DMA_READ|BUS_DMA_NOWAIT); 858 1.3.2.2 nathanw if (err != 0) { 859 1.3.2.2 nathanw printf("iha_push_sense_request: cannot bus_dmamap_load()\n"); 860 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 861 1.3.2.2 nathanw return 1; 862 1.3.2.2 nathanw } 863 1.3.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, scb->dmap, 864 1.3.2.2 nathanw 0, scb->buflen, BUS_DMASYNC_PREREAD); 865 1.3.2.2 nathanw 866 1.3.2.2 nathanw /* XXX What about queued command? */ 867 1.3.2.3 nathanw iha_exec_scb(sc, scb); 868 1.3.2.2 nathanw 869 1.3.2.2 nathanw return 0; 870 1.3.2.2 nathanw } 871 1.3.2.2 nathanw 872 1.3.2.2 nathanw /* 873 1.3.2.3 nathanw * iha_main - process the active SCB, taking one off pending and making it 874 1.3.2.2 nathanw * active if necessary, and any done SCB's created as 875 1.3.2.2 nathanw * a result until there are no interrupts pending and no pending 876 1.3.2.2 nathanw * SCB's that can be started. 877 1.3.2.2 nathanw */ 878 1.3.2.2 nathanw static void 879 1.3.2.3 nathanw iha_main(sc) 880 1.3.2.2 nathanw struct iha_softc *sc; 881 1.3.2.2 nathanw { 882 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 883 1.3.2.2 nathanw bus_space_handle_t ioh =sc->sc_ioh; 884 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 885 1.3.2.2 nathanw 886 1.3.2.2 nathanw for (;;) { 887 1.3.2.3 nathanw iha_scsi(sc); 888 1.3.2.2 nathanw 889 1.3.2.3 nathanw while ((scb = iha_pop_done_scb(sc)) != NULL) 890 1.3.2.3 nathanw iha_done_scb(sc, scb); 891 1.3.2.2 nathanw 892 1.3.2.2 nathanw /* 893 1.3.2.2 nathanw * If there are no interrupts pending, or we can't start 894 1.3.2.2 nathanw * a pending sc, break out of the for(;;). Otherwise 895 1.3.2.2 nathanw * continue the good work with another call to 896 1.3.2.3 nathanw * iha_scsi(). 897 1.3.2.2 nathanw */ 898 1.3.2.2 nathanw if (((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 899 1.3.2.3 nathanw && (iha_find_pend_scb(sc) == NULL)) 900 1.3.2.2 nathanw break; 901 1.3.2.2 nathanw } 902 1.3.2.2 nathanw } 903 1.3.2.2 nathanw 904 1.3.2.2 nathanw /* 905 1.3.2.3 nathanw * iha_scsi - service any outstanding interrupts. If there are none, try to 906 1.3.2.2 nathanw * start another SCB currently in the pending queue. 907 1.3.2.2 nathanw */ 908 1.3.2.2 nathanw static void 909 1.3.2.3 nathanw iha_scsi(sc) 910 1.3.2.2 nathanw struct iha_softc *sc; 911 1.3.2.2 nathanw { 912 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 913 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 914 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 915 1.3.2.2 nathanw struct tcs *tcs; 916 1.3.2.2 nathanw u_int8_t stat; 917 1.3.2.2 nathanw 918 1.3.2.2 nathanw /* service pending interrupts asap */ 919 1.3.2.2 nathanw 920 1.3.2.2 nathanw stat = bus_space_read_1(iot, ioh, TUL_STAT0); 921 1.3.2.2 nathanw if ((stat & INTPD) != 0) { 922 1.3.2.2 nathanw sc->sc_status0 = stat; 923 1.3.2.2 nathanw sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 924 1.3.2.2 nathanw sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 925 1.3.2.2 nathanw 926 1.3.2.2 nathanw sc->sc_phase = sc->sc_status0 & PH_MASK; 927 1.3.2.2 nathanw 928 1.3.2.2 nathanw if ((sc->sc_sistat & SRSTD) != 0) { 929 1.3.2.3 nathanw iha_reset_scsi_bus(sc); 930 1.3.2.2 nathanw return; 931 1.3.2.2 nathanw } 932 1.3.2.2 nathanw 933 1.3.2.2 nathanw if ((sc->sc_sistat & RSELED) != 0) { 934 1.3.2.3 nathanw iha_resel(sc); 935 1.3.2.2 nathanw return; 936 1.3.2.2 nathanw } 937 1.3.2.2 nathanw 938 1.3.2.2 nathanw if ((sc->sc_sistat & (STIMEO | DISCD)) != 0) { 939 1.3.2.3 nathanw iha_busfree(sc); 940 1.3.2.2 nathanw return; 941 1.3.2.2 nathanw } 942 1.3.2.2 nathanw 943 1.3.2.2 nathanw if ((sc->sc_sistat & (SCMDN | SBSRV)) != 0) { 944 1.3.2.3 nathanw iha_next_state(sc); 945 1.3.2.2 nathanw return; 946 1.3.2.2 nathanw } 947 1.3.2.2 nathanw 948 1.3.2.2 nathanw if ((sc->sc_sistat & SELED) != 0) 949 1.3.2.3 nathanw iha_set_ssig(sc, 0, 0); 950 1.3.2.2 nathanw } 951 1.3.2.2 nathanw 952 1.3.2.2 nathanw /* 953 1.3.2.2 nathanw * There were no interrupts pending which required action elsewhere, so 954 1.3.2.2 nathanw * see if it is possible to start the selection phase on a pending SCB 955 1.3.2.2 nathanw */ 956 1.3.2.3 nathanw if ((scb = iha_find_pend_scb(sc)) == NULL) 957 1.3.2.2 nathanw return; 958 1.3.2.2 nathanw 959 1.3.2.2 nathanw tcs = scb->tcs; 960 1.3.2.2 nathanw 961 1.3.2.2 nathanw /* program HBA's SCSI ID & target SCSI ID */ 962 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SID, (sc->sc_id << 4) | scb->target); 963 1.3.2.2 nathanw 964 1.3.2.6 nathanw if ((scb->xs->xs_control & XS_CTL_RESET) == 0) { 965 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 966 1.3.2.2 nathanw 967 1.3.2.2 nathanw if ((tcs->flags & FLAG_NO_NEG_SYNC) == 0 || 968 1.3.2.2 nathanw (tcs->flags & FLAG_NO_NEG_WIDE) == 0) 969 1.3.2.3 nathanw iha_select(sc, scb, SELATNSTOP); 970 1.3.2.2 nathanw 971 1.3.2.2 nathanw else if (scb->scb_tagmsg != 0) 972 1.3.2.3 nathanw iha_select(sc, scb, SEL_ATN3); 973 1.3.2.2 nathanw 974 1.3.2.2 nathanw else 975 1.3.2.3 nathanw iha_select(sc, scb, SEL_ATN); 976 1.3.2.2 nathanw 977 1.3.2.2 nathanw } else { 978 1.3.2.3 nathanw iha_select(sc, scb, SELATNSTOP); 979 1.3.2.2 nathanw scb->nextstat = 8; 980 1.3.2.2 nathanw } 981 1.3.2.2 nathanw 982 1.3.2.6 nathanw if ((scb->xs->xs_control & XS_CTL_POLL) != 0) { 983 1.3.2.6 nathanw int timeout; 984 1.3.2.6 nathanw for (timeout = scb->xs->timeout; timeout > 0; timeout--) { 985 1.3.2.3 nathanw if (iha_wait(sc, NO_OP) == -1) 986 1.3.2.2 nathanw break; 987 1.3.2.3 nathanw if (iha_next_state(sc) == -1) 988 1.3.2.2 nathanw break; 989 1.3.2.2 nathanw delay(1000); /* Only happens in boot, so it's ok */ 990 1.3.2.2 nathanw } 991 1.3.2.2 nathanw 992 1.3.2.2 nathanw /* 993 1.3.2.2 nathanw * Since done queue processing not done until AFTER this 994 1.3.2.2 nathanw * function returns, scb is on the done queue, not 995 1.3.2.2 nathanw * the free queue at this point and still has valid data 996 1.3.2.2 nathanw * 997 1.3.2.2 nathanw * Conversely, xs->error has not been set yet 998 1.3.2.2 nathanw */ 999 1.3.2.6 nathanw if (timeout == 0) 1000 1.3.2.3 nathanw iha_timeout(scb); 1001 1.3.2.2 nathanw } 1002 1.3.2.2 nathanw } 1003 1.3.2.2 nathanw 1004 1.3.2.2 nathanw /* 1005 1.3.2.3 nathanw * iha_data_over_run - return HOST_OK for all SCSI opcodes where BufLen 1006 1.3.2.2 nathanw * is an 'Allocation Length'. All other SCSI opcodes 1007 1.3.2.2 nathanw * get HOST_DO_DU as they SHOULD have xferred all the 1008 1.3.2.2 nathanw * data requested. 1009 1.3.2.2 nathanw * 1010 1.3.2.2 nathanw * The list of opcodes using 'Allocation Length' was 1011 1.3.2.2 nathanw * found by scanning all the SCSI-3 T10 drafts. See 1012 1.3.2.2 nathanw * www.t10.org for the curious with a .pdf reader. 1013 1.3.2.2 nathanw */ 1014 1.3.2.2 nathanw static u_int8_t 1015 1.3.2.3 nathanw iha_data_over_run(scb) 1016 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1017 1.3.2.2 nathanw { 1018 1.3.2.2 nathanw switch (scb->cmd[0]) { 1019 1.3.2.2 nathanw case 0x03: /* Request Sense SPC-2 */ 1020 1.3.2.2 nathanw case 0x12: /* Inquiry SPC-2 */ 1021 1.3.2.2 nathanw case 0x1a: /* Mode Sense (6 byte version) SPC-2 */ 1022 1.3.2.2 nathanw case 0x1c: /* Receive Diagnostic Results SPC-2 */ 1023 1.3.2.2 nathanw case 0x23: /* Read Format Capacities MMC-2 */ 1024 1.3.2.2 nathanw case 0x29: /* Read Generation SBC */ 1025 1.3.2.2 nathanw case 0x34: /* Read Position SSC-2 */ 1026 1.3.2.2 nathanw case 0x37: /* Read Defect Data SBC */ 1027 1.3.2.2 nathanw case 0x3c: /* Read Buffer SPC-2 */ 1028 1.3.2.2 nathanw case 0x42: /* Read Sub Channel MMC-2 */ 1029 1.3.2.2 nathanw case 0x43: /* Read TOC/PMA/ATIP MMC */ 1030 1.3.2.2 nathanw 1031 1.3.2.2 nathanw /* XXX - 2 with same opcode of 0x44? */ 1032 1.3.2.2 nathanw case 0x44: /* Read Header/Read Density Suprt MMC/SSC*/ 1033 1.3.2.2 nathanw 1034 1.3.2.2 nathanw case 0x46: /* Get Configuration MMC-2 */ 1035 1.3.2.2 nathanw case 0x4a: /* Get Event/Status Notification MMC-2 */ 1036 1.3.2.2 nathanw case 0x4d: /* Log Sense SPC-2 */ 1037 1.3.2.2 nathanw case 0x51: /* Read Disc Information MMC */ 1038 1.3.2.2 nathanw case 0x52: /* Read Track Information MMC */ 1039 1.3.2.2 nathanw case 0x59: /* Read Master CUE MMC */ 1040 1.3.2.2 nathanw case 0x5a: /* Mode Sense (10 byte version) SPC-2 */ 1041 1.3.2.2 nathanw case 0x5c: /* Read Buffer Capacity MMC */ 1042 1.3.2.2 nathanw case 0x5e: /* Persistant Reserve In SPC-2 */ 1043 1.3.2.2 nathanw case 0x84: /* Receive Copy Results SPC-2 */ 1044 1.3.2.2 nathanw case 0xa0: /* Report LUNs SPC-2 */ 1045 1.3.2.2 nathanw case 0xa3: /* Various Report requests SBC-2/SCC-2*/ 1046 1.3.2.2 nathanw case 0xa4: /* Report Key MMC-2 */ 1047 1.3.2.2 nathanw case 0xad: /* Read DVD Structure MMC-2 */ 1048 1.3.2.2 nathanw case 0xb4: /* Read Element Status (Attached) SMC */ 1049 1.3.2.2 nathanw case 0xb5: /* Request Volume Element Address SMC */ 1050 1.3.2.2 nathanw case 0xb7: /* Read Defect Data (12 byte ver.) SBC */ 1051 1.3.2.2 nathanw case 0xb8: /* Read Element Status (Independ.) SMC */ 1052 1.3.2.2 nathanw case 0xba: /* Report Redundancy SCC-2 */ 1053 1.3.2.2 nathanw case 0xbd: /* Mechanism Status MMC */ 1054 1.3.2.2 nathanw case 0xbe: /* Report Basic Redundancy SCC-2 */ 1055 1.3.2.2 nathanw 1056 1.3.2.2 nathanw return (HOST_OK); 1057 1.3.2.2 nathanw break; 1058 1.3.2.2 nathanw 1059 1.3.2.2 nathanw default: 1060 1.3.2.2 nathanw return (HOST_DO_DU); 1061 1.3.2.2 nathanw break; 1062 1.3.2.2 nathanw } 1063 1.3.2.2 nathanw } 1064 1.3.2.2 nathanw 1065 1.3.2.2 nathanw /* 1066 1.3.2.3 nathanw * iha_next_state - prcess the current SCB as requested in it's 1067 1.3.2.2 nathanw * nextstat member. 1068 1.3.2.2 nathanw */ 1069 1.3.2.2 nathanw static int 1070 1.3.2.3 nathanw iha_next_state(sc) 1071 1.3.2.2 nathanw struct iha_softc *sc; 1072 1.3.2.2 nathanw { 1073 1.3.2.2 nathanw 1074 1.3.2.2 nathanw if (sc->sc_actscb == NULL) 1075 1.3.2.2 nathanw return (-1); 1076 1.3.2.2 nathanw 1077 1.3.2.2 nathanw switch (sc->sc_actscb->nextstat) { 1078 1.3.2.2 nathanw case 1: 1079 1.3.2.3 nathanw if (iha_state_1(sc) == 3) 1080 1.3.2.2 nathanw goto state_3; 1081 1.3.2.2 nathanw break; 1082 1.3.2.2 nathanw 1083 1.3.2.2 nathanw case 2: 1084 1.3.2.3 nathanw switch (iha_state_2(sc)) { 1085 1.3.2.2 nathanw case 3: 1086 1.3.2.2 nathanw goto state_3; 1087 1.3.2.2 nathanw case 4: 1088 1.3.2.2 nathanw goto state_4; 1089 1.3.2.2 nathanw default: 1090 1.3.2.2 nathanw break; 1091 1.3.2.2 nathanw } 1092 1.3.2.2 nathanw break; 1093 1.3.2.2 nathanw 1094 1.3.2.2 nathanw case 3: 1095 1.3.2.2 nathanw state_3: 1096 1.3.2.3 nathanw if (iha_state_3(sc) == 4) 1097 1.3.2.2 nathanw goto state_4; 1098 1.3.2.2 nathanw break; 1099 1.3.2.2 nathanw 1100 1.3.2.2 nathanw case 4: 1101 1.3.2.2 nathanw state_4: 1102 1.3.2.3 nathanw switch (iha_state_4(sc)) { 1103 1.3.2.2 nathanw case 0: 1104 1.3.2.2 nathanw return (0); 1105 1.3.2.2 nathanw case 6: 1106 1.3.2.2 nathanw goto state_6; 1107 1.3.2.2 nathanw default: 1108 1.3.2.2 nathanw break; 1109 1.3.2.2 nathanw } 1110 1.3.2.2 nathanw break; 1111 1.3.2.2 nathanw 1112 1.3.2.2 nathanw case 5: 1113 1.3.2.3 nathanw switch (iha_state_5(sc)) { 1114 1.3.2.2 nathanw case 4: 1115 1.3.2.2 nathanw goto state_4; 1116 1.3.2.2 nathanw case 6: 1117 1.3.2.2 nathanw goto state_6; 1118 1.3.2.2 nathanw default: 1119 1.3.2.2 nathanw break; 1120 1.3.2.2 nathanw } 1121 1.3.2.2 nathanw break; 1122 1.3.2.2 nathanw 1123 1.3.2.2 nathanw case 6: 1124 1.3.2.2 nathanw state_6: 1125 1.3.2.3 nathanw iha_state_6(sc); 1126 1.3.2.2 nathanw break; 1127 1.3.2.2 nathanw 1128 1.3.2.2 nathanw case 8: 1129 1.3.2.3 nathanw iha_state_8(sc); 1130 1.3.2.2 nathanw break; 1131 1.3.2.2 nathanw 1132 1.3.2.2 nathanw default: 1133 1.3.2.2 nathanw #ifdef IHA_DEBUG_STATE 1134 1.3.2.2 nathanw printf("[debug] -unknown state: %i-\n", 1135 1.3.2.2 nathanw sc->sc_actscb->nextstat); 1136 1.3.2.2 nathanw #endif 1137 1.3.2.3 nathanw iha_bad_seq(sc); 1138 1.3.2.2 nathanw break; 1139 1.3.2.2 nathanw } 1140 1.3.2.2 nathanw 1141 1.3.2.2 nathanw return (-1); 1142 1.3.2.2 nathanw } 1143 1.3.2.2 nathanw 1144 1.3.2.2 nathanw /* 1145 1.3.2.3 nathanw * iha_state_1 - selection is complete after a SELATNSTOP. If the target 1146 1.3.2.2 nathanw * has put the bus into MSG_OUT phase start wide/sync 1147 1.3.2.2 nathanw * negotiation. Otherwise clear the FIFO and go to state 3, 1148 1.3.2.2 nathanw * which will send the SCSI CDB to the target. 1149 1.3.2.2 nathanw */ 1150 1.3.2.2 nathanw static int 1151 1.3.2.3 nathanw iha_state_1(sc) 1152 1.3.2.2 nathanw struct iha_softc *sc; 1153 1.3.2.2 nathanw { 1154 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1155 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1156 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1157 1.3.2.2 nathanw struct tcs *tcs; 1158 1.3.2.2 nathanw int flags; 1159 1.3.2.2 nathanw 1160 1.3.2.3 nathanw iha_mark_busy_scb(scb); 1161 1.3.2.2 nathanw 1162 1.3.2.2 nathanw tcs = scb->tcs; 1163 1.3.2.2 nathanw 1164 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 1165 1.3.2.2 nathanw 1166 1.3.2.2 nathanw /* 1167 1.3.2.2 nathanw * If we are in PHASE_MSG_OUT, send 1168 1.3.2.2 nathanw * a) IDENT message (with tags if appropriate) 1169 1.3.2.2 nathanw * b) WDTR if the target is configured to negotiate wide xfers 1170 1.3.2.2 nathanw * ** OR ** 1171 1.3.2.2 nathanw * c) SDTR if the target is configured to negotiate sync xfers 1172 1.3.2.2 nathanw * but not wide ones 1173 1.3.2.2 nathanw * 1174 1.3.2.2 nathanw * If we are NOT, then the target is not asking for anything but 1175 1.3.2.2 nathanw * the data/command, so go straight to state 3. 1176 1.3.2.2 nathanw */ 1177 1.3.2.2 nathanw if (sc->sc_phase == PHASE_MSG_OUT) { 1178 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL1, (ESBUSIN | EHRSL)); 1179 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1180 1.3.2.2 nathanw 1181 1.3.2.2 nathanw if (scb->scb_tagmsg != 0) { 1182 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, 1183 1.3.2.2 nathanw scb->scb_tagmsg); 1184 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, 1185 1.3.2.2 nathanw scb->scb_tagid); 1186 1.3.2.2 nathanw } 1187 1.3.2.2 nathanw 1188 1.3.2.2 nathanw flags = tcs->flags; 1189 1.3.2.2 nathanw if ((flags & FLAG_NO_NEG_WIDE) == 0) { 1190 1.3.2.3 nathanw if (iha_msgout_wdtr(sc) == -1) 1191 1.3.2.2 nathanw return (-1); 1192 1.3.2.2 nathanw } else if ((flags & FLAG_NO_NEG_SYNC) == 0) { 1193 1.3.2.3 nathanw if (iha_msgout_sdtr(sc) == -1) 1194 1.3.2.2 nathanw return (-1); 1195 1.3.2.2 nathanw } 1196 1.3.2.2 nathanw 1197 1.3.2.2 nathanw } else { 1198 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1199 1.3.2.3 nathanw iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1200 1.3.2.2 nathanw } 1201 1.3.2.2 nathanw 1202 1.3.2.2 nathanw return (3); 1203 1.3.2.2 nathanw } 1204 1.3.2.2 nathanw 1205 1.3.2.2 nathanw /* 1206 1.3.2.3 nathanw * iha_state_2 - selection is complete after a SEL_ATN or SEL_ATN3. If the SCSI 1207 1.3.2.2 nathanw * CDB has already been send, go to state 4 to start the data 1208 1.3.2.2 nathanw * xfer. Otherwise reset the FIFO and go to state 3, sending 1209 1.3.2.2 nathanw * the SCSI CDB. 1210 1.3.2.2 nathanw */ 1211 1.3.2.2 nathanw static int 1212 1.3.2.3 nathanw iha_state_2(sc) 1213 1.3.2.2 nathanw struct iha_softc *sc; 1214 1.3.2.2 nathanw { 1215 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1216 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1217 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1218 1.3.2.2 nathanw 1219 1.3.2.3 nathanw iha_mark_busy_scb(scb); 1220 1.3.2.2 nathanw 1221 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, scb->tcs->sconfig0); 1222 1.3.2.2 nathanw 1223 1.3.2.2 nathanw if ((sc->sc_status1 & CPDNE) != 0) 1224 1.3.2.2 nathanw return (4); 1225 1.3.2.2 nathanw 1226 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1227 1.3.2.2 nathanw 1228 1.3.2.3 nathanw iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1229 1.3.2.2 nathanw 1230 1.3.2.2 nathanw return (3); 1231 1.3.2.2 nathanw } 1232 1.3.2.2 nathanw 1233 1.3.2.2 nathanw /* 1234 1.3.2.3 nathanw * iha_state_3 - send the SCSI CDB to the target, processing any status 1235 1.3.2.2 nathanw * or other messages received until that is done or 1236 1.3.2.2 nathanw * abandoned. 1237 1.3.2.2 nathanw */ 1238 1.3.2.2 nathanw static int 1239 1.3.2.3 nathanw iha_state_3(sc) 1240 1.3.2.2 nathanw struct iha_softc *sc; 1241 1.3.2.2 nathanw { 1242 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1243 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1244 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1245 1.3.2.2 nathanw int flags; 1246 1.3.2.2 nathanw 1247 1.3.2.2 nathanw for (;;) { 1248 1.3.2.2 nathanw switch (sc->sc_phase) { 1249 1.3.2.2 nathanw case PHASE_CMD_OUT: 1250 1.3.2.2 nathanw bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1251 1.3.2.2 nathanw scb->cmd, scb->cmdlen); 1252 1.3.2.3 nathanw if (iha_wait(sc, XF_FIFO_OUT) == -1) 1253 1.3.2.2 nathanw return (-1); 1254 1.3.2.2 nathanw else if (sc->sc_phase == PHASE_CMD_OUT) { 1255 1.3.2.3 nathanw iha_bad_seq(sc); 1256 1.3.2.2 nathanw return (-1); 1257 1.3.2.2 nathanw } else 1258 1.3.2.2 nathanw return (4); 1259 1.3.2.2 nathanw 1260 1.3.2.2 nathanw case PHASE_MSG_IN: 1261 1.3.2.2 nathanw scb->nextstat = 3; 1262 1.3.2.3 nathanw if (iha_msgin(sc) == -1) 1263 1.3.2.2 nathanw return (-1); 1264 1.3.2.2 nathanw break; 1265 1.3.2.2 nathanw 1266 1.3.2.2 nathanw case PHASE_STATUS_IN: 1267 1.3.2.3 nathanw if (iha_status_msg(sc) == -1) 1268 1.3.2.2 nathanw return (-1); 1269 1.3.2.2 nathanw break; 1270 1.3.2.2 nathanw 1271 1.3.2.2 nathanw case PHASE_MSG_OUT: 1272 1.3.2.2 nathanw flags = scb->tcs->flags; 1273 1.3.2.2 nathanw if ((flags & FLAG_NO_NEG_SYNC) != 0) { 1274 1.3.2.3 nathanw if (iha_msgout(sc, MSG_NOOP) == -1) 1275 1.3.2.2 nathanw return (-1); 1276 1.3.2.3 nathanw } else if (iha_msgout_sdtr(sc) == -1) 1277 1.3.2.2 nathanw return (-1); 1278 1.3.2.2 nathanw break; 1279 1.3.2.2 nathanw 1280 1.3.2.2 nathanw default: 1281 1.3.2.2 nathanw printf("[debug] -s3- bad phase = %d\n", sc->sc_phase); 1282 1.3.2.3 nathanw iha_bad_seq(sc); 1283 1.3.2.2 nathanw return (-1); 1284 1.3.2.2 nathanw } 1285 1.3.2.2 nathanw } 1286 1.3.2.2 nathanw } 1287 1.3.2.2 nathanw 1288 1.3.2.2 nathanw /* 1289 1.3.2.3 nathanw * iha_state_4 - start a data xfer. Handle any bus state 1290 1.3.2.2 nathanw * transitions until PHASE_DATA_IN/_OUT 1291 1.3.2.2 nathanw * or the attempt is abandoned. If there is 1292 1.3.2.2 nathanw * no data to xfer, go to state 6 and finish 1293 1.3.2.2 nathanw * processing the current SCB. 1294 1.3.2.2 nathanw */ 1295 1.3.2.2 nathanw static int 1296 1.3.2.3 nathanw iha_state_4(sc) 1297 1.3.2.2 nathanw struct iha_softc *sc; 1298 1.3.2.2 nathanw { 1299 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1300 1.3.2.2 nathanw 1301 1.3.2.6 nathanw if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) == 1302 1.3.2.6 nathanw (FLAG_DATAIN | FLAG_DATAOUT)) 1303 1.3.2.2 nathanw return (6); /* Both dir flags set => NO xfer was requested */ 1304 1.3.2.2 nathanw 1305 1.3.2.2 nathanw for (;;) { 1306 1.3.2.2 nathanw if (scb->buflen == 0) 1307 1.3.2.2 nathanw return (6); 1308 1.3.2.2 nathanw 1309 1.3.2.2 nathanw switch (sc->sc_phase) { 1310 1.3.2.2 nathanw case PHASE_STATUS_IN: 1311 1.3.2.6 nathanw if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1312 1.3.2.3 nathanw scb->ha_stat = iha_data_over_run(scb); 1313 1.3.2.3 nathanw if ((iha_status_msg(sc)) == -1) 1314 1.3.2.2 nathanw return (-1); 1315 1.3.2.2 nathanw break; 1316 1.3.2.2 nathanw 1317 1.3.2.2 nathanw case PHASE_MSG_IN: 1318 1.3.2.2 nathanw scb->nextstat = 4; 1319 1.3.2.3 nathanw if (iha_msgin(sc) == -1) 1320 1.3.2.2 nathanw return (-1); 1321 1.3.2.2 nathanw break; 1322 1.3.2.2 nathanw 1323 1.3.2.2 nathanw case PHASE_MSG_OUT: 1324 1.3.2.2 nathanw if ((sc->sc_status0 & SPERR) != 0) { 1325 1.3.2.2 nathanw scb->buflen = 0; 1326 1.3.2.2 nathanw scb->ha_stat = HOST_SPERR; 1327 1.3.2.3 nathanw if (iha_msgout(sc, MSG_INITIATOR_DET_ERR) == -1) 1328 1.3.2.2 nathanw return (-1); 1329 1.3.2.2 nathanw else 1330 1.3.2.2 nathanw return (6); 1331 1.3.2.2 nathanw } else { 1332 1.3.2.3 nathanw if (iha_msgout(sc, MSG_NOOP) == -1) 1333 1.3.2.2 nathanw return (-1); 1334 1.3.2.2 nathanw } 1335 1.3.2.2 nathanw break; 1336 1.3.2.2 nathanw 1337 1.3.2.2 nathanw case PHASE_DATA_IN: 1338 1.3.2.6 nathanw return (iha_xfer_data(sc, scb, FLAG_DATAIN)); 1339 1.3.2.2 nathanw 1340 1.3.2.2 nathanw case PHASE_DATA_OUT: 1341 1.3.2.6 nathanw return (iha_xfer_data(sc, scb, FLAG_DATAOUT)); 1342 1.3.2.2 nathanw 1343 1.3.2.2 nathanw default: 1344 1.3.2.3 nathanw iha_bad_seq(sc); 1345 1.3.2.2 nathanw return (-1); 1346 1.3.2.2 nathanw } 1347 1.3.2.2 nathanw } 1348 1.3.2.2 nathanw } 1349 1.3.2.2 nathanw 1350 1.3.2.2 nathanw /* 1351 1.3.2.3 nathanw * iha_state_5 - handle the partial or final completion of the current 1352 1.3.2.2 nathanw * data xfer. If DMA is still active stop it. If there is 1353 1.3.2.2 nathanw * more data to xfer, go to state 4 and start the xfer. 1354 1.3.2.2 nathanw * If not go to state 6 and finish the SCB. 1355 1.3.2.2 nathanw */ 1356 1.3.2.2 nathanw static int 1357 1.3.2.3 nathanw iha_state_5(sc) 1358 1.3.2.2 nathanw struct iha_softc *sc; 1359 1.3.2.2 nathanw { 1360 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1361 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1362 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1363 1.3.2.2 nathanw struct iha_sg_element *sg; 1364 1.3.2.2 nathanw u_int32_t cnt; 1365 1.3.2.2 nathanw u_int8_t period, stat; 1366 1.3.2.2 nathanw long xcnt; /* cannot use unsigned!! see code: if (xcnt < 0) */ 1367 1.3.2.2 nathanw int i; 1368 1.3.2.2 nathanw 1369 1.3.2.2 nathanw cnt = bus_space_read_4(iot, ioh, TUL_STCNT0) & TCNT; 1370 1.3.2.2 nathanw 1371 1.3.2.2 nathanw /* 1372 1.3.2.2 nathanw * Stop any pending DMA activity and check for parity error. 1373 1.3.2.2 nathanw */ 1374 1.3.2.2 nathanw 1375 1.3.2.2 nathanw if ((bus_space_read_1(iot, ioh, TUL_DCMD) & XDIR) != 0) { 1376 1.3.2.2 nathanw /* Input Operation */ 1377 1.3.2.2 nathanw if ((sc->sc_status0 & SPERR) != 0) 1378 1.3.2.2 nathanw scb->ha_stat = HOST_SPERR; 1379 1.3.2.2 nathanw 1380 1.3.2.2 nathanw if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1381 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_DCTRL0, 1382 1.3.2.2 nathanw bus_space_read_1(iot, ioh, TUL_DCTRL0) | SXSTP); 1383 1.3.2.2 nathanw while (bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) 1384 1.3.2.2 nathanw ; 1385 1.3.2.2 nathanw } 1386 1.3.2.2 nathanw 1387 1.3.2.2 nathanw } else { 1388 1.3.2.2 nathanw /* Output Operation */ 1389 1.3.2.2 nathanw if ((sc->sc_status1 & SXCMP) == 0) { 1390 1.3.2.2 nathanw period = scb->tcs->syncm; 1391 1.3.2.2 nathanw if ((period & PERIOD_WIDE_SCSI) != 0) 1392 1.3.2.2 nathanw cnt += (bus_space_read_1(iot, ioh, 1393 1.3.2.2 nathanw TUL_SFIFOCNT) & FIFOC) * 2; 1394 1.3.2.2 nathanw else 1395 1.3.2.2 nathanw cnt += bus_space_read_1(iot, ioh, 1396 1.3.2.2 nathanw TUL_SFIFOCNT) & FIFOC; 1397 1.3.2.2 nathanw } 1398 1.3.2.2 nathanw 1399 1.3.2.2 nathanw if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1400 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 1401 1.3.2.2 nathanw do 1402 1.3.2.2 nathanw stat = bus_space_read_1(iot, ioh, TUL_ISTUS0); 1403 1.3.2.2 nathanw while ((stat & DABT) == 0); 1404 1.3.2.2 nathanw } 1405 1.3.2.2 nathanw 1406 1.3.2.2 nathanw if ((cnt == 1) && (sc->sc_phase == PHASE_DATA_OUT)) { 1407 1.3.2.3 nathanw if (iha_wait(sc, XF_FIFO_OUT) == -1) 1408 1.3.2.2 nathanw return (-1); 1409 1.3.2.2 nathanw cnt = 0; 1410 1.3.2.2 nathanw 1411 1.3.2.2 nathanw } else if ((sc->sc_status1 & SXCMP) == 0) 1412 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1413 1.3.2.2 nathanw } 1414 1.3.2.2 nathanw 1415 1.3.2.2 nathanw if (cnt == 0) { 1416 1.3.2.2 nathanw scb->buflen = 0; 1417 1.3.2.2 nathanw return (6); 1418 1.3.2.2 nathanw } 1419 1.3.2.2 nathanw 1420 1.3.2.2 nathanw /* Update active data pointer and restart the I/O at the new point */ 1421 1.3.2.2 nathanw 1422 1.3.2.2 nathanw xcnt = scb->buflen - cnt; /* xcnt == bytes xferred */ 1423 1.3.2.2 nathanw scb->buflen = cnt; /* cnt == bytes left */ 1424 1.3.2.2 nathanw 1425 1.3.2.2 nathanw if ((scb->flags & FLAG_SG) != 0) { 1426 1.3.2.2 nathanw sg = &scb->sglist[scb->sg_index]; 1427 1.3.2.2 nathanw for (i = scb->sg_index; i < scb->sg_max; sg++, i++) { 1428 1.3.2.2 nathanw xcnt -= le32toh(sg->sg_len); 1429 1.3.2.2 nathanw if (xcnt < 0) { 1430 1.3.2.2 nathanw xcnt += le32toh(sg->sg_len); 1431 1.3.2.2 nathanw 1432 1.3.2.2 nathanw sg->sg_addr = 1433 1.3.2.2 nathanw htole32(le32toh(sg->sg_addr) + xcnt); 1434 1.3.2.2 nathanw sg->sg_len = 1435 1.3.2.2 nathanw htole32(le32toh(sg->sg_len) - xcnt); 1436 1.3.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1437 1.3.2.2 nathanw scb->sgoffset, IHA_SG_SIZE, 1438 1.3.2.2 nathanw BUS_DMASYNC_PREWRITE); 1439 1.3.2.2 nathanw 1440 1.3.2.2 nathanw scb->bufaddr += (i - scb->sg_index) * 1441 1.3.2.2 nathanw sizeof(struct iha_sg_element); 1442 1.3.2.2 nathanw scb->sg_size = scb->sg_max - i; 1443 1.3.2.2 nathanw scb->sg_index = i; 1444 1.3.2.2 nathanw 1445 1.3.2.2 nathanw return (4); 1446 1.3.2.2 nathanw } 1447 1.3.2.2 nathanw } 1448 1.3.2.2 nathanw return (6); 1449 1.3.2.2 nathanw 1450 1.3.2.2 nathanw } else 1451 1.3.2.2 nathanw scb->bufaddr += xcnt; 1452 1.3.2.2 nathanw 1453 1.3.2.2 nathanw return (4); 1454 1.3.2.2 nathanw } 1455 1.3.2.2 nathanw 1456 1.3.2.2 nathanw /* 1457 1.3.2.3 nathanw * iha_state_6 - finish off the active scb (may require several 1458 1.3.2.2 nathanw * iterations if PHASE_MSG_IN) and return -1 to indicate 1459 1.3.2.2 nathanw * the bus is free. 1460 1.3.2.2 nathanw */ 1461 1.3.2.2 nathanw static int 1462 1.3.2.3 nathanw iha_state_6(sc) 1463 1.3.2.2 nathanw struct iha_softc *sc; 1464 1.3.2.2 nathanw { 1465 1.3.2.2 nathanw 1466 1.3.2.2 nathanw for (;;) { 1467 1.3.2.2 nathanw switch (sc->sc_phase) { 1468 1.3.2.2 nathanw case PHASE_STATUS_IN: 1469 1.3.2.3 nathanw if (iha_status_msg(sc) == -1) 1470 1.3.2.2 nathanw return (-1); 1471 1.3.2.2 nathanw break; 1472 1.3.2.2 nathanw 1473 1.3.2.2 nathanw case PHASE_MSG_IN: 1474 1.3.2.2 nathanw sc->sc_actscb->nextstat = 6; 1475 1.3.2.3 nathanw if ((iha_msgin(sc)) == -1) 1476 1.3.2.2 nathanw return (-1); 1477 1.3.2.2 nathanw break; 1478 1.3.2.2 nathanw 1479 1.3.2.2 nathanw case PHASE_MSG_OUT: 1480 1.3.2.3 nathanw if ((iha_msgout(sc, MSG_NOOP)) == -1) 1481 1.3.2.2 nathanw return (-1); 1482 1.3.2.2 nathanw break; 1483 1.3.2.2 nathanw 1484 1.3.2.2 nathanw case PHASE_DATA_IN: 1485 1.3.2.3 nathanw if (iha_xpad_in(sc) == -1) 1486 1.3.2.2 nathanw return (-1); 1487 1.3.2.2 nathanw break; 1488 1.3.2.2 nathanw 1489 1.3.2.2 nathanw case PHASE_DATA_OUT: 1490 1.3.2.3 nathanw if (iha_xpad_out(sc) == -1) 1491 1.3.2.2 nathanw return (-1); 1492 1.3.2.2 nathanw break; 1493 1.3.2.2 nathanw 1494 1.3.2.2 nathanw default: 1495 1.3.2.3 nathanw iha_bad_seq(sc); 1496 1.3.2.2 nathanw return (-1); 1497 1.3.2.2 nathanw } 1498 1.3.2.2 nathanw } 1499 1.3.2.2 nathanw } 1500 1.3.2.2 nathanw 1501 1.3.2.2 nathanw /* 1502 1.3.2.3 nathanw * iha_state_8 - reset the active device and all busy SCBs using it 1503 1.3.2.2 nathanw */ 1504 1.3.2.2 nathanw static int 1505 1.3.2.3 nathanw iha_state_8(sc) 1506 1.3.2.2 nathanw struct iha_softc *sc; 1507 1.3.2.2 nathanw { 1508 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1509 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1510 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1511 1.3.2.2 nathanw int i; 1512 1.3.2.2 nathanw u_int8_t tar; 1513 1.3.2.2 nathanw 1514 1.3.2.2 nathanw if (sc->sc_phase == PHASE_MSG_OUT) { 1515 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_BUS_DEV_RESET); 1516 1.3.2.2 nathanw 1517 1.3.2.2 nathanw scb = sc->sc_actscb; 1518 1.3.2.2 nathanw 1519 1.3.2.2 nathanw /* This SCB finished correctly -- resetting the device */ 1520 1.3.2.3 nathanw iha_append_done_scb(sc, scb, HOST_OK); 1521 1.3.2.2 nathanw 1522 1.3.2.3 nathanw iha_reset_tcs(scb->tcs, sc->sc_sconf1); 1523 1.3.2.2 nathanw 1524 1.3.2.2 nathanw tar = scb->target; 1525 1.3.2.2 nathanw for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1526 1.3.2.2 nathanw if (scb->target == tar) 1527 1.3.2.2 nathanw switch (scb->status) { 1528 1.3.2.2 nathanw case STATUS_BUSY: 1529 1.3.2.3 nathanw iha_append_done_scb(sc, 1530 1.3.2.2 nathanw scb, HOST_DEV_RST); 1531 1.3.2.2 nathanw break; 1532 1.3.2.2 nathanw 1533 1.3.2.2 nathanw case STATUS_SELECT: 1534 1.3.2.3 nathanw iha_push_pend_scb(sc, scb); 1535 1.3.2.2 nathanw break; 1536 1.3.2.2 nathanw 1537 1.3.2.2 nathanw default: 1538 1.3.2.2 nathanw break; 1539 1.3.2.2 nathanw } 1540 1.3.2.2 nathanw 1541 1.3.2.2 nathanw sc->sc_flags |= FLAG_EXPECT_DISC; 1542 1.3.2.2 nathanw 1543 1.3.2.3 nathanw if (iha_wait(sc, XF_FIFO_OUT) == -1) 1544 1.3.2.2 nathanw return (-1); 1545 1.3.2.2 nathanw } 1546 1.3.2.2 nathanw 1547 1.3.2.3 nathanw iha_bad_seq(sc); 1548 1.3.2.2 nathanw return (-1); 1549 1.3.2.2 nathanw } 1550 1.3.2.2 nathanw 1551 1.3.2.2 nathanw /* 1552 1.3.2.3 nathanw * iha_xfer_data - initiate the DMA xfer of the data 1553 1.3.2.2 nathanw */ 1554 1.3.2.2 nathanw static int 1555 1.3.2.3 nathanw iha_xfer_data(sc, scb, direction) 1556 1.3.2.2 nathanw struct iha_softc *sc; 1557 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1558 1.3.2.2 nathanw int direction; 1559 1.3.2.2 nathanw { 1560 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1561 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1562 1.3.2.2 nathanw u_int32_t xferlen; 1563 1.3.2.6 nathanw u_int8_t xfercmd; 1564 1.3.2.2 nathanw 1565 1.3.2.6 nathanw if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != direction) 1566 1.3.2.2 nathanw return (6); /* wrong direction, abandon I/O */ 1567 1.3.2.2 nathanw 1568 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, scb->buflen); 1569 1.3.2.2 nathanw 1570 1.3.2.6 nathanw xfercmd = STRXFR; 1571 1.3.2.6 nathanw if (direction == FLAG_DATAIN) 1572 1.3.2.6 nathanw xfercmd |= XDIR; 1573 1.3.2.2 nathanw 1574 1.3.2.6 nathanw if (scb->flags & FLAG_SG) { 1575 1.3.2.2 nathanw xferlen = scb->sg_size * sizeof(struct iha_sg_element); 1576 1.3.2.6 nathanw xfercmd |= SGXFR; 1577 1.3.2.6 nathanw } else 1578 1.3.2.6 nathanw xferlen = scb->buflen; 1579 1.3.2.2 nathanw 1580 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_DXC, xferlen); 1581 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_DXPA, scb->bufaddr); 1582 1.3.2.6 nathanw bus_space_write_1(iot, ioh, TUL_DCMD, xfercmd); 1583 1.3.2.2 nathanw 1584 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCMD, 1585 1.3.2.6 nathanw (direction == FLAG_DATAIN) ? XF_DMA_IN : XF_DMA_OUT); 1586 1.3.2.2 nathanw 1587 1.3.2.2 nathanw scb->nextstat = 5; 1588 1.3.2.2 nathanw 1589 1.3.2.2 nathanw return (0); 1590 1.3.2.2 nathanw } 1591 1.3.2.2 nathanw 1592 1.3.2.2 nathanw static int 1593 1.3.2.3 nathanw iha_xpad_in(sc) 1594 1.3.2.2 nathanw struct iha_softc *sc; 1595 1.3.2.2 nathanw { 1596 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1597 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1598 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1599 1.3.2.2 nathanw 1600 1.3.2.6 nathanw if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1601 1.3.2.2 nathanw scb->ha_stat = HOST_DO_DU; 1602 1.3.2.2 nathanw 1603 1.3.2.2 nathanw for (;;) { 1604 1.3.2.2 nathanw if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 1605 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 1606 1.3.2.2 nathanw else 1607 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1608 1.3.2.2 nathanw 1609 1.3.2.3 nathanw switch (iha_wait(sc, XF_FIFO_IN)) { 1610 1.3.2.2 nathanw case -1: 1611 1.3.2.2 nathanw return (-1); 1612 1.3.2.2 nathanw 1613 1.3.2.2 nathanw case PHASE_DATA_IN: 1614 1.3.2.2 nathanw bus_space_read_1(iot, ioh, TUL_SFIFO); 1615 1.3.2.2 nathanw break; 1616 1.3.2.2 nathanw 1617 1.3.2.2 nathanw default: 1618 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1619 1.3.2.2 nathanw return (6); 1620 1.3.2.2 nathanw } 1621 1.3.2.2 nathanw } 1622 1.3.2.2 nathanw } 1623 1.3.2.2 nathanw 1624 1.3.2.2 nathanw static int 1625 1.3.2.3 nathanw iha_xpad_out(sc) 1626 1.3.2.2 nathanw struct iha_softc *sc; 1627 1.3.2.2 nathanw { 1628 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1629 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1630 1.3.2.2 nathanw struct iha_scsi_req_q *scb = sc->sc_actscb; 1631 1.3.2.2 nathanw 1632 1.3.2.6 nathanw if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1633 1.3.2.2 nathanw scb->ha_stat = HOST_DO_DU; 1634 1.3.2.2 nathanw 1635 1.3.2.2 nathanw for (;;) { 1636 1.3.2.2 nathanw if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 1637 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 1638 1.3.2.2 nathanw else 1639 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1640 1.3.2.2 nathanw 1641 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 1642 1.3.2.2 nathanw 1643 1.3.2.3 nathanw switch (iha_wait(sc, XF_FIFO_OUT)) { 1644 1.3.2.2 nathanw case -1: 1645 1.3.2.2 nathanw return (-1); 1646 1.3.2.2 nathanw 1647 1.3.2.2 nathanw case PHASE_DATA_OUT: 1648 1.3.2.2 nathanw break; 1649 1.3.2.2 nathanw 1650 1.3.2.2 nathanw default: 1651 1.3.2.2 nathanw /* Disable wide CPU to allow read 16 bits */ 1652 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1653 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1654 1.3.2.2 nathanw return (6); 1655 1.3.2.2 nathanw } 1656 1.3.2.2 nathanw } 1657 1.3.2.2 nathanw } 1658 1.3.2.2 nathanw 1659 1.3.2.2 nathanw static int 1660 1.3.2.3 nathanw iha_status_msg(sc) 1661 1.3.2.2 nathanw struct iha_softc *sc; 1662 1.3.2.2 nathanw { 1663 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1664 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1665 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1666 1.3.2.2 nathanw u_int8_t msg; 1667 1.3.2.2 nathanw int phase; 1668 1.3.2.2 nathanw 1669 1.3.2.3 nathanw if ((phase = iha_wait(sc, CMD_COMP)) == -1) 1670 1.3.2.2 nathanw return (-1); 1671 1.3.2.2 nathanw 1672 1.3.2.2 nathanw scb = sc->sc_actscb; 1673 1.3.2.2 nathanw 1674 1.3.2.2 nathanw scb->ta_stat = bus_space_read_1(iot, ioh, TUL_SFIFO); 1675 1.3.2.2 nathanw 1676 1.3.2.2 nathanw if (phase == PHASE_MSG_OUT) { 1677 1.3.2.2 nathanw if ((sc->sc_status0 & SPERR) == 0) 1678 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_NOOP); 1679 1.3.2.2 nathanw else 1680 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, 1681 1.3.2.2 nathanw MSG_PARITY_ERROR); 1682 1.3.2.2 nathanw 1683 1.3.2.3 nathanw return (iha_wait(sc, XF_FIFO_OUT)); 1684 1.3.2.2 nathanw 1685 1.3.2.2 nathanw } else if (phase == PHASE_MSG_IN) { 1686 1.3.2.2 nathanw msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 1687 1.3.2.2 nathanw 1688 1.3.2.2 nathanw if ((sc->sc_status0 & SPERR) != 0) 1689 1.3.2.3 nathanw switch (iha_wait(sc, MSG_ACCEPT)) { 1690 1.3.2.2 nathanw case -1: 1691 1.3.2.2 nathanw return (-1); 1692 1.3.2.2 nathanw case PHASE_MSG_OUT: 1693 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, 1694 1.3.2.2 nathanw MSG_PARITY_ERROR); 1695 1.3.2.3 nathanw return (iha_wait(sc, XF_FIFO_OUT)); 1696 1.3.2.2 nathanw default: 1697 1.3.2.3 nathanw iha_bad_seq(sc); 1698 1.3.2.2 nathanw return (-1); 1699 1.3.2.2 nathanw } 1700 1.3.2.2 nathanw 1701 1.3.2.2 nathanw if (msg == MSG_CMDCOMPLETE) { 1702 1.3.2.2 nathanw if ((scb->ta_stat & 1703 1.3.2.2 nathanw (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) { 1704 1.3.2.3 nathanw iha_bad_seq(sc); 1705 1.3.2.2 nathanw return (-1); 1706 1.3.2.2 nathanw } 1707 1.3.2.2 nathanw sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 1708 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1709 1.3.2.3 nathanw return (iha_wait(sc, MSG_ACCEPT)); 1710 1.3.2.2 nathanw } 1711 1.3.2.2 nathanw 1712 1.3.2.2 nathanw if ((msg == MSG_LINK_CMD_COMPLETE) 1713 1.3.2.2 nathanw || (msg == MSG_LINK_CMD_COMPLETEF)) { 1714 1.3.2.2 nathanw if ((scb->ta_stat & 1715 1.3.2.2 nathanw (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) 1716 1.3.2.3 nathanw return (iha_wait(sc, MSG_ACCEPT)); 1717 1.3.2.2 nathanw } 1718 1.3.2.2 nathanw } 1719 1.3.2.2 nathanw 1720 1.3.2.3 nathanw iha_bad_seq(sc); 1721 1.3.2.2 nathanw return (-1); 1722 1.3.2.2 nathanw } 1723 1.3.2.2 nathanw 1724 1.3.2.2 nathanw /* 1725 1.3.2.3 nathanw * iha_busfree - SCSI bus free detected as a result of a TIMEOUT or 1726 1.3.2.2 nathanw * DISCONNECT interrupt. Reset the tulip FIFO and 1727 1.3.2.2 nathanw * SCONFIG0 and enable hardware reselect. Move any active 1728 1.3.2.2 nathanw * SCB to sc_donescb list. Return an appropriate host status 1729 1.3.2.2 nathanw * if an I/O was active. 1730 1.3.2.2 nathanw */ 1731 1.3.2.2 nathanw static void 1732 1.3.2.3 nathanw iha_busfree(sc) 1733 1.3.2.2 nathanw struct iha_softc *sc; 1734 1.3.2.2 nathanw { 1735 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1736 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1737 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1738 1.3.2.2 nathanw 1739 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1740 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, SCONFIG0DEFAULT); 1741 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1742 1.3.2.2 nathanw 1743 1.3.2.2 nathanw scb = sc->sc_actscb; 1744 1.3.2.2 nathanw 1745 1.3.2.2 nathanw if (scb != NULL) { 1746 1.3.2.2 nathanw if (scb->status == STATUS_SELECT) 1747 1.3.2.2 nathanw /* selection timeout */ 1748 1.3.2.3 nathanw iha_append_done_scb(sc, scb, HOST_SEL_TOUT); 1749 1.3.2.2 nathanw else 1750 1.3.2.2 nathanw /* Unexpected bus free */ 1751 1.3.2.3 nathanw iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 1752 1.3.2.2 nathanw } 1753 1.3.2.2 nathanw } 1754 1.3.2.2 nathanw 1755 1.3.2.2 nathanw static void 1756 1.3.2.3 nathanw iha_reset_scsi_bus(sc) 1757 1.3.2.2 nathanw struct iha_softc *sc; 1758 1.3.2.2 nathanw { 1759 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1760 1.3.2.2 nathanw struct tcs *tcs; 1761 1.3.2.2 nathanw int i, s; 1762 1.3.2.2 nathanw 1763 1.3.2.2 nathanw s = splbio(); 1764 1.3.2.2 nathanw 1765 1.3.2.3 nathanw iha_reset_dma(sc); 1766 1.3.2.2 nathanw 1767 1.3.2.2 nathanw for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1768 1.3.2.2 nathanw switch (scb->status) { 1769 1.3.2.2 nathanw case STATUS_BUSY: 1770 1.3.2.3 nathanw iha_append_done_scb(sc, scb, HOST_SCSI_RST); 1771 1.3.2.2 nathanw break; 1772 1.3.2.2 nathanw 1773 1.3.2.2 nathanw case STATUS_SELECT: 1774 1.3.2.3 nathanw iha_push_pend_scb(sc, scb); 1775 1.3.2.2 nathanw break; 1776 1.3.2.2 nathanw 1777 1.3.2.2 nathanw default: 1778 1.3.2.2 nathanw break; 1779 1.3.2.2 nathanw } 1780 1.3.2.2 nathanw 1781 1.3.2.2 nathanw for (i = 0, tcs = sc->sc_tcs; i < IHA_MAX_TARGETS; i++, tcs++) 1782 1.3.2.3 nathanw iha_reset_tcs(tcs, sc->sc_sconf1); 1783 1.3.2.2 nathanw 1784 1.3.2.2 nathanw splx(s); 1785 1.3.2.2 nathanw } 1786 1.3.2.2 nathanw 1787 1.3.2.2 nathanw /* 1788 1.3.2.3 nathanw * iha_resel - handle a detected SCSI bus reselection request. 1789 1.3.2.2 nathanw */ 1790 1.3.2.2 nathanw static int 1791 1.3.2.3 nathanw iha_resel(sc) 1792 1.3.2.2 nathanw struct iha_softc *sc; 1793 1.3.2.2 nathanw { 1794 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1795 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1796 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 1797 1.3.2.2 nathanw struct tcs *tcs; 1798 1.3.2.2 nathanw u_int8_t tag, target, lun, msg, abortmsg; 1799 1.3.2.2 nathanw 1800 1.3.2.2 nathanw if (sc->sc_actscb != NULL) { 1801 1.3.2.2 nathanw if ((sc->sc_actscb->status == STATUS_SELECT)) 1802 1.3.2.3 nathanw iha_push_pend_scb(sc, sc->sc_actscb); 1803 1.3.2.3 nathanw sc->sc_actscb = NULL; 1804 1.3.2.2 nathanw } 1805 1.3.2.2 nathanw 1806 1.3.2.2 nathanw target = bus_space_read_1(iot, ioh, TUL_SBID); 1807 1.3.2.2 nathanw lun = bus_space_read_1(iot, ioh, TUL_SALVC) & MSG_IDENTIFY_LUNMASK; 1808 1.3.2.2 nathanw 1809 1.3.2.2 nathanw tcs = &sc->sc_tcs[target]; 1810 1.3.2.2 nathanw 1811 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 1812 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 1813 1.3.2.2 nathanw 1814 1.3.2.2 nathanw abortmsg = MSG_ABORT; /* until a valid tag has been obtained */ 1815 1.3.2.2 nathanw 1816 1.3.2.2 nathanw if (tcs->ntagscb != NULL) 1817 1.3.2.2 nathanw /* There is a non-tagged I/O active on the target */ 1818 1.3.2.2 nathanw scb = tcs->ntagscb; 1819 1.3.2.2 nathanw 1820 1.3.2.2 nathanw else { 1821 1.3.2.2 nathanw /* 1822 1.3.2.2 nathanw * Since there is no active non-tagged operation 1823 1.3.2.2 nathanw * read the tag type, the tag itself, and find 1824 1.3.2.2 nathanw * the appropriate scb by indexing sc_scb with 1825 1.3.2.2 nathanw * the tag. 1826 1.3.2.2 nathanw */ 1827 1.3.2.2 nathanw 1828 1.3.2.3 nathanw switch (iha_wait(sc, MSG_ACCEPT)) { 1829 1.3.2.2 nathanw case -1: 1830 1.3.2.2 nathanw return (-1); 1831 1.3.2.2 nathanw case PHASE_MSG_IN: 1832 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1833 1.3.2.3 nathanw if ((iha_wait(sc, XF_FIFO_IN)) == -1) 1834 1.3.2.2 nathanw return (-1); 1835 1.3.2.2 nathanw break; 1836 1.3.2.2 nathanw default: 1837 1.3.2.2 nathanw goto abort; 1838 1.3.2.2 nathanw } 1839 1.3.2.2 nathanw 1840 1.3.2.2 nathanw msg = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag Msg */ 1841 1.3.2.2 nathanw 1842 1.3.2.2 nathanw if ((msg < MSG_SIMPLE_Q_TAG) || (msg > MSG_ORDERED_Q_TAG)) 1843 1.3.2.2 nathanw goto abort; 1844 1.3.2.2 nathanw 1845 1.3.2.3 nathanw switch (iha_wait(sc, MSG_ACCEPT)) { 1846 1.3.2.2 nathanw case -1: 1847 1.3.2.2 nathanw return (-1); 1848 1.3.2.2 nathanw case PHASE_MSG_IN: 1849 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1850 1.3.2.3 nathanw if ((iha_wait(sc, XF_FIFO_IN)) == -1) 1851 1.3.2.2 nathanw return (-1); 1852 1.3.2.2 nathanw break; 1853 1.3.2.2 nathanw default: 1854 1.3.2.2 nathanw goto abort; 1855 1.3.2.2 nathanw } 1856 1.3.2.2 nathanw 1857 1.3.2.2 nathanw tag = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag ID */ 1858 1.3.2.2 nathanw scb = &sc->sc_scb[tag]; 1859 1.3.2.2 nathanw 1860 1.3.2.2 nathanw abortmsg = MSG_ABORT_TAG; /* Now that we have valdid tag! */ 1861 1.3.2.2 nathanw } 1862 1.3.2.2 nathanw 1863 1.3.2.2 nathanw if ((scb->target != target) 1864 1.3.2.2 nathanw || (scb->lun != lun) 1865 1.3.2.2 nathanw || (scb->status != STATUS_BUSY)) { 1866 1.3.2.2 nathanw abort: 1867 1.3.2.3 nathanw iha_msgout_abort(sc, abortmsg); 1868 1.3.2.2 nathanw return (-1); 1869 1.3.2.2 nathanw } 1870 1.3.2.2 nathanw 1871 1.3.2.2 nathanw sc->sc_actscb = scb; 1872 1.3.2.2 nathanw 1873 1.3.2.3 nathanw if (iha_wait(sc, MSG_ACCEPT) == -1) 1874 1.3.2.2 nathanw return (-1); 1875 1.3.2.2 nathanw 1876 1.3.2.3 nathanw return (iha_next_state(sc)); 1877 1.3.2.2 nathanw } 1878 1.3.2.2 nathanw 1879 1.3.2.2 nathanw static int 1880 1.3.2.3 nathanw iha_msgin(sc) 1881 1.3.2.2 nathanw struct iha_softc *sc; 1882 1.3.2.2 nathanw { 1883 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1884 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1885 1.3.2.2 nathanw int flags; 1886 1.3.2.2 nathanw int phase; 1887 1.3.2.2 nathanw u_int8_t msg; 1888 1.3.2.2 nathanw 1889 1.3.2.2 nathanw for (;;) { 1890 1.3.2.2 nathanw if ((bus_space_read_1(iot, ioh, TUL_SFIFOCNT) & FIFOC) > 0) 1891 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1892 1.3.2.2 nathanw 1893 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1894 1.3.2.2 nathanw 1895 1.3.2.3 nathanw phase = iha_wait(sc, XF_FIFO_IN); 1896 1.3.2.2 nathanw msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 1897 1.3.2.2 nathanw 1898 1.3.2.2 nathanw switch (msg) { 1899 1.3.2.2 nathanw case MSG_DISCONNECT: 1900 1.3.2.2 nathanw sc->sc_flags |= FLAG_EXPECT_DISC; 1901 1.3.2.3 nathanw if (iha_wait(sc, MSG_ACCEPT) != -1) 1902 1.3.2.3 nathanw iha_bad_seq(sc); 1903 1.3.2.2 nathanw phase = -1; 1904 1.3.2.2 nathanw break; 1905 1.3.2.2 nathanw case MSG_SAVEDATAPOINTER: 1906 1.3.2.2 nathanw case MSG_RESTOREPOINTERS: 1907 1.3.2.2 nathanw case MSG_NOOP: 1908 1.3.2.3 nathanw phase = iha_wait(sc, MSG_ACCEPT); 1909 1.3.2.2 nathanw break; 1910 1.3.2.2 nathanw case MSG_MESSAGE_REJECT: 1911 1.3.2.2 nathanw /* XXX - need to clear FIFO like other 'Clear ATN'?*/ 1912 1.3.2.3 nathanw iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1913 1.3.2.2 nathanw flags = sc->sc_actscb->tcs->flags; 1914 1.3.2.2 nathanw if ((flags & FLAG_NO_NEG_SYNC) == 0) 1915 1.3.2.3 nathanw iha_set_ssig(sc, REQ | BSY | SEL, ATN); 1916 1.3.2.3 nathanw phase = iha_wait(sc, MSG_ACCEPT); 1917 1.3.2.2 nathanw break; 1918 1.3.2.2 nathanw case MSG_EXTENDED: 1919 1.3.2.3 nathanw phase = iha_msgin_extended(sc); 1920 1.3.2.2 nathanw break; 1921 1.3.2.2 nathanw case MSG_IGN_WIDE_RESIDUE: 1922 1.3.2.3 nathanw phase = iha_msgin_ignore_wid_resid(sc); 1923 1.3.2.2 nathanw break; 1924 1.3.2.2 nathanw case MSG_CMDCOMPLETE: 1925 1.3.2.2 nathanw sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 1926 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1927 1.3.2.3 nathanw phase = iha_wait(sc, MSG_ACCEPT); 1928 1.3.2.2 nathanw if (phase != -1) { 1929 1.3.2.3 nathanw iha_bad_seq(sc); 1930 1.3.2.2 nathanw return (-1); 1931 1.3.2.2 nathanw } 1932 1.3.2.2 nathanw break; 1933 1.3.2.2 nathanw default: 1934 1.3.2.3 nathanw printf("[debug] iha_msgin: bad msg type: %d\n", msg); 1935 1.3.2.3 nathanw phase = iha_msgout_reject(sc); 1936 1.3.2.2 nathanw break; 1937 1.3.2.2 nathanw } 1938 1.3.2.2 nathanw 1939 1.3.2.2 nathanw if (phase != PHASE_MSG_IN) 1940 1.3.2.2 nathanw return (phase); 1941 1.3.2.2 nathanw } 1942 1.3.2.2 nathanw /* NOTREACHED */ 1943 1.3.2.2 nathanw } 1944 1.3.2.2 nathanw 1945 1.3.2.2 nathanw static int 1946 1.3.2.3 nathanw iha_msgin_ignore_wid_resid(sc) 1947 1.3.2.2 nathanw struct iha_softc *sc; 1948 1.3.2.2 nathanw { 1949 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1950 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1951 1.3.2.2 nathanw int phase; 1952 1.3.2.2 nathanw 1953 1.3.2.3 nathanw phase = iha_wait(sc, MSG_ACCEPT); 1954 1.3.2.2 nathanw 1955 1.3.2.2 nathanw if (phase == PHASE_MSG_IN) { 1956 1.3.2.3 nathanw phase = iha_wait(sc, XF_FIFO_IN); 1957 1.3.2.2 nathanw 1958 1.3.2.3 nathanw if (phase != -1) { 1959 1.3.2.3 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 1960 1.3.2.3 nathanw bus_space_read_1(iot, ioh, TUL_SFIFO); 1961 1.3.2.3 nathanw bus_space_read_1(iot, ioh, TUL_SFIFO); 1962 1.3.2.2 nathanw 1963 1.3.2.3 nathanw phase = iha_wait(sc, MSG_ACCEPT); 1964 1.3.2.3 nathanw } 1965 1.3.2.2 nathanw } 1966 1.3.2.3 nathanw 1967 1.3.2.3 nathanw return (phase); 1968 1.3.2.2 nathanw } 1969 1.3.2.2 nathanw 1970 1.3.2.2 nathanw static int 1971 1.3.2.3 nathanw iha_msgin_extended(sc) 1972 1.3.2.2 nathanw struct iha_softc *sc; 1973 1.3.2.2 nathanw { 1974 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1975 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1976 1.3.2.2 nathanw int flags, i, phase, msglen, msgcode; 1977 1.3.2.2 nathanw 1978 1.3.2.2 nathanw /* 1979 1.3.2.2 nathanw * XXX - can we just stop reading and reject, or do we have to 1980 1.3.2.2 nathanw * read all input, discarding the excess, and then reject 1981 1.3.2.2 nathanw */ 1982 1.3.2.2 nathanw for (i = 0; i < IHA_MAX_EXTENDED_MSG; i++) { 1983 1.3.2.3 nathanw phase = iha_wait(sc, MSG_ACCEPT); 1984 1.3.2.2 nathanw 1985 1.3.2.2 nathanw if (phase != PHASE_MSG_IN) 1986 1.3.2.2 nathanw return (phase); 1987 1.3.2.2 nathanw 1988 1.3.2.2 nathanw bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1989 1.3.2.2 nathanw 1990 1.3.2.3 nathanw if (iha_wait(sc, XF_FIFO_IN) == -1) 1991 1.3.2.2 nathanw return (-1); 1992 1.3.2.2 nathanw 1993 1.3.2.2 nathanw sc->sc_msg[i] = bus_space_read_1(iot, ioh, TUL_SFIFO); 1994 1.3.2.2 nathanw 1995 1.3.2.2 nathanw if (sc->sc_msg[0] == i) 1996 1.3.2.2 nathanw break; 1997 1.3.2.2 nathanw } 1998 1.3.2.2 nathanw 1999 1.3.2.2 nathanw msglen = sc->sc_msg[0]; 2000 1.3.2.2 nathanw msgcode = sc->sc_msg[1]; 2001 1.3.2.2 nathanw 2002 1.3.2.2 nathanw if ((msglen == MSG_EXT_SDTR_LEN) && (msgcode == MSG_EXT_SDTR)) { 2003 1.3.2.3 nathanw if (iha_msgin_sdtr(sc) == 0) { 2004 1.3.2.3 nathanw iha_sync_done(sc); 2005 1.3.2.3 nathanw return (iha_wait(sc, MSG_ACCEPT)); 2006 1.3.2.2 nathanw } 2007 1.3.2.2 nathanw 2008 1.3.2.3 nathanw iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2009 1.3.2.2 nathanw 2010 1.3.2.3 nathanw phase = iha_wait(sc, MSG_ACCEPT); 2011 1.3.2.2 nathanw if (phase != PHASE_MSG_OUT) 2012 1.3.2.2 nathanw return (phase); 2013 1.3.2.2 nathanw 2014 1.3.2.2 nathanw /* Clear FIFO for important message - final SYNC offer */ 2015 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2016 1.3.2.2 nathanw 2017 1.3.2.3 nathanw iha_sync_done(sc); /* This is our final offer */ 2018 1.3.2.2 nathanw 2019 1.3.2.2 nathanw } else if ((msglen == MSG_EXT_WDTR_LEN) && (msgcode == MSG_EXT_WDTR)) { 2020 1.3.2.2 nathanw 2021 1.3.2.2 nathanw flags = sc->sc_actscb->tcs->flags; 2022 1.3.2.2 nathanw 2023 1.3.2.2 nathanw if ((flags & FLAG_NO_WIDE) != 0) 2024 1.3.2.6 nathanw /* Offer 8bit xfers only */ 2025 1.3.2.6 nathanw sc->sc_msg[2] = MSG_EXT_WDTR_BUS_8_BIT; 2026 1.3.2.2 nathanw 2027 1.3.2.6 nathanw else if (sc->sc_msg[2] > MSG_EXT_WDTR_BUS_32_BIT) 2028 1.3.2.6 nathanw /* BAD MSG */ 2029 1.3.2.3 nathanw return (iha_msgout_reject(sc)); 2030 1.3.2.2 nathanw 2031 1.3.2.6 nathanw else if (sc->sc_msg[2] == MSG_EXT_WDTR_BUS_32_BIT) 2032 1.3.2.6 nathanw /* Offer 16bit instead */ 2033 1.3.2.6 nathanw sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2034 1.3.2.2 nathanw 2035 1.3.2.2 nathanw else { 2036 1.3.2.3 nathanw iha_wide_done(sc); 2037 1.3.2.2 nathanw if ((flags & FLAG_NO_NEG_SYNC) == 0) 2038 1.3.2.3 nathanw iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2039 1.3.2.3 nathanw return (iha_wait(sc, MSG_ACCEPT)); 2040 1.3.2.2 nathanw } 2041 1.3.2.2 nathanw 2042 1.3.2.3 nathanw iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2043 1.3.2.2 nathanw 2044 1.3.2.3 nathanw phase = iha_wait(sc, MSG_ACCEPT); 2045 1.3.2.2 nathanw if (phase != PHASE_MSG_OUT) 2046 1.3.2.2 nathanw return (phase); 2047 1.3.2.2 nathanw } else 2048 1.3.2.3 nathanw return (iha_msgout_reject(sc)); 2049 1.3.2.2 nathanw 2050 1.3.2.3 nathanw return (iha_msgout_extended(sc)); 2051 1.3.2.2 nathanw } 2052 1.3.2.2 nathanw 2053 1.3.2.2 nathanw /* 2054 1.3.2.3 nathanw * iha_msgin_sdtr - check SDTR msg in sc_msg. If the offer is 2055 1.3.2.2 nathanw * acceptable leave sc_msg as is and return 0. 2056 1.3.2.2 nathanw * If the negotiation must continue, modify sc_msg 2057 1.3.2.2 nathanw * as needed and return 1. Else return 0. 2058 1.3.2.2 nathanw */ 2059 1.3.2.2 nathanw static int 2060 1.3.2.3 nathanw iha_msgin_sdtr(sc) 2061 1.3.2.2 nathanw struct iha_softc *sc; 2062 1.3.2.2 nathanw { 2063 1.3.2.2 nathanw int flags; 2064 1.3.2.2 nathanw int newoffer; 2065 1.3.2.2 nathanw u_int8_t default_period; 2066 1.3.2.2 nathanw 2067 1.3.2.2 nathanw flags = sc->sc_actscb->tcs->flags; 2068 1.3.2.2 nathanw 2069 1.3.2.3 nathanw default_period = iha_rate_tbl[flags & FLAG_SCSI_RATE]; 2070 1.3.2.2 nathanw 2071 1.3.2.6 nathanw if (sc->sc_msg[3] == 0) 2072 1.3.2.6 nathanw /* target offered async only. Accept it. */ 2073 1.3.2.2 nathanw return (0); 2074 1.3.2.2 nathanw 2075 1.3.2.2 nathanw newoffer = 0; 2076 1.3.2.2 nathanw 2077 1.3.2.2 nathanw if ((flags & FLAG_NO_SYNC) != 0) { 2078 1.3.2.2 nathanw sc->sc_msg[3] = 0; 2079 1.3.2.6 nathanw newoffer = 1; 2080 1.3.2.2 nathanw } 2081 1.3.2.2 nathanw 2082 1.3.2.2 nathanw if (sc->sc_msg[3] > IHA_MAX_OFFSET) { 2083 1.3.2.2 nathanw sc->sc_msg[3] = IHA_MAX_OFFSET; 2084 1.3.2.6 nathanw newoffer = 1; 2085 1.3.2.2 nathanw } 2086 1.3.2.2 nathanw 2087 1.3.2.2 nathanw if (sc->sc_msg[2] < default_period) { 2088 1.3.2.2 nathanw sc->sc_msg[2] = default_period; 2089 1.3.2.6 nathanw newoffer = 1; 2090 1.3.2.2 nathanw } 2091 1.3.2.2 nathanw 2092 1.3.2.6 nathanw if (sc->sc_msg[2] > IHA_MAX_PERIOD) { 2093 1.3.2.6 nathanw /* Use async */ 2094 1.3.2.2 nathanw sc->sc_msg[3] = 0; 2095 1.3.2.6 nathanw newoffer = 1; 2096 1.3.2.2 nathanw } 2097 1.3.2.2 nathanw 2098 1.3.2.2 nathanw return (newoffer); 2099 1.3.2.2 nathanw } 2100 1.3.2.2 nathanw 2101 1.3.2.2 nathanw static int 2102 1.3.2.3 nathanw iha_msgout(sc, msg) 2103 1.3.2.2 nathanw struct iha_softc *sc; 2104 1.3.2.2 nathanw u_int8_t msg; 2105 1.3.2.2 nathanw { 2106 1.3.2.2 nathanw 2107 1.3.2.2 nathanw bus_space_write_1(sc->sc_iot, sc->sc_ioh, TUL_SFIFO, msg); 2108 1.3.2.2 nathanw 2109 1.3.2.3 nathanw return (iha_wait(sc, XF_FIFO_OUT)); 2110 1.3.2.2 nathanw } 2111 1.3.2.2 nathanw 2112 1.3.2.2 nathanw static void 2113 1.3.2.3 nathanw iha_msgout_abort(sc, aborttype) 2114 1.3.2.2 nathanw struct iha_softc *sc; 2115 1.3.2.2 nathanw u_int8_t aborttype; 2116 1.3.2.2 nathanw { 2117 1.3.2.2 nathanw 2118 1.3.2.3 nathanw iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2119 1.3.2.2 nathanw 2120 1.3.2.3 nathanw switch (iha_wait(sc, MSG_ACCEPT)) { 2121 1.3.2.2 nathanw case -1: 2122 1.3.2.2 nathanw break; 2123 1.3.2.2 nathanw 2124 1.3.2.2 nathanw case PHASE_MSG_OUT: 2125 1.3.2.2 nathanw sc->sc_flags |= FLAG_EXPECT_DISC; 2126 1.3.2.3 nathanw if (iha_msgout(sc, aborttype) != -1) 2127 1.3.2.3 nathanw iha_bad_seq(sc); 2128 1.3.2.2 nathanw break; 2129 1.3.2.2 nathanw 2130 1.3.2.2 nathanw default: 2131 1.3.2.3 nathanw iha_bad_seq(sc); 2132 1.3.2.2 nathanw break; 2133 1.3.2.2 nathanw } 2134 1.3.2.2 nathanw } 2135 1.3.2.2 nathanw 2136 1.3.2.2 nathanw static int 2137 1.3.2.3 nathanw iha_msgout_reject(sc) 2138 1.3.2.2 nathanw struct iha_softc *sc; 2139 1.3.2.2 nathanw { 2140 1.3.2.2 nathanw 2141 1.3.2.3 nathanw iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2142 1.3.2.2 nathanw 2143 1.3.2.3 nathanw if (iha_wait(sc, MSG_ACCEPT) == PHASE_MSG_OUT) 2144 1.3.2.3 nathanw return (iha_msgout(sc, MSG_MESSAGE_REJECT)); 2145 1.3.2.2 nathanw 2146 1.3.2.3 nathanw return (-1); 2147 1.3.2.2 nathanw } 2148 1.3.2.2 nathanw 2149 1.3.2.2 nathanw static int 2150 1.3.2.3 nathanw iha_msgout_extended(sc) 2151 1.3.2.2 nathanw struct iha_softc *sc; 2152 1.3.2.2 nathanw { 2153 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2154 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2155 1.3.2.2 nathanw int phase; 2156 1.3.2.2 nathanw 2157 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXTENDED); 2158 1.3.2.2 nathanw 2159 1.3.2.3 nathanw bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 2160 1.3.2.3 nathanw sc->sc_msg, sc->sc_msg[0] + 1); 2161 1.3.2.3 nathanw 2162 1.3.2.3 nathanw phase = iha_wait(sc, XF_FIFO_OUT); 2163 1.3.2.2 nathanw 2164 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2165 1.3.2.3 nathanw iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2166 1.3.2.2 nathanw 2167 1.3.2.2 nathanw return (phase); 2168 1.3.2.2 nathanw } 2169 1.3.2.2 nathanw 2170 1.3.2.2 nathanw static int 2171 1.3.2.3 nathanw iha_msgout_wdtr(sc) 2172 1.3.2.2 nathanw struct iha_softc *sc; 2173 1.3.2.2 nathanw { 2174 1.3.2.2 nathanw 2175 1.3.2.3 nathanw sc->sc_actscb->tcs->flags |= FLAG_WIDE_DONE; 2176 1.3.2.2 nathanw 2177 1.3.2.3 nathanw sc->sc_msg[0] = MSG_EXT_WDTR_LEN; 2178 1.3.2.3 nathanw sc->sc_msg[1] = MSG_EXT_WDTR; 2179 1.3.2.3 nathanw sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2180 1.3.2.2 nathanw 2181 1.3.2.3 nathanw return (iha_msgout_extended(sc)); 2182 1.3.2.3 nathanw } 2183 1.3.2.3 nathanw 2184 1.3.2.3 nathanw static int 2185 1.3.2.3 nathanw iha_msgout_sdtr(sc) 2186 1.3.2.3 nathanw struct iha_softc *sc; 2187 1.3.2.3 nathanw { 2188 1.3.2.6 nathanw struct tcs *tcs = sc->sc_actscb->tcs; 2189 1.3.2.2 nathanw 2190 1.3.2.6 nathanw tcs->flags |= FLAG_SYNC_DONE; 2191 1.3.2.2 nathanw 2192 1.3.2.3 nathanw sc->sc_msg[0] = MSG_EXT_SDTR_LEN; 2193 1.3.2.3 nathanw sc->sc_msg[1] = MSG_EXT_SDTR; 2194 1.3.2.6 nathanw sc->sc_msg[2] = iha_rate_tbl[tcs->flags & FLAG_SCSI_RATE]; 2195 1.3.2.3 nathanw sc->sc_msg[3] = IHA_MAX_OFFSET; /* REQ/ACK */ 2196 1.3.2.2 nathanw 2197 1.3.2.3 nathanw return (iha_msgout_extended(sc)); 2198 1.3.2.2 nathanw } 2199 1.3.2.2 nathanw 2200 1.3.2.2 nathanw static void 2201 1.3.2.3 nathanw iha_wide_done(sc) 2202 1.3.2.2 nathanw struct iha_softc *sc; 2203 1.3.2.2 nathanw { 2204 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2205 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2206 1.3.2.2 nathanw struct tcs *tcs = sc->sc_actscb->tcs; 2207 1.3.2.2 nathanw 2208 1.3.2.2 nathanw tcs->syncm = 0; 2209 1.3.2.2 nathanw tcs->period = 0; 2210 1.3.2.2 nathanw tcs->offset = 0; 2211 1.3.2.2 nathanw 2212 1.3.2.2 nathanw if (sc->sc_msg[2] != 0) 2213 1.3.2.2 nathanw tcs->syncm |= PERIOD_WIDE_SCSI; 2214 1.3.2.2 nathanw 2215 1.3.2.2 nathanw tcs->sconfig0 &= ~ALTPD; 2216 1.3.2.2 nathanw tcs->flags &= ~FLAG_SYNC_DONE; 2217 1.3.2.2 nathanw tcs->flags |= FLAG_WIDE_DONE; 2218 1.3.2.2 nathanw 2219 1.3.2.6 nathanw iha_update_xfer_mode(sc, sc->sc_actscb->target); 2220 1.3.2.6 nathanw 2221 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2222 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2223 1.3.2.2 nathanw } 2224 1.3.2.2 nathanw 2225 1.3.2.2 nathanw static void 2226 1.3.2.3 nathanw iha_sync_done(sc) 2227 1.3.2.2 nathanw struct iha_softc *sc; 2228 1.3.2.2 nathanw { 2229 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2230 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2231 1.3.2.2 nathanw struct tcs *tcs = sc->sc_actscb->tcs; 2232 1.3.2.2 nathanw int i; 2233 1.3.2.2 nathanw 2234 1.3.2.6 nathanw tcs->period = sc->sc_msg[2]; 2235 1.3.2.6 nathanw tcs->offset = sc->sc_msg[3]; 2236 1.3.2.6 nathanw if (tcs->offset != 0) { 2237 1.3.2.6 nathanw tcs->syncm |= tcs->offset; 2238 1.3.2.6 nathanw 2239 1.3.2.6 nathanw /* pick the highest possible rate */ 2240 1.3.2.6 nathanw for (i = 0; i < sizeof(iha_rate_tbl); i++) 2241 1.3.2.6 nathanw if (iha_rate_tbl[i] >= tcs->period) 2242 1.3.2.6 nathanw break; 2243 1.3.2.2 nathanw 2244 1.3.2.6 nathanw tcs->syncm |= (i << 4); 2245 1.3.2.6 nathanw tcs->sconfig0 |= ALTPD; 2246 1.3.2.6 nathanw } 2247 1.3.2.2 nathanw 2248 1.3.2.6 nathanw tcs->flags |= FLAG_SYNC_DONE; 2249 1.3.2.2 nathanw 2250 1.3.2.6 nathanw iha_update_xfer_mode(sc, sc->sc_actscb->target); 2251 1.3.2.6 nathanw 2252 1.3.2.6 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2253 1.3.2.6 nathanw bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2254 1.3.2.2 nathanw } 2255 1.3.2.2 nathanw 2256 1.3.2.2 nathanw void 2257 1.3.2.3 nathanw iha_reset_chip(sc) 2258 1.3.2.2 nathanw struct iha_softc *sc; 2259 1.3.2.2 nathanw { 2260 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2261 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2262 1.3.2.2 nathanw 2263 1.3.2.2 nathanw /* reset tulip chip */ 2264 1.3.2.2 nathanw 2265 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSCSI); 2266 1.3.2.2 nathanw 2267 1.3.2.2 nathanw do { 2268 1.3.2.2 nathanw sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 2269 1.3.2.2 nathanw } while ((sc->sc_sistat & SRSTD) == 0); 2270 1.3.2.2 nathanw 2271 1.3.2.3 nathanw iha_set_ssig(sc, 0, 0); 2272 1.3.2.2 nathanw 2273 1.3.2.2 nathanw bus_space_read_1(iot, ioh, TUL_SISTAT); /* Clear any active interrupt*/ 2274 1.3.2.2 nathanw } 2275 1.3.2.2 nathanw 2276 1.3.2.2 nathanw static void 2277 1.3.2.3 nathanw iha_select(sc, scb, select_type) 2278 1.3.2.2 nathanw struct iha_softc *sc; 2279 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 2280 1.3.2.2 nathanw u_int8_t select_type; 2281 1.3.2.2 nathanw { 2282 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2283 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2284 1.3.2.2 nathanw 2285 1.3.2.2 nathanw switch (select_type) { 2286 1.3.2.2 nathanw case SEL_ATN: 2287 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 2288 1.3.2.2 nathanw bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 2289 1.3.2.2 nathanw scb->cmd, scb->cmdlen); 2290 1.3.2.2 nathanw 2291 1.3.2.2 nathanw scb->nextstat = 2; 2292 1.3.2.2 nathanw break; 2293 1.3.2.2 nathanw 2294 1.3.2.2 nathanw case SELATNSTOP: 2295 1.3.2.2 nathanw scb->nextstat = 1; 2296 1.3.2.2 nathanw break; 2297 1.3.2.2 nathanw 2298 1.3.2.2 nathanw case SEL_ATN3: 2299 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 2300 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagmsg); 2301 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagid); 2302 1.3.2.2 nathanw 2303 1.3.2.2 nathanw bus_space_write_multi_1(iot, ioh, TUL_SFIFO, scb->cmd, 2304 1.3.2.2 nathanw scb->cmdlen); 2305 1.3.2.2 nathanw 2306 1.3.2.2 nathanw scb->nextstat = 2; 2307 1.3.2.2 nathanw break; 2308 1.3.2.2 nathanw 2309 1.3.2.2 nathanw default: 2310 1.3.2.3 nathanw printf("[debug] iha_select() - unknown select type = 0x%02x\n", 2311 1.3.2.2 nathanw select_type); 2312 1.3.2.2 nathanw return; 2313 1.3.2.2 nathanw } 2314 1.3.2.2 nathanw 2315 1.3.2.3 nathanw iha_del_pend_scb(sc, scb); 2316 1.3.2.2 nathanw scb->status = STATUS_SELECT; 2317 1.3.2.2 nathanw 2318 1.3.2.2 nathanw sc->sc_actscb = scb; 2319 1.3.2.2 nathanw 2320 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCMD, select_type); 2321 1.3.2.2 nathanw } 2322 1.3.2.2 nathanw 2323 1.3.2.2 nathanw /* 2324 1.3.2.3 nathanw * iha_wait - wait for an interrupt to service or a SCSI bus phase change 2325 1.3.2.2 nathanw * after writing the supplied command to the tulip chip. If 2326 1.3.2.2 nathanw * the command is NO_OP, skip the command writing. 2327 1.3.2.2 nathanw */ 2328 1.3.2.2 nathanw static int 2329 1.3.2.3 nathanw iha_wait(sc, cmd) 2330 1.3.2.2 nathanw struct iha_softc *sc; 2331 1.3.2.2 nathanw u_int8_t cmd; 2332 1.3.2.2 nathanw { 2333 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2334 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2335 1.3.2.2 nathanw 2336 1.3.2.2 nathanw if (cmd != NO_OP) 2337 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCMD, cmd); 2338 1.3.2.2 nathanw 2339 1.3.2.2 nathanw /* 2340 1.3.2.2 nathanw * Have to do this here, in addition to in iha_isr, because 2341 1.3.2.2 nathanw * interrupts might be turned off when we get here. 2342 1.3.2.2 nathanw */ 2343 1.3.2.2 nathanw do { 2344 1.3.2.2 nathanw sc->sc_status0 = bus_space_read_1(iot, ioh, TUL_STAT0); 2345 1.3.2.2 nathanw } while ((sc->sc_status0 & INTPD) == 0); 2346 1.3.2.2 nathanw 2347 1.3.2.2 nathanw sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 2348 1.3.2.2 nathanw sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 2349 1.3.2.2 nathanw 2350 1.3.2.2 nathanw sc->sc_phase = sc->sc_status0 & PH_MASK; 2351 1.3.2.2 nathanw 2352 1.3.2.2 nathanw if ((sc->sc_sistat & SRSTD) != 0) { 2353 1.3.2.2 nathanw /* SCSI bus reset interrupt */ 2354 1.3.2.3 nathanw iha_reset_scsi_bus(sc); 2355 1.3.2.2 nathanw return (-1); 2356 1.3.2.2 nathanw } 2357 1.3.2.2 nathanw 2358 1.3.2.2 nathanw if ((sc->sc_sistat & RSELED) != 0) 2359 1.3.2.2 nathanw /* Reselection interrupt */ 2360 1.3.2.3 nathanw return (iha_resel(sc)); 2361 1.3.2.2 nathanw 2362 1.3.2.2 nathanw if ((sc->sc_sistat & STIMEO) != 0) { 2363 1.3.2.2 nathanw /* selected/reselected timeout interrupt */ 2364 1.3.2.3 nathanw iha_busfree(sc); 2365 1.3.2.2 nathanw return (-1); 2366 1.3.2.2 nathanw } 2367 1.3.2.2 nathanw 2368 1.3.2.2 nathanw if ((sc->sc_sistat & DISCD) != 0) { 2369 1.3.2.2 nathanw /* BUS disconnection interrupt */ 2370 1.3.2.2 nathanw if ((sc->sc_flags & FLAG_EXPECT_DONE_DISC) != 0) { 2371 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2372 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, 2373 1.3.2.2 nathanw SCONFIG0DEFAULT); 2374 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2375 1.3.2.3 nathanw iha_append_done_scb(sc, sc->sc_actscb, HOST_OK); 2376 1.3.2.2 nathanw sc->sc_flags &= ~FLAG_EXPECT_DONE_DISC; 2377 1.3.2.2 nathanw 2378 1.3.2.2 nathanw } else if ((sc->sc_flags & FLAG_EXPECT_DISC) != 0) { 2379 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2380 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCONFIG0, 2381 1.3.2.2 nathanw SCONFIG0DEFAULT); 2382 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2383 1.3.2.2 nathanw sc->sc_actscb = NULL; 2384 1.3.2.2 nathanw sc->sc_flags &= ~FLAG_EXPECT_DISC; 2385 1.3.2.2 nathanw 2386 1.3.2.2 nathanw } else 2387 1.3.2.3 nathanw iha_busfree(sc); 2388 1.3.2.2 nathanw 2389 1.3.2.2 nathanw return (-1); 2390 1.3.2.2 nathanw } 2391 1.3.2.2 nathanw 2392 1.3.2.2 nathanw return (sc->sc_phase); 2393 1.3.2.2 nathanw } 2394 1.3.2.2 nathanw 2395 1.3.2.2 nathanw /* 2396 1.3.2.3 nathanw * iha_done_scb - We have a scb which has been processed by the 2397 1.3.2.2 nathanw * adaptor, now we look to see how the operation went. 2398 1.3.2.2 nathanw */ 2399 1.3.2.2 nathanw static void 2400 1.3.2.3 nathanw iha_done_scb(sc, scb) 2401 1.3.2.2 nathanw struct iha_softc *sc; 2402 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 2403 1.3.2.2 nathanw { 2404 1.3.2.2 nathanw struct scsipi_xfer *xs = scb->xs; 2405 1.3.2.2 nathanw 2406 1.3.2.2 nathanw if (xs != NULL) { 2407 1.3.2.2 nathanw /* Cancel the timeout. */ 2408 1.3.2.2 nathanw callout_stop(&xs->xs_callout); 2409 1.3.2.2 nathanw 2410 1.3.2.6 nathanw if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 2411 1.3.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, scb->dmap, 2412 1.3.2.2 nathanw 0, scb->dmap->dm_mapsize, 2413 1.3.2.6 nathanw (scb->flags & FLAG_DATAIN) ? 2414 1.3.2.2 nathanw BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2415 1.3.2.2 nathanw bus_dmamap_unload(sc->sc_dmat, scb->dmap); 2416 1.3.2.2 nathanw } 2417 1.3.2.2 nathanw 2418 1.3.2.2 nathanw xs->status = scb->ta_stat; 2419 1.3.2.2 nathanw 2420 1.3.2.2 nathanw switch (scb->ha_stat) { 2421 1.3.2.2 nathanw case HOST_OK: 2422 1.3.2.2 nathanw switch (scb->ta_stat) { 2423 1.3.2.2 nathanw case SCSI_OK: 2424 1.3.2.2 nathanw case SCSI_CONDITION_MET: 2425 1.3.2.2 nathanw case SCSI_INTERM: 2426 1.3.2.2 nathanw case SCSI_INTERM_COND_MET: 2427 1.3.2.2 nathanw xs->resid = scb->buflen; 2428 1.3.2.2 nathanw xs->error = XS_NOERROR; 2429 1.3.2.2 nathanw if ((scb->flags & FLAG_RSENS) != 0) 2430 1.3.2.2 nathanw xs->error = XS_SENSE; 2431 1.3.2.2 nathanw break; 2432 1.3.2.2 nathanw 2433 1.3.2.2 nathanw case SCSI_RESV_CONFLICT: 2434 1.3.2.2 nathanw case SCSI_BUSY: 2435 1.3.2.2 nathanw case SCSI_QUEUE_FULL: 2436 1.3.2.2 nathanw xs->error = XS_BUSY; 2437 1.3.2.2 nathanw break; 2438 1.3.2.2 nathanw 2439 1.3.2.2 nathanw case SCSI_TERMINATED: 2440 1.3.2.2 nathanw case SCSI_ACA_ACTIVE: 2441 1.3.2.2 nathanw case SCSI_CHECK: 2442 1.3.2.2 nathanw scb->tcs->flags &= 2443 1.3.2.2 nathanw ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 2444 1.3.2.2 nathanw 2445 1.3.2.2 nathanw if ((scb->flags & FLAG_RSENS) != 0 || 2446 1.3.2.3 nathanw iha_push_sense_request(sc, scb) != 0) { 2447 1.3.2.6 nathanw scb->flags &= ~FLAG_RSENS; 2448 1.3.2.2 nathanw printf("%s: request sense failed\n", 2449 1.3.2.2 nathanw sc->sc_dev.dv_xname); 2450 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 2451 1.3.2.2 nathanw break; 2452 1.3.2.2 nathanw } 2453 1.3.2.2 nathanw 2454 1.3.2.2 nathanw xs->error = XS_SENSE; 2455 1.3.2.2 nathanw return; 2456 1.3.2.2 nathanw 2457 1.3.2.2 nathanw default: 2458 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 2459 1.3.2.2 nathanw break; 2460 1.3.2.2 nathanw } 2461 1.3.2.2 nathanw break; 2462 1.3.2.2 nathanw 2463 1.3.2.2 nathanw case HOST_SEL_TOUT: 2464 1.3.2.2 nathanw xs->error = XS_SELTIMEOUT; 2465 1.3.2.2 nathanw break; 2466 1.3.2.2 nathanw 2467 1.3.2.2 nathanw case HOST_SCSI_RST: 2468 1.3.2.2 nathanw case HOST_DEV_RST: 2469 1.3.2.2 nathanw xs->error = XS_RESET; 2470 1.3.2.2 nathanw break; 2471 1.3.2.2 nathanw 2472 1.3.2.2 nathanw case HOST_SPERR: 2473 1.3.2.2 nathanw printf("%s: SCSI Parity error detected\n", 2474 1.3.2.2 nathanw sc->sc_dev.dv_xname); 2475 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 2476 1.3.2.2 nathanw break; 2477 1.3.2.2 nathanw 2478 1.3.2.2 nathanw case HOST_TIMED_OUT: 2479 1.3.2.2 nathanw xs->error = XS_TIMEOUT; 2480 1.3.2.2 nathanw break; 2481 1.3.2.2 nathanw 2482 1.3.2.2 nathanw case HOST_DO_DU: 2483 1.3.2.2 nathanw case HOST_BAD_PHAS: 2484 1.3.2.2 nathanw default: 2485 1.3.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 2486 1.3.2.2 nathanw break; 2487 1.3.2.2 nathanw } 2488 1.3.2.2 nathanw 2489 1.3.2.2 nathanw scsipi_done(xs); 2490 1.3.2.2 nathanw } 2491 1.3.2.2 nathanw 2492 1.3.2.3 nathanw iha_append_free_scb(sc, scb); 2493 1.3.2.2 nathanw } 2494 1.3.2.2 nathanw 2495 1.3.2.2 nathanw static void 2496 1.3.2.3 nathanw iha_timeout(arg) 2497 1.3.2.2 nathanw void *arg; 2498 1.3.2.2 nathanw { 2499 1.3.2.2 nathanw struct iha_scsi_req_q *scb = (struct iha_scsi_req_q *)arg; 2500 1.3.2.2 nathanw struct scsipi_xfer *xs = scb->xs; 2501 1.3.2.2 nathanw struct scsipi_periph *periph = xs->xs_periph; 2502 1.3.2.2 nathanw struct iha_softc *sc; 2503 1.3.2.2 nathanw 2504 1.3.2.2 nathanw sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 2505 1.3.2.2 nathanw 2506 1.3.2.2 nathanw if (xs == NULL) 2507 1.3.2.3 nathanw printf("[debug] iha_timeout called with xs == NULL\n"); 2508 1.3.2.2 nathanw 2509 1.3.2.2 nathanw else { 2510 1.3.2.2 nathanw scsipi_printaddr(periph); 2511 1.3.2.2 nathanw printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 2512 1.3.2.2 nathanw 2513 1.3.2.3 nathanw iha_abort_xs(sc, xs, HOST_TIMED_OUT); 2514 1.3.2.2 nathanw } 2515 1.3.2.2 nathanw } 2516 1.3.2.2 nathanw 2517 1.3.2.2 nathanw static void 2518 1.3.2.3 nathanw iha_exec_scb(sc, scb) 2519 1.3.2.2 nathanw struct iha_softc *sc; 2520 1.3.2.2 nathanw struct iha_scsi_req_q *scb; 2521 1.3.2.2 nathanw { 2522 1.3.2.2 nathanw bus_space_tag_t iot; 2523 1.3.2.2 nathanw bus_space_handle_t ioh; 2524 1.3.2.2 nathanw bus_dmamap_t dm; 2525 1.3.2.2 nathanw struct scsipi_xfer *xs = scb->xs; 2526 1.3.2.2 nathanw int nseg, s; 2527 1.3.2.2 nathanw 2528 1.3.2.2 nathanw dm = scb->dmap; 2529 1.3.2.2 nathanw nseg = dm->dm_nsegs; 2530 1.3.2.2 nathanw 2531 1.3.2.2 nathanw if (nseg > 1) { 2532 1.3.2.2 nathanw struct iha_sg_element *sg = scb->sglist; 2533 1.3.2.2 nathanw int i; 2534 1.3.2.2 nathanw 2535 1.3.2.2 nathanw for (i = 0; i < nseg; i++) { 2536 1.3.2.2 nathanw sg[i].sg_len = htole32(dm->dm_segs[i].ds_len); 2537 1.3.2.2 nathanw sg[i].sg_addr = htole32(dm->dm_segs[i].ds_addr); 2538 1.3.2.2 nathanw } 2539 1.3.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2540 1.3.2.2 nathanw scb->sgoffset, IHA_SG_SIZE, 2541 1.3.2.2 nathanw BUS_DMASYNC_PREWRITE); 2542 1.3.2.2 nathanw 2543 1.3.2.6 nathanw scb->flags |= FLAG_SG; 2544 1.3.2.2 nathanw scb->sg_size = scb->sg_max = nseg; 2545 1.3.2.6 nathanw scb->sg_index = 0; 2546 1.3.2.2 nathanw 2547 1.3.2.2 nathanw scb->bufaddr = scb->sg_addr; 2548 1.3.2.2 nathanw } else 2549 1.3.2.2 nathanw scb->bufaddr = dm->dm_segs[0].ds_addr; 2550 1.3.2.2 nathanw 2551 1.3.2.2 nathanw if ((xs->xs_control & XS_CTL_POLL) == 0) { 2552 1.3.2.2 nathanw int timeout = xs->timeout; 2553 1.3.2.2 nathanw timeout = (timeout > 100000) ? 2554 1.3.2.2 nathanw timeout / 1000 * hz : timeout * hz / 1000; 2555 1.3.2.2 nathanw if (timeout == 0) 2556 1.3.2.2 nathanw timeout = 1; 2557 1.3.2.3 nathanw callout_reset(&xs->xs_callout, timeout, iha_timeout, scb); 2558 1.3.2.2 nathanw } 2559 1.3.2.2 nathanw 2560 1.3.2.2 nathanw s = splbio(); 2561 1.3.2.2 nathanw 2562 1.3.2.6 nathanw if (((scb->xs->xs_control & XS_RESET) != 0) || 2563 1.3.2.6 nathanw (scb->cmd[0] == REQUEST_SENSE)) 2564 1.3.2.3 nathanw iha_push_pend_scb(sc, scb); /* Insert SCB at head of Pend */ 2565 1.3.2.2 nathanw else 2566 1.3.2.3 nathanw iha_append_pend_scb(sc, scb); /* Append SCB to tail of Pend */ 2567 1.3.2.2 nathanw 2568 1.3.2.2 nathanw /* 2569 1.3.2.3 nathanw * Run through iha_main() to ensure something is active, if 2570 1.3.2.2 nathanw * only this new SCB. 2571 1.3.2.2 nathanw */ 2572 1.3.2.2 nathanw if (sc->sc_semaph != SEMAPH_IN_MAIN) { 2573 1.3.2.2 nathanw iot = sc->sc_iot; 2574 1.3.2.2 nathanw ioh = sc->sc_ioh; 2575 1.3.2.2 nathanw 2576 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 2577 1.3.2.2 nathanw sc->sc_semaph = SEMAPH_IN_MAIN;; 2578 1.3.2.2 nathanw 2579 1.3.2.2 nathanw splx(s); 2580 1.3.2.3 nathanw iha_main(sc); 2581 1.3.2.2 nathanw s = splbio(); 2582 1.3.2.2 nathanw 2583 1.3.2.2 nathanw sc->sc_semaph = ~SEMAPH_IN_MAIN;; 2584 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 2585 1.3.2.2 nathanw } 2586 1.3.2.2 nathanw 2587 1.3.2.2 nathanw splx(s); 2588 1.3.2.2 nathanw } 2589 1.3.2.2 nathanw 2590 1.3.2.2 nathanw 2591 1.3.2.2 nathanw /* 2592 1.3.2.3 nathanw * iha_set_ssig - read the current scsi signal mask, then write a new 2593 1.3.2.2 nathanw * one which turns off/on the specified signals. 2594 1.3.2.2 nathanw */ 2595 1.3.2.2 nathanw static void 2596 1.3.2.3 nathanw iha_set_ssig(sc, offsigs, onsigs) 2597 1.3.2.2 nathanw struct iha_softc *sc; 2598 1.3.2.2 nathanw u_int8_t offsigs, onsigs; 2599 1.3.2.2 nathanw { 2600 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2601 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2602 1.3.2.2 nathanw u_int8_t currsigs; 2603 1.3.2.2 nathanw 2604 1.3.2.2 nathanw currsigs = bus_space_read_1(iot, ioh, TUL_SSIGI); 2605 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_SSIGO, (currsigs & ~offsigs) | onsigs); 2606 1.3.2.2 nathanw } 2607 1.3.2.2 nathanw 2608 1.3.2.2 nathanw /* 2609 1.3.2.3 nathanw * iha_alloc_sglist - allocate and map sglist for SCB's 2610 1.3.2.2 nathanw */ 2611 1.3.2.2 nathanw static int 2612 1.3.2.3 nathanw iha_alloc_sglist(sc) 2613 1.3.2.2 nathanw struct iha_softc *sc; 2614 1.3.2.2 nathanw { 2615 1.3.2.2 nathanw bus_dma_segment_t seg; 2616 1.3.2.2 nathanw int error, rseg; 2617 1.3.2.2 nathanw 2618 1.3.2.2 nathanw /* 2619 1.3.2.2 nathanw * Allocate dma-safe memory for the SCB's sglist 2620 1.3.2.2 nathanw */ 2621 1.3.2.2 nathanw if ((error = bus_dmamem_alloc(sc->sc_dmat, 2622 1.3.2.2 nathanw IHA_SG_SIZE * IHA_MAX_SCB, 2623 1.3.2.2 nathanw PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 2624 1.3.2.2 nathanw printf(": unable to allocate sglist, error = %d\n", error); 2625 1.3.2.2 nathanw return (error); 2626 1.3.2.2 nathanw } 2627 1.3.2.2 nathanw if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 2628 1.3.2.2 nathanw IHA_SG_SIZE * IHA_MAX_SCB, (caddr_t *)&sc->sc_sglist, 2629 1.3.2.2 nathanw BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 2630 1.3.2.2 nathanw printf(": unable to map sglist, error = %d\n", error); 2631 1.3.2.2 nathanw return (error); 2632 1.3.2.2 nathanw } 2633 1.3.2.2 nathanw 2634 1.3.2.2 nathanw /* 2635 1.3.2.2 nathanw * Create and load the DMA map used for the SCBs 2636 1.3.2.2 nathanw */ 2637 1.3.2.2 nathanw if ((error = bus_dmamap_create(sc->sc_dmat, 2638 1.3.2.2 nathanw IHA_SG_SIZE * IHA_MAX_SCB, 1, IHA_SG_SIZE * IHA_MAX_SCB, 2639 1.3.2.2 nathanw 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 2640 1.3.2.2 nathanw printf(": unable to create control DMA map, error = %d\n", 2641 1.3.2.2 nathanw error); 2642 1.3.2.2 nathanw return (error); 2643 1.3.2.2 nathanw } 2644 1.3.2.2 nathanw if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 2645 1.3.2.2 nathanw sc->sc_sglist, IHA_SG_SIZE * IHA_MAX_SCB, 2646 1.3.2.2 nathanw NULL, BUS_DMA_NOWAIT)) != 0) { 2647 1.3.2.2 nathanw printf(": unable to load control DMA map, error = %d\n", error); 2648 1.3.2.2 nathanw return (error); 2649 1.3.2.2 nathanw } 2650 1.3.2.2 nathanw 2651 1.3.2.3 nathanw memset(sc->sc_sglist, 0, IHA_SG_SIZE * IHA_MAX_SCB); 2652 1.3.2.2 nathanw 2653 1.3.2.2 nathanw return (0); 2654 1.3.2.2 nathanw } 2655 1.3.2.2 nathanw 2656 1.3.2.2 nathanw /* 2657 1.3.2.3 nathanw * iha_read_eeprom - read Serial EEPROM value & set to defaults 2658 1.3.2.2 nathanw * if required. XXX - Writing does NOT work! 2659 1.3.2.2 nathanw */ 2660 1.3.2.2 nathanw void 2661 1.3.2.3 nathanw iha_read_eeprom(sc, eeprom) 2662 1.3.2.2 nathanw struct iha_softc *sc; 2663 1.3.2.2 nathanw struct iha_eeprom *eeprom; 2664 1.3.2.2 nathanw { 2665 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2666 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2667 1.3.2.2 nathanw u_int16_t *buf = (u_int16_t *)eeprom; 2668 1.3.2.2 nathanw u_int8_t gctrl; 2669 1.3.2.2 nathanw 2670 1.3.2.3 nathanw /* Enable EEProm programming */ 2671 1.3.2.2 nathanw gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) | EEPRG; 2672 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2673 1.3.2.2 nathanw 2674 1.3.2.3 nathanw /* Read EEProm */ 2675 1.3.2.3 nathanw if (iha_se2_rd_all(sc, buf) == 0) 2676 1.3.2.3 nathanw panic("%s: cannot read EEPROM\n", sc->sc_dev.dv_xname); 2677 1.3.2.2 nathanw 2678 1.3.2.3 nathanw /* Disable EEProm programming */ 2679 1.3.2.2 nathanw gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) & ~EEPRG; 2680 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2681 1.3.2.2 nathanw } 2682 1.3.2.2 nathanw 2683 1.3.2.3 nathanw #ifdef notused 2684 1.3.2.2 nathanw /* 2685 1.3.2.3 nathanw * iha_se2_update_all - Update SCSI H/A configuration parameters from 2686 1.3.2.2 nathanw * serial EEPROM Setup default pattern. Only 2687 1.3.2.2 nathanw * change those values different from the values 2688 1.3.2.3 nathanw * in iha_eeprom. 2689 1.3.2.2 nathanw */ 2690 1.3.2.2 nathanw void 2691 1.3.2.3 nathanw iha_se2_update_all(sc) 2692 1.3.2.2 nathanw struct iha_softc *sc; 2693 1.3.2.2 nathanw { 2694 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2695 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2696 1.3.2.2 nathanw u_int16_t *np; 2697 1.3.2.2 nathanw u_int32_t chksum; 2698 1.3.2.2 nathanw int i; 2699 1.3.2.2 nathanw 2700 1.3.2.2 nathanw /* Enable erase/write state of EEPROM */ 2701 1.3.2.3 nathanw iha_se2_instr(sc, ENABLE_ERASE); 2702 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2703 1.3.2.2 nathanw EEP_WAIT(); 2704 1.3.2.2 nathanw 2705 1.3.2.2 nathanw np = (u_int16_t *)&eeprom_default; 2706 1.3.2.2 nathanw 2707 1.3.2.2 nathanw for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2708 1.3.2.3 nathanw iha_se2_wr(sc, i, *np); 2709 1.3.2.2 nathanw chksum += *np++; 2710 1.3.2.2 nathanw } 2711 1.3.2.2 nathanw 2712 1.3.2.2 nathanw chksum &= 0x0000ffff; 2713 1.3.2.3 nathanw iha_se2_wr(sc, 31, chksum); 2714 1.3.2.2 nathanw 2715 1.3.2.2 nathanw /* Disable erase/write state of EEPROM */ 2716 1.3.2.3 nathanw iha_se2_instr(sc, 0); 2717 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2718 1.3.2.2 nathanw EEP_WAIT(); 2719 1.3.2.2 nathanw } 2720 1.3.2.2 nathanw 2721 1.3.2.2 nathanw /* 2722 1.3.2.3 nathanw * iha_se2_wr - write the given 16 bit value into the Serial EEPROM 2723 1.3.2.2 nathanw * at the specified offset 2724 1.3.2.2 nathanw */ 2725 1.3.2.2 nathanw void 2726 1.3.2.3 nathanw iha_se2_wr(sc, addr, writeword) 2727 1.3.2.2 nathanw struct iha_softc *sc; 2728 1.3.2.2 nathanw int addr; 2729 1.3.2.2 nathanw u_int16_t writeword; 2730 1.3.2.2 nathanw { 2731 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2732 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2733 1.3.2.2 nathanw int i, bit; 2734 1.3.2.2 nathanw 2735 1.3.2.2 nathanw /* send 'WRITE' Instruction == address | WRITE bit */ 2736 1.3.2.3 nathanw iha_se2_instr(sc, addr | WRITE); 2737 1.3.2.2 nathanw 2738 1.3.2.2 nathanw for (i = 16; i > 0; i--) { 2739 1.3.2.2 nathanw if (writeword & (1 << (i - 1))) 2740 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRDO); 2741 1.3.2.2 nathanw else 2742 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2743 1.3.2.2 nathanw EEP_WAIT(); 2744 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2745 1.3.2.2 nathanw EEP_WAIT(); 2746 1.3.2.2 nathanw } 2747 1.3.2.2 nathanw 2748 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2749 1.3.2.2 nathanw EEP_WAIT(); 2750 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2751 1.3.2.2 nathanw EEP_WAIT(); 2752 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2753 1.3.2.2 nathanw EEP_WAIT(); 2754 1.3.2.2 nathanw 2755 1.3.2.2 nathanw for (;;) { 2756 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2757 1.3.2.2 nathanw EEP_WAIT(); 2758 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2759 1.3.2.2 nathanw EEP_WAIT(); 2760 1.3.2.2 nathanw bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI; 2761 1.3.2.2 nathanw EEP_WAIT(); 2762 1.3.2.2 nathanw if (bit != 0) 2763 1.3.2.2 nathanw break; /* write complete */ 2764 1.3.2.2 nathanw } 2765 1.3.2.2 nathanw 2766 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2767 1.3.2.2 nathanw } 2768 1.3.2.3 nathanw #endif 2769 1.3.2.2 nathanw 2770 1.3.2.2 nathanw /* 2771 1.3.2.3 nathanw * iha_se2_rd - read & return the 16 bit value at the specified 2772 1.3.2.2 nathanw * offset in the Serial E2PROM 2773 1.3.2.2 nathanw * 2774 1.3.2.2 nathanw */ 2775 1.3.2.2 nathanw u_int16_t 2776 1.3.2.3 nathanw iha_se2_rd(sc, addr) 2777 1.3.2.2 nathanw struct iha_softc *sc; 2778 1.3.2.2 nathanw int addr; 2779 1.3.2.2 nathanw { 2780 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2781 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2782 1.3.2.2 nathanw int i, bit; 2783 1.3.2.2 nathanw u_int16_t readword; 2784 1.3.2.2 nathanw 2785 1.3.2.2 nathanw /* Send 'READ' instruction == address | READ bit */ 2786 1.3.2.3 nathanw iha_se2_instr(sc, addr | READ); 2787 1.3.2.2 nathanw 2788 1.3.2.2 nathanw readword = 0; 2789 1.3.2.2 nathanw for (i = 16; i > 0; i--) { 2790 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2791 1.3.2.2 nathanw EEP_WAIT(); 2792 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2793 1.3.2.2 nathanw EEP_WAIT(); 2794 1.3.2.2 nathanw /* sample data after the following edge of clock */ 2795 1.3.2.2 nathanw bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI ? 1 : 0; 2796 1.3.2.2 nathanw EEP_WAIT(); 2797 1.3.2.2 nathanw 2798 1.3.2.2 nathanw readword |= bit << (i - 1); 2799 1.3.2.2 nathanw } 2800 1.3.2.2 nathanw 2801 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2802 1.3.2.2 nathanw 2803 1.3.2.2 nathanw return (readword); 2804 1.3.2.2 nathanw } 2805 1.3.2.2 nathanw 2806 1.3.2.2 nathanw /* 2807 1.3.2.3 nathanw * iha_se2_rd_all - Read SCSI H/A config parameters from serial EEPROM 2808 1.3.2.2 nathanw */ 2809 1.3.2.2 nathanw int 2810 1.3.2.3 nathanw iha_se2_rd_all(sc, buf) 2811 1.3.2.2 nathanw struct iha_softc *sc; 2812 1.3.2.2 nathanw u_int16_t *buf; 2813 1.3.2.2 nathanw { 2814 1.3.2.2 nathanw struct iha_eeprom *eeprom = (struct iha_eeprom *)buf; 2815 1.3.2.2 nathanw u_int32_t chksum; 2816 1.3.2.2 nathanw int i; 2817 1.3.2.2 nathanw 2818 1.3.2.2 nathanw for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2819 1.3.2.3 nathanw *buf = iha_se2_rd(sc, i); 2820 1.3.2.2 nathanw chksum += *buf++; 2821 1.3.2.2 nathanw } 2822 1.3.2.3 nathanw *buf = iha_se2_rd(sc, 31); /* read checksum from EEPROM */ 2823 1.3.2.2 nathanw 2824 1.3.2.3 nathanw chksum &= 0x0000ffff; /* lower 16 bits */ 2825 1.3.2.2 nathanw 2826 1.3.2.2 nathanw return (eeprom->signature == EEP_SIGNATURE) && 2827 1.3.2.2 nathanw (eeprom->checksum == chksum); 2828 1.3.2.2 nathanw } 2829 1.3.2.2 nathanw 2830 1.3.2.2 nathanw /* 2831 1.3.2.3 nathanw * iha_se2_instr - write an octet to serial E2PROM one bit at a time 2832 1.3.2.2 nathanw */ 2833 1.3.2.2 nathanw void 2834 1.3.2.3 nathanw iha_se2_instr(sc, instr) 2835 1.3.2.2 nathanw struct iha_softc *sc; 2836 1.3.2.2 nathanw int instr; 2837 1.3.2.2 nathanw { 2838 1.3.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2839 1.3.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2840 1.3.2.2 nathanw int b, i; 2841 1.3.2.2 nathanw 2842 1.3.2.2 nathanw b = NVRCS | NVRDO; /* Write the start bit (== 1) */ 2843 1.3.2.2 nathanw 2844 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2845 1.3.2.2 nathanw EEP_WAIT(); 2846 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2847 1.3.2.2 nathanw EEP_WAIT(); 2848 1.3.2.2 nathanw 2849 1.3.2.2 nathanw for (i = 8; i > 0; i--) { 2850 1.3.2.2 nathanw if (instr & (1 << (i - 1))) 2851 1.3.2.2 nathanw b = NVRCS | NVRDO; /* Write a 1 bit */ 2852 1.3.2.2 nathanw else 2853 1.3.2.2 nathanw b = NVRCS; /* Write a 0 bit */ 2854 1.3.2.2 nathanw 2855 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2856 1.3.2.2 nathanw EEP_WAIT(); 2857 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2858 1.3.2.2 nathanw EEP_WAIT(); 2859 1.3.2.2 nathanw } 2860 1.3.2.2 nathanw 2861 1.3.2.2 nathanw bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2862 1.3.2.2 nathanw } 2863 1.3.2.2 nathanw 2864 1.3.2.2 nathanw /* 2865 1.3.2.3 nathanw * iha_reset_tcs - reset the target control structure pointed 2866 1.3.2.2 nathanw * to by tcs to default values. tcs flags 2867 1.3.2.2 nathanw * only has the negotiation done bits reset as 2868 1.3.2.2 nathanw * the other bits are fixed at initialization. 2869 1.3.2.2 nathanw */ 2870 1.3.2.2 nathanw void 2871 1.3.2.3 nathanw iha_reset_tcs(tcs, config0) 2872 1.3.2.2 nathanw struct tcs *tcs; 2873 1.3.2.2 nathanw u_int8_t config0; 2874 1.3.2.2 nathanw { 2875 1.3.2.2 nathanw 2876 1.3.2.2 nathanw tcs->flags &= ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 2877 1.3.2.2 nathanw tcs->period = 0; 2878 1.3.2.2 nathanw tcs->offset = 0; 2879 1.3.2.2 nathanw tcs->tagcnt = 0; 2880 1.3.2.2 nathanw tcs->ntagscb = NULL; 2881 1.3.2.2 nathanw tcs->syncm = 0; 2882 1.3.2.2 nathanw tcs->sconfig0 = config0; 2883 1.3.2.2 nathanw } 2884 1.3.2.6 nathanw 2885 1.3.2.6 nathanw void 2886 1.3.2.6 nathanw iha_update_xfer_mode(sc, target) 2887 1.3.2.6 nathanw struct iha_softc *sc; 2888 1.3.2.6 nathanw int target; 2889 1.3.2.6 nathanw { 2890 1.3.2.6 nathanw struct tcs *tcs = &sc->sc_tcs[target]; 2891 1.3.2.6 nathanw struct scsipi_xfer_mode xm; 2892 1.3.2.6 nathanw 2893 1.3.2.6 nathanw xm.xm_target = target; 2894 1.3.2.6 nathanw xm.xm_mode = 0; 2895 1.3.2.6 nathanw xm.xm_period = 0; 2896 1.3.2.6 nathanw xm.xm_offset = 0; 2897 1.3.2.6 nathanw 2898 1.3.2.6 nathanw if (tcs->syncm & PERIOD_WIDE_SCSI) 2899 1.3.2.6 nathanw xm.xm_mode |= PERIPH_CAP_WIDE16; 2900 1.3.2.6 nathanw 2901 1.3.2.6 nathanw if (tcs->period) { 2902 1.3.2.6 nathanw xm.xm_mode |= PERIPH_CAP_SYNC; 2903 1.3.2.6 nathanw xm.xm_period = tcs->period; 2904 1.3.2.6 nathanw xm.xm_offset = tcs->offset; 2905 1.3.2.6 nathanw } 2906 1.3.2.6 nathanw 2907 1.3.2.6 nathanw scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 2908 1.3.2.6 nathanw } 2909 1.3.2.6 nathanw 2910
Indexes created Sun Oct 26 21:10:03 GMT 2025