iha.c revision 1.10
1 /* $NetBSD: iha.c,v 1.10 2001/09/29 14:23:37 tsutsui Exp $ */ 2 /* 3 * Initio INI-9xxxU/UW SCSI Device Driver 4 * 5 * Copyright (c) 2000 Ken Westerback 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer, 13 * without modification, immediately at the beginning of the file. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 21 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 *------------------------------------------------------------------------- 30 * 31 * Ported from i91u.c, provided by Initio Corporation, which credits: 32 * 33 * Device driver for the INI-9XXXU/UW or INIC-940/950 PCI SCSI Controller. 34 * 35 * FreeBSD 36 * 37 * Written for 386bsd and FreeBSD by 38 * Winston Hung <winstonh (at) initio.com> 39 * 40 * Copyright (c) 1997-99 Initio Corp. All rights reserved. 41 * 42 *------------------------------------------------------------------------- 43 */ 44 45 /* 46 * Ported to NetBSD by Izumi Tsutsui <tsutsui (at) ceres.dti.ne.jp> from OpenBSD: 47 * $OpenBSD: iha.c,v 1.3 2001/02/20 00:47:33 krw Exp $ 48 */ 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/buf.h> 54 #include <sys/device.h> 55 #include <sys/malloc.h> 56 57 #include <uvm/uvm_extern.h> 58 59 #include <machine/bus.h> 60 #include <machine/intr.h> 61 62 #include <dev/scsipi/scsi_all.h> 63 #include <dev/scsipi/scsipi_all.h> 64 #include <dev/scsipi/scsiconf.h> 65 #include <dev/scsipi/scsi_message.h> 66 67 #include <dev/ic/ihareg.h> 68 #include <dev/ic/ihavar.h> 69 70 /* 71 * SCSI Rate Table, indexed by FLAG_SCSI_RATE field of 72 * tcs flags. 73 */ 74 static const u_int8_t iha_rate_tbl[8] = { 75 /* fast 20 */ 76 /* nanosecond divide by 4 */ 77 12, /* 50ns, 20M */ 78 18, /* 75ns, 13.3M */ 79 25, /* 100ns, 10M */ 80 31, /* 125ns, 8M */ 81 37, /* 150ns, 6.6M */ 82 43, /* 175ns, 5.7M */ 83 50, /* 200ns, 5M */ 84 62 /* 250ns, 4M */ 85 }; 86 87 #ifdef notused 88 static u_int16_t eeprom_default[EEPROM_SIZE] = { 89 /* -- Header ------------------------------------ */ 90 /* signature */ 91 EEP_SIGNATURE, 92 /* size, revision */ 93 EEP_WORD(EEPROM_SIZE * 2, 0x01), 94 /* -- Host Adapter Structure -------------------- */ 95 /* model */ 96 0x0095, 97 /* model info, number of channel */ 98 EEP_WORD(0x00, 1), 99 /* BIOS config */ 100 EEP_BIOSCFG_DEFAULT, 101 /* host adapter config */ 102 0, 103 104 /* -- eeprom_adapter[0] ------------------------------- */ 105 /* ID, adapter config 1 */ 106 EEP_WORD(7, CFG_DEFAULT), 107 /* adapter config 2, number of targets */ 108 EEP_WORD(0x00, 8), 109 /* target flags */ 110 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 111 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 112 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 113 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 114 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 115 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 116 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 117 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 118 119 /* -- eeprom_adapter[1] ------------------------------- */ 120 /* ID, adapter config 1 */ 121 EEP_WORD(7, CFG_DEFAULT), 122 /* adapter config 2, number of targets */ 123 EEP_WORD(0x00, 8), 124 /* target flags */ 125 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 126 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 127 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 128 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 129 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 130 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 131 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 132 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 133 /* reserved[5] */ 134 0, 0, 0, 0, 0, 135 /* checksum */ 136 0 137 }; 138 #endif 139 140 static u_int8_t iha_data_over_run(struct iha_scsi_req_q *); 141 142 static int iha_push_sense_request(struct iha_softc *, struct iha_scsi_req_q *); 143 static void iha_timeout(void *); 144 static int iha_alloc_sglist(struct iha_softc *); 145 146 static void iha_read_eeprom(struct iha_softc *, struct iha_eeprom *); 147 static int iha_se2_rd_all(struct iha_softc *, u_int16_t *); 148 static void iha_se2_instr(struct iha_softc *, int); 149 static u_int16_t iha_se2_rd(struct iha_softc *, int); 150 #ifdef notused 151 static void iha_se2_update_all(struct iha_softc *); 152 static void iha_se2_wr(struct iha_softc *, int, u_int16_t); 153 #endif 154 155 static void iha_reset_scsi_bus(struct iha_softc *); 156 static void iha_reset_chip(struct iha_softc *); 157 static void iha_reset_dma(struct iha_softc *); 158 159 static void iha_reset_tcs(struct tcs *, u_int8_t); 160 161 static void iha_done_scb(struct iha_softc *, struct iha_scsi_req_q *); 162 static void iha_exec_scb(struct iha_softc *, struct iha_scsi_req_q *); 163 164 static void iha_main(struct iha_softc *); 165 static void iha_scsi(struct iha_softc *); 166 167 static int iha_wait(struct iha_softc *, u_int8_t); 168 169 static __inline void iha_mark_busy_scb(struct iha_scsi_req_q *); 170 171 static void iha_append_free_scb(struct iha_softc *, struct iha_scsi_req_q *); 172 static void iha_append_done_scb(struct iha_softc *, struct iha_scsi_req_q *, 173 u_int8_t); 174 static __inline struct iha_scsi_req_q *iha_pop_done_scb(struct iha_softc *); 175 176 static __inline void iha_append_pend_scb(struct iha_softc *, 177 struct iha_scsi_req_q *); 178 static __inline void iha_push_pend_scb(struct iha_softc *, 179 struct iha_scsi_req_q *); 180 static __inline void iha_del_pend_scb(struct iha_softc *, 181 struct iha_scsi_req_q *); 182 static struct iha_scsi_req_q *iha_find_pend_scb(struct iha_softc *); 183 184 static void iha_sync_done(struct iha_softc *); 185 static void iha_wide_done(struct iha_softc *); 186 static void iha_bad_seq(struct iha_softc *); 187 188 static int iha_next_state(struct iha_softc *); 189 static int iha_state_1(struct iha_softc *); 190 static int iha_state_2(struct iha_softc *); 191 static int iha_state_3(struct iha_softc *); 192 static int iha_state_4(struct iha_softc *); 193 static int iha_state_5(struct iha_softc *); 194 static int iha_state_6(struct iha_softc *); 195 static int iha_state_8(struct iha_softc *); 196 197 static void iha_set_ssig(struct iha_softc *, u_int8_t, u_int8_t); 198 199 static int iha_xpad_in(struct iha_softc *); 200 static int iha_xpad_out(struct iha_softc *); 201 202 static int iha_xfer_data(struct iha_softc *, struct iha_scsi_req_q *, 203 int direction); 204 205 static int iha_status_msg(struct iha_softc *); 206 207 static int iha_msgin(struct iha_softc *); 208 static int iha_msgin_sdtr(struct iha_softc *); 209 static int iha_msgin_extended(struct iha_softc *); 210 static int iha_msgin_ignore_wid_resid(struct iha_softc *); 211 212 static int iha_msgout(struct iha_softc *, u_int8_t); 213 static int iha_msgout_extended(struct iha_softc *); 214 static void iha_msgout_abort(struct iha_softc *, u_int8_t); 215 static int iha_msgout_reject(struct iha_softc *); 216 static int iha_msgout_sdtr(struct iha_softc *); 217 static int iha_msgout_wdtr(struct iha_softc *); 218 219 static void iha_select(struct iha_softc *, struct iha_scsi_req_q *, u_int8_t); 220 221 static void iha_busfree(struct iha_softc *); 222 static int iha_resel(struct iha_softc *); 223 224 static void iha_abort_xs(struct iha_softc *, struct scsipi_xfer *, u_int8_t); 225 226 void iha_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 227 void *arg); 228 229 /* 230 * iha_intr - the interrupt service routine for the iha driver 231 */ 232 int 233 iha_intr(arg) 234 void *arg; 235 { 236 bus_space_tag_t iot; 237 bus_space_handle_t ioh; 238 struct iha_softc *sc; 239 int s; 240 241 sc = (struct iha_softc *)arg; 242 iot = sc->sc_iot; 243 ioh = sc->sc_ioh; 244 245 if ((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 246 return (0); 247 248 s = splbio(); /* XXX - Or are interrupts off when ISR's are called? */ 249 250 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 251 /* XXX - need these inside a splbio()/splx()? */ 252 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 253 sc->sc_semaph = SEMAPH_IN_MAIN; 254 255 iha_main(sc); 256 257 sc->sc_semaph = ~SEMAPH_IN_MAIN; 258 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 259 } 260 261 splx(s); 262 263 return (1); 264 } 265 266 void 267 iha_scsipi_request(chan, req, arg) 268 struct scsipi_channel *chan; 269 scsipi_adapter_req_t req; 270 void *arg; 271 { 272 struct scsipi_xfer *xs; 273 struct scsipi_periph *periph; 274 struct iha_scsi_req_q *scb; 275 struct iha_softc *sc; 276 int error, flags, s; 277 278 sc = (struct iha_softc *)chan->chan_adapter->adapt_dev; 279 280 switch (req) { 281 case ADAPTER_REQ_RUN_XFER: 282 xs = arg; 283 periph = xs->xs_periph; 284 flags = xs->xs_control; 285 286 if (xs->cmdlen > sizeof(struct scsi_generic) || 287 periph->periph_target >= IHA_MAX_TARGETS) { 288 xs->error = XS_DRIVER_STUFFUP; 289 return; 290 } 291 292 s = splbio(); 293 scb = TAILQ_FIRST(&sc->sc_freescb); 294 if (scb != NULL) { 295 scb->status = STATUS_RENT; 296 TAILQ_REMOVE(&sc->sc_freescb, scb, chain); 297 } 298 #ifdef DIAGNOSTIC 299 else { 300 scsipi_printaddr(periph); 301 printf("unable to allocate scb\n"); 302 panic("iha_scsipi_request"); 303 } 304 #endif 305 splx(s); 306 307 scb->target = periph->periph_target; 308 scb->lun = periph->periph_lun; 309 scb->tcs = &sc->sc_tcs[scb->target]; 310 scb->flags = xs->xs_control; /* XXX */ 311 scb->scb_id = MSG_IDENTIFY(periph->periph_lun, 312 (xs->xs_control & XS_CTL_REQSENSE) == 0); 313 314 scb->xs = xs; 315 scb->timeout = xs->timeout; 316 scb->cmdlen = xs->cmdlen; 317 memcpy(&scb->cmd, xs->cmd, xs->cmdlen); 318 319 scb->buflen = xs->datalen; 320 321 if (scb->buflen > 0) { 322 error = bus_dmamap_load(sc->sc_dmat, scb->dmap, 323 xs->data, scb->buflen, NULL, 324 ((xs->xs_control & XS_CTL_NOSLEEP) ? 325 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 326 BUS_DMA_STREAMING | 327 ((xs->xs_control & XS_CTL_DATA_IN) ? 328 BUS_DMA_READ : BUS_DMA_WRITE)); 329 330 if (error) { 331 printf("%s: error %d loading dma map\n", 332 sc->sc_dev.dv_xname, error); 333 iha_append_free_scb(sc, scb); 334 xs->error = XS_DRIVER_STUFFUP; 335 scsipi_done(xs); 336 return; 337 } 338 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 339 0, scb->dmap->dm_mapsize, 340 (xs->xs_control & XS_CTL_DATA_IN) ? 341 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 342 } 343 344 iha_exec_scb(sc, scb); 345 return; 346 347 case ADAPTER_REQ_GROW_RESOURCES: 348 return; /* XXX */ 349 350 case ADAPTER_REQ_SET_XFER_MODE: 351 return; /* XXX */ 352 } 353 } 354 355 void 356 iha_attach(sc) 357 struct iha_softc *sc; 358 { 359 bus_space_tag_t iot = sc->sc_iot; 360 bus_space_handle_t ioh = sc->sc_ioh; 361 struct iha_scsi_req_q *scb; 362 struct iha_eeprom eeprom; 363 struct eeprom_adapter *conf; 364 int i, error, reg; 365 366 iha_read_eeprom(sc, &eeprom); 367 368 conf = &eeprom.adapter[0]; 369 370 /* 371 * fill in the rest of the iha_softc fields 372 */ 373 sc->sc_id = CFG_ID(conf->config1); 374 sc->sc_semaph = ~SEMAPH_IN_MAIN; 375 sc->sc_status0 = 0; 376 sc->sc_actscb = NULL; 377 378 TAILQ_INIT(&sc->sc_freescb); 379 TAILQ_INIT(&sc->sc_pendscb); 380 TAILQ_INIT(&sc->sc_donescb); 381 error = iha_alloc_sglist(sc); 382 if (error != 0) { 383 printf(": cannot allocate sglist\n"); 384 return; 385 } 386 387 sc->sc_scb = malloc(sizeof(struct iha_scsi_req_q) * IHA_MAX_SCB, 388 M_DEVBUF, M_NOWAIT); 389 if (sc->sc_scb == NULL) { 390 printf(": cannot allocate SCB\n"); 391 return; 392 } 393 memset(sc->sc_scb, 0, sizeof(struct iha_scsi_req_q) * IHA_MAX_SCB); 394 395 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) { 396 scb->scb_tagid = i; 397 scb->sgoffset = IHA_SG_SIZE * i; 398 scb->sglist = sc->sc_sglist + IHA_MAX_SG_ENTRIES * i; 399 scb->sg_addr = 400 sc->sc_dmamap->dm_segs[0].ds_addr + scb->sgoffset; 401 402 error = bus_dmamap_create(sc->sc_dmat, 403 MAXPHYS, IHA_MAX_SG_ENTRIES, MAXPHYS, 0, 404 BUS_DMA_NOWAIT, &scb->dmap); 405 406 if (error != 0) { 407 printf(": couldn't create SCB DMA map, error = %d\n", 408 error); 409 return; 410 } 411 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 412 } 413 414 /* Mask all the interrupts */ 415 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 416 417 /* Stop any I/O and reset the scsi module */ 418 iha_reset_dma(sc); 419 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSMOD); 420 421 /* Program HBA's SCSI ID */ 422 bus_space_write_1(iot, ioh, TUL_SID, sc->sc_id << 4); 423 424 /* 425 * Configure the channel as requested by the NVRAM settings read 426 * by iha_read_eeprom() above. 427 */ 428 429 sc->sc_sconf1 = SCONFIG0DEFAULT; 430 if ((conf->config1 & CFG_EN_PAR) != 0) 431 sc->sc_sconf1 |= SPCHK; 432 bus_space_write_1(iot, ioh, TUL_SCONFIG0, sc->sc_sconf1); 433 434 /* set selection time out 250 ms */ 435 bus_space_write_1(iot, ioh, TUL_STIMO, STIMO_250MS); 436 437 /* Enable desired SCSI termination configuration read from eeprom */ 438 reg = 0; 439 if (conf->config1 & CFG_ACT_TERM1) 440 reg |= ENTMW; 441 if (conf->config1 & CFG_ACT_TERM2) 442 reg |= ENTM; 443 bus_space_write_1(iot, ioh, TUL_DCTRL0, reg); 444 445 reg = bus_space_read_1(iot, ioh, TUL_GCTRL1) & ~ATDEN; 446 if (conf->config1 & CFG_AUTO_TERM) 447 reg |= ATDEN; 448 bus_space_write_1(iot, ioh, TUL_GCTRL1, reg); 449 450 for (i = 0; i < IHA_MAX_TARGETS / 2; i++) { 451 sc->sc_tcs[i * 2 ].flags = EEP_LBYTE(conf->tflags[i]); 452 sc->sc_tcs[i * 2 + 1].flags = EEP_HBYTE(conf->tflags[i]); 453 iha_reset_tcs(&sc->sc_tcs[i * 2 ], sc->sc_sconf1); 454 iha_reset_tcs(&sc->sc_tcs[i * 2 + 1], sc->sc_sconf1); 455 } 456 457 iha_reset_chip(sc); 458 bus_space_write_1(iot, ioh, TUL_SIEN, ALL_INTERRUPTS); 459 460 /* 461 * fill in the adapter. 462 */ 463 sc->sc_adapter.adapt_dev = &sc->sc_dev; 464 sc->sc_adapter.adapt_nchannels = 1; 465 sc->sc_adapter.adapt_openings = IHA_MAX_SCB; 466 sc->sc_adapter.adapt_max_periph = IHA_MAX_SCB; 467 sc->sc_adapter.adapt_ioctl = NULL; 468 sc->sc_adapter.adapt_minphys = minphys; 469 sc->sc_adapter.adapt_request = iha_scsipi_request; 470 471 /* 472 * fill in the channel. 473 */ 474 sc->sc_channel.chan_adapter = &sc->sc_adapter; 475 sc->sc_channel.chan_bustype = &scsi_bustype; 476 sc->sc_channel.chan_channel = 0; 477 sc->sc_channel.chan_ntargets = CFG_TARGET(conf->config2); 478 sc->sc_channel.chan_nluns = 8; 479 sc->sc_channel.chan_id = sc->sc_id; 480 481 /* 482 * Now try to attach all the sub devices. 483 */ 484 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 485 } 486 487 /* 488 * iha_reset_dma - abort any active DMA xfer, reset tulip FIFO. 489 */ 490 static void 491 iha_reset_dma(sc) 492 struct iha_softc *sc; 493 { 494 bus_space_tag_t iot = sc->sc_iot; 495 bus_space_handle_t ioh = sc->sc_ioh; 496 497 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 498 /* if DMA xfer is pending, abort DMA xfer */ 499 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 500 /* wait Abort DMA xfer done */ 501 while ((bus_space_read_1(iot, ioh, TUL_ISTUS0) & DABT) == 0) 502 ; 503 } 504 505 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 506 } 507 508 /* 509 * iha_append_free_scb - append the supplied SCB to the tail of the 510 * sc_freescb queue after clearing and resetting 511 * everything possible. 512 */ 513 static void 514 iha_append_free_scb(sc, scb) 515 struct iha_softc *sc; 516 struct iha_scsi_req_q *scb; 517 { 518 int s; 519 520 s = splbio(); 521 522 if (scb == sc->sc_actscb) 523 sc->sc_actscb = NULL; 524 525 scb->status = STATUS_QUEUED; 526 scb->ha_stat = HOST_OK; 527 scb->ta_stat = SCSI_OK; 528 529 scb->nextstat = 0; 530 scb->sg_index = 0; 531 scb->sg_max = 0; 532 scb->flags = 0; 533 scb->target = 0; 534 scb->lun = 0; 535 scb->buflen = 0; 536 scb->sg_size = 0; 537 scb->cmdlen = 0; 538 scb->scb_id = 0; 539 scb->scb_tagmsg = 0; 540 scb->timeout = 0; 541 scb->bufaddr = 0; 542 543 scb->xs = NULL; 544 scb->tcs = NULL; 545 546 memset(scb->cmd, 0, sizeof(scb->cmd)); 547 memset(scb->sglist, 0, sizeof(scb->sglist)); 548 549 /* 550 * scb_tagid, sg_addr, sglist 551 * SCB_SensePtr are set at initialization 552 * and never change 553 */ 554 555 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 556 557 splx(s); 558 } 559 560 static __inline void 561 iha_append_pend_scb(sc, scb) 562 struct iha_softc *sc; 563 struct iha_scsi_req_q *scb; 564 { 565 /* ASSUMPTION: only called within a splbio()/splx() pair */ 566 567 if (scb == sc->sc_actscb) 568 sc->sc_actscb = NULL; 569 570 scb->status = STATUS_QUEUED; 571 572 TAILQ_INSERT_TAIL(&sc->sc_pendscb, scb, chain); 573 } 574 575 static __inline void 576 iha_push_pend_scb(sc, scb) 577 struct iha_softc *sc; 578 struct iha_scsi_req_q *scb; 579 { 580 int s; 581 582 s = splbio(); 583 584 if (scb == sc->sc_actscb) 585 sc->sc_actscb = NULL; 586 587 scb->status = STATUS_QUEUED; 588 589 TAILQ_INSERT_HEAD(&sc->sc_pendscb, scb, chain); 590 591 splx(s); 592 } 593 594 /* 595 * iha_find_pend_scb - scan the pending queue for a SCB that can be 596 * processed immediately. Return NULL if none found 597 * and a pointer to the SCB if one is found. If there 598 * is an active SCB, return NULL! 599 */ 600 static struct iha_scsi_req_q * 601 iha_find_pend_scb(sc) 602 struct iha_softc *sc; 603 { 604 struct iha_scsi_req_q *scb; 605 struct tcs *tcs; 606 int s; 607 608 s = splbio(); 609 610 if (sc->sc_actscb != NULL) 611 scb = NULL; 612 613 else 614 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) { 615 if ((scb->flags & XS_CTL_RESET) != 0) 616 /* ALWAYS willing to reset a device */ 617 break; 618 619 tcs = scb->tcs; 620 621 if ((scb->scb_tagmsg) != 0) { 622 /* 623 * A Tagged I/O. OK to start If no 624 * non-tagged I/O is active on the same 625 * target 626 */ 627 if (tcs->ntagscb == NULL) 628 break; 629 630 } else if (scb->cmd[0] == REQUEST_SENSE) { 631 /* 632 * OK to do a non-tagged request sense 633 * even if a non-tagged I/O has been 634 * started, 'cuz we don't allow any 635 * disconnect during a request sense op 636 */ 637 break; 638 639 } else if (tcs->tagcnt == 0) { 640 /* 641 * No tagged I/O active on this target, 642 * ok to start a non-tagged one if one 643 * is not already active 644 */ 645 if (tcs->ntagscb == NULL) 646 break; 647 } 648 } 649 650 splx(s); 651 652 return (scb); 653 } 654 655 /* 656 * iha_del_pend_scb - remove scb from sc_pendscb 657 */ 658 static __inline void 659 iha_del_pend_scb(sc, scb) 660 struct iha_softc *sc; 661 struct iha_scsi_req_q *scb; 662 { 663 int s; 664 665 s = splbio(); 666 667 TAILQ_REMOVE(&sc->sc_pendscb, scb, chain); 668 669 splx(s); 670 } 671 672 static __inline void 673 iha_mark_busy_scb(scb) 674 struct iha_scsi_req_q *scb; 675 { 676 int s; 677 678 s = splbio(); 679 680 scb->status = STATUS_BUSY; 681 682 if (scb->scb_tagmsg == 0) 683 scb->tcs->ntagscb = scb; 684 else 685 scb->tcs->tagcnt++; 686 687 splx(s); 688 } 689 690 static void 691 iha_append_done_scb(sc, scb, hastat) 692 struct iha_softc *sc; 693 struct iha_scsi_req_q *scb; 694 u_int8_t hastat; 695 { 696 struct tcs *tcs; 697 int s; 698 699 s = splbio(); 700 701 if (scb->xs != NULL) 702 callout_stop(&scb->xs->xs_callout); 703 704 if (scb == sc->sc_actscb) 705 sc->sc_actscb = NULL; 706 707 tcs = scb->tcs; 708 709 if (scb->scb_tagmsg != 0) { 710 if (tcs->tagcnt) 711 tcs->tagcnt--; 712 } else if (tcs->ntagscb == scb) 713 tcs->ntagscb = NULL; 714 715 scb->status = STATUS_QUEUED; 716 scb->ha_stat = hastat; 717 718 TAILQ_INSERT_TAIL(&sc->sc_donescb, scb, chain); 719 720 splx(s); 721 } 722 723 static __inline struct iha_scsi_req_q * 724 iha_pop_done_scb(sc) 725 struct iha_softc *sc; 726 { 727 struct iha_scsi_req_q *scb; 728 int s; 729 730 s = splbio(); 731 732 scb = TAILQ_FIRST(&sc->sc_donescb); 733 734 if (scb != NULL) { 735 scb->status = STATUS_RENT; 736 TAILQ_REMOVE(&sc->sc_donescb, scb, chain); 737 } 738 739 splx(s); 740 741 return (scb); 742 } 743 744 /* 745 * iha_abort_xs - find the SCB associated with the supplied xs and 746 * stop all processing on it, moving it to the done 747 * queue with the supplied host status value. 748 */ 749 static void 750 iha_abort_xs(sc, xs, hastat) 751 struct iha_softc *sc; 752 struct scsipi_xfer *xs; 753 u_int8_t hastat; 754 { 755 struct iha_scsi_req_q *scb; 756 int i, s; 757 758 s = splbio(); 759 760 /* Check the pending queue for the SCB pointing to xs */ 761 762 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) 763 if (scb->xs == xs) { 764 iha_del_pend_scb(sc, scb); 765 iha_append_done_scb(sc, scb, hastat); 766 splx(s); 767 return; 768 } 769 770 /* 771 * If that didn't work, check all BUSY/SELECTING SCB's for one 772 * pointing to xs 773 */ 774 775 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 776 switch (scb->status) { 777 case STATUS_BUSY: 778 case STATUS_SELECT: 779 if (scb->xs == xs) { 780 iha_append_done_scb(sc, scb, hastat); 781 splx(s); 782 return; 783 } 784 break; 785 default: 786 break; 787 } 788 789 splx(s); 790 } 791 792 /* 793 * iha_bad_seq - a SCSI bus phase was encountered out of the 794 * correct/expected sequence. Reset the SCSI bus. 795 */ 796 static void 797 iha_bad_seq(sc) 798 struct iha_softc *sc; 799 { 800 struct iha_scsi_req_q *scb = sc->sc_actscb; 801 802 if (scb != NULL) 803 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 804 805 iha_reset_scsi_bus(sc); 806 iha_reset_chip(sc); 807 } 808 809 /* 810 * iha_push_sense_request - obtain auto sense data by pushing the 811 * SCB needing it back onto the pending 812 * queue with a REQUEST_SENSE CDB. 813 */ 814 static int 815 iha_push_sense_request(sc, scb) 816 struct iha_softc *sc; 817 struct iha_scsi_req_q *scb; 818 { 819 struct scsipi_xfer *xs = scb->xs; 820 struct scsipi_periph *periph = xs->xs_periph; 821 struct scsipi_sense *ss = (struct scsipi_sense *)scb->cmd; 822 int lun = periph->periph_lun; 823 int err; 824 825 ss->opcode = REQUEST_SENSE; 826 ss->byte2 = lun << SCSI_CMD_LUN_SHIFT; 827 ss->unused[0] = ss->unused[1] = 0; 828 ss->length = sizeof(struct scsipi_sense_data); 829 ss->control = 0; 830 831 scb->flags &= ~(FLAG_SG | XS_CTL_DATA_OUT); 832 scb->flags |= FLAG_RSENS | XS_CTL_DATA_IN; 833 834 scb->scb_id &= ~MSG_IDENTIFY_DISCFLAG; 835 836 scb->scb_tagmsg = 0; 837 scb->ta_stat = SCSI_OK; 838 839 scb->cmdlen = sizeof(struct scsipi_sense); 840 scb->buflen = ss->length; 841 842 err = bus_dmamap_load(sc->sc_dmat, scb->dmap, 843 &xs->sense.scsi_sense, scb->buflen, NULL, 844 BUS_DMA_READ|BUS_DMA_NOWAIT); 845 if (err != 0) { 846 printf("iha_push_sense_request: cannot bus_dmamap_load()\n"); 847 xs->error = XS_DRIVER_STUFFUP; 848 return 1; 849 } 850 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 851 0, scb->buflen, BUS_DMASYNC_PREREAD); 852 853 /* XXX What about queued command? */ 854 iha_exec_scb(sc, scb); 855 856 return 0; 857 } 858 859 /* 860 * iha_main - process the active SCB, taking one off pending and making it 861 * active if necessary, and any done SCB's created as 862 * a result until there are no interrupts pending and no pending 863 * SCB's that can be started. 864 */ 865 static void 866 iha_main(sc) 867 struct iha_softc *sc; 868 { 869 bus_space_tag_t iot = sc->sc_iot; 870 bus_space_handle_t ioh =sc->sc_ioh; 871 struct iha_scsi_req_q *scb; 872 873 for (;;) { 874 iha_scsi(sc); 875 876 while ((scb = iha_pop_done_scb(sc)) != NULL) 877 iha_done_scb(sc, scb); 878 879 /* 880 * If there are no interrupts pending, or we can't start 881 * a pending sc, break out of the for(;;). Otherwise 882 * continue the good work with another call to 883 * iha_scsi(). 884 */ 885 if (((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 886 && (iha_find_pend_scb(sc) == NULL)) 887 break; 888 } 889 } 890 891 /* 892 * iha_scsi - service any outstanding interrupts. If there are none, try to 893 * start another SCB currently in the pending queue. 894 */ 895 static void 896 iha_scsi(sc) 897 struct iha_softc *sc; 898 { 899 bus_space_tag_t iot = sc->sc_iot; 900 bus_space_handle_t ioh = sc->sc_ioh; 901 struct iha_scsi_req_q *scb; 902 struct tcs *tcs; 903 u_int8_t stat; 904 905 /* service pending interrupts asap */ 906 907 stat = bus_space_read_1(iot, ioh, TUL_STAT0); 908 if ((stat & INTPD) != 0) { 909 sc->sc_status0 = stat; 910 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 911 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 912 913 sc->sc_phase = sc->sc_status0 & PH_MASK; 914 915 if ((sc->sc_sistat & SRSTD) != 0) { 916 iha_reset_scsi_bus(sc); 917 return; 918 } 919 920 if ((sc->sc_sistat & RSELED) != 0) { 921 iha_resel(sc); 922 return; 923 } 924 925 if ((sc->sc_sistat & (STIMEO | DISCD)) != 0) { 926 iha_busfree(sc); 927 return; 928 } 929 930 if ((sc->sc_sistat & (SCMDN | SBSRV)) != 0) { 931 iha_next_state(sc); 932 return; 933 } 934 935 if ((sc->sc_sistat & SELED) != 0) 936 iha_set_ssig(sc, 0, 0); 937 } 938 939 /* 940 * There were no interrupts pending which required action elsewhere, so 941 * see if it is possible to start the selection phase on a pending SCB 942 */ 943 if ((scb = iha_find_pend_scb(sc)) == NULL) 944 return; 945 946 tcs = scb->tcs; 947 948 /* program HBA's SCSI ID & target SCSI ID */ 949 bus_space_write_1(iot, ioh, TUL_SID, (sc->sc_id << 4) | scb->target); 950 951 if ((scb->flags & XS_CTL_RESET) == 0) { 952 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 953 954 if ((tcs->flags & FLAG_NO_NEG_SYNC) == 0 || 955 (tcs->flags & FLAG_NO_NEG_WIDE) == 0) 956 iha_select(sc, scb, SELATNSTOP); 957 958 else if (scb->scb_tagmsg != 0) 959 iha_select(sc, scb, SEL_ATN3); 960 961 else 962 iha_select(sc, scb, SEL_ATN); 963 964 } else { 965 iha_select(sc, scb, SELATNSTOP); 966 scb->nextstat = 8; 967 } 968 969 if ((scb->flags & XS_CTL_POLL) != 0) { 970 for (; scb->timeout > 0; scb->timeout--) { 971 if (iha_wait(sc, NO_OP) == -1) 972 break; 973 if (iha_next_state(sc) == -1) 974 break; 975 delay(1000); /* Only happens in boot, so it's ok */ 976 } 977 978 /* 979 * Since done queue processing not done until AFTER this 980 * function returns, scb is on the done queue, not 981 * the free queue at this point and still has valid data 982 * 983 * Conversely, xs->error has not been set yet 984 */ 985 if (scb->timeout == 0) 986 iha_timeout(scb); 987 } 988 } 989 990 /* 991 * iha_data_over_run - return HOST_OK for all SCSI opcodes where BufLen 992 * is an 'Allocation Length'. All other SCSI opcodes 993 * get HOST_DO_DU as they SHOULD have xferred all the 994 * data requested. 995 * 996 * The list of opcodes using 'Allocation Length' was 997 * found by scanning all the SCSI-3 T10 drafts. See 998 * www.t10.org for the curious with a .pdf reader. 999 */ 1000 static u_int8_t 1001 iha_data_over_run(scb) 1002 struct iha_scsi_req_q *scb; 1003 { 1004 switch (scb->cmd[0]) { 1005 case 0x03: /* Request Sense SPC-2 */ 1006 case 0x12: /* Inquiry SPC-2 */ 1007 case 0x1a: /* Mode Sense (6 byte version) SPC-2 */ 1008 case 0x1c: /* Receive Diagnostic Results SPC-2 */ 1009 case 0x23: /* Read Format Capacities MMC-2 */ 1010 case 0x29: /* Read Generation SBC */ 1011 case 0x34: /* Read Position SSC-2 */ 1012 case 0x37: /* Read Defect Data SBC */ 1013 case 0x3c: /* Read Buffer SPC-2 */ 1014 case 0x42: /* Read Sub Channel MMC-2 */ 1015 case 0x43: /* Read TOC/PMA/ATIP MMC */ 1016 1017 /* XXX - 2 with same opcode of 0x44? */ 1018 case 0x44: /* Read Header/Read Density Suprt MMC/SSC*/ 1019 1020 case 0x46: /* Get Configuration MMC-2 */ 1021 case 0x4a: /* Get Event/Status Notification MMC-2 */ 1022 case 0x4d: /* Log Sense SPC-2 */ 1023 case 0x51: /* Read Disc Information MMC */ 1024 case 0x52: /* Read Track Information MMC */ 1025 case 0x59: /* Read Master CUE MMC */ 1026 case 0x5a: /* Mode Sense (10 byte version) SPC-2 */ 1027 case 0x5c: /* Read Buffer Capacity MMC */ 1028 case 0x5e: /* Persistant Reserve In SPC-2 */ 1029 case 0x84: /* Receive Copy Results SPC-2 */ 1030 case 0xa0: /* Report LUNs SPC-2 */ 1031 case 0xa3: /* Various Report requests SBC-2/SCC-2*/ 1032 case 0xa4: /* Report Key MMC-2 */ 1033 case 0xad: /* Read DVD Structure MMC-2 */ 1034 case 0xb4: /* Read Element Status (Attached) SMC */ 1035 case 0xb5: /* Request Volume Element Address SMC */ 1036 case 0xb7: /* Read Defect Data (12 byte ver.) SBC */ 1037 case 0xb8: /* Read Element Status (Independ.) SMC */ 1038 case 0xba: /* Report Redundancy SCC-2 */ 1039 case 0xbd: /* Mechanism Status MMC */ 1040 case 0xbe: /* Report Basic Redundancy SCC-2 */ 1041 1042 return (HOST_OK); 1043 break; 1044 1045 default: 1046 return (HOST_DO_DU); 1047 break; 1048 } 1049 } 1050 1051 /* 1052 * iha_next_state - prcess the current SCB as requested in it's 1053 * nextstat member. 1054 */ 1055 static int 1056 iha_next_state(sc) 1057 struct iha_softc *sc; 1058 { 1059 1060 if (sc->sc_actscb == NULL) 1061 return (-1); 1062 1063 switch (sc->sc_actscb->nextstat) { 1064 case 1: 1065 if (iha_state_1(sc) == 3) 1066 goto state_3; 1067 break; 1068 1069 case 2: 1070 switch (iha_state_2(sc)) { 1071 case 3: 1072 goto state_3; 1073 case 4: 1074 goto state_4; 1075 default: 1076 break; 1077 } 1078 break; 1079 1080 case 3: 1081 state_3: 1082 if (iha_state_3(sc) == 4) 1083 goto state_4; 1084 break; 1085 1086 case 4: 1087 state_4: 1088 switch (iha_state_4(sc)) { 1089 case 0: 1090 return (0); 1091 case 6: 1092 goto state_6; 1093 default: 1094 break; 1095 } 1096 break; 1097 1098 case 5: 1099 switch (iha_state_5(sc)) { 1100 case 4: 1101 goto state_4; 1102 case 6: 1103 goto state_6; 1104 default: 1105 break; 1106 } 1107 break; 1108 1109 case 6: 1110 state_6: 1111 iha_state_6(sc); 1112 break; 1113 1114 case 8: 1115 iha_state_8(sc); 1116 break; 1117 1118 default: 1119 #ifdef IHA_DEBUG_STATE 1120 printf("[debug] -unknown state: %i-\n", 1121 sc->sc_actscb->nextstat); 1122 #endif 1123 iha_bad_seq(sc); 1124 break; 1125 } 1126 1127 return (-1); 1128 } 1129 1130 /* 1131 * iha_state_1 - selection is complete after a SELATNSTOP. If the target 1132 * has put the bus into MSG_OUT phase start wide/sync 1133 * negotiation. Otherwise clear the FIFO and go to state 3, 1134 * which will send the SCSI CDB to the target. 1135 */ 1136 static int 1137 iha_state_1(sc) 1138 struct iha_softc *sc; 1139 { 1140 bus_space_tag_t iot = sc->sc_iot; 1141 bus_space_handle_t ioh = sc->sc_ioh; 1142 struct iha_scsi_req_q *scb = sc->sc_actscb; 1143 struct tcs *tcs; 1144 int flags; 1145 1146 iha_mark_busy_scb(scb); 1147 1148 tcs = scb->tcs; 1149 1150 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 1151 1152 /* 1153 * If we are in PHASE_MSG_OUT, send 1154 * a) IDENT message (with tags if appropriate) 1155 * b) WDTR if the target is configured to negotiate wide xfers 1156 * ** OR ** 1157 * c) SDTR if the target is configured to negotiate sync xfers 1158 * but not wide ones 1159 * 1160 * If we are NOT, then the target is not asking for anything but 1161 * the data/command, so go straight to state 3. 1162 */ 1163 if (sc->sc_phase == PHASE_MSG_OUT) { 1164 bus_space_write_1(iot, ioh, TUL_SCTRL1, (ESBUSIN | EHRSL)); 1165 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1166 1167 if (scb->scb_tagmsg != 0) { 1168 bus_space_write_1(iot, ioh, TUL_SFIFO, 1169 scb->scb_tagmsg); 1170 bus_space_write_1(iot, ioh, TUL_SFIFO, 1171 scb->scb_tagid); 1172 } 1173 1174 flags = tcs->flags; 1175 if ((flags & FLAG_NO_NEG_WIDE) == 0) { 1176 if (iha_msgout_wdtr(sc) == -1) 1177 return (-1); 1178 } else if ((flags & FLAG_NO_NEG_SYNC) == 0) { 1179 if (iha_msgout_sdtr(sc) == -1) 1180 return (-1); 1181 } 1182 1183 } else { 1184 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1185 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1186 } 1187 1188 return (3); 1189 } 1190 1191 /* 1192 * iha_state_2 - selection is complete after a SEL_ATN or SEL_ATN3. If the SCSI 1193 * CDB has already been send, go to state 4 to start the data 1194 * xfer. Otherwise reset the FIFO and go to state 3, sending 1195 * the SCSI CDB. 1196 */ 1197 static int 1198 iha_state_2(sc) 1199 struct iha_softc *sc; 1200 { 1201 bus_space_tag_t iot = sc->sc_iot; 1202 bus_space_handle_t ioh = sc->sc_ioh; 1203 struct iha_scsi_req_q *scb = sc->sc_actscb; 1204 1205 iha_mark_busy_scb(scb); 1206 1207 bus_space_write_1(iot, ioh, TUL_SCONFIG0, scb->tcs->sconfig0); 1208 1209 if ((sc->sc_status1 & CPDNE) != 0) 1210 return (4); 1211 1212 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1213 1214 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1215 1216 return (3); 1217 } 1218 1219 /* 1220 * iha_state_3 - send the SCSI CDB to the target, processing any status 1221 * or other messages received until that is done or 1222 * abandoned. 1223 */ 1224 static int 1225 iha_state_3(sc) 1226 struct iha_softc *sc; 1227 { 1228 bus_space_tag_t iot = sc->sc_iot; 1229 bus_space_handle_t ioh = sc->sc_ioh; 1230 struct iha_scsi_req_q *scb = sc->sc_actscb; 1231 int flags; 1232 1233 for (;;) { 1234 switch (sc->sc_phase) { 1235 case PHASE_CMD_OUT: 1236 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1237 scb->cmd, scb->cmdlen); 1238 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1239 return (-1); 1240 else if (sc->sc_phase == PHASE_CMD_OUT) { 1241 iha_bad_seq(sc); 1242 return (-1); 1243 } else 1244 return (4); 1245 1246 case PHASE_MSG_IN: 1247 scb->nextstat = 3; 1248 if (iha_msgin(sc) == -1) 1249 return (-1); 1250 break; 1251 1252 case PHASE_STATUS_IN: 1253 if (iha_status_msg(sc) == -1) 1254 return (-1); 1255 break; 1256 1257 case PHASE_MSG_OUT: 1258 flags = scb->tcs->flags; 1259 if ((flags & FLAG_NO_NEG_SYNC) != 0) { 1260 if (iha_msgout(sc, MSG_NOOP) == -1) 1261 return (-1); 1262 } else if (iha_msgout_sdtr(sc) == -1) 1263 return (-1); 1264 break; 1265 1266 default: 1267 printf("[debug] -s3- bad phase = %d\n", sc->sc_phase); 1268 iha_bad_seq(sc); 1269 return (-1); 1270 } 1271 } 1272 } 1273 1274 /* 1275 * iha_state_4 - start a data xfer. Handle any bus state 1276 * transitions until PHASE_DATA_IN/_OUT 1277 * or the attempt is abandoned. If there is 1278 * no data to xfer, go to state 6 and finish 1279 * processing the current SCB. 1280 */ 1281 static int 1282 iha_state_4(sc) 1283 struct iha_softc *sc; 1284 { 1285 struct iha_scsi_req_q *scb = sc->sc_actscb; 1286 1287 if ((scb->flags & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) == 1288 (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) 1289 return (6); /* Both dir flags set => NO xfer was requested */ 1290 1291 for (;;) { 1292 if (scb->buflen == 0) 1293 return (6); 1294 1295 switch (sc->sc_phase) { 1296 case PHASE_STATUS_IN: 1297 if ((scb->flags & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) 1298 != 0) 1299 scb->ha_stat = iha_data_over_run(scb); 1300 if ((iha_status_msg(sc)) == -1) 1301 return (-1); 1302 break; 1303 1304 case PHASE_MSG_IN: 1305 scb->nextstat = 4; 1306 if (iha_msgin(sc) == -1) 1307 return (-1); 1308 break; 1309 1310 case PHASE_MSG_OUT: 1311 if ((sc->sc_status0 & SPERR) != 0) { 1312 scb->buflen = 0; 1313 scb->ha_stat = HOST_SPERR; 1314 if (iha_msgout(sc, MSG_INITIATOR_DET_ERR) == -1) 1315 return (-1); 1316 else 1317 return (6); 1318 } else { 1319 if (iha_msgout(sc, MSG_NOOP) == -1) 1320 return (-1); 1321 } 1322 break; 1323 1324 case PHASE_DATA_IN: 1325 return (iha_xfer_data(sc, scb, XS_CTL_DATA_IN)); 1326 1327 case PHASE_DATA_OUT: 1328 return (iha_xfer_data(sc, scb, XS_CTL_DATA_OUT)); 1329 1330 default: 1331 iha_bad_seq(sc); 1332 return (-1); 1333 } 1334 } 1335 } 1336 1337 /* 1338 * iha_state_5 - handle the partial or final completion of the current 1339 * data xfer. If DMA is still active stop it. If there is 1340 * more data to xfer, go to state 4 and start the xfer. 1341 * If not go to state 6 and finish the SCB. 1342 */ 1343 static int 1344 iha_state_5(sc) 1345 struct iha_softc *sc; 1346 { 1347 bus_space_tag_t iot = sc->sc_iot; 1348 bus_space_handle_t ioh = sc->sc_ioh; 1349 struct iha_scsi_req_q *scb = sc->sc_actscb; 1350 struct iha_sg_element *sg; 1351 u_int32_t cnt; 1352 u_int8_t period, stat; 1353 long xcnt; /* cannot use unsigned!! see code: if (xcnt < 0) */ 1354 int i; 1355 1356 cnt = bus_space_read_4(iot, ioh, TUL_STCNT0) & TCNT; 1357 1358 /* 1359 * Stop any pending DMA activity and check for parity error. 1360 */ 1361 1362 if ((bus_space_read_1(iot, ioh, TUL_DCMD) & XDIR) != 0) { 1363 /* Input Operation */ 1364 if ((sc->sc_status0 & SPERR) != 0) 1365 scb->ha_stat = HOST_SPERR; 1366 1367 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1368 bus_space_write_1(iot, ioh, TUL_DCTRL0, 1369 bus_space_read_1(iot, ioh, TUL_DCTRL0) | SXSTP); 1370 while (bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) 1371 ; 1372 } 1373 1374 } else { 1375 /* Output Operation */ 1376 if ((sc->sc_status1 & SXCMP) == 0) { 1377 period = scb->tcs->syncm; 1378 if ((period & PERIOD_WIDE_SCSI) != 0) 1379 cnt += (bus_space_read_1(iot, ioh, 1380 TUL_SFIFOCNT) & FIFOC) * 2; 1381 else 1382 cnt += bus_space_read_1(iot, ioh, 1383 TUL_SFIFOCNT) & FIFOC; 1384 } 1385 1386 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1387 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 1388 do 1389 stat = bus_space_read_1(iot, ioh, TUL_ISTUS0); 1390 while ((stat & DABT) == 0); 1391 } 1392 1393 if ((cnt == 1) && (sc->sc_phase == PHASE_DATA_OUT)) { 1394 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1395 return (-1); 1396 cnt = 0; 1397 1398 } else if ((sc->sc_status1 & SXCMP) == 0) 1399 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1400 } 1401 1402 if (cnt == 0) { 1403 scb->buflen = 0; 1404 return (6); 1405 } 1406 1407 /* Update active data pointer and restart the I/O at the new point */ 1408 1409 xcnt = scb->buflen - cnt; /* xcnt == bytes xferred */ 1410 scb->buflen = cnt; /* cnt == bytes left */ 1411 1412 if ((scb->flags & FLAG_SG) != 0) { 1413 sg = &scb->sglist[scb->sg_index]; 1414 for (i = scb->sg_index; i < scb->sg_max; sg++, i++) { 1415 xcnt -= le32toh(sg->sg_len); 1416 if (xcnt < 0) { 1417 xcnt += le32toh(sg->sg_len); 1418 1419 sg->sg_addr = 1420 htole32(le32toh(sg->sg_addr) + xcnt); 1421 sg->sg_len = 1422 htole32(le32toh(sg->sg_len) - xcnt); 1423 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1424 scb->sgoffset, IHA_SG_SIZE, 1425 BUS_DMASYNC_PREWRITE); 1426 1427 scb->bufaddr += (i - scb->sg_index) * 1428 sizeof(struct iha_sg_element); 1429 scb->sg_size = scb->sg_max - i; 1430 scb->sg_index = i; 1431 1432 return (4); 1433 } 1434 } 1435 return (6); 1436 1437 } else 1438 scb->bufaddr += xcnt; 1439 1440 return (4); 1441 } 1442 1443 /* 1444 * iha_state_6 - finish off the active scb (may require several 1445 * iterations if PHASE_MSG_IN) and return -1 to indicate 1446 * the bus is free. 1447 */ 1448 static int 1449 iha_state_6(sc) 1450 struct iha_softc *sc; 1451 { 1452 1453 for (;;) { 1454 switch (sc->sc_phase) { 1455 case PHASE_STATUS_IN: 1456 if (iha_status_msg(sc) == -1) 1457 return (-1); 1458 break; 1459 1460 case PHASE_MSG_IN: 1461 sc->sc_actscb->nextstat = 6; 1462 if ((iha_msgin(sc)) == -1) 1463 return (-1); 1464 break; 1465 1466 case PHASE_MSG_OUT: 1467 if ((iha_msgout(sc, MSG_NOOP)) == -1) 1468 return (-1); 1469 break; 1470 1471 case PHASE_DATA_IN: 1472 if (iha_xpad_in(sc) == -1) 1473 return (-1); 1474 break; 1475 1476 case PHASE_DATA_OUT: 1477 if (iha_xpad_out(sc) == -1) 1478 return (-1); 1479 break; 1480 1481 default: 1482 iha_bad_seq(sc); 1483 return (-1); 1484 } 1485 } 1486 } 1487 1488 /* 1489 * iha_state_8 - reset the active device and all busy SCBs using it 1490 */ 1491 static int 1492 iha_state_8(sc) 1493 struct iha_softc *sc; 1494 { 1495 bus_space_tag_t iot = sc->sc_iot; 1496 bus_space_handle_t ioh = sc->sc_ioh; 1497 struct iha_scsi_req_q *scb; 1498 int i; 1499 u_int8_t tar; 1500 1501 if (sc->sc_phase == PHASE_MSG_OUT) { 1502 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_BUS_DEV_RESET); 1503 1504 scb = sc->sc_actscb; 1505 1506 /* This SCB finished correctly -- resetting the device */ 1507 iha_append_done_scb(sc, scb, HOST_OK); 1508 1509 iha_reset_tcs(scb->tcs, sc->sc_sconf1); 1510 1511 tar = scb->target; 1512 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1513 if (scb->target == tar) 1514 switch (scb->status) { 1515 case STATUS_BUSY: 1516 iha_append_done_scb(sc, 1517 scb, HOST_DEV_RST); 1518 break; 1519 1520 case STATUS_SELECT: 1521 iha_push_pend_scb(sc, scb); 1522 break; 1523 1524 default: 1525 break; 1526 } 1527 1528 sc->sc_flags |= FLAG_EXPECT_DISC; 1529 1530 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1531 return (-1); 1532 } 1533 1534 iha_bad_seq(sc); 1535 return (-1); 1536 } 1537 1538 /* 1539 * iha_xfer_data - initiate the DMA xfer of the data 1540 */ 1541 static int 1542 iha_xfer_data(sc, scb, direction) 1543 struct iha_softc *sc; 1544 struct iha_scsi_req_q *scb; 1545 int direction; 1546 { 1547 bus_space_tag_t iot = sc->sc_iot; 1548 bus_space_handle_t ioh = sc->sc_ioh; 1549 u_int32_t xferlen; 1550 u_int8_t xfertype; 1551 1552 if ((scb->flags & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) != direction) 1553 return (6); /* wrong direction, abandon I/O */ 1554 1555 bus_space_write_4(iot, ioh, TUL_STCNT0, scb->buflen); 1556 1557 if ((scb->flags & FLAG_SG) == 0) { 1558 xferlen = scb->buflen; 1559 xfertype = (direction == XS_CTL_DATA_IN) ? ST_X_IN : ST_X_OUT; 1560 1561 } else { 1562 xferlen = scb->sg_size * sizeof(struct iha_sg_element); 1563 xfertype = (direction == XS_CTL_DATA_IN) ? ST_SG_IN : ST_SG_OUT; 1564 } 1565 1566 bus_space_write_4(iot, ioh, TUL_DXC, xferlen); 1567 bus_space_write_4(iot, ioh, TUL_DXPA, scb->bufaddr); 1568 bus_space_write_1(iot, ioh, TUL_DCMD, xfertype); 1569 1570 bus_space_write_1(iot, ioh, TUL_SCMD, 1571 (direction == XS_CTL_DATA_IN) ? XF_DMA_IN : XF_DMA_OUT); 1572 1573 scb->nextstat = 5; 1574 1575 return (0); 1576 } 1577 1578 static int 1579 iha_xpad_in(sc) 1580 struct iha_softc *sc; 1581 { 1582 bus_space_tag_t iot = sc->sc_iot; 1583 bus_space_handle_t ioh = sc->sc_ioh; 1584 struct iha_scsi_req_q *scb = sc->sc_actscb; 1585 1586 if ((scb->flags & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) != 0) 1587 scb->ha_stat = HOST_DO_DU; 1588 1589 for (;;) { 1590 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 1591 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 1592 else 1593 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1594 1595 switch (iha_wait(sc, XF_FIFO_IN)) { 1596 case -1: 1597 return (-1); 1598 1599 case PHASE_DATA_IN: 1600 bus_space_read_1(iot, ioh, TUL_SFIFO); 1601 break; 1602 1603 default: 1604 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1605 return (6); 1606 } 1607 } 1608 } 1609 1610 static int 1611 iha_xpad_out(sc) 1612 struct iha_softc *sc; 1613 { 1614 bus_space_tag_t iot = sc->sc_iot; 1615 bus_space_handle_t ioh = sc->sc_ioh; 1616 struct iha_scsi_req_q *scb = sc->sc_actscb; 1617 1618 if ((scb->flags & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) != 0) 1619 scb->ha_stat = HOST_DO_DU; 1620 1621 for (;;) { 1622 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 1623 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 1624 else 1625 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1626 1627 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 1628 1629 switch (iha_wait(sc, XF_FIFO_OUT)) { 1630 case -1: 1631 return (-1); 1632 1633 case PHASE_DATA_OUT: 1634 break; 1635 1636 default: 1637 /* Disable wide CPU to allow read 16 bits */ 1638 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1639 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1640 return (6); 1641 } 1642 } 1643 } 1644 1645 static int 1646 iha_status_msg(sc) 1647 struct iha_softc *sc; 1648 { 1649 bus_space_tag_t iot = sc->sc_iot; 1650 bus_space_handle_t ioh = sc->sc_ioh; 1651 struct iha_scsi_req_q *scb; 1652 u_int8_t msg; 1653 int phase; 1654 1655 if ((phase = iha_wait(sc, CMD_COMP)) == -1) 1656 return (-1); 1657 1658 scb = sc->sc_actscb; 1659 1660 scb->ta_stat = bus_space_read_1(iot, ioh, TUL_SFIFO); 1661 1662 if (phase == PHASE_MSG_OUT) { 1663 if ((sc->sc_status0 & SPERR) == 0) 1664 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_NOOP); 1665 else 1666 bus_space_write_1(iot, ioh, TUL_SFIFO, 1667 MSG_PARITY_ERROR); 1668 1669 return (iha_wait(sc, XF_FIFO_OUT)); 1670 1671 } else if (phase == PHASE_MSG_IN) { 1672 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 1673 1674 if ((sc->sc_status0 & SPERR) != 0) 1675 switch (iha_wait(sc, MSG_ACCEPT)) { 1676 case -1: 1677 return (-1); 1678 case PHASE_MSG_OUT: 1679 bus_space_write_1(iot, ioh, TUL_SFIFO, 1680 MSG_PARITY_ERROR); 1681 return (iha_wait(sc, XF_FIFO_OUT)); 1682 default: 1683 iha_bad_seq(sc); 1684 return (-1); 1685 } 1686 1687 if (msg == MSG_CMDCOMPLETE) { 1688 if ((scb->ta_stat & 1689 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) { 1690 iha_bad_seq(sc); 1691 return (-1); 1692 } 1693 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 1694 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1695 return (iha_wait(sc, MSG_ACCEPT)); 1696 } 1697 1698 if ((msg == MSG_LINK_CMD_COMPLETE) 1699 || (msg == MSG_LINK_CMD_COMPLETEF)) { 1700 if ((scb->ta_stat & 1701 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) 1702 return (iha_wait(sc, MSG_ACCEPT)); 1703 } 1704 } 1705 1706 iha_bad_seq(sc); 1707 return (-1); 1708 } 1709 1710 /* 1711 * iha_busfree - SCSI bus free detected as a result of a TIMEOUT or 1712 * DISCONNECT interrupt. Reset the tulip FIFO and 1713 * SCONFIG0 and enable hardware reselect. Move any active 1714 * SCB to sc_donescb list. Return an appropriate host status 1715 * if an I/O was active. 1716 */ 1717 static void 1718 iha_busfree(sc) 1719 struct iha_softc *sc; 1720 { 1721 bus_space_tag_t iot = sc->sc_iot; 1722 bus_space_handle_t ioh = sc->sc_ioh; 1723 struct iha_scsi_req_q *scb; 1724 1725 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1726 bus_space_write_1(iot, ioh, TUL_SCONFIG0, SCONFIG0DEFAULT); 1727 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1728 1729 scb = sc->sc_actscb; 1730 1731 if (scb != NULL) { 1732 if (scb->status == STATUS_SELECT) 1733 /* selection timeout */ 1734 iha_append_done_scb(sc, scb, HOST_SEL_TOUT); 1735 else 1736 /* Unexpected bus free */ 1737 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 1738 } 1739 } 1740 1741 static void 1742 iha_reset_scsi_bus(sc) 1743 struct iha_softc *sc; 1744 { 1745 struct iha_scsi_req_q *scb; 1746 struct tcs *tcs; 1747 int i, s; 1748 1749 s = splbio(); 1750 1751 iha_reset_dma(sc); 1752 1753 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1754 switch (scb->status) { 1755 case STATUS_BUSY: 1756 iha_append_done_scb(sc, scb, HOST_SCSI_RST); 1757 break; 1758 1759 case STATUS_SELECT: 1760 iha_push_pend_scb(sc, scb); 1761 break; 1762 1763 default: 1764 break; 1765 } 1766 1767 for (i = 0, tcs = sc->sc_tcs; i < IHA_MAX_TARGETS; i++, tcs++) 1768 iha_reset_tcs(tcs, sc->sc_sconf1); 1769 1770 splx(s); 1771 } 1772 1773 /* 1774 * iha_resel - handle a detected SCSI bus reselection request. 1775 */ 1776 static int 1777 iha_resel(sc) 1778 struct iha_softc *sc; 1779 { 1780 bus_space_tag_t iot = sc->sc_iot; 1781 bus_space_handle_t ioh = sc->sc_ioh; 1782 struct iha_scsi_req_q *scb; 1783 struct tcs *tcs; 1784 u_int8_t tag, target, lun, msg, abortmsg; 1785 1786 if (sc->sc_actscb != NULL) { 1787 if ((sc->sc_actscb->status == STATUS_SELECT)) 1788 iha_push_pend_scb(sc, sc->sc_actscb); 1789 sc->sc_actscb = NULL; 1790 } 1791 1792 target = bus_space_read_1(iot, ioh, TUL_SBID); 1793 lun = bus_space_read_1(iot, ioh, TUL_SALVC) & MSG_IDENTIFY_LUNMASK; 1794 1795 tcs = &sc->sc_tcs[target]; 1796 1797 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 1798 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 1799 1800 abortmsg = MSG_ABORT; /* until a valid tag has been obtained */ 1801 1802 if (tcs->ntagscb != NULL) 1803 /* There is a non-tagged I/O active on the target */ 1804 scb = tcs->ntagscb; 1805 1806 else { 1807 /* 1808 * Since there is no active non-tagged operation 1809 * read the tag type, the tag itself, and find 1810 * the appropriate scb by indexing sc_scb with 1811 * the tag. 1812 */ 1813 1814 switch (iha_wait(sc, MSG_ACCEPT)) { 1815 case -1: 1816 return (-1); 1817 case PHASE_MSG_IN: 1818 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1819 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 1820 return (-1); 1821 break; 1822 default: 1823 goto abort; 1824 } 1825 1826 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag Msg */ 1827 1828 if ((msg < MSG_SIMPLE_Q_TAG) || (msg > MSG_ORDERED_Q_TAG)) 1829 goto abort; 1830 1831 switch (iha_wait(sc, MSG_ACCEPT)) { 1832 case -1: 1833 return (-1); 1834 case PHASE_MSG_IN: 1835 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1836 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 1837 return (-1); 1838 break; 1839 default: 1840 goto abort; 1841 } 1842 1843 tag = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag ID */ 1844 scb = &sc->sc_scb[tag]; 1845 1846 abortmsg = MSG_ABORT_TAG; /* Now that we have valdid tag! */ 1847 } 1848 1849 if ((scb->target != target) 1850 || (scb->lun != lun) 1851 || (scb->status != STATUS_BUSY)) { 1852 abort: 1853 iha_msgout_abort(sc, abortmsg); 1854 return (-1); 1855 } 1856 1857 sc->sc_actscb = scb; 1858 1859 if (iha_wait(sc, MSG_ACCEPT) == -1) 1860 return (-1); 1861 1862 return (iha_next_state(sc)); 1863 } 1864 1865 static int 1866 iha_msgin(sc) 1867 struct iha_softc *sc; 1868 { 1869 bus_space_tag_t iot = sc->sc_iot; 1870 bus_space_handle_t ioh = sc->sc_ioh; 1871 int flags; 1872 int phase; 1873 u_int8_t msg; 1874 1875 for (;;) { 1876 if ((bus_space_read_1(iot, ioh, TUL_SFIFOCNT) & FIFOC) > 0) 1877 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1878 1879 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1880 1881 phase = iha_wait(sc, XF_FIFO_IN); 1882 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 1883 1884 switch (msg) { 1885 case MSG_DISCONNECT: 1886 sc->sc_flags |= FLAG_EXPECT_DISC; 1887 if (iha_wait(sc, MSG_ACCEPT) != -1) 1888 iha_bad_seq(sc); 1889 phase = -1; 1890 break; 1891 case MSG_SAVEDATAPOINTER: 1892 case MSG_RESTOREPOINTERS: 1893 case MSG_NOOP: 1894 phase = iha_wait(sc, MSG_ACCEPT); 1895 break; 1896 case MSG_MESSAGE_REJECT: 1897 /* XXX - need to clear FIFO like other 'Clear ATN'?*/ 1898 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1899 flags = sc->sc_actscb->tcs->flags; 1900 if ((flags & FLAG_NO_NEG_SYNC) == 0) 1901 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 1902 phase = iha_wait(sc, MSG_ACCEPT); 1903 break; 1904 case MSG_EXTENDED: 1905 phase = iha_msgin_extended(sc); 1906 break; 1907 case MSG_IGN_WIDE_RESIDUE: 1908 phase = iha_msgin_ignore_wid_resid(sc); 1909 break; 1910 case MSG_CMDCOMPLETE: 1911 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 1912 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1913 phase = iha_wait(sc, MSG_ACCEPT); 1914 if (phase != -1) { 1915 iha_bad_seq(sc); 1916 return (-1); 1917 } 1918 break; 1919 default: 1920 printf("[debug] iha_msgin: bad msg type: %d\n", msg); 1921 phase = iha_msgout_reject(sc); 1922 break; 1923 } 1924 1925 if (phase != PHASE_MSG_IN) 1926 return (phase); 1927 } 1928 /* NOTREACHED */ 1929 } 1930 1931 static int 1932 iha_msgin_ignore_wid_resid(sc) 1933 struct iha_softc *sc; 1934 { 1935 bus_space_tag_t iot = sc->sc_iot; 1936 bus_space_handle_t ioh = sc->sc_ioh; 1937 int phase; 1938 1939 phase = iha_wait(sc, MSG_ACCEPT); 1940 1941 if (phase == PHASE_MSG_IN) { 1942 phase = iha_wait(sc, XF_FIFO_IN); 1943 1944 if (phase != -1) { 1945 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 1946 bus_space_read_1(iot, ioh, TUL_SFIFO); 1947 bus_space_read_1(iot, ioh, TUL_SFIFO); 1948 1949 phase = iha_wait(sc, MSG_ACCEPT); 1950 } 1951 } 1952 1953 return (phase); 1954 } 1955 1956 static int 1957 iha_msgin_extended(sc) 1958 struct iha_softc *sc; 1959 { 1960 bus_space_tag_t iot = sc->sc_iot; 1961 bus_space_handle_t ioh = sc->sc_ioh; 1962 int flags, i, phase, msglen, msgcode; 1963 1964 /* 1965 * XXX - can we just stop reading and reject, or do we have to 1966 * read all input, discarding the excess, and then reject 1967 */ 1968 for (i = 0; i < IHA_MAX_EXTENDED_MSG; i++) { 1969 phase = iha_wait(sc, MSG_ACCEPT); 1970 1971 if (phase != PHASE_MSG_IN) 1972 return (phase); 1973 1974 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1975 1976 if (iha_wait(sc, XF_FIFO_IN) == -1) 1977 return (-1); 1978 1979 sc->sc_msg[i] = bus_space_read_1(iot, ioh, TUL_SFIFO); 1980 1981 if (sc->sc_msg[0] == i) 1982 break; 1983 } 1984 1985 msglen = sc->sc_msg[0]; 1986 msgcode = sc->sc_msg[1]; 1987 1988 if ((msglen == MSG_EXT_SDTR_LEN) && (msgcode == MSG_EXT_SDTR)) { 1989 if (iha_msgin_sdtr(sc) == 0) { 1990 iha_sync_done(sc); 1991 return (iha_wait(sc, MSG_ACCEPT)); 1992 } 1993 1994 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 1995 1996 phase = iha_wait(sc, MSG_ACCEPT); 1997 if (phase != PHASE_MSG_OUT) 1998 return (phase); 1999 2000 /* Clear FIFO for important message - final SYNC offer */ 2001 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2002 2003 iha_sync_done(sc); /* This is our final offer */ 2004 2005 } else if ((msglen == MSG_EXT_WDTR_LEN) && (msgcode == MSG_EXT_WDTR)) { 2006 2007 flags = sc->sc_actscb->tcs->flags; 2008 2009 if ((flags & FLAG_NO_WIDE) != 0) 2010 sc->sc_msg[2] = 0; /* Offer async xfers only */ 2011 2012 else if (sc->sc_msg[2] > 2) /* BAD MSG: 2 is max value */ 2013 return (iha_msgout_reject(sc)); 2014 2015 else if (sc->sc_msg[2] == 2) /* a request for 32 bit xfers*/ 2016 sc->sc_msg[2] = 1; /* Offer 16 instead */ 2017 2018 else { 2019 iha_wide_done(sc); 2020 if ((flags & FLAG_NO_NEG_SYNC) == 0) 2021 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2022 return (iha_wait(sc, MSG_ACCEPT)); 2023 } 2024 2025 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2026 2027 phase = iha_wait(sc, MSG_ACCEPT); 2028 if (phase != PHASE_MSG_OUT) 2029 return (phase); 2030 } else 2031 return (iha_msgout_reject(sc)); 2032 2033 return (iha_msgout_extended(sc)); 2034 } 2035 2036 /* 2037 * iha_msgin_sdtr - check SDTR msg in sc_msg. If the offer is 2038 * acceptable leave sc_msg as is and return 0. 2039 * If the negotiation must continue, modify sc_msg 2040 * as needed and return 1. Else return 0. 2041 */ 2042 static int 2043 iha_msgin_sdtr(sc) 2044 struct iha_softc *sc; 2045 { 2046 int flags; 2047 int newoffer; 2048 u_int8_t default_period; 2049 2050 flags = sc->sc_actscb->tcs->flags; 2051 2052 default_period = iha_rate_tbl[flags & FLAG_SCSI_RATE]; 2053 2054 if (sc->sc_msg[3] == 0) /* target offered async only. Accept it. */ 2055 return (0); 2056 2057 newoffer = 0; 2058 2059 if ((flags & FLAG_NO_SYNC) != 0) { 2060 sc->sc_msg[3] = 0; 2061 newoffer = 1; 2062 } 2063 2064 if (sc->sc_msg[3] > IHA_MAX_OFFSET) { 2065 sc->sc_msg[3] = IHA_MAX_OFFSET; 2066 newoffer = 1; 2067 } 2068 2069 if (sc->sc_msg[2] < default_period) { 2070 sc->sc_msg[2] = default_period; 2071 newoffer = 1; 2072 } 2073 2074 if (sc->sc_msg[2] >= 59) { /* XXX magic */ 2075 sc->sc_msg[3] = 0; 2076 newoffer = 1; 2077 } 2078 2079 return (newoffer); 2080 } 2081 2082 static int 2083 iha_msgout(sc, msg) 2084 struct iha_softc *sc; 2085 u_int8_t msg; 2086 { 2087 2088 bus_space_write_1(sc->sc_iot, sc->sc_ioh, TUL_SFIFO, msg); 2089 2090 return (iha_wait(sc, XF_FIFO_OUT)); 2091 } 2092 2093 static void 2094 iha_msgout_abort(sc, aborttype) 2095 struct iha_softc *sc; 2096 u_int8_t aborttype; 2097 { 2098 2099 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2100 2101 switch (iha_wait(sc, MSG_ACCEPT)) { 2102 case -1: 2103 break; 2104 2105 case PHASE_MSG_OUT: 2106 sc->sc_flags |= FLAG_EXPECT_DISC; 2107 if (iha_msgout(sc, aborttype) != -1) 2108 iha_bad_seq(sc); 2109 break; 2110 2111 default: 2112 iha_bad_seq(sc); 2113 break; 2114 } 2115 } 2116 2117 static int 2118 iha_msgout_reject(sc) 2119 struct iha_softc *sc; 2120 { 2121 2122 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2123 2124 if (iha_wait(sc, MSG_ACCEPT) == PHASE_MSG_OUT) 2125 return (iha_msgout(sc, MSG_MESSAGE_REJECT)); 2126 2127 return (-1); 2128 } 2129 2130 static int 2131 iha_msgout_extended(sc) 2132 struct iha_softc *sc; 2133 { 2134 bus_space_tag_t iot = sc->sc_iot; 2135 bus_space_handle_t ioh = sc->sc_ioh; 2136 int phase; 2137 2138 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXTENDED); 2139 2140 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 2141 sc->sc_msg, sc->sc_msg[0] + 1); 2142 2143 phase = iha_wait(sc, XF_FIFO_OUT); 2144 2145 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2146 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2147 2148 return (phase); 2149 } 2150 2151 static int 2152 iha_msgout_wdtr(sc) 2153 struct iha_softc *sc; 2154 { 2155 2156 sc->sc_actscb->tcs->flags |= FLAG_WIDE_DONE; 2157 2158 sc->sc_msg[0] = MSG_EXT_WDTR_LEN; 2159 sc->sc_msg[1] = MSG_EXT_WDTR; 2160 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2161 2162 return (iha_msgout_extended(sc)); 2163 } 2164 2165 static int 2166 iha_msgout_sdtr(sc) 2167 struct iha_softc *sc; 2168 { 2169 int rateindex; 2170 2171 rateindex = sc->sc_actscb->tcs->flags & FLAG_SCSI_RATE; 2172 2173 sc->sc_msg[0] = MSG_EXT_SDTR_LEN; 2174 sc->sc_msg[1] = MSG_EXT_SDTR; 2175 sc->sc_msg[2] = iha_rate_tbl[rateindex]; 2176 sc->sc_msg[3] = IHA_MAX_OFFSET; /* REQ/ACK */ 2177 2178 return (iha_msgout_extended(sc)); 2179 } 2180 2181 static void 2182 iha_wide_done(sc) 2183 struct iha_softc *sc; 2184 { 2185 bus_space_tag_t iot = sc->sc_iot; 2186 bus_space_handle_t ioh = sc->sc_ioh; 2187 struct tcs *tcs = sc->sc_actscb->tcs; 2188 2189 tcs->syncm = 0; 2190 tcs->period = 0; 2191 tcs->offset = 0; 2192 2193 if (sc->sc_msg[2] != 0) 2194 tcs->syncm |= PERIOD_WIDE_SCSI; 2195 2196 tcs->sconfig0 &= ~ALTPD; 2197 tcs->flags &= ~FLAG_SYNC_DONE; 2198 tcs->flags |= FLAG_WIDE_DONE; 2199 2200 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2201 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2202 } 2203 2204 static void 2205 iha_sync_done(sc) 2206 struct iha_softc *sc; 2207 { 2208 bus_space_tag_t iot = sc->sc_iot; 2209 bus_space_handle_t ioh = sc->sc_ioh; 2210 struct tcs *tcs = sc->sc_actscb->tcs; 2211 int i; 2212 2213 if ((tcs->flags & FLAG_SYNC_DONE) == 0) { 2214 tcs->period = sc->sc_msg[2]; 2215 tcs->offset = sc->sc_msg[3]; 2216 if (tcs->offset != 0) { 2217 tcs->syncm |= tcs->offset; 2218 2219 /* pick the highest possible rate */ 2220 for (i = 0; i < 8; i++) 2221 if (iha_rate_tbl[i] >= tcs->period) 2222 break; 2223 2224 tcs->syncm |= (i << 4); 2225 tcs->sconfig0 |= ALTPD; 2226 } 2227 2228 tcs->flags |= FLAG_SYNC_DONE; 2229 2230 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2231 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2232 } 2233 } 2234 2235 void 2236 iha_reset_chip(sc) 2237 struct iha_softc *sc; 2238 { 2239 bus_space_tag_t iot = sc->sc_iot; 2240 bus_space_handle_t ioh = sc->sc_ioh; 2241 2242 /* reset tulip chip */ 2243 2244 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSCSI); 2245 2246 do { 2247 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 2248 } while ((sc->sc_sistat & SRSTD) == 0); 2249 2250 iha_set_ssig(sc, 0, 0); 2251 2252 bus_space_read_1(iot, ioh, TUL_SISTAT); /* Clear any active interrupt*/ 2253 } 2254 2255 static void 2256 iha_select(sc, scb, select_type) 2257 struct iha_softc *sc; 2258 struct iha_scsi_req_q *scb; 2259 u_int8_t select_type; 2260 { 2261 bus_space_tag_t iot = sc->sc_iot; 2262 bus_space_handle_t ioh = sc->sc_ioh; 2263 2264 switch (select_type) { 2265 case SEL_ATN: 2266 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 2267 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 2268 scb->cmd, scb->cmdlen); 2269 2270 scb->nextstat = 2; 2271 break; 2272 2273 case SELATNSTOP: 2274 scb->nextstat = 1; 2275 break; 2276 2277 case SEL_ATN3: 2278 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 2279 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagmsg); 2280 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagid); 2281 2282 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, scb->cmd, 2283 scb->cmdlen); 2284 2285 scb->nextstat = 2; 2286 break; 2287 2288 default: 2289 printf("[debug] iha_select() - unknown select type = 0x%02x\n", 2290 select_type); 2291 return; 2292 } 2293 2294 iha_del_pend_scb(sc, scb); 2295 scb->status = STATUS_SELECT; 2296 2297 sc->sc_actscb = scb; 2298 2299 bus_space_write_1(iot, ioh, TUL_SCMD, select_type); 2300 } 2301 2302 /* 2303 * iha_wait - wait for an interrupt to service or a SCSI bus phase change 2304 * after writing the supplied command to the tulip chip. If 2305 * the command is NO_OP, skip the command writing. 2306 */ 2307 static int 2308 iha_wait(sc, cmd) 2309 struct iha_softc *sc; 2310 u_int8_t cmd; 2311 { 2312 bus_space_tag_t iot = sc->sc_iot; 2313 bus_space_handle_t ioh = sc->sc_ioh; 2314 2315 if (cmd != NO_OP) 2316 bus_space_write_1(iot, ioh, TUL_SCMD, cmd); 2317 2318 /* 2319 * Have to do this here, in addition to in iha_isr, because 2320 * interrupts might be turned off when we get here. 2321 */ 2322 do { 2323 sc->sc_status0 = bus_space_read_1(iot, ioh, TUL_STAT0); 2324 } while ((sc->sc_status0 & INTPD) == 0); 2325 2326 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 2327 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 2328 2329 sc->sc_phase = sc->sc_status0 & PH_MASK; 2330 2331 if ((sc->sc_sistat & SRSTD) != 0) { 2332 /* SCSI bus reset interrupt */ 2333 iha_reset_scsi_bus(sc); 2334 return (-1); 2335 } 2336 2337 if ((sc->sc_sistat & RSELED) != 0) 2338 /* Reselection interrupt */ 2339 return (iha_resel(sc)); 2340 2341 if ((sc->sc_sistat & STIMEO) != 0) { 2342 /* selected/reselected timeout interrupt */ 2343 iha_busfree(sc); 2344 return (-1); 2345 } 2346 2347 if ((sc->sc_sistat & DISCD) != 0) { 2348 /* BUS disconnection interrupt */ 2349 if ((sc->sc_flags & FLAG_EXPECT_DONE_DISC) != 0) { 2350 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2351 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 2352 SCONFIG0DEFAULT); 2353 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2354 iha_append_done_scb(sc, sc->sc_actscb, HOST_OK); 2355 sc->sc_flags &= ~FLAG_EXPECT_DONE_DISC; 2356 2357 } else if ((sc->sc_flags & FLAG_EXPECT_DISC) != 0) { 2358 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2359 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 2360 SCONFIG0DEFAULT); 2361 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2362 sc->sc_actscb = NULL; 2363 sc->sc_flags &= ~FLAG_EXPECT_DISC; 2364 2365 } else 2366 iha_busfree(sc); 2367 2368 return (-1); 2369 } 2370 2371 return (sc->sc_phase); 2372 } 2373 2374 /* 2375 * iha_done_scb - We have a scb which has been processed by the 2376 * adaptor, now we look to see how the operation went. 2377 */ 2378 static void 2379 iha_done_scb(sc, scb) 2380 struct iha_softc *sc; 2381 struct iha_scsi_req_q *scb; 2382 { 2383 struct scsipi_xfer *xs = scb->xs; 2384 2385 if (xs != NULL) { 2386 /* Cancel the timeout. */ 2387 callout_stop(&xs->xs_callout); 2388 2389 if (xs->datalen > 0) { 2390 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 2391 0, scb->dmap->dm_mapsize, 2392 (xs->xs_control & XS_CTL_DATA_IN) ? 2393 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2394 bus_dmamap_unload(sc->sc_dmat, scb->dmap); 2395 } 2396 2397 xs->status = scb->ta_stat; 2398 2399 switch (scb->ha_stat) { 2400 case HOST_OK: 2401 switch (scb->ta_stat) { 2402 case SCSI_OK: 2403 case SCSI_CONDITION_MET: 2404 case SCSI_INTERM: 2405 case SCSI_INTERM_COND_MET: 2406 xs->resid = scb->buflen; 2407 xs->error = XS_NOERROR; 2408 if ((scb->flags & FLAG_RSENS) != 0) 2409 xs->error = XS_SENSE; 2410 break; 2411 2412 case SCSI_RESV_CONFLICT: 2413 case SCSI_BUSY: 2414 case SCSI_QUEUE_FULL: 2415 xs->error = XS_BUSY; 2416 break; 2417 2418 case SCSI_TERMINATED: 2419 case SCSI_ACA_ACTIVE: 2420 case SCSI_CHECK: 2421 scb->tcs->flags &= 2422 ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 2423 2424 if ((scb->flags & FLAG_RSENS) != 0 || 2425 iha_push_sense_request(sc, scb) != 0) { 2426 scb->flags &= FLAG_RSENS; 2427 printf("%s: request sense failed\n", 2428 sc->sc_dev.dv_xname); 2429 xs->error = XS_DRIVER_STUFFUP; 2430 break; 2431 } 2432 2433 xs->error = XS_SENSE; 2434 return; 2435 2436 default: 2437 xs->error = XS_DRIVER_STUFFUP; 2438 break; 2439 } 2440 break; 2441 2442 case HOST_SEL_TOUT: 2443 xs->error = XS_SELTIMEOUT; 2444 break; 2445 2446 case HOST_SCSI_RST: 2447 case HOST_DEV_RST: 2448 xs->error = XS_RESET; 2449 break; 2450 2451 case HOST_SPERR: 2452 printf("%s: SCSI Parity error detected\n", 2453 sc->sc_dev.dv_xname); 2454 xs->error = XS_DRIVER_STUFFUP; 2455 break; 2456 2457 case HOST_TIMED_OUT: 2458 xs->error = XS_TIMEOUT; 2459 break; 2460 2461 case HOST_DO_DU: 2462 case HOST_BAD_PHAS: 2463 default: 2464 xs->error = XS_DRIVER_STUFFUP; 2465 break; 2466 } 2467 2468 scsipi_done(xs); 2469 } 2470 2471 iha_append_free_scb(sc, scb); 2472 } 2473 2474 static void 2475 iha_timeout(arg) 2476 void *arg; 2477 { 2478 struct iha_scsi_req_q *scb = (struct iha_scsi_req_q *)arg; 2479 struct scsipi_xfer *xs = scb->xs; 2480 struct scsipi_periph *periph = xs->xs_periph; 2481 struct iha_softc *sc; 2482 2483 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 2484 2485 if (xs == NULL) 2486 printf("[debug] iha_timeout called with xs == NULL\n"); 2487 2488 else { 2489 scsipi_printaddr(periph); 2490 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 2491 2492 iha_abort_xs(sc, xs, HOST_TIMED_OUT); 2493 } 2494 } 2495 2496 static void 2497 iha_exec_scb(sc, scb) 2498 struct iha_softc *sc; 2499 struct iha_scsi_req_q *scb; 2500 { 2501 bus_space_tag_t iot; 2502 bus_space_handle_t ioh; 2503 bus_dmamap_t dm; 2504 struct scsipi_xfer *xs = scb->xs; 2505 int nseg, s; 2506 2507 dm = scb->dmap; 2508 nseg = dm->dm_nsegs; 2509 2510 if (nseg > 1) { 2511 struct iha_sg_element *sg = scb->sglist; 2512 int i; 2513 2514 for (i = 0; i < nseg; i++) { 2515 sg[i].sg_len = htole32(dm->dm_segs[i].ds_len); 2516 sg[i].sg_addr = htole32(dm->dm_segs[i].ds_addr); 2517 } 2518 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2519 scb->sgoffset, IHA_SG_SIZE, 2520 BUS_DMASYNC_PREWRITE); 2521 2522 scb->flags |= FLAG_SG; /* XXX */ 2523 scb->sg_size = scb->sg_max = nseg; 2524 2525 scb->bufaddr = scb->sg_addr; 2526 } else 2527 scb->bufaddr = dm->dm_segs[0].ds_addr; 2528 2529 if ((xs->xs_control & XS_CTL_POLL) == 0) { 2530 int timeout = xs->timeout; 2531 timeout = (timeout > 100000) ? 2532 timeout / 1000 * hz : timeout * hz / 1000; 2533 if (timeout == 0) 2534 timeout = 1; 2535 callout_reset(&xs->xs_callout, timeout, iha_timeout, scb); 2536 } 2537 2538 s = splbio(); 2539 2540 if (((scb->flags & XS_RESET) != 0) || (scb->cmd[0] == REQUEST_SENSE)) 2541 iha_push_pend_scb(sc, scb); /* Insert SCB at head of Pend */ 2542 else 2543 iha_append_pend_scb(sc, scb); /* Append SCB to tail of Pend */ 2544 2545 /* 2546 * Run through iha_main() to ensure something is active, if 2547 * only this new SCB. 2548 */ 2549 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 2550 iot = sc->sc_iot; 2551 ioh = sc->sc_ioh; 2552 2553 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 2554 sc->sc_semaph = SEMAPH_IN_MAIN;; 2555 2556 splx(s); 2557 iha_main(sc); 2558 s = splbio(); 2559 2560 sc->sc_semaph = ~SEMAPH_IN_MAIN;; 2561 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 2562 } 2563 2564 splx(s); 2565 } 2566 2567 2568 /* 2569 * iha_set_ssig - read the current scsi signal mask, then write a new 2570 * one which turns off/on the specified signals. 2571 */ 2572 static void 2573 iha_set_ssig(sc, offsigs, onsigs) 2574 struct iha_softc *sc; 2575 u_int8_t offsigs, onsigs; 2576 { 2577 bus_space_tag_t iot = sc->sc_iot; 2578 bus_space_handle_t ioh = sc->sc_ioh; 2579 u_int8_t currsigs; 2580 2581 currsigs = bus_space_read_1(iot, ioh, TUL_SSIGI); 2582 bus_space_write_1(iot, ioh, TUL_SSIGO, (currsigs & ~offsigs) | onsigs); 2583 } 2584 2585 /* 2586 * iha_alloc_sglist - allocate and map sglist for SCB's 2587 */ 2588 static int 2589 iha_alloc_sglist(sc) 2590 struct iha_softc *sc; 2591 { 2592 bus_dma_segment_t seg; 2593 int error, rseg; 2594 2595 /* 2596 * Allocate dma-safe memory for the SCB's sglist 2597 */ 2598 if ((error = bus_dmamem_alloc(sc->sc_dmat, 2599 IHA_SG_SIZE * IHA_MAX_SCB, 2600 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 2601 printf(": unable to allocate sglist, error = %d\n", error); 2602 return (error); 2603 } 2604 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 2605 IHA_SG_SIZE * IHA_MAX_SCB, (caddr_t *)&sc->sc_sglist, 2606 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 2607 printf(": unable to map sglist, error = %d\n", error); 2608 return (error); 2609 } 2610 2611 /* 2612 * Create and load the DMA map used for the SCBs 2613 */ 2614 if ((error = bus_dmamap_create(sc->sc_dmat, 2615 IHA_SG_SIZE * IHA_MAX_SCB, 1, IHA_SG_SIZE * IHA_MAX_SCB, 2616 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 2617 printf(": unable to create control DMA map, error = %d\n", 2618 error); 2619 return (error); 2620 } 2621 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 2622 sc->sc_sglist, IHA_SG_SIZE * IHA_MAX_SCB, 2623 NULL, BUS_DMA_NOWAIT)) != 0) { 2624 printf(": unable to load control DMA map, error = %d\n", error); 2625 return (error); 2626 } 2627 2628 memset(sc->sc_sglist, 0, IHA_SG_SIZE * IHA_MAX_SCB); 2629 2630 return (0); 2631 } 2632 2633 /* 2634 * iha_read_eeprom - read Serial EEPROM value & set to defaults 2635 * if required. XXX - Writing does NOT work! 2636 */ 2637 void 2638 iha_read_eeprom(sc, eeprom) 2639 struct iha_softc *sc; 2640 struct iha_eeprom *eeprom; 2641 { 2642 bus_space_tag_t iot = sc->sc_iot; 2643 bus_space_handle_t ioh = sc->sc_ioh; 2644 u_int16_t *buf = (u_int16_t *)eeprom; 2645 u_int8_t gctrl; 2646 2647 /* Enable EEProm programming */ 2648 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) | EEPRG; 2649 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2650 2651 /* Read EEProm */ 2652 if (iha_se2_rd_all(sc, buf) == 0) 2653 panic("%s: cannot read EEPROM\n", sc->sc_dev.dv_xname); 2654 2655 /* Disable EEProm programming */ 2656 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) & ~EEPRG; 2657 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2658 } 2659 2660 #ifdef notused 2661 /* 2662 * iha_se2_update_all - Update SCSI H/A configuration parameters from 2663 * serial EEPROM Setup default pattern. Only 2664 * change those values different from the values 2665 * in iha_eeprom. 2666 */ 2667 void 2668 iha_se2_update_all(sc) 2669 struct iha_softc *sc; 2670 { 2671 bus_space_tag_t iot = sc->sc_iot; 2672 bus_space_handle_t ioh = sc->sc_ioh; 2673 u_int16_t *np; 2674 u_int32_t chksum; 2675 int i; 2676 2677 /* Enable erase/write state of EEPROM */ 2678 iha_se2_instr(sc, ENABLE_ERASE); 2679 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2680 EEP_WAIT(); 2681 2682 np = (u_int16_t *)&eeprom_default; 2683 2684 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2685 iha_se2_wr(sc, i, *np); 2686 chksum += *np++; 2687 } 2688 2689 chksum &= 0x0000ffff; 2690 iha_se2_wr(sc, 31, chksum); 2691 2692 /* Disable erase/write state of EEPROM */ 2693 iha_se2_instr(sc, 0); 2694 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2695 EEP_WAIT(); 2696 } 2697 2698 /* 2699 * iha_se2_wr - write the given 16 bit value into the Serial EEPROM 2700 * at the specified offset 2701 */ 2702 void 2703 iha_se2_wr(sc, addr, writeword) 2704 struct iha_softc *sc; 2705 int addr; 2706 u_int16_t writeword; 2707 { 2708 bus_space_tag_t iot = sc->sc_iot; 2709 bus_space_handle_t ioh = sc->sc_ioh; 2710 int i, bit; 2711 2712 /* send 'WRITE' Instruction == address | WRITE bit */ 2713 iha_se2_instr(sc, addr | WRITE); 2714 2715 for (i = 16; i > 0; i--) { 2716 if (writeword & (1 << (i - 1))) 2717 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRDO); 2718 else 2719 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2720 EEP_WAIT(); 2721 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2722 EEP_WAIT(); 2723 } 2724 2725 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2726 EEP_WAIT(); 2727 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2728 EEP_WAIT(); 2729 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2730 EEP_WAIT(); 2731 2732 for (;;) { 2733 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2734 EEP_WAIT(); 2735 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2736 EEP_WAIT(); 2737 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI; 2738 EEP_WAIT(); 2739 if (bit != 0) 2740 break; /* write complete */ 2741 } 2742 2743 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2744 } 2745 #endif 2746 2747 /* 2748 * iha_se2_rd - read & return the 16 bit value at the specified 2749 * offset in the Serial E2PROM 2750 * 2751 */ 2752 u_int16_t 2753 iha_se2_rd(sc, addr) 2754 struct iha_softc *sc; 2755 int addr; 2756 { 2757 bus_space_tag_t iot = sc->sc_iot; 2758 bus_space_handle_t ioh = sc->sc_ioh; 2759 int i, bit; 2760 u_int16_t readword; 2761 2762 /* Send 'READ' instruction == address | READ bit */ 2763 iha_se2_instr(sc, addr | READ); 2764 2765 readword = 0; 2766 for (i = 16; i > 0; i--) { 2767 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2768 EEP_WAIT(); 2769 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2770 EEP_WAIT(); 2771 /* sample data after the following edge of clock */ 2772 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI ? 1 : 0; 2773 EEP_WAIT(); 2774 2775 readword |= bit << (i - 1); 2776 } 2777 2778 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2779 2780 return (readword); 2781 } 2782 2783 /* 2784 * iha_se2_rd_all - Read SCSI H/A config parameters from serial EEPROM 2785 */ 2786 int 2787 iha_se2_rd_all(sc, buf) 2788 struct iha_softc *sc; 2789 u_int16_t *buf; 2790 { 2791 struct iha_eeprom *eeprom = (struct iha_eeprom *)buf; 2792 u_int32_t chksum; 2793 int i; 2794 2795 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2796 *buf = iha_se2_rd(sc, i); 2797 chksum += *buf++; 2798 } 2799 *buf = iha_se2_rd(sc, 31); /* read checksum from EEPROM */ 2800 2801 chksum &= 0x0000ffff; /* lower 16 bits */ 2802 2803 return (eeprom->signature == EEP_SIGNATURE) && 2804 (eeprom->checksum == chksum); 2805 } 2806 2807 /* 2808 * iha_se2_instr - write an octet to serial E2PROM one bit at a time 2809 */ 2810 void 2811 iha_se2_instr(sc, instr) 2812 struct iha_softc *sc; 2813 int instr; 2814 { 2815 bus_space_tag_t iot = sc->sc_iot; 2816 bus_space_handle_t ioh = sc->sc_ioh; 2817 int b, i; 2818 2819 b = NVRCS | NVRDO; /* Write the start bit (== 1) */ 2820 2821 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2822 EEP_WAIT(); 2823 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2824 EEP_WAIT(); 2825 2826 for (i = 8; i > 0; i--) { 2827 if (instr & (1 << (i - 1))) 2828 b = NVRCS | NVRDO; /* Write a 1 bit */ 2829 else 2830 b = NVRCS; /* Write a 0 bit */ 2831 2832 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2833 EEP_WAIT(); 2834 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2835 EEP_WAIT(); 2836 } 2837 2838 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2839 } 2840 2841 /* 2842 * iha_reset_tcs - reset the target control structure pointed 2843 * to by tcs to default values. tcs flags 2844 * only has the negotiation done bits reset as 2845 * the other bits are fixed at initialization. 2846 */ 2847 void 2848 iha_reset_tcs(tcs, config0) 2849 struct tcs *tcs; 2850 u_int8_t config0; 2851 { 2852 2853 tcs->flags &= ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 2854 tcs->period = 0; 2855 tcs->offset = 0; 2856 tcs->tagcnt = 0; 2857 tcs->ntagscb = NULL; 2858 tcs->syncm = 0; 2859 tcs->sconfig0 = config0; 2860 } 2861
Indexes created Thu Sep 25 02:09:54 GMT 2025