iha.c revision 1.25
1 /* $NetBSD: iha.c,v 1.25 2004/09/25 09:46:17 tsutsui Exp $ */ 2 3 /*- 4 * Device driver for the INI-9XXXU/UW or INIC-940/950 PCI SCSI Controller. 5 * 6 * Written for 386bsd and FreeBSD by 7 * Winston Hung <winstonh (at) initio.com> 8 * 9 * Copyright (c) 1997-1999 Initio Corp. 10 * Copyright (c) 2000, 2001 Ken Westerback 11 * Copyright (c) 2001, 2002 Izumi Tsutsui 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer, 19 * without modification, immediately at the beginning of the file. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 32 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Ported to NetBSD by Izumi Tsutsui <tsutsui (at) ceres.dti.ne.jp> from OpenBSD: 38 * $OpenBSD: iha.c,v 1.3 2001/02/20 00:47:33 krw Exp $ 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: iha.c,v 1.25 2004/09/25 09:46:17 tsutsui Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/buf.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsiconf.h> 59 #include <dev/scsipi/scsi_message.h> 60 61 #include <dev/ic/ihareg.h> 62 #include <dev/ic/ihavar.h> 63 64 /* 65 * SCSI Rate Table, indexed by FLAG_SCSI_RATE field of 66 * tcs flags. 67 */ 68 static const u_int8_t iha_rate_tbl[] = { 69 /* fast 20 */ 70 /* nanosecond divide by 4 */ 71 12, /* 50ns, 20M */ 72 18, /* 75ns, 13.3M */ 73 25, /* 100ns, 10M */ 74 31, /* 125ns, 8M */ 75 37, /* 150ns, 6.6M */ 76 43, /* 175ns, 5.7M */ 77 50, /* 200ns, 5M */ 78 62 /* 250ns, 4M */ 79 }; 80 #define IHA_MAX_PERIOD 62 81 82 #ifdef notused 83 static u_int16_t eeprom_default[EEPROM_SIZE] = { 84 /* -- Header ------------------------------------ */ 85 /* signature */ 86 EEP_SIGNATURE, 87 /* size, revision */ 88 EEP_WORD(EEPROM_SIZE * 2, 0x01), 89 /* -- Host Adapter Structure -------------------- */ 90 /* model */ 91 0x0095, 92 /* model info, number of channel */ 93 EEP_WORD(0x00, 1), 94 /* BIOS config */ 95 EEP_BIOSCFG_DEFAULT, 96 /* host adapter config */ 97 0, 98 99 /* -- eeprom_adapter[0] ------------------------------- */ 100 /* ID, adapter config 1 */ 101 EEP_WORD(7, CFG_DEFAULT), 102 /* adapter config 2, number of targets */ 103 EEP_WORD(0x00, 8), 104 /* target flags */ 105 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 106 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 107 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 108 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 109 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 110 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 111 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 112 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 113 114 /* -- eeprom_adapter[1] ------------------------------- */ 115 /* ID, adapter config 1 */ 116 EEP_WORD(7, CFG_DEFAULT), 117 /* adapter config 2, number of targets */ 118 EEP_WORD(0x00, 8), 119 /* target flags */ 120 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 121 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 122 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 123 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 124 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 125 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 126 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 127 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 128 /* reserved[5] */ 129 0, 0, 0, 0, 0, 130 /* checksum */ 131 0 132 }; 133 #endif 134 135 static void iha_append_free_scb(struct iha_softc *, struct iha_scb *); 136 static void iha_append_done_scb(struct iha_softc *, struct iha_scb *, u_int8_t); 137 static __inline struct iha_scb *iha_pop_done_scb(struct iha_softc *); 138 139 static struct iha_scb *iha_find_pend_scb(struct iha_softc *); 140 static __inline void iha_append_pend_scb(struct iha_softc *, struct iha_scb *); 141 static __inline void iha_push_pend_scb(struct iha_softc *, struct iha_scb *); 142 static __inline void iha_del_pend_scb(struct iha_softc *, struct iha_scb *); 143 static __inline void iha_mark_busy_scb(struct iha_scb *); 144 145 static __inline void iha_set_ssig(struct iha_softc *, u_int8_t, u_int8_t); 146 147 static int iha_alloc_sglist(struct iha_softc *); 148 149 static void iha_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 150 void *); 151 static void iha_update_xfer_mode(struct iha_softc *, int); 152 153 static void iha_reset_scsi_bus(struct iha_softc *); 154 static void iha_reset_chip(struct iha_softc *); 155 static void iha_reset_dma(struct iha_softc *); 156 static void iha_reset_tcs(struct tcs *, u_int8_t); 157 158 static void iha_main(struct iha_softc *); 159 static void iha_scsi(struct iha_softc *); 160 static void iha_select(struct iha_softc *, struct iha_scb *, u_int8_t); 161 static int iha_wait(struct iha_softc *, u_int8_t); 162 163 static void iha_exec_scb(struct iha_softc *, struct iha_scb *); 164 static void iha_done_scb(struct iha_softc *, struct iha_scb *); 165 static int iha_push_sense_request(struct iha_softc *, struct iha_scb *); 166 167 static void iha_timeout(void *); 168 static void iha_abort_xs(struct iha_softc *, struct scsipi_xfer *, u_int8_t); 169 static u_int8_t iha_data_over_run(struct iha_scb *); 170 171 static int iha_next_state(struct iha_softc *); 172 static int iha_state_1(struct iha_softc *); 173 static int iha_state_2(struct iha_softc *); 174 static int iha_state_3(struct iha_softc *); 175 static int iha_state_4(struct iha_softc *); 176 static int iha_state_5(struct iha_softc *); 177 static int iha_state_6(struct iha_softc *); 178 static int iha_state_8(struct iha_softc *); 179 180 static int iha_xfer_data(struct iha_softc *, struct iha_scb *, int); 181 static int iha_xpad_in(struct iha_softc *); 182 static int iha_xpad_out(struct iha_softc *); 183 184 static int iha_status_msg(struct iha_softc *); 185 static void iha_busfree(struct iha_softc *); 186 static int iha_resel(struct iha_softc *); 187 188 static int iha_msgin(struct iha_softc *); 189 static int iha_msgin_extended(struct iha_softc *); 190 static int iha_msgin_sdtr(struct iha_softc *); 191 static int iha_msgin_ignore_wid_resid(struct iha_softc *); 192 193 static int iha_msgout(struct iha_softc *, u_int8_t); 194 static void iha_msgout_abort(struct iha_softc *, u_int8_t); 195 static int iha_msgout_reject(struct iha_softc *); 196 static int iha_msgout_extended(struct iha_softc *); 197 static int iha_msgout_wdtr(struct iha_softc *); 198 static int iha_msgout_sdtr(struct iha_softc *); 199 200 static void iha_wide_done(struct iha_softc *); 201 static void iha_sync_done(struct iha_softc *); 202 203 static void iha_bad_seq(struct iha_softc *); 204 205 static void iha_read_eeprom(struct iha_softc *, struct iha_eeprom *); 206 static int iha_se2_rd_all(struct iha_softc *, u_int16_t *); 207 static void iha_se2_instr(struct iha_softc *, int); 208 static u_int16_t iha_se2_rd(struct iha_softc *, int); 209 #ifdef notused 210 static void iha_se2_update_all(struct iha_softc *); 211 static void iha_se2_wr(struct iha_softc *, int, u_int16_t); 212 #endif 213 214 /* 215 * iha_append_free_scb - append the supplied SCB to the tail of the 216 * sc_freescb queue after clearing and resetting 217 * everything possible. 218 */ 219 static void 220 iha_append_free_scb(struct iha_softc *sc, struct iha_scb *scb) 221 { 222 int s; 223 224 s = splbio(); 225 226 if (scb == sc->sc_actscb) 227 sc->sc_actscb = NULL; 228 229 scb->status = STATUS_QUEUED; 230 scb->ha_stat = HOST_OK; 231 scb->ta_stat = SCSI_OK; 232 233 scb->nextstat = 0; 234 scb->scb_tagmsg = 0; 235 236 scb->xs = NULL; 237 scb->tcs = NULL; 238 239 /* 240 * scb_tagid, sg_addr, sglist 241 * SCB_SensePtr are set at initialization 242 * and never change 243 */ 244 245 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 246 247 splx(s); 248 } 249 250 static void 251 iha_append_done_scb(struct iha_softc *sc, struct iha_scb *scb, u_int8_t hastat) 252 { 253 struct tcs *tcs; 254 int s; 255 256 s = splbio(); 257 258 if (scb->xs != NULL) 259 callout_stop(&scb->xs->xs_callout); 260 261 if (scb == sc->sc_actscb) 262 sc->sc_actscb = NULL; 263 264 tcs = scb->tcs; 265 266 if (scb->scb_tagmsg != 0) { 267 if (tcs->tagcnt) 268 tcs->tagcnt--; 269 } else if (tcs->ntagscb == scb) 270 tcs->ntagscb = NULL; 271 272 scb->status = STATUS_QUEUED; 273 scb->ha_stat = hastat; 274 275 TAILQ_INSERT_TAIL(&sc->sc_donescb, scb, chain); 276 277 splx(s); 278 } 279 280 static __inline struct iha_scb * 281 iha_pop_done_scb(struct iha_softc *sc) 282 { 283 struct iha_scb *scb; 284 int s; 285 286 s = splbio(); 287 288 scb = TAILQ_FIRST(&sc->sc_donescb); 289 290 if (scb != NULL) { 291 scb->status = STATUS_RENT; 292 TAILQ_REMOVE(&sc->sc_donescb, scb, chain); 293 } 294 295 splx(s); 296 297 return (scb); 298 } 299 300 /* 301 * iha_find_pend_scb - scan the pending queue for a SCB that can be 302 * processed immediately. Return NULL if none found 303 * and a pointer to the SCB if one is found. If there 304 * is an active SCB, return NULL! 305 */ 306 static struct iha_scb * 307 iha_find_pend_scb(struct iha_softc *sc) 308 { 309 struct iha_scb *scb; 310 struct tcs *tcs; 311 int s; 312 313 s = splbio(); 314 315 if (sc->sc_actscb != NULL) 316 scb = NULL; 317 318 else 319 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) { 320 if ((scb->xs->xs_control & XS_CTL_RESET) != 0) 321 /* ALWAYS willing to reset a device */ 322 break; 323 324 tcs = scb->tcs; 325 326 if ((scb->scb_tagmsg) != 0) { 327 /* 328 * A Tagged I/O. OK to start If no 329 * non-tagged I/O is active on the same 330 * target 331 */ 332 if (tcs->ntagscb == NULL) 333 break; 334 335 } else if (scb->cmd[0] == REQUEST_SENSE) { 336 /* 337 * OK to do a non-tagged request sense 338 * even if a non-tagged I/O has been 339 * started, 'cuz we don't allow any 340 * disconnect during a request sense op 341 */ 342 break; 343 344 } else if (tcs->tagcnt == 0) { 345 /* 346 * No tagged I/O active on this target, 347 * ok to start a non-tagged one if one 348 * is not already active 349 */ 350 if (tcs->ntagscb == NULL) 351 break; 352 } 353 } 354 355 splx(s); 356 357 return (scb); 358 } 359 360 static __inline void 361 iha_append_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 362 { 363 /* ASSUMPTION: only called within a splbio()/splx() pair */ 364 365 if (scb == sc->sc_actscb) 366 sc->sc_actscb = NULL; 367 368 scb->status = STATUS_QUEUED; 369 370 TAILQ_INSERT_TAIL(&sc->sc_pendscb, scb, chain); 371 } 372 373 static __inline void 374 iha_push_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 375 { 376 int s; 377 378 s = splbio(); 379 380 if (scb == sc->sc_actscb) 381 sc->sc_actscb = NULL; 382 383 scb->status = STATUS_QUEUED; 384 385 TAILQ_INSERT_HEAD(&sc->sc_pendscb, scb, chain); 386 387 splx(s); 388 } 389 390 /* 391 * iha_del_pend_scb - remove scb from sc_pendscb 392 */ 393 static __inline void 394 iha_del_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 395 { 396 int s; 397 398 s = splbio(); 399 400 TAILQ_REMOVE(&sc->sc_pendscb, scb, chain); 401 402 splx(s); 403 } 404 405 static __inline void 406 iha_mark_busy_scb(struct iha_scb *scb) 407 { 408 int s; 409 410 s = splbio(); 411 412 scb->status = STATUS_BUSY; 413 414 if (scb->scb_tagmsg == 0) 415 scb->tcs->ntagscb = scb; 416 else 417 scb->tcs->tagcnt++; 418 419 splx(s); 420 } 421 422 /* 423 * iha_set_ssig - read the current scsi signal mask, then write a new 424 * one which turns off/on the specified signals. 425 */ 426 static __inline void 427 iha_set_ssig(struct iha_softc *sc, u_int8_t offsigs, u_int8_t onsigs) 428 { 429 bus_space_tag_t iot = sc->sc_iot; 430 bus_space_handle_t ioh = sc->sc_ioh; 431 u_int8_t currsigs; 432 433 currsigs = bus_space_read_1(iot, ioh, TUL_SSIGI); 434 bus_space_write_1(iot, ioh, TUL_SSIGO, (currsigs & ~offsigs) | onsigs); 435 } 436 437 /* 438 * iha_intr - the interrupt service routine for the iha driver 439 */ 440 int 441 iha_intr(void *arg) 442 { 443 bus_space_tag_t iot; 444 bus_space_handle_t ioh; 445 struct iha_softc *sc; 446 int s; 447 448 sc = (struct iha_softc *)arg; 449 iot = sc->sc_iot; 450 ioh = sc->sc_ioh; 451 452 if ((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 453 return (0); 454 455 s = splbio(); /* XXX - Or are interrupts off when ISR's are called? */ 456 457 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 458 /* XXX - need these inside a splbio()/splx()? */ 459 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 460 sc->sc_semaph = SEMAPH_IN_MAIN; 461 462 iha_main(sc); 463 464 sc->sc_semaph = ~SEMAPH_IN_MAIN; 465 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 466 } 467 468 splx(s); 469 470 return (1); 471 } 472 473 void 474 iha_attach(struct iha_softc *sc) 475 { 476 bus_space_tag_t iot = sc->sc_iot; 477 bus_space_handle_t ioh = sc->sc_ioh; 478 struct iha_scb *scb; 479 struct iha_eeprom eeprom; 480 struct eeprom_adapter *conf; 481 int i, error, reg; 482 483 iha_read_eeprom(sc, &eeprom); 484 485 conf = &eeprom.adapter[0]; 486 487 /* 488 * fill in the rest of the iha_softc fields 489 */ 490 sc->sc_id = CFG_ID(conf->config1); 491 sc->sc_semaph = ~SEMAPH_IN_MAIN; 492 sc->sc_status0 = 0; 493 sc->sc_actscb = NULL; 494 495 TAILQ_INIT(&sc->sc_freescb); 496 TAILQ_INIT(&sc->sc_pendscb); 497 TAILQ_INIT(&sc->sc_donescb); 498 error = iha_alloc_sglist(sc); 499 if (error != 0) { 500 printf(": cannot allocate sglist\n"); 501 return; 502 } 503 504 sc->sc_scb = malloc(sizeof(struct iha_scb) * IHA_MAX_SCB, 505 M_DEVBUF, M_NOWAIT|M_ZERO); 506 if (sc->sc_scb == NULL) { 507 printf(": cannot allocate SCB\n"); 508 return; 509 } 510 511 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) { 512 scb->scb_tagid = i; 513 scb->sgoffset = IHA_SG_SIZE * i; 514 scb->sglist = sc->sc_sglist + IHA_MAX_SG_ENTRIES * i; 515 scb->sg_addr = 516 sc->sc_dmamap->dm_segs[0].ds_addr + scb->sgoffset; 517 518 error = bus_dmamap_create(sc->sc_dmat, 519 MAXPHYS, IHA_MAX_SG_ENTRIES, MAXPHYS, 0, 520 BUS_DMA_NOWAIT, &scb->dmap); 521 522 if (error != 0) { 523 printf(": couldn't create SCB DMA map, error = %d\n", 524 error); 525 return; 526 } 527 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 528 } 529 530 /* Mask all the interrupts */ 531 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 532 533 /* Stop any I/O and reset the scsi module */ 534 iha_reset_dma(sc); 535 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSMOD); 536 537 /* Program HBA's SCSI ID */ 538 bus_space_write_1(iot, ioh, TUL_SID, sc->sc_id << 4); 539 540 /* 541 * Configure the channel as requested by the NVRAM settings read 542 * by iha_read_eeprom() above. 543 */ 544 545 sc->sc_sconf1 = SCONFIG0DEFAULT; 546 if ((conf->config1 & CFG_EN_PAR) != 0) 547 sc->sc_sconf1 |= SPCHK; 548 bus_space_write_1(iot, ioh, TUL_SCONFIG0, sc->sc_sconf1); 549 550 /* set selection time out 250 ms */ 551 bus_space_write_1(iot, ioh, TUL_STIMO, STIMO_250MS); 552 553 /* Enable desired SCSI termination configuration read from eeprom */ 554 reg = 0; 555 if (conf->config1 & CFG_ACT_TERM1) 556 reg |= ENTMW; 557 if (conf->config1 & CFG_ACT_TERM2) 558 reg |= ENTM; 559 bus_space_write_1(iot, ioh, TUL_DCTRL0, reg); 560 561 reg = bus_space_read_1(iot, ioh, TUL_GCTRL1) & ~ATDEN; 562 if (conf->config1 & CFG_AUTO_TERM) 563 reg |= ATDEN; 564 bus_space_write_1(iot, ioh, TUL_GCTRL1, reg); 565 566 for (i = 0; i < IHA_MAX_TARGETS / 2; i++) { 567 sc->sc_tcs[i * 2 ].flags = EEP_LBYTE(conf->tflags[i]); 568 sc->sc_tcs[i * 2 + 1].flags = EEP_HBYTE(conf->tflags[i]); 569 iha_reset_tcs(&sc->sc_tcs[i * 2 ], sc->sc_sconf1); 570 iha_reset_tcs(&sc->sc_tcs[i * 2 + 1], sc->sc_sconf1); 571 } 572 573 iha_reset_chip(sc); 574 bus_space_write_1(iot, ioh, TUL_SIEN, ALL_INTERRUPTS); 575 576 /* 577 * fill in the adapter. 578 */ 579 sc->sc_adapter.adapt_dev = &sc->sc_dev; 580 sc->sc_adapter.adapt_nchannels = 1; 581 sc->sc_adapter.adapt_openings = IHA_MAX_SCB; 582 sc->sc_adapter.adapt_max_periph = IHA_MAX_SCB; 583 sc->sc_adapter.adapt_ioctl = NULL; 584 sc->sc_adapter.adapt_minphys = minphys; 585 sc->sc_adapter.adapt_request = iha_scsipi_request; 586 587 /* 588 * fill in the channel. 589 */ 590 sc->sc_channel.chan_adapter = &sc->sc_adapter; 591 sc->sc_channel.chan_bustype = &scsi_bustype; 592 sc->sc_channel.chan_channel = 0; 593 sc->sc_channel.chan_ntargets = CFG_TARGET(conf->config2); 594 sc->sc_channel.chan_nluns = 8; 595 sc->sc_channel.chan_id = sc->sc_id; 596 597 /* 598 * Now try to attach all the sub devices. 599 */ 600 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 601 } 602 603 /* 604 * iha_alloc_sglist - allocate and map sglist for SCB's 605 */ 606 static int 607 iha_alloc_sglist(struct iha_softc *sc) 608 { 609 bus_dma_segment_t seg; 610 int error, rseg; 611 612 /* 613 * Allocate DMA-safe memory for the SCB's sglist 614 */ 615 if ((error = bus_dmamem_alloc(sc->sc_dmat, 616 IHA_SG_SIZE * IHA_MAX_SCB, 617 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 618 printf(": unable to allocate sglist, error = %d\n", error); 619 return (error); 620 } 621 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 622 IHA_SG_SIZE * IHA_MAX_SCB, (caddr_t *)&sc->sc_sglist, 623 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 624 printf(": unable to map sglist, error = %d\n", error); 625 return (error); 626 } 627 628 /* 629 * Create and load the DMA map used for the SCBs 630 */ 631 if ((error = bus_dmamap_create(sc->sc_dmat, 632 IHA_SG_SIZE * IHA_MAX_SCB, 1, IHA_SG_SIZE * IHA_MAX_SCB, 633 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 634 printf(": unable to create control DMA map, error = %d\n", 635 error); 636 return (error); 637 } 638 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 639 sc->sc_sglist, IHA_SG_SIZE * IHA_MAX_SCB, 640 NULL, BUS_DMA_NOWAIT)) != 0) { 641 printf(": unable to load control DMA map, error = %d\n", error); 642 return (error); 643 } 644 645 memset(sc->sc_sglist, 0, IHA_SG_SIZE * IHA_MAX_SCB); 646 647 return (0); 648 } 649 650 void 651 iha_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 652 void *arg) 653 { 654 struct scsipi_xfer *xs; 655 struct scsipi_periph *periph; 656 struct iha_scb *scb; 657 struct iha_softc *sc; 658 int error, s; 659 660 sc = (struct iha_softc *)chan->chan_adapter->adapt_dev; 661 662 switch (req) { 663 case ADAPTER_REQ_RUN_XFER: 664 xs = arg; 665 periph = xs->xs_periph; 666 667 if (xs->cmdlen > sizeof(struct scsi_generic) || 668 periph->periph_target >= IHA_MAX_TARGETS) { 669 xs->error = XS_DRIVER_STUFFUP; 670 return; 671 } 672 673 s = splbio(); 674 scb = TAILQ_FIRST(&sc->sc_freescb); 675 if (scb != NULL) { 676 scb->status = STATUS_RENT; 677 TAILQ_REMOVE(&sc->sc_freescb, scb, chain); 678 } 679 #ifdef DIAGNOSTIC 680 else { 681 scsipi_printaddr(periph); 682 printf("unable to allocate scb\n"); 683 panic("iha_scsipi_request"); 684 } 685 #endif 686 splx(s); 687 688 scb->target = periph->periph_target; 689 scb->lun = periph->periph_lun; 690 scb->tcs = &sc->sc_tcs[scb->target]; 691 scb->scb_id = MSG_IDENTIFY(periph->periph_lun, 692 (xs->xs_control & XS_CTL_REQSENSE) == 0); 693 694 scb->xs = xs; 695 scb->cmdlen = xs->cmdlen; 696 memcpy(&scb->cmd, xs->cmd, xs->cmdlen); 697 scb->buflen = xs->datalen; 698 scb->flags = 0; 699 if (xs->xs_control & XS_CTL_DATA_OUT) 700 scb->flags |= FLAG_DATAOUT; 701 if (xs->xs_control & XS_CTL_DATA_IN) 702 scb->flags |= FLAG_DATAIN; 703 704 if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 705 error = bus_dmamap_load(sc->sc_dmat, scb->dmap, 706 xs->data, scb->buflen, NULL, 707 ((xs->xs_control & XS_CTL_NOSLEEP) ? 708 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 709 BUS_DMA_STREAMING | 710 ((scb->flags & FLAG_DATAIN) ? 711 BUS_DMA_READ : BUS_DMA_WRITE)); 712 713 if (error) { 714 printf("%s: error %d loading DMA map\n", 715 sc->sc_dev.dv_xname, error); 716 iha_append_free_scb(sc, scb); 717 xs->error = XS_DRIVER_STUFFUP; 718 scsipi_done(xs); 719 return; 720 } 721 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 722 0, scb->dmap->dm_mapsize, 723 (scb->flags & FLAG_DATAIN) ? 724 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 725 } 726 727 iha_exec_scb(sc, scb); 728 return; 729 730 case ADAPTER_REQ_GROW_RESOURCES: 731 return; /* XXX */ 732 733 case ADAPTER_REQ_SET_XFER_MODE: 734 { 735 struct tcs *tcs; 736 struct scsipi_xfer_mode *xm = arg; 737 738 tcs = &sc->sc_tcs[xm->xm_target]; 739 740 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 741 (tcs->flags & FLAG_NO_WIDE) == 0) 742 tcs->flags &= ~(FLAG_WIDE_DONE|FLAG_SYNC_DONE); 743 744 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 745 (tcs->flags & FLAG_NO_SYNC) == 0) 746 tcs->flags &= ~FLAG_SYNC_DONE; 747 748 /* 749 * If we're not going to negotiate, send the 750 * notification now, since it won't happen later. 751 */ 752 if ((tcs->flags & (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) == 753 (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) 754 iha_update_xfer_mode(sc, xm->xm_target); 755 756 return; 757 } 758 } 759 } 760 761 void 762 iha_update_xfer_mode(struct iha_softc *sc, int target) 763 { 764 struct tcs *tcs = &sc->sc_tcs[target]; 765 struct scsipi_xfer_mode xm; 766 767 xm.xm_target = target; 768 xm.xm_mode = 0; 769 xm.xm_period = 0; 770 xm.xm_offset = 0; 771 772 if (tcs->syncm & PERIOD_WIDE_SCSI) 773 xm.xm_mode |= PERIPH_CAP_WIDE16; 774 775 if (tcs->period) { 776 xm.xm_mode |= PERIPH_CAP_SYNC; 777 xm.xm_period = tcs->period; 778 xm.xm_offset = tcs->offset; 779 } 780 781 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 782 } 783 784 static void 785 iha_reset_scsi_bus(struct iha_softc *sc) 786 { 787 struct iha_scb *scb; 788 struct tcs *tcs; 789 int i, s; 790 791 s = splbio(); 792 793 iha_reset_dma(sc); 794 795 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 796 switch (scb->status) { 797 case STATUS_BUSY: 798 iha_append_done_scb(sc, scb, HOST_SCSI_RST); 799 break; 800 801 case STATUS_SELECT: 802 iha_push_pend_scb(sc, scb); 803 break; 804 805 default: 806 break; 807 } 808 809 for (i = 0, tcs = sc->sc_tcs; i < IHA_MAX_TARGETS; i++, tcs++) 810 iha_reset_tcs(tcs, sc->sc_sconf1); 811 812 splx(s); 813 } 814 815 void 816 iha_reset_chip(struct iha_softc *sc) 817 { 818 bus_space_tag_t iot = sc->sc_iot; 819 bus_space_handle_t ioh = sc->sc_ioh; 820 821 /* reset tulip chip */ 822 823 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSCSI); 824 825 do { 826 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 827 } while ((sc->sc_sistat & SRSTD) == 0); 828 829 iha_set_ssig(sc, 0, 0); 830 831 bus_space_read_1(iot, ioh, TUL_SISTAT); /* Clear any active interrupt*/ 832 } 833 834 /* 835 * iha_reset_dma - abort any active DMA xfer, reset tulip FIFO. 836 */ 837 static void 838 iha_reset_dma(struct iha_softc *sc) 839 { 840 bus_space_tag_t iot = sc->sc_iot; 841 bus_space_handle_t ioh = sc->sc_ioh; 842 843 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 844 /* if DMA xfer is pending, abort DMA xfer */ 845 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 846 /* wait Abort DMA xfer done */ 847 while ((bus_space_read_1(iot, ioh, TUL_ISTUS0) & DABT) == 0) 848 ; 849 } 850 851 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 852 } 853 854 /* 855 * iha_reset_tcs - reset the target control structure pointed 856 * to by tcs to default values. tcs flags 857 * only has the negotiation done bits reset as 858 * the other bits are fixed at initialization. 859 */ 860 static void 861 iha_reset_tcs(struct tcs *tcs, u_int8_t config0) 862 { 863 864 tcs->flags &= ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 865 tcs->period = 0; 866 tcs->offset = 0; 867 tcs->tagcnt = 0; 868 tcs->ntagscb = NULL; 869 tcs->syncm = 0; 870 tcs->sconfig0 = config0; 871 } 872 873 /* 874 * iha_main - process the active SCB, taking one off pending and making it 875 * active if necessary, and any done SCB's created as 876 * a result until there are no interrupts pending and no pending 877 * SCB's that can be started. 878 */ 879 static void 880 iha_main(struct iha_softc *sc) 881 { 882 bus_space_tag_t iot = sc->sc_iot; 883 bus_space_handle_t ioh =sc->sc_ioh; 884 struct iha_scb *scb; 885 886 for (;;) { 887 iha_scsi(sc); 888 889 while ((scb = iha_pop_done_scb(sc)) != NULL) 890 iha_done_scb(sc, scb); 891 892 /* 893 * If there are no interrupts pending, or we can't start 894 * a pending sc, break out of the for(;;). Otherwise 895 * continue the good work with another call to 896 * iha_scsi(). 897 */ 898 if (((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 899 && (iha_find_pend_scb(sc) == NULL)) 900 break; 901 } 902 } 903 904 /* 905 * iha_scsi - service any outstanding interrupts. If there are none, try to 906 * start another SCB currently in the pending queue. 907 */ 908 static void 909 iha_scsi(struct iha_softc *sc) 910 { 911 bus_space_tag_t iot = sc->sc_iot; 912 bus_space_handle_t ioh = sc->sc_ioh; 913 struct iha_scb *scb; 914 struct tcs *tcs; 915 u_int8_t stat; 916 917 /* service pending interrupts asap */ 918 919 stat = bus_space_read_1(iot, ioh, TUL_STAT0); 920 if ((stat & INTPD) != 0) { 921 sc->sc_status0 = stat; 922 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 923 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 924 925 sc->sc_phase = sc->sc_status0 & PH_MASK; 926 927 if ((sc->sc_sistat & SRSTD) != 0) { 928 iha_reset_scsi_bus(sc); 929 return; 930 } 931 932 if ((sc->sc_sistat & RSELED) != 0) { 933 iha_resel(sc); 934 return; 935 } 936 937 if ((sc->sc_sistat & (STIMEO | DISCD)) != 0) { 938 iha_busfree(sc); 939 return; 940 } 941 942 if ((sc->sc_sistat & (SCMDN | SBSRV)) != 0) { 943 iha_next_state(sc); 944 return; 945 } 946 947 if ((sc->sc_sistat & SELED) != 0) 948 iha_set_ssig(sc, 0, 0); 949 } 950 951 /* 952 * There were no interrupts pending which required action elsewhere, so 953 * see if it is possible to start the selection phase on a pending SCB 954 */ 955 if ((scb = iha_find_pend_scb(sc)) == NULL) 956 return; 957 958 tcs = scb->tcs; 959 960 /* program HBA's SCSI ID & target SCSI ID */ 961 bus_space_write_1(iot, ioh, TUL_SID, (sc->sc_id << 4) | scb->target); 962 963 if ((scb->xs->xs_control & XS_CTL_RESET) == 0) { 964 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 965 966 if ((tcs->flags & FLAG_NO_NEG_SYNC) == 0 || 967 (tcs->flags & FLAG_NO_NEG_WIDE) == 0) 968 iha_select(sc, scb, SELATNSTOP); 969 970 else if (scb->scb_tagmsg != 0) 971 iha_select(sc, scb, SEL_ATN3); 972 973 else 974 iha_select(sc, scb, SEL_ATN); 975 976 } else { 977 iha_select(sc, scb, SELATNSTOP); 978 scb->nextstat = 8; 979 } 980 981 if ((scb->xs->xs_control & XS_CTL_POLL) != 0) { 982 int timeout; 983 for (timeout = scb->xs->timeout; timeout > 0; timeout--) { 984 if (iha_wait(sc, NO_OP) == -1) 985 break; 986 if (iha_next_state(sc) == -1) 987 break; 988 delay(1000); /* Only happens in boot, so it's ok */ 989 } 990 991 /* 992 * Since done queue processing not done until AFTER this 993 * function returns, scb is on the done queue, not 994 * the free queue at this point and still has valid data 995 * 996 * Conversely, xs->error has not been set yet 997 */ 998 if (timeout == 0) 999 iha_timeout(scb); 1000 } 1001 } 1002 1003 static void 1004 iha_select(struct iha_softc *sc, struct iha_scb *scb, u_int8_t select_type) 1005 { 1006 bus_space_tag_t iot = sc->sc_iot; 1007 bus_space_handle_t ioh = sc->sc_ioh; 1008 1009 switch (select_type) { 1010 case SEL_ATN: 1011 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1012 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1013 scb->cmd, scb->cmdlen); 1014 1015 scb->nextstat = 2; 1016 break; 1017 1018 case SELATNSTOP: 1019 scb->nextstat = 1; 1020 break; 1021 1022 case SEL_ATN3: 1023 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1024 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagmsg); 1025 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagid); 1026 1027 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, scb->cmd, 1028 scb->cmdlen); 1029 1030 scb->nextstat = 2; 1031 break; 1032 1033 default: 1034 printf("[debug] iha_select() - unknown select type = 0x%02x\n", 1035 select_type); 1036 return; 1037 } 1038 1039 iha_del_pend_scb(sc, scb); 1040 scb->status = STATUS_SELECT; 1041 1042 sc->sc_actscb = scb; 1043 1044 bus_space_write_1(iot, ioh, TUL_SCMD, select_type); 1045 } 1046 1047 /* 1048 * iha_wait - wait for an interrupt to service or a SCSI bus phase change 1049 * after writing the supplied command to the tulip chip. If 1050 * the command is NO_OP, skip the command writing. 1051 */ 1052 static int 1053 iha_wait(struct iha_softc *sc, u_int8_t cmd) 1054 { 1055 bus_space_tag_t iot = sc->sc_iot; 1056 bus_space_handle_t ioh = sc->sc_ioh; 1057 1058 if (cmd != NO_OP) 1059 bus_space_write_1(iot, ioh, TUL_SCMD, cmd); 1060 1061 /* 1062 * Have to do this here, in addition to in iha_isr, because 1063 * interrupts might be turned off when we get here. 1064 */ 1065 do { 1066 sc->sc_status0 = bus_space_read_1(iot, ioh, TUL_STAT0); 1067 } while ((sc->sc_status0 & INTPD) == 0); 1068 1069 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 1070 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 1071 1072 sc->sc_phase = sc->sc_status0 & PH_MASK; 1073 1074 if ((sc->sc_sistat & SRSTD) != 0) { 1075 /* SCSI bus reset interrupt */ 1076 iha_reset_scsi_bus(sc); 1077 return (-1); 1078 } 1079 1080 if ((sc->sc_sistat & RSELED) != 0) 1081 /* Reselection interrupt */ 1082 return (iha_resel(sc)); 1083 1084 if ((sc->sc_sistat & STIMEO) != 0) { 1085 /* selected/reselected timeout interrupt */ 1086 iha_busfree(sc); 1087 return (-1); 1088 } 1089 1090 if ((sc->sc_sistat & DISCD) != 0) { 1091 /* BUS disconnection interrupt */ 1092 if ((sc->sc_flags & FLAG_EXPECT_DONE_DISC) != 0) { 1093 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1094 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 1095 SCONFIG0DEFAULT); 1096 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1097 iha_append_done_scb(sc, sc->sc_actscb, HOST_OK); 1098 sc->sc_flags &= ~FLAG_EXPECT_DONE_DISC; 1099 1100 } else if ((sc->sc_flags & FLAG_EXPECT_DISC) != 0) { 1101 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1102 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 1103 SCONFIG0DEFAULT); 1104 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1105 sc->sc_actscb = NULL; 1106 sc->sc_flags &= ~FLAG_EXPECT_DISC; 1107 1108 } else 1109 iha_busfree(sc); 1110 1111 return (-1); 1112 } 1113 1114 return (sc->sc_phase); 1115 } 1116 1117 static void 1118 iha_exec_scb(struct iha_softc *sc, struct iha_scb *scb) 1119 { 1120 bus_space_tag_t iot; 1121 bus_space_handle_t ioh; 1122 bus_dmamap_t dm; 1123 struct scsipi_xfer *xs = scb->xs; 1124 int nseg, s; 1125 1126 dm = scb->dmap; 1127 nseg = dm->dm_nsegs; 1128 1129 if (nseg > 1) { 1130 struct iha_sg_element *sg = scb->sglist; 1131 int i; 1132 1133 for (i = 0; i < nseg; i++) { 1134 sg[i].sg_len = htole32(dm->dm_segs[i].ds_len); 1135 sg[i].sg_addr = htole32(dm->dm_segs[i].ds_addr); 1136 } 1137 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1138 scb->sgoffset, IHA_SG_SIZE, 1139 BUS_DMASYNC_PREWRITE); 1140 1141 scb->flags |= FLAG_SG; 1142 scb->sg_size = scb->sg_max = nseg; 1143 scb->sg_index = 0; 1144 1145 scb->bufaddr = scb->sg_addr; 1146 } else 1147 scb->bufaddr = dm->dm_segs[0].ds_addr; 1148 1149 if ((xs->xs_control & XS_CTL_POLL) == 0) { 1150 int timeout = mstohz(xs->timeout); 1151 if (timeout == 0) 1152 timeout = 1; 1153 callout_reset(&xs->xs_callout, timeout, iha_timeout, scb); 1154 } 1155 1156 s = splbio(); 1157 1158 if (((scb->xs->xs_control & XS_RESET) != 0) || 1159 (scb->cmd[0] == REQUEST_SENSE)) 1160 iha_push_pend_scb(sc, scb); /* Insert SCB at head of Pend */ 1161 else 1162 iha_append_pend_scb(sc, scb); /* Append SCB to tail of Pend */ 1163 1164 /* 1165 * Run through iha_main() to ensure something is active, if 1166 * only this new SCB. 1167 */ 1168 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 1169 iot = sc->sc_iot; 1170 ioh = sc->sc_ioh; 1171 1172 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 1173 sc->sc_semaph = SEMAPH_IN_MAIN; 1174 1175 splx(s); 1176 iha_main(sc); 1177 s = splbio(); 1178 1179 sc->sc_semaph = ~SEMAPH_IN_MAIN; 1180 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 1181 } 1182 1183 splx(s); 1184 } 1185 1186 /* 1187 * iha_done_scb - We have a scb which has been processed by the 1188 * adaptor, now we look to see how the operation went. 1189 */ 1190 static void 1191 iha_done_scb(struct iha_softc *sc, struct iha_scb *scb) 1192 { 1193 struct scsipi_xfer *xs = scb->xs; 1194 1195 if (xs != NULL) { 1196 /* Cancel the timeout. */ 1197 callout_stop(&xs->xs_callout); 1198 1199 if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 1200 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 1201 0, scb->dmap->dm_mapsize, 1202 (scb->flags & FLAG_DATAIN) ? 1203 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1204 bus_dmamap_unload(sc->sc_dmat, scb->dmap); 1205 } 1206 1207 xs->status = scb->ta_stat; 1208 1209 switch (scb->ha_stat) { 1210 case HOST_OK: 1211 switch (scb->ta_stat) { 1212 case SCSI_OK: 1213 case SCSI_CONDITION_MET: 1214 case SCSI_INTERM: 1215 case SCSI_INTERM_COND_MET: 1216 xs->resid = scb->buflen; 1217 xs->error = XS_NOERROR; 1218 if ((scb->flags & FLAG_RSENS) != 0) 1219 xs->error = XS_SENSE; 1220 break; 1221 1222 case SCSI_RESV_CONFLICT: 1223 case SCSI_BUSY: 1224 case SCSI_QUEUE_FULL: 1225 xs->error = XS_BUSY; 1226 break; 1227 1228 case SCSI_TERMINATED: 1229 case SCSI_ACA_ACTIVE: 1230 case SCSI_CHECK: 1231 scb->tcs->flags &= 1232 ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 1233 1234 if ((scb->flags & FLAG_RSENS) != 0 || 1235 iha_push_sense_request(sc, scb) != 0) { 1236 scb->flags &= ~FLAG_RSENS; 1237 printf("%s: request sense failed\n", 1238 sc->sc_dev.dv_xname); 1239 xs->error = XS_DRIVER_STUFFUP; 1240 break; 1241 } 1242 1243 xs->error = XS_SENSE; 1244 return; 1245 1246 default: 1247 xs->error = XS_DRIVER_STUFFUP; 1248 break; 1249 } 1250 break; 1251 1252 case HOST_SEL_TOUT: 1253 xs->error = XS_SELTIMEOUT; 1254 break; 1255 1256 case HOST_SCSI_RST: 1257 case HOST_DEV_RST: 1258 xs->error = XS_RESET; 1259 break; 1260 1261 case HOST_SPERR: 1262 printf("%s: SCSI Parity error detected\n", 1263 sc->sc_dev.dv_xname); 1264 xs->error = XS_DRIVER_STUFFUP; 1265 break; 1266 1267 case HOST_TIMED_OUT: 1268 xs->error = XS_TIMEOUT; 1269 break; 1270 1271 case HOST_DO_DU: 1272 case HOST_BAD_PHAS: 1273 default: 1274 xs->error = XS_DRIVER_STUFFUP; 1275 break; 1276 } 1277 1278 scsipi_done(xs); 1279 } 1280 1281 iha_append_free_scb(sc, scb); 1282 } 1283 1284 /* 1285 * iha_push_sense_request - obtain auto sense data by pushing the 1286 * SCB needing it back onto the pending 1287 * queue with a REQUEST_SENSE CDB. 1288 */ 1289 static int 1290 iha_push_sense_request(struct iha_softc *sc, struct iha_scb *scb) 1291 { 1292 struct scsipi_xfer *xs = scb->xs; 1293 struct scsipi_periph *periph = xs->xs_periph; 1294 struct scsipi_sense *ss = (struct scsipi_sense *)scb->cmd; 1295 int lun = periph->periph_lun; 1296 int err; 1297 1298 ss->opcode = REQUEST_SENSE; 1299 ss->byte2 = lun << SCSI_CMD_LUN_SHIFT; 1300 ss->unused[0] = ss->unused[1] = 0; 1301 ss->length = sizeof(struct scsipi_sense_data); 1302 ss->control = 0; 1303 1304 scb->flags = FLAG_RSENS | FLAG_DATAIN; 1305 1306 scb->scb_id &= ~MSG_IDENTIFY_DISCFLAG; 1307 1308 scb->scb_tagmsg = 0; 1309 scb->ta_stat = SCSI_OK; 1310 1311 scb->cmdlen = sizeof(struct scsipi_sense); 1312 scb->buflen = ss->length; 1313 1314 err = bus_dmamap_load(sc->sc_dmat, scb->dmap, 1315 &xs->sense.scsi_sense, scb->buflen, NULL, 1316 BUS_DMA_READ|BUS_DMA_NOWAIT); 1317 if (err != 0) { 1318 printf("iha_push_sense_request: cannot bus_dmamap_load()\n"); 1319 xs->error = XS_DRIVER_STUFFUP; 1320 return 1; 1321 } 1322 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 1323 0, scb->buflen, BUS_DMASYNC_PREREAD); 1324 1325 /* XXX What about queued command? */ 1326 iha_exec_scb(sc, scb); 1327 1328 return 0; 1329 } 1330 1331 static void 1332 iha_timeout(void *arg) 1333 { 1334 struct iha_scb *scb = (struct iha_scb *)arg; 1335 struct scsipi_xfer *xs = scb->xs; 1336 struct scsipi_periph *periph = xs->xs_periph; 1337 struct iha_softc *sc; 1338 1339 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1340 1341 if (xs == NULL) 1342 printf("[debug] iha_timeout called with xs == NULL\n"); 1343 1344 else { 1345 scsipi_printaddr(periph); 1346 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1347 1348 iha_abort_xs(sc, xs, HOST_TIMED_OUT); 1349 } 1350 } 1351 1352 /* 1353 * iha_abort_xs - find the SCB associated with the supplied xs and 1354 * stop all processing on it, moving it to the done 1355 * queue with the supplied host status value. 1356 */ 1357 static void 1358 iha_abort_xs(struct iha_softc *sc, struct scsipi_xfer *xs, u_int8_t hastat) 1359 { 1360 struct iha_scb *scb; 1361 int i, s; 1362 1363 s = splbio(); 1364 1365 /* Check the pending queue for the SCB pointing to xs */ 1366 1367 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) 1368 if (scb->xs == xs) { 1369 iha_del_pend_scb(sc, scb); 1370 iha_append_done_scb(sc, scb, hastat); 1371 splx(s); 1372 return; 1373 } 1374 1375 /* 1376 * If that didn't work, check all BUSY/SELECTING SCB's for one 1377 * pointing to xs 1378 */ 1379 1380 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1381 switch (scb->status) { 1382 case STATUS_BUSY: 1383 case STATUS_SELECT: 1384 if (scb->xs == xs) { 1385 iha_append_done_scb(sc, scb, hastat); 1386 splx(s); 1387 return; 1388 } 1389 break; 1390 default: 1391 break; 1392 } 1393 1394 splx(s); 1395 } 1396 1397 /* 1398 * iha_data_over_run - return HOST_OK for all SCSI opcodes where BufLen 1399 * is an 'Allocation Length'. All other SCSI opcodes 1400 * get HOST_DO_DU as they SHOULD have xferred all the 1401 * data requested. 1402 * 1403 * The list of opcodes using 'Allocation Length' was 1404 * found by scanning all the SCSI-3 T10 drafts. See 1405 * www.t10.org for the curious with a .pdf reader. 1406 */ 1407 static u_int8_t 1408 iha_data_over_run(struct iha_scb *scb) 1409 { 1410 switch (scb->cmd[0]) { 1411 case 0x03: /* Request Sense SPC-2 */ 1412 case 0x12: /* Inquiry SPC-2 */ 1413 case 0x1a: /* Mode Sense (6 byte version) SPC-2 */ 1414 case 0x1c: /* Receive Diagnostic Results SPC-2 */ 1415 case 0x23: /* Read Format Capacities MMC-2 */ 1416 case 0x29: /* Read Generation SBC */ 1417 case 0x34: /* Read Position SSC-2 */ 1418 case 0x37: /* Read Defect Data SBC */ 1419 case 0x3c: /* Read Buffer SPC-2 */ 1420 case 0x42: /* Read Sub Channel MMC-2 */ 1421 case 0x43: /* Read TOC/PMA/ATIP MMC */ 1422 1423 /* XXX - 2 with same opcode of 0x44? */ 1424 case 0x44: /* Read Header/Read Density Suprt MMC/SSC*/ 1425 1426 case 0x46: /* Get Configuration MMC-2 */ 1427 case 0x4a: /* Get Event/Status Notification MMC-2 */ 1428 case 0x4d: /* Log Sense SPC-2 */ 1429 case 0x51: /* Read Disc Information MMC */ 1430 case 0x52: /* Read Track Information MMC */ 1431 case 0x59: /* Read Master CUE MMC */ 1432 case 0x5a: /* Mode Sense (10 byte version) SPC-2 */ 1433 case 0x5c: /* Read Buffer Capacity MMC */ 1434 case 0x5e: /* Persistent Reserve In SPC-2 */ 1435 case 0x84: /* Receive Copy Results SPC-2 */ 1436 case 0xa0: /* Report LUNs SPC-2 */ 1437 case 0xa3: /* Various Report requests SBC-2/SCC-2*/ 1438 case 0xa4: /* Report Key MMC-2 */ 1439 case 0xad: /* Read DVD Structure MMC-2 */ 1440 case 0xb4: /* Read Element Status (Attached) SMC */ 1441 case 0xb5: /* Request Volume Element Address SMC */ 1442 case 0xb7: /* Read Defect Data (12 byte ver.) SBC */ 1443 case 0xb8: /* Read Element Status (Independ.) SMC */ 1444 case 0xba: /* Report Redundancy SCC-2 */ 1445 case 0xbd: /* Mechanism Status MMC */ 1446 case 0xbe: /* Report Basic Redundancy SCC-2 */ 1447 1448 return (HOST_OK); 1449 1450 default: 1451 return (HOST_DO_DU); 1452 } 1453 } 1454 1455 /* 1456 * iha_next_state - process the current SCB as requested in its 1457 * nextstat member. 1458 */ 1459 static int 1460 iha_next_state(struct iha_softc *sc) 1461 { 1462 1463 if (sc->sc_actscb == NULL) 1464 return (-1); 1465 1466 switch (sc->sc_actscb->nextstat) { 1467 case 1: 1468 if (iha_state_1(sc) == 3) 1469 goto state_3; 1470 break; 1471 1472 case 2: 1473 switch (iha_state_2(sc)) { 1474 case 3: 1475 goto state_3; 1476 case 4: 1477 goto state_4; 1478 default: 1479 break; 1480 } 1481 break; 1482 1483 case 3: 1484 state_3: 1485 if (iha_state_3(sc) == 4) 1486 goto state_4; 1487 break; 1488 1489 case 4: 1490 state_4: 1491 switch (iha_state_4(sc)) { 1492 case 0: 1493 return (0); 1494 case 6: 1495 goto state_6; 1496 default: 1497 break; 1498 } 1499 break; 1500 1501 case 5: 1502 switch (iha_state_5(sc)) { 1503 case 4: 1504 goto state_4; 1505 case 6: 1506 goto state_6; 1507 default: 1508 break; 1509 } 1510 break; 1511 1512 case 6: 1513 state_6: 1514 iha_state_6(sc); 1515 break; 1516 1517 case 8: 1518 iha_state_8(sc); 1519 break; 1520 1521 default: 1522 #ifdef IHA_DEBUG_STATE 1523 printf("[debug] -unknown state: %i-\n", 1524 sc->sc_actscb->nextstat); 1525 #endif 1526 iha_bad_seq(sc); 1527 break; 1528 } 1529 1530 return (-1); 1531 } 1532 1533 /* 1534 * iha_state_1 - selection is complete after a SELATNSTOP. If the target 1535 * has put the bus into MSG_OUT phase start wide/sync 1536 * negotiation. Otherwise clear the FIFO and go to state 3, 1537 * which will send the SCSI CDB to the target. 1538 */ 1539 static int 1540 iha_state_1(struct iha_softc *sc) 1541 { 1542 bus_space_tag_t iot = sc->sc_iot; 1543 bus_space_handle_t ioh = sc->sc_ioh; 1544 struct iha_scb *scb = sc->sc_actscb; 1545 struct tcs *tcs; 1546 int flags; 1547 1548 iha_mark_busy_scb(scb); 1549 1550 tcs = scb->tcs; 1551 1552 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 1553 1554 /* 1555 * If we are in PHASE_MSG_OUT, send 1556 * a) IDENT message (with tags if appropriate) 1557 * b) WDTR if the target is configured to negotiate wide xfers 1558 * ** OR ** 1559 * c) SDTR if the target is configured to negotiate sync xfers 1560 * but not wide ones 1561 * 1562 * If we are NOT, then the target is not asking for anything but 1563 * the data/command, so go straight to state 3. 1564 */ 1565 if (sc->sc_phase == PHASE_MSG_OUT) { 1566 bus_space_write_1(iot, ioh, TUL_SCTRL1, (ESBUSIN | EHRSL)); 1567 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1568 1569 if (scb->scb_tagmsg != 0) { 1570 bus_space_write_1(iot, ioh, TUL_SFIFO, 1571 scb->scb_tagmsg); 1572 bus_space_write_1(iot, ioh, TUL_SFIFO, 1573 scb->scb_tagid); 1574 } 1575 1576 flags = tcs->flags; 1577 if ((flags & FLAG_NO_NEG_WIDE) == 0) { 1578 if (iha_msgout_wdtr(sc) == -1) 1579 return (-1); 1580 } else if ((flags & FLAG_NO_NEG_SYNC) == 0) { 1581 if (iha_msgout_sdtr(sc) == -1) 1582 return (-1); 1583 } 1584 1585 } else { 1586 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1587 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1588 } 1589 1590 return (3); 1591 } 1592 1593 /* 1594 * iha_state_2 - selection is complete after a SEL_ATN or SEL_ATN3. If the SCSI 1595 * CDB has already been send, go to state 4 to start the data 1596 * xfer. Otherwise reset the FIFO and go to state 3, sending 1597 * the SCSI CDB. 1598 */ 1599 static int 1600 iha_state_2(struct iha_softc *sc) 1601 { 1602 bus_space_tag_t iot = sc->sc_iot; 1603 bus_space_handle_t ioh = sc->sc_ioh; 1604 struct iha_scb *scb = sc->sc_actscb; 1605 1606 iha_mark_busy_scb(scb); 1607 1608 bus_space_write_1(iot, ioh, TUL_SCONFIG0, scb->tcs->sconfig0); 1609 1610 if ((sc->sc_status1 & CPDNE) != 0) 1611 return (4); 1612 1613 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1614 1615 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1616 1617 return (3); 1618 } 1619 1620 /* 1621 * iha_state_3 - send the SCSI CDB to the target, processing any status 1622 * or other messages received until that is done or 1623 * abandoned. 1624 */ 1625 static int 1626 iha_state_3(struct iha_softc *sc) 1627 { 1628 bus_space_tag_t iot = sc->sc_iot; 1629 bus_space_handle_t ioh = sc->sc_ioh; 1630 struct iha_scb *scb = sc->sc_actscb; 1631 int flags; 1632 1633 for (;;) { 1634 switch (sc->sc_phase) { 1635 case PHASE_CMD_OUT: 1636 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1637 scb->cmd, scb->cmdlen); 1638 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1639 return (-1); 1640 else if (sc->sc_phase == PHASE_CMD_OUT) { 1641 iha_bad_seq(sc); 1642 return (-1); 1643 } else 1644 return (4); 1645 1646 case PHASE_MSG_IN: 1647 scb->nextstat = 3; 1648 if (iha_msgin(sc) == -1) 1649 return (-1); 1650 break; 1651 1652 case PHASE_STATUS_IN: 1653 if (iha_status_msg(sc) == -1) 1654 return (-1); 1655 break; 1656 1657 case PHASE_MSG_OUT: 1658 flags = scb->tcs->flags; 1659 if ((flags & FLAG_NO_NEG_SYNC) != 0) { 1660 if (iha_msgout(sc, MSG_NOOP) == -1) 1661 return (-1); 1662 } else if (iha_msgout_sdtr(sc) == -1) 1663 return (-1); 1664 break; 1665 1666 default: 1667 printf("[debug] -s3- bad phase = %d\n", sc->sc_phase); 1668 iha_bad_seq(sc); 1669 return (-1); 1670 } 1671 } 1672 } 1673 1674 /* 1675 * iha_state_4 - start a data xfer. Handle any bus state 1676 * transitions until PHASE_DATA_IN/_OUT 1677 * or the attempt is abandoned. If there is 1678 * no data to xfer, go to state 6 and finish 1679 * processing the current SCB. 1680 */ 1681 static int 1682 iha_state_4(struct iha_softc *sc) 1683 { 1684 struct iha_scb *scb = sc->sc_actscb; 1685 1686 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) == 1687 (FLAG_DATAIN | FLAG_DATAOUT)) 1688 return (6); /* Both dir flags set => NO xfer was requested */ 1689 1690 for (;;) { 1691 if (scb->buflen == 0) 1692 return (6); 1693 1694 switch (sc->sc_phase) { 1695 case PHASE_STATUS_IN: 1696 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1697 scb->ha_stat = iha_data_over_run(scb); 1698 if ((iha_status_msg(sc)) == -1) 1699 return (-1); 1700 break; 1701 1702 case PHASE_MSG_IN: 1703 scb->nextstat = 4; 1704 if (iha_msgin(sc) == -1) 1705 return (-1); 1706 break; 1707 1708 case PHASE_MSG_OUT: 1709 if ((sc->sc_status0 & SPERR) != 0) { 1710 scb->buflen = 0; 1711 scb->ha_stat = HOST_SPERR; 1712 if (iha_msgout(sc, MSG_INITIATOR_DET_ERR) == -1) 1713 return (-1); 1714 else 1715 return (6); 1716 } else { 1717 if (iha_msgout(sc, MSG_NOOP) == -1) 1718 return (-1); 1719 } 1720 break; 1721 1722 case PHASE_DATA_IN: 1723 return (iha_xfer_data(sc, scb, FLAG_DATAIN)); 1724 1725 case PHASE_DATA_OUT: 1726 return (iha_xfer_data(sc, scb, FLAG_DATAOUT)); 1727 1728 default: 1729 iha_bad_seq(sc); 1730 return (-1); 1731 } 1732 } 1733 } 1734 1735 /* 1736 * iha_state_5 - handle the partial or final completion of the current 1737 * data xfer. If DMA is still active stop it. If there is 1738 * more data to xfer, go to state 4 and start the xfer. 1739 * If not go to state 6 and finish the SCB. 1740 */ 1741 static int 1742 iha_state_5(struct iha_softc *sc) 1743 { 1744 bus_space_tag_t iot = sc->sc_iot; 1745 bus_space_handle_t ioh = sc->sc_ioh; 1746 struct iha_scb *scb = sc->sc_actscb; 1747 struct iha_sg_element *sg; 1748 u_int32_t cnt; 1749 u_int8_t period, stat; 1750 long xcnt; /* cannot use unsigned!! see code: if (xcnt < 0) */ 1751 int i; 1752 1753 cnt = bus_space_read_4(iot, ioh, TUL_STCNT0) & TCNT; 1754 1755 /* 1756 * Stop any pending DMA activity and check for parity error. 1757 */ 1758 1759 if ((bus_space_read_1(iot, ioh, TUL_DCMD) & XDIR) != 0) { 1760 /* Input Operation */ 1761 if ((sc->sc_status0 & SPERR) != 0) 1762 scb->ha_stat = HOST_SPERR; 1763 1764 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1765 bus_space_write_1(iot, ioh, TUL_DCTRL0, 1766 bus_space_read_1(iot, ioh, TUL_DCTRL0) | SXSTP); 1767 while (bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) 1768 ; 1769 } 1770 1771 } else { 1772 /* Output Operation */ 1773 if ((sc->sc_status1 & SXCMP) == 0) { 1774 period = scb->tcs->syncm; 1775 if ((period & PERIOD_WIDE_SCSI) != 0) 1776 cnt += (bus_space_read_1(iot, ioh, 1777 TUL_SFIFOCNT) & FIFOC) * 2; 1778 else 1779 cnt += bus_space_read_1(iot, ioh, 1780 TUL_SFIFOCNT) & FIFOC; 1781 } 1782 1783 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1784 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 1785 do 1786 stat = bus_space_read_1(iot, ioh, TUL_ISTUS0); 1787 while ((stat & DABT) == 0); 1788 } 1789 1790 if ((cnt == 1) && (sc->sc_phase == PHASE_DATA_OUT)) { 1791 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1792 return (-1); 1793 cnt = 0; 1794 1795 } else if ((sc->sc_status1 & SXCMP) == 0) 1796 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1797 } 1798 1799 if (cnt == 0) { 1800 scb->buflen = 0; 1801 return (6); 1802 } 1803 1804 /* Update active data pointer and restart the I/O at the new point */ 1805 1806 xcnt = scb->buflen - cnt; /* xcnt == bytes xferred */ 1807 scb->buflen = cnt; /* cnt == bytes left */ 1808 1809 if ((scb->flags & FLAG_SG) != 0) { 1810 sg = &scb->sglist[scb->sg_index]; 1811 for (i = scb->sg_index; i < scb->sg_max; sg++, i++) { 1812 xcnt -= le32toh(sg->sg_len); 1813 if (xcnt < 0) { 1814 xcnt += le32toh(sg->sg_len); 1815 1816 sg->sg_addr = 1817 htole32(le32toh(sg->sg_addr) + xcnt); 1818 sg->sg_len = 1819 htole32(le32toh(sg->sg_len) - xcnt); 1820 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1821 scb->sgoffset, IHA_SG_SIZE, 1822 BUS_DMASYNC_PREWRITE); 1823 1824 scb->bufaddr += (i - scb->sg_index) * 1825 sizeof(struct iha_sg_element); 1826 scb->sg_size = scb->sg_max - i; 1827 scb->sg_index = i; 1828 1829 return (4); 1830 } 1831 } 1832 return (6); 1833 1834 } else 1835 scb->bufaddr += xcnt; 1836 1837 return (4); 1838 } 1839 1840 /* 1841 * iha_state_6 - finish off the active scb (may require several 1842 * iterations if PHASE_MSG_IN) and return -1 to indicate 1843 * the bus is free. 1844 */ 1845 static int 1846 iha_state_6(struct iha_softc *sc) 1847 { 1848 1849 for (;;) { 1850 switch (sc->sc_phase) { 1851 case PHASE_STATUS_IN: 1852 if (iha_status_msg(sc) == -1) 1853 return (-1); 1854 break; 1855 1856 case PHASE_MSG_IN: 1857 sc->sc_actscb->nextstat = 6; 1858 if ((iha_msgin(sc)) == -1) 1859 return (-1); 1860 break; 1861 1862 case PHASE_MSG_OUT: 1863 if ((iha_msgout(sc, MSG_NOOP)) == -1) 1864 return (-1); 1865 break; 1866 1867 case PHASE_DATA_IN: 1868 if (iha_xpad_in(sc) == -1) 1869 return (-1); 1870 break; 1871 1872 case PHASE_DATA_OUT: 1873 if (iha_xpad_out(sc) == -1) 1874 return (-1); 1875 break; 1876 1877 default: 1878 iha_bad_seq(sc); 1879 return (-1); 1880 } 1881 } 1882 } 1883 1884 /* 1885 * iha_state_8 - reset the active device and all busy SCBs using it 1886 */ 1887 static int 1888 iha_state_8(struct iha_softc *sc) 1889 { 1890 bus_space_tag_t iot = sc->sc_iot; 1891 bus_space_handle_t ioh = sc->sc_ioh; 1892 struct iha_scb *scb; 1893 int i; 1894 u_int8_t tar; 1895 1896 if (sc->sc_phase == PHASE_MSG_OUT) { 1897 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_BUS_DEV_RESET); 1898 1899 scb = sc->sc_actscb; 1900 1901 /* This SCB finished correctly -- resetting the device */ 1902 iha_append_done_scb(sc, scb, HOST_OK); 1903 1904 iha_reset_tcs(scb->tcs, sc->sc_sconf1); 1905 1906 tar = scb->target; 1907 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1908 if (scb->target == tar) 1909 switch (scb->status) { 1910 case STATUS_BUSY: 1911 iha_append_done_scb(sc, 1912 scb, HOST_DEV_RST); 1913 break; 1914 1915 case STATUS_SELECT: 1916 iha_push_pend_scb(sc, scb); 1917 break; 1918 1919 default: 1920 break; 1921 } 1922 1923 sc->sc_flags |= FLAG_EXPECT_DISC; 1924 1925 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1926 return (-1); 1927 } 1928 1929 iha_bad_seq(sc); 1930 return (-1); 1931 } 1932 1933 /* 1934 * iha_xfer_data - initiate the DMA xfer of the data 1935 */ 1936 static int 1937 iha_xfer_data(struct iha_softc *sc, struct iha_scb *scb, int direction) 1938 { 1939 bus_space_tag_t iot = sc->sc_iot; 1940 bus_space_handle_t ioh = sc->sc_ioh; 1941 u_int32_t xferlen; 1942 u_int8_t xfercmd; 1943 1944 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != direction) 1945 return (6); /* wrong direction, abandon I/O */ 1946 1947 bus_space_write_4(iot, ioh, TUL_STCNT0, scb->buflen); 1948 1949 xfercmd = STRXFR; 1950 if (direction == FLAG_DATAIN) 1951 xfercmd |= XDIR; 1952 1953 if (scb->flags & FLAG_SG) { 1954 xferlen = scb->sg_size * sizeof(struct iha_sg_element); 1955 xfercmd |= SGXFR; 1956 } else 1957 xferlen = scb->buflen; 1958 1959 bus_space_write_4(iot, ioh, TUL_DXC, xferlen); 1960 bus_space_write_4(iot, ioh, TUL_DXPA, scb->bufaddr); 1961 bus_space_write_1(iot, ioh, TUL_DCMD, xfercmd); 1962 1963 bus_space_write_1(iot, ioh, TUL_SCMD, 1964 (direction == FLAG_DATAIN) ? XF_DMA_IN : XF_DMA_OUT); 1965 1966 scb->nextstat = 5; 1967 1968 return (0); 1969 } 1970 1971 static int 1972 iha_xpad_in(struct iha_softc *sc) 1973 { 1974 bus_space_tag_t iot = sc->sc_iot; 1975 bus_space_handle_t ioh = sc->sc_ioh; 1976 struct iha_scb *scb = sc->sc_actscb; 1977 1978 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1979 scb->ha_stat = HOST_DO_DU; 1980 1981 for (;;) { 1982 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 1983 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 1984 else 1985 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1986 1987 switch (iha_wait(sc, XF_FIFO_IN)) { 1988 case -1: 1989 return (-1); 1990 1991 case PHASE_DATA_IN: 1992 bus_space_read_1(iot, ioh, TUL_SFIFO); 1993 break; 1994 1995 default: 1996 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1997 return (6); 1998 } 1999 } 2000 } 2001 2002 static int 2003 iha_xpad_out(struct iha_softc *sc) 2004 { 2005 bus_space_tag_t iot = sc->sc_iot; 2006 bus_space_handle_t ioh = sc->sc_ioh; 2007 struct iha_scb *scb = sc->sc_actscb; 2008 2009 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 2010 scb->ha_stat = HOST_DO_DU; 2011 2012 for (;;) { 2013 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 2014 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 2015 else 2016 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2017 2018 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 2019 2020 switch (iha_wait(sc, XF_FIFO_OUT)) { 2021 case -1: 2022 return (-1); 2023 2024 case PHASE_DATA_OUT: 2025 break; 2026 2027 default: 2028 /* Disable wide CPU to allow read 16 bits */ 2029 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2030 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2031 return (6); 2032 } 2033 } 2034 } 2035 2036 static int 2037 iha_status_msg(struct iha_softc *sc) 2038 { 2039 bus_space_tag_t iot = sc->sc_iot; 2040 bus_space_handle_t ioh = sc->sc_ioh; 2041 struct iha_scb *scb; 2042 u_int8_t msg; 2043 int phase; 2044 2045 if ((phase = iha_wait(sc, CMD_COMP)) == -1) 2046 return (-1); 2047 2048 scb = sc->sc_actscb; 2049 2050 scb->ta_stat = bus_space_read_1(iot, ioh, TUL_SFIFO); 2051 2052 if (phase == PHASE_MSG_OUT) { 2053 if ((sc->sc_status0 & SPERR) == 0) 2054 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_NOOP); 2055 else 2056 bus_space_write_1(iot, ioh, TUL_SFIFO, 2057 MSG_PARITY_ERROR); 2058 2059 return (iha_wait(sc, XF_FIFO_OUT)); 2060 2061 } else if (phase == PHASE_MSG_IN) { 2062 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 2063 2064 if ((sc->sc_status0 & SPERR) != 0) 2065 switch (iha_wait(sc, MSG_ACCEPT)) { 2066 case -1: 2067 return (-1); 2068 case PHASE_MSG_OUT: 2069 bus_space_write_1(iot, ioh, TUL_SFIFO, 2070 MSG_PARITY_ERROR); 2071 return (iha_wait(sc, XF_FIFO_OUT)); 2072 default: 2073 iha_bad_seq(sc); 2074 return (-1); 2075 } 2076 2077 if (msg == MSG_CMDCOMPLETE) { 2078 if ((scb->ta_stat & 2079 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) { 2080 iha_bad_seq(sc); 2081 return (-1); 2082 } 2083 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 2084 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2085 return (iha_wait(sc, MSG_ACCEPT)); 2086 } 2087 2088 if ((msg == MSG_LINK_CMD_COMPLETE) 2089 || (msg == MSG_LINK_CMD_COMPLETEF)) { 2090 if ((scb->ta_stat & 2091 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) 2092 return (iha_wait(sc, MSG_ACCEPT)); 2093 } 2094 } 2095 2096 iha_bad_seq(sc); 2097 return (-1); 2098 } 2099 2100 /* 2101 * iha_busfree - SCSI bus free detected as a result of a TIMEOUT or 2102 * DISCONNECT interrupt. Reset the tulip FIFO and 2103 * SCONFIG0 and enable hardware reselect. Move any active 2104 * SCB to sc_donescb list. Return an appropriate host status 2105 * if an I/O was active. 2106 */ 2107 static void 2108 iha_busfree(struct iha_softc *sc) 2109 { 2110 bus_space_tag_t iot = sc->sc_iot; 2111 bus_space_handle_t ioh = sc->sc_ioh; 2112 struct iha_scb *scb; 2113 2114 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2115 bus_space_write_1(iot, ioh, TUL_SCONFIG0, SCONFIG0DEFAULT); 2116 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2117 2118 scb = sc->sc_actscb; 2119 2120 if (scb != NULL) { 2121 if (scb->status == STATUS_SELECT) 2122 /* selection timeout */ 2123 iha_append_done_scb(sc, scb, HOST_SEL_TOUT); 2124 else 2125 /* Unexpected bus free */ 2126 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 2127 } 2128 } 2129 2130 /* 2131 * iha_resel - handle a detected SCSI bus reselection request. 2132 */ 2133 static int 2134 iha_resel(struct iha_softc *sc) 2135 { 2136 bus_space_tag_t iot = sc->sc_iot; 2137 bus_space_handle_t ioh = sc->sc_ioh; 2138 struct iha_scb *scb; 2139 struct tcs *tcs; 2140 u_int8_t tag, target, lun, msg, abortmsg; 2141 2142 if (sc->sc_actscb != NULL) { 2143 if ((sc->sc_actscb->status == STATUS_SELECT)) 2144 iha_push_pend_scb(sc, sc->sc_actscb); 2145 sc->sc_actscb = NULL; 2146 } 2147 2148 target = bus_space_read_1(iot, ioh, TUL_SBID); 2149 lun = bus_space_read_1(iot, ioh, TUL_SALVC) & IHA_MSG_IDENTIFY_LUNMASK; 2150 2151 tcs = &sc->sc_tcs[target]; 2152 2153 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2154 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2155 2156 abortmsg = MSG_ABORT; /* until a valid tag has been obtained */ 2157 2158 if (tcs->ntagscb != NULL) 2159 /* There is a non-tagged I/O active on the target */ 2160 scb = tcs->ntagscb; 2161 2162 else { 2163 /* 2164 * Since there is no active non-tagged operation 2165 * read the tag type, the tag itself, and find 2166 * the appropriate scb by indexing sc_scb with 2167 * the tag. 2168 */ 2169 2170 switch (iha_wait(sc, MSG_ACCEPT)) { 2171 case -1: 2172 return (-1); 2173 case PHASE_MSG_IN: 2174 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2175 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 2176 return (-1); 2177 break; 2178 default: 2179 goto abort; 2180 } 2181 2182 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag Msg */ 2183 2184 if ((msg < MSG_SIMPLE_Q_TAG) || (msg > MSG_ORDERED_Q_TAG)) 2185 goto abort; 2186 2187 switch (iha_wait(sc, MSG_ACCEPT)) { 2188 case -1: 2189 return (-1); 2190 case PHASE_MSG_IN: 2191 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2192 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 2193 return (-1); 2194 break; 2195 default: 2196 goto abort; 2197 } 2198 2199 tag = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag ID */ 2200 scb = &sc->sc_scb[tag]; 2201 2202 abortmsg = MSG_ABORT_TAG; /* Now that we have valdid tag! */ 2203 } 2204 2205 if ((scb->target != target) 2206 || (scb->lun != lun) 2207 || (scb->status != STATUS_BUSY)) { 2208 abort: 2209 iha_msgout_abort(sc, abortmsg); 2210 return (-1); 2211 } 2212 2213 sc->sc_actscb = scb; 2214 2215 if (iha_wait(sc, MSG_ACCEPT) == -1) 2216 return (-1); 2217 2218 return (iha_next_state(sc)); 2219 } 2220 2221 static int 2222 iha_msgin(struct iha_softc *sc) 2223 { 2224 bus_space_tag_t iot = sc->sc_iot; 2225 bus_space_handle_t ioh = sc->sc_ioh; 2226 int flags; 2227 int phase; 2228 u_int8_t msg; 2229 2230 for (;;) { 2231 if ((bus_space_read_1(iot, ioh, TUL_SFIFOCNT) & FIFOC) > 0) 2232 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2233 2234 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2235 2236 phase = iha_wait(sc, XF_FIFO_IN); 2237 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 2238 2239 switch (msg) { 2240 case MSG_DISCONNECT: 2241 sc->sc_flags |= FLAG_EXPECT_DISC; 2242 if (iha_wait(sc, MSG_ACCEPT) != -1) 2243 iha_bad_seq(sc); 2244 phase = -1; 2245 break; 2246 case MSG_SAVEDATAPOINTER: 2247 case MSG_RESTOREPOINTERS: 2248 case MSG_NOOP: 2249 phase = iha_wait(sc, MSG_ACCEPT); 2250 break; 2251 case MSG_MESSAGE_REJECT: 2252 /* XXX - need to clear FIFO like other 'Clear ATN'?*/ 2253 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2254 flags = sc->sc_actscb->tcs->flags; 2255 if ((flags & FLAG_NO_NEG_SYNC) == 0) 2256 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2257 phase = iha_wait(sc, MSG_ACCEPT); 2258 break; 2259 case MSG_EXTENDED: 2260 phase = iha_msgin_extended(sc); 2261 break; 2262 case MSG_IGN_WIDE_RESIDUE: 2263 phase = iha_msgin_ignore_wid_resid(sc); 2264 break; 2265 case MSG_CMDCOMPLETE: 2266 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 2267 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2268 phase = iha_wait(sc, MSG_ACCEPT); 2269 if (phase != -1) { 2270 iha_bad_seq(sc); 2271 return (-1); 2272 } 2273 break; 2274 default: 2275 printf("[debug] iha_msgin: bad msg type: %d\n", msg); 2276 phase = iha_msgout_reject(sc); 2277 break; 2278 } 2279 2280 if (phase != PHASE_MSG_IN) 2281 return (phase); 2282 } 2283 /* NOTREACHED */ 2284 } 2285 2286 static int 2287 iha_msgin_extended(struct iha_softc *sc) 2288 { 2289 bus_space_tag_t iot = sc->sc_iot; 2290 bus_space_handle_t ioh = sc->sc_ioh; 2291 int flags, i, phase, msglen, msgcode; 2292 2293 /* 2294 * XXX - can we just stop reading and reject, or do we have to 2295 * read all input, discarding the excess, and then reject 2296 */ 2297 for (i = 0; i < IHA_MAX_EXTENDED_MSG; i++) { 2298 phase = iha_wait(sc, MSG_ACCEPT); 2299 2300 if (phase != PHASE_MSG_IN) 2301 return (phase); 2302 2303 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2304 2305 if (iha_wait(sc, XF_FIFO_IN) == -1) 2306 return (-1); 2307 2308 sc->sc_msg[i] = bus_space_read_1(iot, ioh, TUL_SFIFO); 2309 2310 if (sc->sc_msg[0] == i) 2311 break; 2312 } 2313 2314 msglen = sc->sc_msg[0]; 2315 msgcode = sc->sc_msg[1]; 2316 2317 if ((msglen == MSG_EXT_SDTR_LEN) && (msgcode == MSG_EXT_SDTR)) { 2318 if (iha_msgin_sdtr(sc) == 0) { 2319 iha_sync_done(sc); 2320 return (iha_wait(sc, MSG_ACCEPT)); 2321 } 2322 2323 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2324 2325 phase = iha_wait(sc, MSG_ACCEPT); 2326 if (phase != PHASE_MSG_OUT) 2327 return (phase); 2328 2329 /* Clear FIFO for important message - final SYNC offer */ 2330 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2331 2332 iha_sync_done(sc); /* This is our final offer */ 2333 2334 } else if ((msglen == MSG_EXT_WDTR_LEN) && (msgcode == MSG_EXT_WDTR)) { 2335 2336 flags = sc->sc_actscb->tcs->flags; 2337 2338 if ((flags & FLAG_NO_WIDE) != 0) 2339 /* Offer 8bit xfers only */ 2340 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_8_BIT; 2341 2342 else if (sc->sc_msg[2] > MSG_EXT_WDTR_BUS_32_BIT) 2343 /* BAD MSG */ 2344 return (iha_msgout_reject(sc)); 2345 2346 else if (sc->sc_msg[2] == MSG_EXT_WDTR_BUS_32_BIT) 2347 /* Offer 16bit instead */ 2348 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2349 2350 else { 2351 iha_wide_done(sc); 2352 if ((flags & FLAG_NO_NEG_SYNC) == 0) 2353 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2354 return (iha_wait(sc, MSG_ACCEPT)); 2355 } 2356 2357 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2358 2359 phase = iha_wait(sc, MSG_ACCEPT); 2360 if (phase != PHASE_MSG_OUT) 2361 return (phase); 2362 } else 2363 return (iha_msgout_reject(sc)); 2364 2365 return (iha_msgout_extended(sc)); 2366 } 2367 2368 /* 2369 * iha_msgin_sdtr - check SDTR msg in sc_msg. If the offer is 2370 * acceptable leave sc_msg as is and return 0. 2371 * If the negotiation must continue, modify sc_msg 2372 * as needed and return 1. Else return 0. 2373 */ 2374 static int 2375 iha_msgin_sdtr(struct iha_softc *sc) 2376 { 2377 int flags; 2378 int newoffer; 2379 u_int8_t default_period; 2380 2381 flags = sc->sc_actscb->tcs->flags; 2382 2383 default_period = iha_rate_tbl[flags & FLAG_SCSI_RATE]; 2384 2385 if (sc->sc_msg[3] == 0) 2386 /* target offered async only. Accept it. */ 2387 return (0); 2388 2389 newoffer = 0; 2390 2391 if ((flags & FLAG_NO_SYNC) != 0) { 2392 sc->sc_msg[3] = 0; 2393 newoffer = 1; 2394 } 2395 2396 if (sc->sc_msg[3] > IHA_MAX_OFFSET) { 2397 sc->sc_msg[3] = IHA_MAX_OFFSET; 2398 newoffer = 1; 2399 } 2400 2401 if (sc->sc_msg[2] < default_period) { 2402 sc->sc_msg[2] = default_period; 2403 newoffer = 1; 2404 } 2405 2406 if (sc->sc_msg[2] > IHA_MAX_PERIOD) { 2407 /* Use async */ 2408 sc->sc_msg[3] = 0; 2409 newoffer = 1; 2410 } 2411 2412 return (newoffer); 2413 } 2414 2415 static int 2416 iha_msgin_ignore_wid_resid(struct iha_softc *sc) 2417 { 2418 bus_space_tag_t iot = sc->sc_iot; 2419 bus_space_handle_t ioh = sc->sc_ioh; 2420 int phase; 2421 2422 phase = iha_wait(sc, MSG_ACCEPT); 2423 2424 if (phase == PHASE_MSG_IN) { 2425 phase = iha_wait(sc, XF_FIFO_IN); 2426 2427 if (phase != -1) { 2428 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 2429 bus_space_read_1(iot, ioh, TUL_SFIFO); 2430 bus_space_read_1(iot, ioh, TUL_SFIFO); 2431 2432 phase = iha_wait(sc, MSG_ACCEPT); 2433 } 2434 } 2435 2436 return (phase); 2437 } 2438 2439 static int 2440 iha_msgout(struct iha_softc *sc, u_int8_t msg) 2441 { 2442 2443 bus_space_write_1(sc->sc_iot, sc->sc_ioh, TUL_SFIFO, msg); 2444 2445 return (iha_wait(sc, XF_FIFO_OUT)); 2446 } 2447 2448 static void 2449 iha_msgout_abort(struct iha_softc *sc, u_int8_t aborttype) 2450 { 2451 2452 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2453 2454 switch (iha_wait(sc, MSG_ACCEPT)) { 2455 case -1: 2456 break; 2457 2458 case PHASE_MSG_OUT: 2459 sc->sc_flags |= FLAG_EXPECT_DISC; 2460 if (iha_msgout(sc, aborttype) != -1) 2461 iha_bad_seq(sc); 2462 break; 2463 2464 default: 2465 iha_bad_seq(sc); 2466 break; 2467 } 2468 } 2469 2470 static int 2471 iha_msgout_reject(struct iha_softc *sc) 2472 { 2473 2474 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2475 2476 if (iha_wait(sc, MSG_ACCEPT) == PHASE_MSG_OUT) 2477 return (iha_msgout(sc, MSG_MESSAGE_REJECT)); 2478 2479 return (-1); 2480 } 2481 2482 static int 2483 iha_msgout_extended(struct iha_softc *sc) 2484 { 2485 bus_space_tag_t iot = sc->sc_iot; 2486 bus_space_handle_t ioh = sc->sc_ioh; 2487 int phase; 2488 2489 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXTENDED); 2490 2491 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 2492 sc->sc_msg, sc->sc_msg[0] + 1); 2493 2494 phase = iha_wait(sc, XF_FIFO_OUT); 2495 2496 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2497 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2498 2499 return (phase); 2500 } 2501 2502 static int 2503 iha_msgout_wdtr(struct iha_softc *sc) 2504 { 2505 2506 sc->sc_actscb->tcs->flags |= FLAG_WIDE_DONE; 2507 2508 sc->sc_msg[0] = MSG_EXT_WDTR_LEN; 2509 sc->sc_msg[1] = MSG_EXT_WDTR; 2510 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2511 2512 return (iha_msgout_extended(sc)); 2513 } 2514 2515 static int 2516 iha_msgout_sdtr(struct iha_softc *sc) 2517 { 2518 struct tcs *tcs = sc->sc_actscb->tcs; 2519 2520 tcs->flags |= FLAG_SYNC_DONE; 2521 2522 sc->sc_msg[0] = MSG_EXT_SDTR_LEN; 2523 sc->sc_msg[1] = MSG_EXT_SDTR; 2524 sc->sc_msg[2] = iha_rate_tbl[tcs->flags & FLAG_SCSI_RATE]; 2525 sc->sc_msg[3] = IHA_MAX_OFFSET; /* REQ/ACK */ 2526 2527 return (iha_msgout_extended(sc)); 2528 } 2529 2530 static void 2531 iha_wide_done(struct iha_softc *sc) 2532 { 2533 bus_space_tag_t iot = sc->sc_iot; 2534 bus_space_handle_t ioh = sc->sc_ioh; 2535 struct tcs *tcs = sc->sc_actscb->tcs; 2536 2537 tcs->syncm = 0; 2538 tcs->period = 0; 2539 tcs->offset = 0; 2540 2541 if (sc->sc_msg[2] != 0) 2542 tcs->syncm |= PERIOD_WIDE_SCSI; 2543 2544 tcs->sconfig0 &= ~ALTPD; 2545 tcs->flags &= ~FLAG_SYNC_DONE; 2546 tcs->flags |= FLAG_WIDE_DONE; 2547 2548 iha_update_xfer_mode(sc, sc->sc_actscb->target); 2549 2550 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2551 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2552 } 2553 2554 static void 2555 iha_sync_done(struct iha_softc *sc) 2556 { 2557 bus_space_tag_t iot = sc->sc_iot; 2558 bus_space_handle_t ioh = sc->sc_ioh; 2559 struct tcs *tcs = sc->sc_actscb->tcs; 2560 int i; 2561 2562 tcs->period = sc->sc_msg[2]; 2563 tcs->offset = sc->sc_msg[3]; 2564 if (tcs->offset != 0) { 2565 tcs->syncm |= tcs->offset; 2566 2567 /* pick the highest possible rate */ 2568 for (i = 0; i < sizeof(iha_rate_tbl); i++) 2569 if (iha_rate_tbl[i] >= tcs->period) 2570 break; 2571 2572 tcs->syncm |= (i << 4); 2573 tcs->sconfig0 |= ALTPD; 2574 } 2575 2576 tcs->flags |= FLAG_SYNC_DONE; 2577 2578 iha_update_xfer_mode(sc, sc->sc_actscb->target); 2579 2580 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2581 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2582 } 2583 2584 /* 2585 * iha_bad_seq - a SCSI bus phase was encountered out of the 2586 * correct/expected sequence. Reset the SCSI bus. 2587 */ 2588 static void 2589 iha_bad_seq(struct iha_softc *sc) 2590 { 2591 struct iha_scb *scb = sc->sc_actscb; 2592 2593 if (scb != NULL) 2594 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 2595 2596 iha_reset_scsi_bus(sc); 2597 iha_reset_chip(sc); 2598 } 2599 2600 /* 2601 * iha_read_eeprom - read Serial EEPROM value & set to defaults 2602 * if required. XXX - Writing does NOT work! 2603 */ 2604 static void 2605 iha_read_eeprom(struct iha_softc *sc, struct iha_eeprom *eeprom) 2606 { 2607 bus_space_tag_t iot = sc->sc_iot; 2608 bus_space_handle_t ioh = sc->sc_ioh; 2609 u_int16_t *buf = (u_int16_t *)eeprom; 2610 u_int8_t gctrl; 2611 2612 /* Enable EEProm programming */ 2613 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) | EEPRG; 2614 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2615 2616 /* Read EEProm */ 2617 if (iha_se2_rd_all(sc, buf) == 0) 2618 panic("%s: cannot read EEPROM", sc->sc_dev.dv_xname); 2619 2620 /* Disable EEProm programming */ 2621 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) & ~EEPRG; 2622 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2623 } 2624 2625 #ifdef notused 2626 /* 2627 * iha_se2_update_all - Update SCSI H/A configuration parameters from 2628 * serial EEPROM Setup default pattern. Only 2629 * change those values different from the values 2630 * in iha_eeprom. 2631 */ 2632 static void 2633 iha_se2_update_all(struct iha_softc *sc) 2634 { 2635 bus_space_tag_t iot = sc->sc_iot; 2636 bus_space_handle_t ioh = sc->sc_ioh; 2637 u_int16_t *np; 2638 u_int32_t chksum; 2639 int i; 2640 2641 /* Enable erase/write state of EEPROM */ 2642 iha_se2_instr(sc, ENABLE_ERASE); 2643 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2644 EEP_WAIT(); 2645 2646 np = (u_int16_t *)&eeprom_default; 2647 2648 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2649 iha_se2_wr(sc, i, *np); 2650 chksum += *np++; 2651 } 2652 2653 chksum &= 0x0000ffff; 2654 iha_se2_wr(sc, 31, chksum); 2655 2656 /* Disable erase/write state of EEPROM */ 2657 iha_se2_instr(sc, 0); 2658 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2659 EEP_WAIT(); 2660 } 2661 2662 /* 2663 * iha_se2_wr - write the given 16 bit value into the Serial EEPROM 2664 * at the specified offset 2665 */ 2666 static void 2667 iha_se2_wr(struct iha_softc *sc, int addr, u_int16_t writeword) 2668 { 2669 bus_space_tag_t iot = sc->sc_iot; 2670 bus_space_handle_t ioh = sc->sc_ioh; 2671 int i, bit; 2672 2673 /* send 'WRITE' Instruction == address | WRITE bit */ 2674 iha_se2_instr(sc, addr | WRITE); 2675 2676 for (i = 16; i > 0; i--) { 2677 if (writeword & (1 << (i - 1))) 2678 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRDO); 2679 else 2680 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2681 EEP_WAIT(); 2682 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2683 EEP_WAIT(); 2684 } 2685 2686 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2687 EEP_WAIT(); 2688 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2689 EEP_WAIT(); 2690 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2691 EEP_WAIT(); 2692 2693 for (;;) { 2694 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2695 EEP_WAIT(); 2696 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2697 EEP_WAIT(); 2698 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI; 2699 EEP_WAIT(); 2700 if (bit != 0) 2701 break; /* write complete */ 2702 } 2703 2704 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2705 } 2706 #endif 2707 2708 /* 2709 * iha_se2_rd - read & return the 16 bit value at the specified 2710 * offset in the Serial E2PROM 2711 * 2712 */ 2713 static u_int16_t 2714 iha_se2_rd(struct iha_softc *sc, int addr) 2715 { 2716 bus_space_tag_t iot = sc->sc_iot; 2717 bus_space_handle_t ioh = sc->sc_ioh; 2718 int i, bit; 2719 u_int16_t readword; 2720 2721 /* Send 'READ' instruction == address | READ bit */ 2722 iha_se2_instr(sc, addr | READ); 2723 2724 readword = 0; 2725 for (i = 16; i > 0; i--) { 2726 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2727 EEP_WAIT(); 2728 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2729 EEP_WAIT(); 2730 /* sample data after the following edge of clock */ 2731 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI ? 1 : 0; 2732 EEP_WAIT(); 2733 2734 readword |= bit << (i - 1); 2735 } 2736 2737 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2738 2739 return (readword); 2740 } 2741 2742 /* 2743 * iha_se2_rd_all - Read SCSI H/A config parameters from serial EEPROM 2744 */ 2745 static int 2746 iha_se2_rd_all(struct iha_softc *sc, u_int16_t *buf) 2747 { 2748 struct iha_eeprom *eeprom = (struct iha_eeprom *)buf; 2749 u_int32_t chksum; 2750 int i; 2751 2752 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2753 *buf = iha_se2_rd(sc, i); 2754 chksum += *buf++; 2755 } 2756 *buf = iha_se2_rd(sc, 31); /* read checksum from EEPROM */ 2757 2758 chksum &= 0x0000ffff; /* lower 16 bits */ 2759 2760 return (eeprom->signature == EEP_SIGNATURE) && 2761 (eeprom->checksum == chksum); 2762 } 2763 2764 /* 2765 * iha_se2_instr - write an octet to serial E2PROM one bit at a time 2766 */ 2767 static void 2768 iha_se2_instr(struct iha_softc *sc, int instr) 2769 { 2770 bus_space_tag_t iot = sc->sc_iot; 2771 bus_space_handle_t ioh = sc->sc_ioh; 2772 int b, i; 2773 2774 b = NVRCS | NVRDO; /* Write the start bit (== 1) */ 2775 2776 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2777 EEP_WAIT(); 2778 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2779 EEP_WAIT(); 2780 2781 for (i = 8; i > 0; i--) { 2782 if (instr & (1 << (i - 1))) 2783 b = NVRCS | NVRDO; /* Write a 1 bit */ 2784 else 2785 b = NVRCS; /* Write a 0 bit */ 2786 2787 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2788 EEP_WAIT(); 2789 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2790 EEP_WAIT(); 2791 } 2792 2793 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2794 } 2795
Indexes created Sun Sep 28 07:09:56 GMT 2025