iha.c revision 1.26
1 /* $NetBSD: iha.c,v 1.26 2004/12/07 14:48:58 thorpej Exp $ */ 2 3 /*- 4 * Device driver for the INI-9XXXU/UW or INIC-940/950 PCI SCSI Controller. 5 * 6 * Written for 386bsd and FreeBSD by 7 * Winston Hung <winstonh (at) initio.com> 8 * 9 * Copyright (c) 1997-1999 Initio Corp. 10 * Copyright (c) 2000, 2001 Ken Westerback 11 * Copyright (c) 2001, 2002 Izumi Tsutsui 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer, 19 * without modification, immediately at the beginning of the file. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 32 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Ported to NetBSD by Izumi Tsutsui <tsutsui (at) ceres.dti.ne.jp> from OpenBSD: 38 * $OpenBSD: iha.c,v 1.3 2001/02/20 00:47:33 krw Exp $ 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: iha.c,v 1.26 2004/12/07 14:48:58 thorpej Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/buf.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsiconf.h> 59 #include <dev/scsipi/scsi_message.h> 60 61 #include <dev/ic/ihareg.h> 62 #include <dev/ic/ihavar.h> 63 64 /* 65 * SCSI Rate Table, indexed by FLAG_SCSI_RATE field of 66 * tcs flags. 67 */ 68 static const u_int8_t iha_rate_tbl[] = { 69 /* fast 20 */ 70 /* nanosecond divide by 4 */ 71 12, /* 50ns, 20M */ 72 18, /* 75ns, 13.3M */ 73 25, /* 100ns, 10M */ 74 31, /* 125ns, 8M */ 75 37, /* 150ns, 6.6M */ 76 43, /* 175ns, 5.7M */ 77 50, /* 200ns, 5M */ 78 62 /* 250ns, 4M */ 79 }; 80 #define IHA_MAX_PERIOD 62 81 82 #ifdef notused 83 static u_int16_t eeprom_default[EEPROM_SIZE] = { 84 /* -- Header ------------------------------------ */ 85 /* signature */ 86 EEP_SIGNATURE, 87 /* size, revision */ 88 EEP_WORD(EEPROM_SIZE * 2, 0x01), 89 /* -- Host Adapter Structure -------------------- */ 90 /* model */ 91 0x0095, 92 /* model info, number of channel */ 93 EEP_WORD(0x00, 1), 94 /* BIOS config */ 95 EEP_BIOSCFG_DEFAULT, 96 /* host adapter config */ 97 0, 98 99 /* -- eeprom_adapter[0] ------------------------------- */ 100 /* ID, adapter config 1 */ 101 EEP_WORD(7, CFG_DEFAULT), 102 /* adapter config 2, number of targets */ 103 EEP_WORD(0x00, 8), 104 /* target flags */ 105 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 106 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 107 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 108 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 109 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 110 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 111 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 112 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 113 114 /* -- eeprom_adapter[1] ------------------------------- */ 115 /* ID, adapter config 1 */ 116 EEP_WORD(7, CFG_DEFAULT), 117 /* adapter config 2, number of targets */ 118 EEP_WORD(0x00, 8), 119 /* target flags */ 120 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 121 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 122 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 123 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 124 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 125 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 126 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 127 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 128 /* reserved[5] */ 129 0, 0, 0, 0, 0, 130 /* checksum */ 131 0 132 }; 133 #endif 134 135 static void iha_append_free_scb(struct iha_softc *, struct iha_scb *); 136 static void iha_append_done_scb(struct iha_softc *, struct iha_scb *, u_int8_t); 137 static __inline struct iha_scb *iha_pop_done_scb(struct iha_softc *); 138 139 static struct iha_scb *iha_find_pend_scb(struct iha_softc *); 140 static __inline void iha_append_pend_scb(struct iha_softc *, struct iha_scb *); 141 static __inline void iha_push_pend_scb(struct iha_softc *, struct iha_scb *); 142 static __inline void iha_del_pend_scb(struct iha_softc *, struct iha_scb *); 143 static __inline void iha_mark_busy_scb(struct iha_scb *); 144 145 static __inline void iha_set_ssig(struct iha_softc *, u_int8_t, u_int8_t); 146 147 static int iha_alloc_sglist(struct iha_softc *); 148 149 static void iha_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 150 void *); 151 static void iha_update_xfer_mode(struct iha_softc *, int); 152 153 static void iha_reset_scsi_bus(struct iha_softc *); 154 static void iha_reset_chip(struct iha_softc *); 155 static void iha_reset_dma(struct iha_softc *); 156 static void iha_reset_tcs(struct tcs *, u_int8_t); 157 158 static void iha_main(struct iha_softc *); 159 static void iha_scsi(struct iha_softc *); 160 static void iha_select(struct iha_softc *, struct iha_scb *, u_int8_t); 161 static int iha_wait(struct iha_softc *, u_int8_t); 162 163 static void iha_exec_scb(struct iha_softc *, struct iha_scb *); 164 static void iha_done_scb(struct iha_softc *, struct iha_scb *); 165 static int iha_push_sense_request(struct iha_softc *, struct iha_scb *); 166 167 static void iha_timeout(void *); 168 static void iha_abort_xs(struct iha_softc *, struct scsipi_xfer *, u_int8_t); 169 static u_int8_t iha_data_over_run(struct iha_scb *); 170 171 static int iha_next_state(struct iha_softc *); 172 static int iha_state_1(struct iha_softc *); 173 static int iha_state_2(struct iha_softc *); 174 static int iha_state_3(struct iha_softc *); 175 static int iha_state_4(struct iha_softc *); 176 static int iha_state_5(struct iha_softc *); 177 static int iha_state_6(struct iha_softc *); 178 static int iha_state_8(struct iha_softc *); 179 180 static int iha_xfer_data(struct iha_softc *, struct iha_scb *, int); 181 static int iha_xpad_in(struct iha_softc *); 182 static int iha_xpad_out(struct iha_softc *); 183 184 static int iha_status_msg(struct iha_softc *); 185 static void iha_busfree(struct iha_softc *); 186 static int iha_resel(struct iha_softc *); 187 188 static int iha_msgin(struct iha_softc *); 189 static int iha_msgin_extended(struct iha_softc *); 190 static int iha_msgin_sdtr(struct iha_softc *); 191 static int iha_msgin_ignore_wid_resid(struct iha_softc *); 192 193 static int iha_msgout(struct iha_softc *, u_int8_t); 194 static void iha_msgout_abort(struct iha_softc *, u_int8_t); 195 static int iha_msgout_reject(struct iha_softc *); 196 static int iha_msgout_extended(struct iha_softc *); 197 static int iha_msgout_wdtr(struct iha_softc *); 198 static int iha_msgout_sdtr(struct iha_softc *); 199 200 static void iha_wide_done(struct iha_softc *); 201 static void iha_sync_done(struct iha_softc *); 202 203 static void iha_bad_seq(struct iha_softc *); 204 205 static void iha_read_eeprom(struct iha_softc *, struct iha_eeprom *); 206 static int iha_se2_rd_all(struct iha_softc *, u_int16_t *); 207 static void iha_se2_instr(struct iha_softc *, int); 208 static u_int16_t iha_se2_rd(struct iha_softc *, int); 209 #ifdef notused 210 static void iha_se2_update_all(struct iha_softc *); 211 static void iha_se2_wr(struct iha_softc *, int, u_int16_t); 212 #endif 213 214 /* 215 * iha_append_free_scb - append the supplied SCB to the tail of the 216 * sc_freescb queue after clearing and resetting 217 * everything possible. 218 */ 219 static void 220 iha_append_free_scb(struct iha_softc *sc, struct iha_scb *scb) 221 { 222 int s; 223 224 s = splbio(); 225 226 if (scb == sc->sc_actscb) 227 sc->sc_actscb = NULL; 228 229 scb->status = STATUS_QUEUED; 230 scb->ha_stat = HOST_OK; 231 scb->ta_stat = SCSI_OK; 232 233 scb->nextstat = 0; 234 scb->scb_tagmsg = 0; 235 236 scb->xs = NULL; 237 scb->tcs = NULL; 238 239 /* 240 * scb_tagid, sg_addr, sglist 241 * SCB_SensePtr are set at initialization 242 * and never change 243 */ 244 245 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 246 247 splx(s); 248 } 249 250 static void 251 iha_append_done_scb(struct iha_softc *sc, struct iha_scb *scb, u_int8_t hastat) 252 { 253 struct tcs *tcs; 254 int s; 255 256 s = splbio(); 257 258 if (scb->xs != NULL) 259 callout_stop(&scb->xs->xs_callout); 260 261 if (scb == sc->sc_actscb) 262 sc->sc_actscb = NULL; 263 264 tcs = scb->tcs; 265 266 if (scb->scb_tagmsg != 0) { 267 if (tcs->tagcnt) 268 tcs->tagcnt--; 269 } else if (tcs->ntagscb == scb) 270 tcs->ntagscb = NULL; 271 272 scb->status = STATUS_QUEUED; 273 scb->ha_stat = hastat; 274 275 TAILQ_INSERT_TAIL(&sc->sc_donescb, scb, chain); 276 277 splx(s); 278 } 279 280 static __inline struct iha_scb * 281 iha_pop_done_scb(struct iha_softc *sc) 282 { 283 struct iha_scb *scb; 284 int s; 285 286 s = splbio(); 287 288 scb = TAILQ_FIRST(&sc->sc_donescb); 289 290 if (scb != NULL) { 291 scb->status = STATUS_RENT; 292 TAILQ_REMOVE(&sc->sc_donescb, scb, chain); 293 } 294 295 splx(s); 296 297 return (scb); 298 } 299 300 /* 301 * iha_find_pend_scb - scan the pending queue for a SCB that can be 302 * processed immediately. Return NULL if none found 303 * and a pointer to the SCB if one is found. If there 304 * is an active SCB, return NULL! 305 */ 306 static struct iha_scb * 307 iha_find_pend_scb(struct iha_softc *sc) 308 { 309 struct iha_scb *scb; 310 struct tcs *tcs; 311 int s; 312 313 s = splbio(); 314 315 if (sc->sc_actscb != NULL) 316 scb = NULL; 317 318 else 319 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) { 320 if ((scb->xs->xs_control & XS_CTL_RESET) != 0) 321 /* ALWAYS willing to reset a device */ 322 break; 323 324 tcs = scb->tcs; 325 326 if ((scb->scb_tagmsg) != 0) { 327 /* 328 * A Tagged I/O. OK to start If no 329 * non-tagged I/O is active on the same 330 * target 331 */ 332 if (tcs->ntagscb == NULL) 333 break; 334 335 } else if (scb->cmd[0] == REQUEST_SENSE) { 336 /* 337 * OK to do a non-tagged request sense 338 * even if a non-tagged I/O has been 339 * started, 'cuz we don't allow any 340 * disconnect during a request sense op 341 */ 342 break; 343 344 } else if (tcs->tagcnt == 0) { 345 /* 346 * No tagged I/O active on this target, 347 * ok to start a non-tagged one if one 348 * is not already active 349 */ 350 if (tcs->ntagscb == NULL) 351 break; 352 } 353 } 354 355 splx(s); 356 357 return (scb); 358 } 359 360 static __inline void 361 iha_append_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 362 { 363 /* ASSUMPTION: only called within a splbio()/splx() pair */ 364 365 if (scb == sc->sc_actscb) 366 sc->sc_actscb = NULL; 367 368 scb->status = STATUS_QUEUED; 369 370 TAILQ_INSERT_TAIL(&sc->sc_pendscb, scb, chain); 371 } 372 373 static __inline void 374 iha_push_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 375 { 376 int s; 377 378 s = splbio(); 379 380 if (scb == sc->sc_actscb) 381 sc->sc_actscb = NULL; 382 383 scb->status = STATUS_QUEUED; 384 385 TAILQ_INSERT_HEAD(&sc->sc_pendscb, scb, chain); 386 387 splx(s); 388 } 389 390 /* 391 * iha_del_pend_scb - remove scb from sc_pendscb 392 */ 393 static __inline void 394 iha_del_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 395 { 396 int s; 397 398 s = splbio(); 399 400 TAILQ_REMOVE(&sc->sc_pendscb, scb, chain); 401 402 splx(s); 403 } 404 405 static __inline void 406 iha_mark_busy_scb(struct iha_scb *scb) 407 { 408 int s; 409 410 s = splbio(); 411 412 scb->status = STATUS_BUSY; 413 414 if (scb->scb_tagmsg == 0) 415 scb->tcs->ntagscb = scb; 416 else 417 scb->tcs->tagcnt++; 418 419 splx(s); 420 } 421 422 /* 423 * iha_set_ssig - read the current scsi signal mask, then write a new 424 * one which turns off/on the specified signals. 425 */ 426 static __inline void 427 iha_set_ssig(struct iha_softc *sc, u_int8_t offsigs, u_int8_t onsigs) 428 { 429 bus_space_tag_t iot = sc->sc_iot; 430 bus_space_handle_t ioh = sc->sc_ioh; 431 u_int8_t currsigs; 432 433 currsigs = bus_space_read_1(iot, ioh, TUL_SSIGI); 434 bus_space_write_1(iot, ioh, TUL_SSIGO, (currsigs & ~offsigs) | onsigs); 435 } 436 437 /* 438 * iha_intr - the interrupt service routine for the iha driver 439 */ 440 int 441 iha_intr(void *arg) 442 { 443 bus_space_tag_t iot; 444 bus_space_handle_t ioh; 445 struct iha_softc *sc; 446 int s; 447 448 sc = (struct iha_softc *)arg; 449 iot = sc->sc_iot; 450 ioh = sc->sc_ioh; 451 452 if ((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 453 return (0); 454 455 s = splbio(); /* XXX - Or are interrupts off when ISR's are called? */ 456 457 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 458 /* XXX - need these inside a splbio()/splx()? */ 459 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 460 sc->sc_semaph = SEMAPH_IN_MAIN; 461 462 iha_main(sc); 463 464 sc->sc_semaph = ~SEMAPH_IN_MAIN; 465 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 466 } 467 468 splx(s); 469 470 return (1); 471 } 472 473 void 474 iha_attach(struct iha_softc *sc) 475 { 476 bus_space_tag_t iot = sc->sc_iot; 477 bus_space_handle_t ioh = sc->sc_ioh; 478 struct iha_scb *scb; 479 struct iha_eeprom eeprom; 480 struct eeprom_adapter *conf; 481 int i, error, reg; 482 483 iha_read_eeprom(sc, &eeprom); 484 485 conf = &eeprom.adapter[0]; 486 487 /* 488 * fill in the rest of the iha_softc fields 489 */ 490 sc->sc_id = CFG_ID(conf->config1); 491 sc->sc_semaph = ~SEMAPH_IN_MAIN; 492 sc->sc_status0 = 0; 493 sc->sc_actscb = NULL; 494 495 TAILQ_INIT(&sc->sc_freescb); 496 TAILQ_INIT(&sc->sc_pendscb); 497 TAILQ_INIT(&sc->sc_donescb); 498 error = iha_alloc_sglist(sc); 499 if (error != 0) { 500 printf(": cannot allocate sglist\n"); 501 return; 502 } 503 504 sc->sc_scb = malloc(sizeof(struct iha_scb) * IHA_MAX_SCB, 505 M_DEVBUF, M_NOWAIT|M_ZERO); 506 if (sc->sc_scb == NULL) { 507 printf(": cannot allocate SCB\n"); 508 return; 509 } 510 511 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) { 512 scb->scb_tagid = i; 513 scb->sgoffset = IHA_SG_SIZE * i; 514 scb->sglist = sc->sc_sglist + IHA_MAX_SG_ENTRIES * i; 515 scb->sg_addr = 516 sc->sc_dmamap->dm_segs[0].ds_addr + scb->sgoffset; 517 518 error = bus_dmamap_create(sc->sc_dmat, 519 MAXPHYS, IHA_MAX_SG_ENTRIES, MAXPHYS, 0, 520 BUS_DMA_NOWAIT, &scb->dmap); 521 522 if (error != 0) { 523 printf(": couldn't create SCB DMA map, error = %d\n", 524 error); 525 return; 526 } 527 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 528 } 529 530 /* Mask all the interrupts */ 531 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 532 533 /* Stop any I/O and reset the scsi module */ 534 iha_reset_dma(sc); 535 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSMOD); 536 537 /* Program HBA's SCSI ID */ 538 bus_space_write_1(iot, ioh, TUL_SID, sc->sc_id << 4); 539 540 /* 541 * Configure the channel as requested by the NVRAM settings read 542 * by iha_read_eeprom() above. 543 */ 544 545 sc->sc_sconf1 = SCONFIG0DEFAULT; 546 if ((conf->config1 & CFG_EN_PAR) != 0) 547 sc->sc_sconf1 |= SPCHK; 548 bus_space_write_1(iot, ioh, TUL_SCONFIG0, sc->sc_sconf1); 549 550 /* set selection time out 250 ms */ 551 bus_space_write_1(iot, ioh, TUL_STIMO, STIMO_250MS); 552 553 /* Enable desired SCSI termination configuration read from eeprom */ 554 reg = 0; 555 if (conf->config1 & CFG_ACT_TERM1) 556 reg |= ENTMW; 557 if (conf->config1 & CFG_ACT_TERM2) 558 reg |= ENTM; 559 bus_space_write_1(iot, ioh, TUL_DCTRL0, reg); 560 561 reg = bus_space_read_1(iot, ioh, TUL_GCTRL1) & ~ATDEN; 562 if (conf->config1 & CFG_AUTO_TERM) 563 reg |= ATDEN; 564 bus_space_write_1(iot, ioh, TUL_GCTRL1, reg); 565 566 for (i = 0; i < IHA_MAX_TARGETS / 2; i++) { 567 sc->sc_tcs[i * 2 ].flags = EEP_LBYTE(conf->tflags[i]); 568 sc->sc_tcs[i * 2 + 1].flags = EEP_HBYTE(conf->tflags[i]); 569 iha_reset_tcs(&sc->sc_tcs[i * 2 ], sc->sc_sconf1); 570 iha_reset_tcs(&sc->sc_tcs[i * 2 + 1], sc->sc_sconf1); 571 } 572 573 iha_reset_chip(sc); 574 bus_space_write_1(iot, ioh, TUL_SIEN, ALL_INTERRUPTS); 575 576 /* 577 * fill in the adapter. 578 */ 579 sc->sc_adapter.adapt_dev = &sc->sc_dev; 580 sc->sc_adapter.adapt_nchannels = 1; 581 sc->sc_adapter.adapt_openings = IHA_MAX_SCB; 582 sc->sc_adapter.adapt_max_periph = IHA_MAX_SCB; 583 sc->sc_adapter.adapt_ioctl = NULL; 584 sc->sc_adapter.adapt_minphys = minphys; 585 sc->sc_adapter.adapt_request = iha_scsipi_request; 586 587 /* 588 * fill in the channel. 589 */ 590 sc->sc_channel.chan_adapter = &sc->sc_adapter; 591 sc->sc_channel.chan_bustype = &scsi_bustype; 592 sc->sc_channel.chan_channel = 0; 593 sc->sc_channel.chan_ntargets = CFG_TARGET(conf->config2); 594 sc->sc_channel.chan_nluns = 8; 595 sc->sc_channel.chan_id = sc->sc_id; 596 597 /* 598 * Now try to attach all the sub devices. 599 */ 600 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 601 } 602 603 /* 604 * iha_alloc_sglist - allocate and map sglist for SCB's 605 */ 606 static int 607 iha_alloc_sglist(struct iha_softc *sc) 608 { 609 bus_dma_segment_t seg; 610 int error, rseg; 611 612 /* 613 * Allocate DMA-safe memory for the SCB's sglist 614 */ 615 if ((error = bus_dmamem_alloc(sc->sc_dmat, 616 IHA_SG_SIZE * IHA_MAX_SCB, 617 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 618 printf(": unable to allocate sglist, error = %d\n", error); 619 return (error); 620 } 621 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 622 IHA_SG_SIZE * IHA_MAX_SCB, (caddr_t *)&sc->sc_sglist, 623 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 624 printf(": unable to map sglist, error = %d\n", error); 625 return (error); 626 } 627 628 /* 629 * Create and load the DMA map used for the SCBs 630 */ 631 if ((error = bus_dmamap_create(sc->sc_dmat, 632 IHA_SG_SIZE * IHA_MAX_SCB, 1, IHA_SG_SIZE * IHA_MAX_SCB, 633 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 634 printf(": unable to create control DMA map, error = %d\n", 635 error); 636 return (error); 637 } 638 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 639 sc->sc_sglist, IHA_SG_SIZE * IHA_MAX_SCB, 640 NULL, BUS_DMA_NOWAIT)) != 0) { 641 printf(": unable to load control DMA map, error = %d\n", error); 642 return (error); 643 } 644 645 memset(sc->sc_sglist, 0, IHA_SG_SIZE * IHA_MAX_SCB); 646 647 return (0); 648 } 649 650 void 651 iha_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 652 void *arg) 653 { 654 struct scsipi_xfer *xs; 655 struct scsipi_periph *periph; 656 struct iha_scb *scb; 657 struct iha_softc *sc; 658 int error, s; 659 660 sc = (struct iha_softc *)chan->chan_adapter->adapt_dev; 661 662 switch (req) { 663 case ADAPTER_REQ_RUN_XFER: 664 xs = arg; 665 periph = xs->xs_periph; 666 667 /* XXX This size isn't actually a hardware restriction. */ 668 if (xs->cmdlen > sizeof(scb->cmd) || 669 periph->periph_target >= IHA_MAX_TARGETS) { 670 xs->error = XS_DRIVER_STUFFUP; 671 scsipi_done(xs); 672 return; 673 } 674 675 s = splbio(); 676 scb = TAILQ_FIRST(&sc->sc_freescb); 677 if (scb != NULL) { 678 scb->status = STATUS_RENT; 679 TAILQ_REMOVE(&sc->sc_freescb, scb, chain); 680 } 681 #ifdef DIAGNOSTIC 682 else { 683 scsipi_printaddr(periph); 684 printf("unable to allocate scb\n"); 685 panic("iha_scsipi_request"); 686 } 687 #endif 688 splx(s); 689 690 scb->target = periph->periph_target; 691 scb->lun = periph->periph_lun; 692 scb->tcs = &sc->sc_tcs[scb->target]; 693 scb->scb_id = MSG_IDENTIFY(periph->periph_lun, 694 (xs->xs_control & XS_CTL_REQSENSE) == 0); 695 696 scb->xs = xs; 697 scb->cmdlen = xs->cmdlen; 698 memcpy(&scb->cmd, xs->cmd, xs->cmdlen); 699 scb->buflen = xs->datalen; 700 scb->flags = 0; 701 if (xs->xs_control & XS_CTL_DATA_OUT) 702 scb->flags |= FLAG_DATAOUT; 703 if (xs->xs_control & XS_CTL_DATA_IN) 704 scb->flags |= FLAG_DATAIN; 705 706 if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 707 error = bus_dmamap_load(sc->sc_dmat, scb->dmap, 708 xs->data, scb->buflen, NULL, 709 ((xs->xs_control & XS_CTL_NOSLEEP) ? 710 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 711 BUS_DMA_STREAMING | 712 ((scb->flags & FLAG_DATAIN) ? 713 BUS_DMA_READ : BUS_DMA_WRITE)); 714 715 if (error) { 716 printf("%s: error %d loading DMA map\n", 717 sc->sc_dev.dv_xname, error); 718 iha_append_free_scb(sc, scb); 719 xs->error = XS_DRIVER_STUFFUP; 720 scsipi_done(xs); 721 return; 722 } 723 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 724 0, scb->dmap->dm_mapsize, 725 (scb->flags & FLAG_DATAIN) ? 726 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 727 } 728 729 iha_exec_scb(sc, scb); 730 return; 731 732 case ADAPTER_REQ_GROW_RESOURCES: 733 return; /* XXX */ 734 735 case ADAPTER_REQ_SET_XFER_MODE: 736 { 737 struct tcs *tcs; 738 struct scsipi_xfer_mode *xm = arg; 739 740 tcs = &sc->sc_tcs[xm->xm_target]; 741 742 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 743 (tcs->flags & FLAG_NO_WIDE) == 0) 744 tcs->flags &= ~(FLAG_WIDE_DONE|FLAG_SYNC_DONE); 745 746 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 747 (tcs->flags & FLAG_NO_SYNC) == 0) 748 tcs->flags &= ~FLAG_SYNC_DONE; 749 750 /* 751 * If we're not going to negotiate, send the 752 * notification now, since it won't happen later. 753 */ 754 if ((tcs->flags & (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) == 755 (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) 756 iha_update_xfer_mode(sc, xm->xm_target); 757 758 return; 759 } 760 } 761 } 762 763 void 764 iha_update_xfer_mode(struct iha_softc *sc, int target) 765 { 766 struct tcs *tcs = &sc->sc_tcs[target]; 767 struct scsipi_xfer_mode xm; 768 769 xm.xm_target = target; 770 xm.xm_mode = 0; 771 xm.xm_period = 0; 772 xm.xm_offset = 0; 773 774 if (tcs->syncm & PERIOD_WIDE_SCSI) 775 xm.xm_mode |= PERIPH_CAP_WIDE16; 776 777 if (tcs->period) { 778 xm.xm_mode |= PERIPH_CAP_SYNC; 779 xm.xm_period = tcs->period; 780 xm.xm_offset = tcs->offset; 781 } 782 783 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 784 } 785 786 static void 787 iha_reset_scsi_bus(struct iha_softc *sc) 788 { 789 struct iha_scb *scb; 790 struct tcs *tcs; 791 int i, s; 792 793 s = splbio(); 794 795 iha_reset_dma(sc); 796 797 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 798 switch (scb->status) { 799 case STATUS_BUSY: 800 iha_append_done_scb(sc, scb, HOST_SCSI_RST); 801 break; 802 803 case STATUS_SELECT: 804 iha_push_pend_scb(sc, scb); 805 break; 806 807 default: 808 break; 809 } 810 811 for (i = 0, tcs = sc->sc_tcs; i < IHA_MAX_TARGETS; i++, tcs++) 812 iha_reset_tcs(tcs, sc->sc_sconf1); 813 814 splx(s); 815 } 816 817 void 818 iha_reset_chip(struct iha_softc *sc) 819 { 820 bus_space_tag_t iot = sc->sc_iot; 821 bus_space_handle_t ioh = sc->sc_ioh; 822 823 /* reset tulip chip */ 824 825 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSCSI); 826 827 do { 828 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 829 } while ((sc->sc_sistat & SRSTD) == 0); 830 831 iha_set_ssig(sc, 0, 0); 832 833 bus_space_read_1(iot, ioh, TUL_SISTAT); /* Clear any active interrupt*/ 834 } 835 836 /* 837 * iha_reset_dma - abort any active DMA xfer, reset tulip FIFO. 838 */ 839 static void 840 iha_reset_dma(struct iha_softc *sc) 841 { 842 bus_space_tag_t iot = sc->sc_iot; 843 bus_space_handle_t ioh = sc->sc_ioh; 844 845 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 846 /* if DMA xfer is pending, abort DMA xfer */ 847 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 848 /* wait Abort DMA xfer done */ 849 while ((bus_space_read_1(iot, ioh, TUL_ISTUS0) & DABT) == 0) 850 ; 851 } 852 853 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 854 } 855 856 /* 857 * iha_reset_tcs - reset the target control structure pointed 858 * to by tcs to default values. tcs flags 859 * only has the negotiation done bits reset as 860 * the other bits are fixed at initialization. 861 */ 862 static void 863 iha_reset_tcs(struct tcs *tcs, u_int8_t config0) 864 { 865 866 tcs->flags &= ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 867 tcs->period = 0; 868 tcs->offset = 0; 869 tcs->tagcnt = 0; 870 tcs->ntagscb = NULL; 871 tcs->syncm = 0; 872 tcs->sconfig0 = config0; 873 } 874 875 /* 876 * iha_main - process the active SCB, taking one off pending and making it 877 * active if necessary, and any done SCB's created as 878 * a result until there are no interrupts pending and no pending 879 * SCB's that can be started. 880 */ 881 static void 882 iha_main(struct iha_softc *sc) 883 { 884 bus_space_tag_t iot = sc->sc_iot; 885 bus_space_handle_t ioh =sc->sc_ioh; 886 struct iha_scb *scb; 887 888 for (;;) { 889 iha_scsi(sc); 890 891 while ((scb = iha_pop_done_scb(sc)) != NULL) 892 iha_done_scb(sc, scb); 893 894 /* 895 * If there are no interrupts pending, or we can't start 896 * a pending sc, break out of the for(;;). Otherwise 897 * continue the good work with another call to 898 * iha_scsi(). 899 */ 900 if (((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 901 && (iha_find_pend_scb(sc) == NULL)) 902 break; 903 } 904 } 905 906 /* 907 * iha_scsi - service any outstanding interrupts. If there are none, try to 908 * start another SCB currently in the pending queue. 909 */ 910 static void 911 iha_scsi(struct iha_softc *sc) 912 { 913 bus_space_tag_t iot = sc->sc_iot; 914 bus_space_handle_t ioh = sc->sc_ioh; 915 struct iha_scb *scb; 916 struct tcs *tcs; 917 u_int8_t stat; 918 919 /* service pending interrupts asap */ 920 921 stat = bus_space_read_1(iot, ioh, TUL_STAT0); 922 if ((stat & INTPD) != 0) { 923 sc->sc_status0 = stat; 924 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 925 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 926 927 sc->sc_phase = sc->sc_status0 & PH_MASK; 928 929 if ((sc->sc_sistat & SRSTD) != 0) { 930 iha_reset_scsi_bus(sc); 931 return; 932 } 933 934 if ((sc->sc_sistat & RSELED) != 0) { 935 iha_resel(sc); 936 return; 937 } 938 939 if ((sc->sc_sistat & (STIMEO | DISCD)) != 0) { 940 iha_busfree(sc); 941 return; 942 } 943 944 if ((sc->sc_sistat & (SCMDN | SBSRV)) != 0) { 945 iha_next_state(sc); 946 return; 947 } 948 949 if ((sc->sc_sistat & SELED) != 0) 950 iha_set_ssig(sc, 0, 0); 951 } 952 953 /* 954 * There were no interrupts pending which required action elsewhere, so 955 * see if it is possible to start the selection phase on a pending SCB 956 */ 957 if ((scb = iha_find_pend_scb(sc)) == NULL) 958 return; 959 960 tcs = scb->tcs; 961 962 /* program HBA's SCSI ID & target SCSI ID */ 963 bus_space_write_1(iot, ioh, TUL_SID, (sc->sc_id << 4) | scb->target); 964 965 if ((scb->xs->xs_control & XS_CTL_RESET) == 0) { 966 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 967 968 if ((tcs->flags & FLAG_NO_NEG_SYNC) == 0 || 969 (tcs->flags & FLAG_NO_NEG_WIDE) == 0) 970 iha_select(sc, scb, SELATNSTOP); 971 972 else if (scb->scb_tagmsg != 0) 973 iha_select(sc, scb, SEL_ATN3); 974 975 else 976 iha_select(sc, scb, SEL_ATN); 977 978 } else { 979 iha_select(sc, scb, SELATNSTOP); 980 scb->nextstat = 8; 981 } 982 983 if ((scb->xs->xs_control & XS_CTL_POLL) != 0) { 984 int timeout; 985 for (timeout = scb->xs->timeout; timeout > 0; timeout--) { 986 if (iha_wait(sc, NO_OP) == -1) 987 break; 988 if (iha_next_state(sc) == -1) 989 break; 990 delay(1000); /* Only happens in boot, so it's ok */ 991 } 992 993 /* 994 * Since done queue processing not done until AFTER this 995 * function returns, scb is on the done queue, not 996 * the free queue at this point and still has valid data 997 * 998 * Conversely, xs->error has not been set yet 999 */ 1000 if (timeout == 0) 1001 iha_timeout(scb); 1002 } 1003 } 1004 1005 static void 1006 iha_select(struct iha_softc *sc, struct iha_scb *scb, u_int8_t select_type) 1007 { 1008 bus_space_tag_t iot = sc->sc_iot; 1009 bus_space_handle_t ioh = sc->sc_ioh; 1010 1011 switch (select_type) { 1012 case SEL_ATN: 1013 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1014 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1015 scb->cmd, scb->cmdlen); 1016 1017 scb->nextstat = 2; 1018 break; 1019 1020 case SELATNSTOP: 1021 scb->nextstat = 1; 1022 break; 1023 1024 case SEL_ATN3: 1025 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1026 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagmsg); 1027 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagid); 1028 1029 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, scb->cmd, 1030 scb->cmdlen); 1031 1032 scb->nextstat = 2; 1033 break; 1034 1035 default: 1036 printf("[debug] iha_select() - unknown select type = 0x%02x\n", 1037 select_type); 1038 return; 1039 } 1040 1041 iha_del_pend_scb(sc, scb); 1042 scb->status = STATUS_SELECT; 1043 1044 sc->sc_actscb = scb; 1045 1046 bus_space_write_1(iot, ioh, TUL_SCMD, select_type); 1047 } 1048 1049 /* 1050 * iha_wait - wait for an interrupt to service or a SCSI bus phase change 1051 * after writing the supplied command to the tulip chip. If 1052 * the command is NO_OP, skip the command writing. 1053 */ 1054 static int 1055 iha_wait(struct iha_softc *sc, u_int8_t cmd) 1056 { 1057 bus_space_tag_t iot = sc->sc_iot; 1058 bus_space_handle_t ioh = sc->sc_ioh; 1059 1060 if (cmd != NO_OP) 1061 bus_space_write_1(iot, ioh, TUL_SCMD, cmd); 1062 1063 /* 1064 * Have to do this here, in addition to in iha_isr, because 1065 * interrupts might be turned off when we get here. 1066 */ 1067 do { 1068 sc->sc_status0 = bus_space_read_1(iot, ioh, TUL_STAT0); 1069 } while ((sc->sc_status0 & INTPD) == 0); 1070 1071 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 1072 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 1073 1074 sc->sc_phase = sc->sc_status0 & PH_MASK; 1075 1076 if ((sc->sc_sistat & SRSTD) != 0) { 1077 /* SCSI bus reset interrupt */ 1078 iha_reset_scsi_bus(sc); 1079 return (-1); 1080 } 1081 1082 if ((sc->sc_sistat & RSELED) != 0) 1083 /* Reselection interrupt */ 1084 return (iha_resel(sc)); 1085 1086 if ((sc->sc_sistat & STIMEO) != 0) { 1087 /* selected/reselected timeout interrupt */ 1088 iha_busfree(sc); 1089 return (-1); 1090 } 1091 1092 if ((sc->sc_sistat & DISCD) != 0) { 1093 /* BUS disconnection interrupt */ 1094 if ((sc->sc_flags & FLAG_EXPECT_DONE_DISC) != 0) { 1095 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1096 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 1097 SCONFIG0DEFAULT); 1098 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1099 iha_append_done_scb(sc, sc->sc_actscb, HOST_OK); 1100 sc->sc_flags &= ~FLAG_EXPECT_DONE_DISC; 1101 1102 } else if ((sc->sc_flags & FLAG_EXPECT_DISC) != 0) { 1103 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1104 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 1105 SCONFIG0DEFAULT); 1106 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1107 sc->sc_actscb = NULL; 1108 sc->sc_flags &= ~FLAG_EXPECT_DISC; 1109 1110 } else 1111 iha_busfree(sc); 1112 1113 return (-1); 1114 } 1115 1116 return (sc->sc_phase); 1117 } 1118 1119 static void 1120 iha_exec_scb(struct iha_softc *sc, struct iha_scb *scb) 1121 { 1122 bus_space_tag_t iot; 1123 bus_space_handle_t ioh; 1124 bus_dmamap_t dm; 1125 struct scsipi_xfer *xs = scb->xs; 1126 int nseg, s; 1127 1128 dm = scb->dmap; 1129 nseg = dm->dm_nsegs; 1130 1131 if (nseg > 1) { 1132 struct iha_sg_element *sg = scb->sglist; 1133 int i; 1134 1135 for (i = 0; i < nseg; i++) { 1136 sg[i].sg_len = htole32(dm->dm_segs[i].ds_len); 1137 sg[i].sg_addr = htole32(dm->dm_segs[i].ds_addr); 1138 } 1139 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1140 scb->sgoffset, IHA_SG_SIZE, 1141 BUS_DMASYNC_PREWRITE); 1142 1143 scb->flags |= FLAG_SG; 1144 scb->sg_size = scb->sg_max = nseg; 1145 scb->sg_index = 0; 1146 1147 scb->bufaddr = scb->sg_addr; 1148 } else 1149 scb->bufaddr = dm->dm_segs[0].ds_addr; 1150 1151 if ((xs->xs_control & XS_CTL_POLL) == 0) { 1152 int timeout = mstohz(xs->timeout); 1153 if (timeout == 0) 1154 timeout = 1; 1155 callout_reset(&xs->xs_callout, timeout, iha_timeout, scb); 1156 } 1157 1158 s = splbio(); 1159 1160 if (((scb->xs->xs_control & XS_RESET) != 0) || 1161 (scb->cmd[0] == REQUEST_SENSE)) 1162 iha_push_pend_scb(sc, scb); /* Insert SCB at head of Pend */ 1163 else 1164 iha_append_pend_scb(sc, scb); /* Append SCB to tail of Pend */ 1165 1166 /* 1167 * Run through iha_main() to ensure something is active, if 1168 * only this new SCB. 1169 */ 1170 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 1171 iot = sc->sc_iot; 1172 ioh = sc->sc_ioh; 1173 1174 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 1175 sc->sc_semaph = SEMAPH_IN_MAIN; 1176 1177 splx(s); 1178 iha_main(sc); 1179 s = splbio(); 1180 1181 sc->sc_semaph = ~SEMAPH_IN_MAIN; 1182 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 1183 } 1184 1185 splx(s); 1186 } 1187 1188 /* 1189 * iha_done_scb - We have a scb which has been processed by the 1190 * adaptor, now we look to see how the operation went. 1191 */ 1192 static void 1193 iha_done_scb(struct iha_softc *sc, struct iha_scb *scb) 1194 { 1195 struct scsipi_xfer *xs = scb->xs; 1196 1197 if (xs != NULL) { 1198 /* Cancel the timeout. */ 1199 callout_stop(&xs->xs_callout); 1200 1201 if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 1202 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 1203 0, scb->dmap->dm_mapsize, 1204 (scb->flags & FLAG_DATAIN) ? 1205 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1206 bus_dmamap_unload(sc->sc_dmat, scb->dmap); 1207 } 1208 1209 xs->status = scb->ta_stat; 1210 1211 switch (scb->ha_stat) { 1212 case HOST_OK: 1213 switch (scb->ta_stat) { 1214 case SCSI_OK: 1215 case SCSI_CONDITION_MET: 1216 case SCSI_INTERM: 1217 case SCSI_INTERM_COND_MET: 1218 xs->resid = scb->buflen; 1219 xs->error = XS_NOERROR; 1220 if ((scb->flags & FLAG_RSENS) != 0) 1221 xs->error = XS_SENSE; 1222 break; 1223 1224 case SCSI_RESV_CONFLICT: 1225 case SCSI_BUSY: 1226 case SCSI_QUEUE_FULL: 1227 xs->error = XS_BUSY; 1228 break; 1229 1230 case SCSI_TERMINATED: 1231 case SCSI_ACA_ACTIVE: 1232 case SCSI_CHECK: 1233 scb->tcs->flags &= 1234 ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 1235 1236 if ((scb->flags & FLAG_RSENS) != 0 || 1237 iha_push_sense_request(sc, scb) != 0) { 1238 scb->flags &= ~FLAG_RSENS; 1239 printf("%s: request sense failed\n", 1240 sc->sc_dev.dv_xname); 1241 xs->error = XS_DRIVER_STUFFUP; 1242 break; 1243 } 1244 1245 xs->error = XS_SENSE; 1246 return; 1247 1248 default: 1249 xs->error = XS_DRIVER_STUFFUP; 1250 break; 1251 } 1252 break; 1253 1254 case HOST_SEL_TOUT: 1255 xs->error = XS_SELTIMEOUT; 1256 break; 1257 1258 case HOST_SCSI_RST: 1259 case HOST_DEV_RST: 1260 xs->error = XS_RESET; 1261 break; 1262 1263 case HOST_SPERR: 1264 printf("%s: SCSI Parity error detected\n", 1265 sc->sc_dev.dv_xname); 1266 xs->error = XS_DRIVER_STUFFUP; 1267 break; 1268 1269 case HOST_TIMED_OUT: 1270 xs->error = XS_TIMEOUT; 1271 break; 1272 1273 case HOST_DO_DU: 1274 case HOST_BAD_PHAS: 1275 default: 1276 xs->error = XS_DRIVER_STUFFUP; 1277 break; 1278 } 1279 1280 scsipi_done(xs); 1281 } 1282 1283 iha_append_free_scb(sc, scb); 1284 } 1285 1286 /* 1287 * iha_push_sense_request - obtain auto sense data by pushing the 1288 * SCB needing it back onto the pending 1289 * queue with a REQUEST_SENSE CDB. 1290 */ 1291 static int 1292 iha_push_sense_request(struct iha_softc *sc, struct iha_scb *scb) 1293 { 1294 struct scsipi_xfer *xs = scb->xs; 1295 struct scsipi_periph *periph = xs->xs_periph; 1296 struct scsipi_sense *ss = (struct scsipi_sense *)scb->cmd; 1297 int lun = periph->periph_lun; 1298 int err; 1299 1300 ss->opcode = REQUEST_SENSE; 1301 ss->byte2 = lun << SCSI_CMD_LUN_SHIFT; 1302 ss->unused[0] = ss->unused[1] = 0; 1303 ss->length = sizeof(struct scsipi_sense_data); 1304 ss->control = 0; 1305 1306 scb->flags = FLAG_RSENS | FLAG_DATAIN; 1307 1308 scb->scb_id &= ~MSG_IDENTIFY_DISCFLAG; 1309 1310 scb->scb_tagmsg = 0; 1311 scb->ta_stat = SCSI_OK; 1312 1313 scb->cmdlen = sizeof(struct scsipi_sense); 1314 scb->buflen = ss->length; 1315 1316 err = bus_dmamap_load(sc->sc_dmat, scb->dmap, 1317 &xs->sense.scsi_sense, scb->buflen, NULL, 1318 BUS_DMA_READ|BUS_DMA_NOWAIT); 1319 if (err != 0) { 1320 printf("iha_push_sense_request: cannot bus_dmamap_load()\n"); 1321 xs->error = XS_DRIVER_STUFFUP; 1322 return 1; 1323 } 1324 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 1325 0, scb->buflen, BUS_DMASYNC_PREREAD); 1326 1327 /* XXX What about queued command? */ 1328 iha_exec_scb(sc, scb); 1329 1330 return 0; 1331 } 1332 1333 static void 1334 iha_timeout(void *arg) 1335 { 1336 struct iha_scb *scb = (struct iha_scb *)arg; 1337 struct scsipi_xfer *xs = scb->xs; 1338 struct scsipi_periph *periph = xs->xs_periph; 1339 struct iha_softc *sc; 1340 1341 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1342 1343 if (xs == NULL) 1344 printf("[debug] iha_timeout called with xs == NULL\n"); 1345 1346 else { 1347 scsipi_printaddr(periph); 1348 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1349 1350 iha_abort_xs(sc, xs, HOST_TIMED_OUT); 1351 } 1352 } 1353 1354 /* 1355 * iha_abort_xs - find the SCB associated with the supplied xs and 1356 * stop all processing on it, moving it to the done 1357 * queue with the supplied host status value. 1358 */ 1359 static void 1360 iha_abort_xs(struct iha_softc *sc, struct scsipi_xfer *xs, u_int8_t hastat) 1361 { 1362 struct iha_scb *scb; 1363 int i, s; 1364 1365 s = splbio(); 1366 1367 /* Check the pending queue for the SCB pointing to xs */ 1368 1369 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) 1370 if (scb->xs == xs) { 1371 iha_del_pend_scb(sc, scb); 1372 iha_append_done_scb(sc, scb, hastat); 1373 splx(s); 1374 return; 1375 } 1376 1377 /* 1378 * If that didn't work, check all BUSY/SELECTING SCB's for one 1379 * pointing to xs 1380 */ 1381 1382 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1383 switch (scb->status) { 1384 case STATUS_BUSY: 1385 case STATUS_SELECT: 1386 if (scb->xs == xs) { 1387 iha_append_done_scb(sc, scb, hastat); 1388 splx(s); 1389 return; 1390 } 1391 break; 1392 default: 1393 break; 1394 } 1395 1396 splx(s); 1397 } 1398 1399 /* 1400 * iha_data_over_run - return HOST_OK for all SCSI opcodes where BufLen 1401 * is an 'Allocation Length'. All other SCSI opcodes 1402 * get HOST_DO_DU as they SHOULD have xferred all the 1403 * data requested. 1404 * 1405 * The list of opcodes using 'Allocation Length' was 1406 * found by scanning all the SCSI-3 T10 drafts. See 1407 * www.t10.org for the curious with a .pdf reader. 1408 */ 1409 static u_int8_t 1410 iha_data_over_run(struct iha_scb *scb) 1411 { 1412 switch (scb->cmd[0]) { 1413 case 0x03: /* Request Sense SPC-2 */ 1414 case 0x12: /* Inquiry SPC-2 */ 1415 case 0x1a: /* Mode Sense (6 byte version) SPC-2 */ 1416 case 0x1c: /* Receive Diagnostic Results SPC-2 */ 1417 case 0x23: /* Read Format Capacities MMC-2 */ 1418 case 0x29: /* Read Generation SBC */ 1419 case 0x34: /* Read Position SSC-2 */ 1420 case 0x37: /* Read Defect Data SBC */ 1421 case 0x3c: /* Read Buffer SPC-2 */ 1422 case 0x42: /* Read Sub Channel MMC-2 */ 1423 case 0x43: /* Read TOC/PMA/ATIP MMC */ 1424 1425 /* XXX - 2 with same opcode of 0x44? */ 1426 case 0x44: /* Read Header/Read Density Suprt MMC/SSC*/ 1427 1428 case 0x46: /* Get Configuration MMC-2 */ 1429 case 0x4a: /* Get Event/Status Notification MMC-2 */ 1430 case 0x4d: /* Log Sense SPC-2 */ 1431 case 0x51: /* Read Disc Information MMC */ 1432 case 0x52: /* Read Track Information MMC */ 1433 case 0x59: /* Read Master CUE MMC */ 1434 case 0x5a: /* Mode Sense (10 byte version) SPC-2 */ 1435 case 0x5c: /* Read Buffer Capacity MMC */ 1436 case 0x5e: /* Persistent Reserve In SPC-2 */ 1437 case 0x84: /* Receive Copy Results SPC-2 */ 1438 case 0xa0: /* Report LUNs SPC-2 */ 1439 case 0xa3: /* Various Report requests SBC-2/SCC-2*/ 1440 case 0xa4: /* Report Key MMC-2 */ 1441 case 0xad: /* Read DVD Structure MMC-2 */ 1442 case 0xb4: /* Read Element Status (Attached) SMC */ 1443 case 0xb5: /* Request Volume Element Address SMC */ 1444 case 0xb7: /* Read Defect Data (12 byte ver.) SBC */ 1445 case 0xb8: /* Read Element Status (Independ.) SMC */ 1446 case 0xba: /* Report Redundancy SCC-2 */ 1447 case 0xbd: /* Mechanism Status MMC */ 1448 case 0xbe: /* Report Basic Redundancy SCC-2 */ 1449 1450 return (HOST_OK); 1451 1452 default: 1453 return (HOST_DO_DU); 1454 } 1455 } 1456 1457 /* 1458 * iha_next_state - process the current SCB as requested in its 1459 * nextstat member. 1460 */ 1461 static int 1462 iha_next_state(struct iha_softc *sc) 1463 { 1464 1465 if (sc->sc_actscb == NULL) 1466 return (-1); 1467 1468 switch (sc->sc_actscb->nextstat) { 1469 case 1: 1470 if (iha_state_1(sc) == 3) 1471 goto state_3; 1472 break; 1473 1474 case 2: 1475 switch (iha_state_2(sc)) { 1476 case 3: 1477 goto state_3; 1478 case 4: 1479 goto state_4; 1480 default: 1481 break; 1482 } 1483 break; 1484 1485 case 3: 1486 state_3: 1487 if (iha_state_3(sc) == 4) 1488 goto state_4; 1489 break; 1490 1491 case 4: 1492 state_4: 1493 switch (iha_state_4(sc)) { 1494 case 0: 1495 return (0); 1496 case 6: 1497 goto state_6; 1498 default: 1499 break; 1500 } 1501 break; 1502 1503 case 5: 1504 switch (iha_state_5(sc)) { 1505 case 4: 1506 goto state_4; 1507 case 6: 1508 goto state_6; 1509 default: 1510 break; 1511 } 1512 break; 1513 1514 case 6: 1515 state_6: 1516 iha_state_6(sc); 1517 break; 1518 1519 case 8: 1520 iha_state_8(sc); 1521 break; 1522 1523 default: 1524 #ifdef IHA_DEBUG_STATE 1525 printf("[debug] -unknown state: %i-\n", 1526 sc->sc_actscb->nextstat); 1527 #endif 1528 iha_bad_seq(sc); 1529 break; 1530 } 1531 1532 return (-1); 1533 } 1534 1535 /* 1536 * iha_state_1 - selection is complete after a SELATNSTOP. If the target 1537 * has put the bus into MSG_OUT phase start wide/sync 1538 * negotiation. Otherwise clear the FIFO and go to state 3, 1539 * which will send the SCSI CDB to the target. 1540 */ 1541 static int 1542 iha_state_1(struct iha_softc *sc) 1543 { 1544 bus_space_tag_t iot = sc->sc_iot; 1545 bus_space_handle_t ioh = sc->sc_ioh; 1546 struct iha_scb *scb = sc->sc_actscb; 1547 struct tcs *tcs; 1548 int flags; 1549 1550 iha_mark_busy_scb(scb); 1551 1552 tcs = scb->tcs; 1553 1554 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 1555 1556 /* 1557 * If we are in PHASE_MSG_OUT, send 1558 * a) IDENT message (with tags if appropriate) 1559 * b) WDTR if the target is configured to negotiate wide xfers 1560 * ** OR ** 1561 * c) SDTR if the target is configured to negotiate sync xfers 1562 * but not wide ones 1563 * 1564 * If we are NOT, then the target is not asking for anything but 1565 * the data/command, so go straight to state 3. 1566 */ 1567 if (sc->sc_phase == PHASE_MSG_OUT) { 1568 bus_space_write_1(iot, ioh, TUL_SCTRL1, (ESBUSIN | EHRSL)); 1569 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1570 1571 if (scb->scb_tagmsg != 0) { 1572 bus_space_write_1(iot, ioh, TUL_SFIFO, 1573 scb->scb_tagmsg); 1574 bus_space_write_1(iot, ioh, TUL_SFIFO, 1575 scb->scb_tagid); 1576 } 1577 1578 flags = tcs->flags; 1579 if ((flags & FLAG_NO_NEG_WIDE) == 0) { 1580 if (iha_msgout_wdtr(sc) == -1) 1581 return (-1); 1582 } else if ((flags & FLAG_NO_NEG_SYNC) == 0) { 1583 if (iha_msgout_sdtr(sc) == -1) 1584 return (-1); 1585 } 1586 1587 } else { 1588 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1589 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1590 } 1591 1592 return (3); 1593 } 1594 1595 /* 1596 * iha_state_2 - selection is complete after a SEL_ATN or SEL_ATN3. If the SCSI 1597 * CDB has already been send, go to state 4 to start the data 1598 * xfer. Otherwise reset the FIFO and go to state 3, sending 1599 * the SCSI CDB. 1600 */ 1601 static int 1602 iha_state_2(struct iha_softc *sc) 1603 { 1604 bus_space_tag_t iot = sc->sc_iot; 1605 bus_space_handle_t ioh = sc->sc_ioh; 1606 struct iha_scb *scb = sc->sc_actscb; 1607 1608 iha_mark_busy_scb(scb); 1609 1610 bus_space_write_1(iot, ioh, TUL_SCONFIG0, scb->tcs->sconfig0); 1611 1612 if ((sc->sc_status1 & CPDNE) != 0) 1613 return (4); 1614 1615 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1616 1617 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1618 1619 return (3); 1620 } 1621 1622 /* 1623 * iha_state_3 - send the SCSI CDB to the target, processing any status 1624 * or other messages received until that is done or 1625 * abandoned. 1626 */ 1627 static int 1628 iha_state_3(struct iha_softc *sc) 1629 { 1630 bus_space_tag_t iot = sc->sc_iot; 1631 bus_space_handle_t ioh = sc->sc_ioh; 1632 struct iha_scb *scb = sc->sc_actscb; 1633 int flags; 1634 1635 for (;;) { 1636 switch (sc->sc_phase) { 1637 case PHASE_CMD_OUT: 1638 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1639 scb->cmd, scb->cmdlen); 1640 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1641 return (-1); 1642 else if (sc->sc_phase == PHASE_CMD_OUT) { 1643 iha_bad_seq(sc); 1644 return (-1); 1645 } else 1646 return (4); 1647 1648 case PHASE_MSG_IN: 1649 scb->nextstat = 3; 1650 if (iha_msgin(sc) == -1) 1651 return (-1); 1652 break; 1653 1654 case PHASE_STATUS_IN: 1655 if (iha_status_msg(sc) == -1) 1656 return (-1); 1657 break; 1658 1659 case PHASE_MSG_OUT: 1660 flags = scb->tcs->flags; 1661 if ((flags & FLAG_NO_NEG_SYNC) != 0) { 1662 if (iha_msgout(sc, MSG_NOOP) == -1) 1663 return (-1); 1664 } else if (iha_msgout_sdtr(sc) == -1) 1665 return (-1); 1666 break; 1667 1668 default: 1669 printf("[debug] -s3- bad phase = %d\n", sc->sc_phase); 1670 iha_bad_seq(sc); 1671 return (-1); 1672 } 1673 } 1674 } 1675 1676 /* 1677 * iha_state_4 - start a data xfer. Handle any bus state 1678 * transitions until PHASE_DATA_IN/_OUT 1679 * or the attempt is abandoned. If there is 1680 * no data to xfer, go to state 6 and finish 1681 * processing the current SCB. 1682 */ 1683 static int 1684 iha_state_4(struct iha_softc *sc) 1685 { 1686 struct iha_scb *scb = sc->sc_actscb; 1687 1688 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) == 1689 (FLAG_DATAIN | FLAG_DATAOUT)) 1690 return (6); /* Both dir flags set => NO xfer was requested */ 1691 1692 for (;;) { 1693 if (scb->buflen == 0) 1694 return (6); 1695 1696 switch (sc->sc_phase) { 1697 case PHASE_STATUS_IN: 1698 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1699 scb->ha_stat = iha_data_over_run(scb); 1700 if ((iha_status_msg(sc)) == -1) 1701 return (-1); 1702 break; 1703 1704 case PHASE_MSG_IN: 1705 scb->nextstat = 4; 1706 if (iha_msgin(sc) == -1) 1707 return (-1); 1708 break; 1709 1710 case PHASE_MSG_OUT: 1711 if ((sc->sc_status0 & SPERR) != 0) { 1712 scb->buflen = 0; 1713 scb->ha_stat = HOST_SPERR; 1714 if (iha_msgout(sc, MSG_INITIATOR_DET_ERR) == -1) 1715 return (-1); 1716 else 1717 return (6); 1718 } else { 1719 if (iha_msgout(sc, MSG_NOOP) == -1) 1720 return (-1); 1721 } 1722 break; 1723 1724 case PHASE_DATA_IN: 1725 return (iha_xfer_data(sc, scb, FLAG_DATAIN)); 1726 1727 case PHASE_DATA_OUT: 1728 return (iha_xfer_data(sc, scb, FLAG_DATAOUT)); 1729 1730 default: 1731 iha_bad_seq(sc); 1732 return (-1); 1733 } 1734 } 1735 } 1736 1737 /* 1738 * iha_state_5 - handle the partial or final completion of the current 1739 * data xfer. If DMA is still active stop it. If there is 1740 * more data to xfer, go to state 4 and start the xfer. 1741 * If not go to state 6 and finish the SCB. 1742 */ 1743 static int 1744 iha_state_5(struct iha_softc *sc) 1745 { 1746 bus_space_tag_t iot = sc->sc_iot; 1747 bus_space_handle_t ioh = sc->sc_ioh; 1748 struct iha_scb *scb = sc->sc_actscb; 1749 struct iha_sg_element *sg; 1750 u_int32_t cnt; 1751 u_int8_t period, stat; 1752 long xcnt; /* cannot use unsigned!! see code: if (xcnt < 0) */ 1753 int i; 1754 1755 cnt = bus_space_read_4(iot, ioh, TUL_STCNT0) & TCNT; 1756 1757 /* 1758 * Stop any pending DMA activity and check for parity error. 1759 */ 1760 1761 if ((bus_space_read_1(iot, ioh, TUL_DCMD) & XDIR) != 0) { 1762 /* Input Operation */ 1763 if ((sc->sc_status0 & SPERR) != 0) 1764 scb->ha_stat = HOST_SPERR; 1765 1766 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1767 bus_space_write_1(iot, ioh, TUL_DCTRL0, 1768 bus_space_read_1(iot, ioh, TUL_DCTRL0) | SXSTP); 1769 while (bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) 1770 ; 1771 } 1772 1773 } else { 1774 /* Output Operation */ 1775 if ((sc->sc_status1 & SXCMP) == 0) { 1776 period = scb->tcs->syncm; 1777 if ((period & PERIOD_WIDE_SCSI) != 0) 1778 cnt += (bus_space_read_1(iot, ioh, 1779 TUL_SFIFOCNT) & FIFOC) * 2; 1780 else 1781 cnt += bus_space_read_1(iot, ioh, 1782 TUL_SFIFOCNT) & FIFOC; 1783 } 1784 1785 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1786 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 1787 do 1788 stat = bus_space_read_1(iot, ioh, TUL_ISTUS0); 1789 while ((stat & DABT) == 0); 1790 } 1791 1792 if ((cnt == 1) && (sc->sc_phase == PHASE_DATA_OUT)) { 1793 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1794 return (-1); 1795 cnt = 0; 1796 1797 } else if ((sc->sc_status1 & SXCMP) == 0) 1798 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1799 } 1800 1801 if (cnt == 0) { 1802 scb->buflen = 0; 1803 return (6); 1804 } 1805 1806 /* Update active data pointer and restart the I/O at the new point */ 1807 1808 xcnt = scb->buflen - cnt; /* xcnt == bytes xferred */ 1809 scb->buflen = cnt; /* cnt == bytes left */ 1810 1811 if ((scb->flags & FLAG_SG) != 0) { 1812 sg = &scb->sglist[scb->sg_index]; 1813 for (i = scb->sg_index; i < scb->sg_max; sg++, i++) { 1814 xcnt -= le32toh(sg->sg_len); 1815 if (xcnt < 0) { 1816 xcnt += le32toh(sg->sg_len); 1817 1818 sg->sg_addr = 1819 htole32(le32toh(sg->sg_addr) + xcnt); 1820 sg->sg_len = 1821 htole32(le32toh(sg->sg_len) - xcnt); 1822 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1823 scb->sgoffset, IHA_SG_SIZE, 1824 BUS_DMASYNC_PREWRITE); 1825 1826 scb->bufaddr += (i - scb->sg_index) * 1827 sizeof(struct iha_sg_element); 1828 scb->sg_size = scb->sg_max - i; 1829 scb->sg_index = i; 1830 1831 return (4); 1832 } 1833 } 1834 return (6); 1835 1836 } else 1837 scb->bufaddr += xcnt; 1838 1839 return (4); 1840 } 1841 1842 /* 1843 * iha_state_6 - finish off the active scb (may require several 1844 * iterations if PHASE_MSG_IN) and return -1 to indicate 1845 * the bus is free. 1846 */ 1847 static int 1848 iha_state_6(struct iha_softc *sc) 1849 { 1850 1851 for (;;) { 1852 switch (sc->sc_phase) { 1853 case PHASE_STATUS_IN: 1854 if (iha_status_msg(sc) == -1) 1855 return (-1); 1856 break; 1857 1858 case PHASE_MSG_IN: 1859 sc->sc_actscb->nextstat = 6; 1860 if ((iha_msgin(sc)) == -1) 1861 return (-1); 1862 break; 1863 1864 case PHASE_MSG_OUT: 1865 if ((iha_msgout(sc, MSG_NOOP)) == -1) 1866 return (-1); 1867 break; 1868 1869 case PHASE_DATA_IN: 1870 if (iha_xpad_in(sc) == -1) 1871 return (-1); 1872 break; 1873 1874 case PHASE_DATA_OUT: 1875 if (iha_xpad_out(sc) == -1) 1876 return (-1); 1877 break; 1878 1879 default: 1880 iha_bad_seq(sc); 1881 return (-1); 1882 } 1883 } 1884 } 1885 1886 /* 1887 * iha_state_8 - reset the active device and all busy SCBs using it 1888 */ 1889 static int 1890 iha_state_8(struct iha_softc *sc) 1891 { 1892 bus_space_tag_t iot = sc->sc_iot; 1893 bus_space_handle_t ioh = sc->sc_ioh; 1894 struct iha_scb *scb; 1895 int i; 1896 u_int8_t tar; 1897 1898 if (sc->sc_phase == PHASE_MSG_OUT) { 1899 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_BUS_DEV_RESET); 1900 1901 scb = sc->sc_actscb; 1902 1903 /* This SCB finished correctly -- resetting the device */ 1904 iha_append_done_scb(sc, scb, HOST_OK); 1905 1906 iha_reset_tcs(scb->tcs, sc->sc_sconf1); 1907 1908 tar = scb->target; 1909 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1910 if (scb->target == tar) 1911 switch (scb->status) { 1912 case STATUS_BUSY: 1913 iha_append_done_scb(sc, 1914 scb, HOST_DEV_RST); 1915 break; 1916 1917 case STATUS_SELECT: 1918 iha_push_pend_scb(sc, scb); 1919 break; 1920 1921 default: 1922 break; 1923 } 1924 1925 sc->sc_flags |= FLAG_EXPECT_DISC; 1926 1927 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1928 return (-1); 1929 } 1930 1931 iha_bad_seq(sc); 1932 return (-1); 1933 } 1934 1935 /* 1936 * iha_xfer_data - initiate the DMA xfer of the data 1937 */ 1938 static int 1939 iha_xfer_data(struct iha_softc *sc, struct iha_scb *scb, int direction) 1940 { 1941 bus_space_tag_t iot = sc->sc_iot; 1942 bus_space_handle_t ioh = sc->sc_ioh; 1943 u_int32_t xferlen; 1944 u_int8_t xfercmd; 1945 1946 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != direction) 1947 return (6); /* wrong direction, abandon I/O */ 1948 1949 bus_space_write_4(iot, ioh, TUL_STCNT0, scb->buflen); 1950 1951 xfercmd = STRXFR; 1952 if (direction == FLAG_DATAIN) 1953 xfercmd |= XDIR; 1954 1955 if (scb->flags & FLAG_SG) { 1956 xferlen = scb->sg_size * sizeof(struct iha_sg_element); 1957 xfercmd |= SGXFR; 1958 } else 1959 xferlen = scb->buflen; 1960 1961 bus_space_write_4(iot, ioh, TUL_DXC, xferlen); 1962 bus_space_write_4(iot, ioh, TUL_DXPA, scb->bufaddr); 1963 bus_space_write_1(iot, ioh, TUL_DCMD, xfercmd); 1964 1965 bus_space_write_1(iot, ioh, TUL_SCMD, 1966 (direction == FLAG_DATAIN) ? XF_DMA_IN : XF_DMA_OUT); 1967 1968 scb->nextstat = 5; 1969 1970 return (0); 1971 } 1972 1973 static int 1974 iha_xpad_in(struct iha_softc *sc) 1975 { 1976 bus_space_tag_t iot = sc->sc_iot; 1977 bus_space_handle_t ioh = sc->sc_ioh; 1978 struct iha_scb *scb = sc->sc_actscb; 1979 1980 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1981 scb->ha_stat = HOST_DO_DU; 1982 1983 for (;;) { 1984 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 1985 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 1986 else 1987 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1988 1989 switch (iha_wait(sc, XF_FIFO_IN)) { 1990 case -1: 1991 return (-1); 1992 1993 case PHASE_DATA_IN: 1994 bus_space_read_1(iot, ioh, TUL_SFIFO); 1995 break; 1996 1997 default: 1998 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1999 return (6); 2000 } 2001 } 2002 } 2003 2004 static int 2005 iha_xpad_out(struct iha_softc *sc) 2006 { 2007 bus_space_tag_t iot = sc->sc_iot; 2008 bus_space_handle_t ioh = sc->sc_ioh; 2009 struct iha_scb *scb = sc->sc_actscb; 2010 2011 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 2012 scb->ha_stat = HOST_DO_DU; 2013 2014 for (;;) { 2015 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 2016 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 2017 else 2018 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2019 2020 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 2021 2022 switch (iha_wait(sc, XF_FIFO_OUT)) { 2023 case -1: 2024 return (-1); 2025 2026 case PHASE_DATA_OUT: 2027 break; 2028 2029 default: 2030 /* Disable wide CPU to allow read 16 bits */ 2031 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2032 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2033 return (6); 2034 } 2035 } 2036 } 2037 2038 static int 2039 iha_status_msg(struct iha_softc *sc) 2040 { 2041 bus_space_tag_t iot = sc->sc_iot; 2042 bus_space_handle_t ioh = sc->sc_ioh; 2043 struct iha_scb *scb; 2044 u_int8_t msg; 2045 int phase; 2046 2047 if ((phase = iha_wait(sc, CMD_COMP)) == -1) 2048 return (-1); 2049 2050 scb = sc->sc_actscb; 2051 2052 scb->ta_stat = bus_space_read_1(iot, ioh, TUL_SFIFO); 2053 2054 if (phase == PHASE_MSG_OUT) { 2055 if ((sc->sc_status0 & SPERR) == 0) 2056 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_NOOP); 2057 else 2058 bus_space_write_1(iot, ioh, TUL_SFIFO, 2059 MSG_PARITY_ERROR); 2060 2061 return (iha_wait(sc, XF_FIFO_OUT)); 2062 2063 } else if (phase == PHASE_MSG_IN) { 2064 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 2065 2066 if ((sc->sc_status0 & SPERR) != 0) 2067 switch (iha_wait(sc, MSG_ACCEPT)) { 2068 case -1: 2069 return (-1); 2070 case PHASE_MSG_OUT: 2071 bus_space_write_1(iot, ioh, TUL_SFIFO, 2072 MSG_PARITY_ERROR); 2073 return (iha_wait(sc, XF_FIFO_OUT)); 2074 default: 2075 iha_bad_seq(sc); 2076 return (-1); 2077 } 2078 2079 if (msg == MSG_CMDCOMPLETE) { 2080 if ((scb->ta_stat & 2081 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) { 2082 iha_bad_seq(sc); 2083 return (-1); 2084 } 2085 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 2086 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2087 return (iha_wait(sc, MSG_ACCEPT)); 2088 } 2089 2090 if ((msg == MSG_LINK_CMD_COMPLETE) 2091 || (msg == MSG_LINK_CMD_COMPLETEF)) { 2092 if ((scb->ta_stat & 2093 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) 2094 return (iha_wait(sc, MSG_ACCEPT)); 2095 } 2096 } 2097 2098 iha_bad_seq(sc); 2099 return (-1); 2100 } 2101 2102 /* 2103 * iha_busfree - SCSI bus free detected as a result of a TIMEOUT or 2104 * DISCONNECT interrupt. Reset the tulip FIFO and 2105 * SCONFIG0 and enable hardware reselect. Move any active 2106 * SCB to sc_donescb list. Return an appropriate host status 2107 * if an I/O was active. 2108 */ 2109 static void 2110 iha_busfree(struct iha_softc *sc) 2111 { 2112 bus_space_tag_t iot = sc->sc_iot; 2113 bus_space_handle_t ioh = sc->sc_ioh; 2114 struct iha_scb *scb; 2115 2116 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2117 bus_space_write_1(iot, ioh, TUL_SCONFIG0, SCONFIG0DEFAULT); 2118 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2119 2120 scb = sc->sc_actscb; 2121 2122 if (scb != NULL) { 2123 if (scb->status == STATUS_SELECT) 2124 /* selection timeout */ 2125 iha_append_done_scb(sc, scb, HOST_SEL_TOUT); 2126 else 2127 /* Unexpected bus free */ 2128 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 2129 } 2130 } 2131 2132 /* 2133 * iha_resel - handle a detected SCSI bus reselection request. 2134 */ 2135 static int 2136 iha_resel(struct iha_softc *sc) 2137 { 2138 bus_space_tag_t iot = sc->sc_iot; 2139 bus_space_handle_t ioh = sc->sc_ioh; 2140 struct iha_scb *scb; 2141 struct tcs *tcs; 2142 u_int8_t tag, target, lun, msg, abortmsg; 2143 2144 if (sc->sc_actscb != NULL) { 2145 if ((sc->sc_actscb->status == STATUS_SELECT)) 2146 iha_push_pend_scb(sc, sc->sc_actscb); 2147 sc->sc_actscb = NULL; 2148 } 2149 2150 target = bus_space_read_1(iot, ioh, TUL_SBID); 2151 lun = bus_space_read_1(iot, ioh, TUL_SALVC) & IHA_MSG_IDENTIFY_LUNMASK; 2152 2153 tcs = &sc->sc_tcs[target]; 2154 2155 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2156 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2157 2158 abortmsg = MSG_ABORT; /* until a valid tag has been obtained */ 2159 2160 if (tcs->ntagscb != NULL) 2161 /* There is a non-tagged I/O active on the target */ 2162 scb = tcs->ntagscb; 2163 2164 else { 2165 /* 2166 * Since there is no active non-tagged operation 2167 * read the tag type, the tag itself, and find 2168 * the appropriate scb by indexing sc_scb with 2169 * the tag. 2170 */ 2171 2172 switch (iha_wait(sc, MSG_ACCEPT)) { 2173 case -1: 2174 return (-1); 2175 case PHASE_MSG_IN: 2176 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2177 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 2178 return (-1); 2179 break; 2180 default: 2181 goto abort; 2182 } 2183 2184 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag Msg */ 2185 2186 if ((msg < MSG_SIMPLE_Q_TAG) || (msg > MSG_ORDERED_Q_TAG)) 2187 goto abort; 2188 2189 switch (iha_wait(sc, MSG_ACCEPT)) { 2190 case -1: 2191 return (-1); 2192 case PHASE_MSG_IN: 2193 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2194 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 2195 return (-1); 2196 break; 2197 default: 2198 goto abort; 2199 } 2200 2201 tag = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag ID */ 2202 scb = &sc->sc_scb[tag]; 2203 2204 abortmsg = MSG_ABORT_TAG; /* Now that we have valdid tag! */ 2205 } 2206 2207 if ((scb->target != target) 2208 || (scb->lun != lun) 2209 || (scb->status != STATUS_BUSY)) { 2210 abort: 2211 iha_msgout_abort(sc, abortmsg); 2212 return (-1); 2213 } 2214 2215 sc->sc_actscb = scb; 2216 2217 if (iha_wait(sc, MSG_ACCEPT) == -1) 2218 return (-1); 2219 2220 return (iha_next_state(sc)); 2221 } 2222 2223 static int 2224 iha_msgin(struct iha_softc *sc) 2225 { 2226 bus_space_tag_t iot = sc->sc_iot; 2227 bus_space_handle_t ioh = sc->sc_ioh; 2228 int flags; 2229 int phase; 2230 u_int8_t msg; 2231 2232 for (;;) { 2233 if ((bus_space_read_1(iot, ioh, TUL_SFIFOCNT) & FIFOC) > 0) 2234 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2235 2236 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2237 2238 phase = iha_wait(sc, XF_FIFO_IN); 2239 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 2240 2241 switch (msg) { 2242 case MSG_DISCONNECT: 2243 sc->sc_flags |= FLAG_EXPECT_DISC; 2244 if (iha_wait(sc, MSG_ACCEPT) != -1) 2245 iha_bad_seq(sc); 2246 phase = -1; 2247 break; 2248 case MSG_SAVEDATAPOINTER: 2249 case MSG_RESTOREPOINTERS: 2250 case MSG_NOOP: 2251 phase = iha_wait(sc, MSG_ACCEPT); 2252 break; 2253 case MSG_MESSAGE_REJECT: 2254 /* XXX - need to clear FIFO like other 'Clear ATN'?*/ 2255 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2256 flags = sc->sc_actscb->tcs->flags; 2257 if ((flags & FLAG_NO_NEG_SYNC) == 0) 2258 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2259 phase = iha_wait(sc, MSG_ACCEPT); 2260 break; 2261 case MSG_EXTENDED: 2262 phase = iha_msgin_extended(sc); 2263 break; 2264 case MSG_IGN_WIDE_RESIDUE: 2265 phase = iha_msgin_ignore_wid_resid(sc); 2266 break; 2267 case MSG_CMDCOMPLETE: 2268 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 2269 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2270 phase = iha_wait(sc, MSG_ACCEPT); 2271 if (phase != -1) { 2272 iha_bad_seq(sc); 2273 return (-1); 2274 } 2275 break; 2276 default: 2277 printf("[debug] iha_msgin: bad msg type: %d\n", msg); 2278 phase = iha_msgout_reject(sc); 2279 break; 2280 } 2281 2282 if (phase != PHASE_MSG_IN) 2283 return (phase); 2284 } 2285 /* NOTREACHED */ 2286 } 2287 2288 static int 2289 iha_msgin_extended(struct iha_softc *sc) 2290 { 2291 bus_space_tag_t iot = sc->sc_iot; 2292 bus_space_handle_t ioh = sc->sc_ioh; 2293 int flags, i, phase, msglen, msgcode; 2294 2295 /* 2296 * XXX - can we just stop reading and reject, or do we have to 2297 * read all input, discarding the excess, and then reject 2298 */ 2299 for (i = 0; i < IHA_MAX_EXTENDED_MSG; i++) { 2300 phase = iha_wait(sc, MSG_ACCEPT); 2301 2302 if (phase != PHASE_MSG_IN) 2303 return (phase); 2304 2305 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2306 2307 if (iha_wait(sc, XF_FIFO_IN) == -1) 2308 return (-1); 2309 2310 sc->sc_msg[i] = bus_space_read_1(iot, ioh, TUL_SFIFO); 2311 2312 if (sc->sc_msg[0] == i) 2313 break; 2314 } 2315 2316 msglen = sc->sc_msg[0]; 2317 msgcode = sc->sc_msg[1]; 2318 2319 if ((msglen == MSG_EXT_SDTR_LEN) && (msgcode == MSG_EXT_SDTR)) { 2320 if (iha_msgin_sdtr(sc) == 0) { 2321 iha_sync_done(sc); 2322 return (iha_wait(sc, MSG_ACCEPT)); 2323 } 2324 2325 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2326 2327 phase = iha_wait(sc, MSG_ACCEPT); 2328 if (phase != PHASE_MSG_OUT) 2329 return (phase); 2330 2331 /* Clear FIFO for important message - final SYNC offer */ 2332 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2333 2334 iha_sync_done(sc); /* This is our final offer */ 2335 2336 } else if ((msglen == MSG_EXT_WDTR_LEN) && (msgcode == MSG_EXT_WDTR)) { 2337 2338 flags = sc->sc_actscb->tcs->flags; 2339 2340 if ((flags & FLAG_NO_WIDE) != 0) 2341 /* Offer 8bit xfers only */ 2342 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_8_BIT; 2343 2344 else if (sc->sc_msg[2] > MSG_EXT_WDTR_BUS_32_BIT) 2345 /* BAD MSG */ 2346 return (iha_msgout_reject(sc)); 2347 2348 else if (sc->sc_msg[2] == MSG_EXT_WDTR_BUS_32_BIT) 2349 /* Offer 16bit instead */ 2350 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2351 2352 else { 2353 iha_wide_done(sc); 2354 if ((flags & FLAG_NO_NEG_SYNC) == 0) 2355 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2356 return (iha_wait(sc, MSG_ACCEPT)); 2357 } 2358 2359 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2360 2361 phase = iha_wait(sc, MSG_ACCEPT); 2362 if (phase != PHASE_MSG_OUT) 2363 return (phase); 2364 } else 2365 return (iha_msgout_reject(sc)); 2366 2367 return (iha_msgout_extended(sc)); 2368 } 2369 2370 /* 2371 * iha_msgin_sdtr - check SDTR msg in sc_msg. If the offer is 2372 * acceptable leave sc_msg as is and return 0. 2373 * If the negotiation must continue, modify sc_msg 2374 * as needed and return 1. Else return 0. 2375 */ 2376 static int 2377 iha_msgin_sdtr(struct iha_softc *sc) 2378 { 2379 int flags; 2380 int newoffer; 2381 u_int8_t default_period; 2382 2383 flags = sc->sc_actscb->tcs->flags; 2384 2385 default_period = iha_rate_tbl[flags & FLAG_SCSI_RATE]; 2386 2387 if (sc->sc_msg[3] == 0) 2388 /* target offered async only. Accept it. */ 2389 return (0); 2390 2391 newoffer = 0; 2392 2393 if ((flags & FLAG_NO_SYNC) != 0) { 2394 sc->sc_msg[3] = 0; 2395 newoffer = 1; 2396 } 2397 2398 if (sc->sc_msg[3] > IHA_MAX_OFFSET) { 2399 sc->sc_msg[3] = IHA_MAX_OFFSET; 2400 newoffer = 1; 2401 } 2402 2403 if (sc->sc_msg[2] < default_period) { 2404 sc->sc_msg[2] = default_period; 2405 newoffer = 1; 2406 } 2407 2408 if (sc->sc_msg[2] > IHA_MAX_PERIOD) { 2409 /* Use async */ 2410 sc->sc_msg[3] = 0; 2411 newoffer = 1; 2412 } 2413 2414 return (newoffer); 2415 } 2416 2417 static int 2418 iha_msgin_ignore_wid_resid(struct iha_softc *sc) 2419 { 2420 bus_space_tag_t iot = sc->sc_iot; 2421 bus_space_handle_t ioh = sc->sc_ioh; 2422 int phase; 2423 2424 phase = iha_wait(sc, MSG_ACCEPT); 2425 2426 if (phase == PHASE_MSG_IN) { 2427 phase = iha_wait(sc, XF_FIFO_IN); 2428 2429 if (phase != -1) { 2430 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 2431 bus_space_read_1(iot, ioh, TUL_SFIFO); 2432 bus_space_read_1(iot, ioh, TUL_SFIFO); 2433 2434 phase = iha_wait(sc, MSG_ACCEPT); 2435 } 2436 } 2437 2438 return (phase); 2439 } 2440 2441 static int 2442 iha_msgout(struct iha_softc *sc, u_int8_t msg) 2443 { 2444 2445 bus_space_write_1(sc->sc_iot, sc->sc_ioh, TUL_SFIFO, msg); 2446 2447 return (iha_wait(sc, XF_FIFO_OUT)); 2448 } 2449 2450 static void 2451 iha_msgout_abort(struct iha_softc *sc, u_int8_t aborttype) 2452 { 2453 2454 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2455 2456 switch (iha_wait(sc, MSG_ACCEPT)) { 2457 case -1: 2458 break; 2459 2460 case PHASE_MSG_OUT: 2461 sc->sc_flags |= FLAG_EXPECT_DISC; 2462 if (iha_msgout(sc, aborttype) != -1) 2463 iha_bad_seq(sc); 2464 break; 2465 2466 default: 2467 iha_bad_seq(sc); 2468 break; 2469 } 2470 } 2471 2472 static int 2473 iha_msgout_reject(struct iha_softc *sc) 2474 { 2475 2476 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2477 2478 if (iha_wait(sc, MSG_ACCEPT) == PHASE_MSG_OUT) 2479 return (iha_msgout(sc, MSG_MESSAGE_REJECT)); 2480 2481 return (-1); 2482 } 2483 2484 static int 2485 iha_msgout_extended(struct iha_softc *sc) 2486 { 2487 bus_space_tag_t iot = sc->sc_iot; 2488 bus_space_handle_t ioh = sc->sc_ioh; 2489 int phase; 2490 2491 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXTENDED); 2492 2493 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 2494 sc->sc_msg, sc->sc_msg[0] + 1); 2495 2496 phase = iha_wait(sc, XF_FIFO_OUT); 2497 2498 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2499 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2500 2501 return (phase); 2502 } 2503 2504 static int 2505 iha_msgout_wdtr(struct iha_softc *sc) 2506 { 2507 2508 sc->sc_actscb->tcs->flags |= FLAG_WIDE_DONE; 2509 2510 sc->sc_msg[0] = MSG_EXT_WDTR_LEN; 2511 sc->sc_msg[1] = MSG_EXT_WDTR; 2512 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2513 2514 return (iha_msgout_extended(sc)); 2515 } 2516 2517 static int 2518 iha_msgout_sdtr(struct iha_softc *sc) 2519 { 2520 struct tcs *tcs = sc->sc_actscb->tcs; 2521 2522 tcs->flags |= FLAG_SYNC_DONE; 2523 2524 sc->sc_msg[0] = MSG_EXT_SDTR_LEN; 2525 sc->sc_msg[1] = MSG_EXT_SDTR; 2526 sc->sc_msg[2] = iha_rate_tbl[tcs->flags & FLAG_SCSI_RATE]; 2527 sc->sc_msg[3] = IHA_MAX_OFFSET; /* REQ/ACK */ 2528 2529 return (iha_msgout_extended(sc)); 2530 } 2531 2532 static void 2533 iha_wide_done(struct iha_softc *sc) 2534 { 2535 bus_space_tag_t iot = sc->sc_iot; 2536 bus_space_handle_t ioh = sc->sc_ioh; 2537 struct tcs *tcs = sc->sc_actscb->tcs; 2538 2539 tcs->syncm = 0; 2540 tcs->period = 0; 2541 tcs->offset = 0; 2542 2543 if (sc->sc_msg[2] != 0) 2544 tcs->syncm |= PERIOD_WIDE_SCSI; 2545 2546 tcs->sconfig0 &= ~ALTPD; 2547 tcs->flags &= ~FLAG_SYNC_DONE; 2548 tcs->flags |= FLAG_WIDE_DONE; 2549 2550 iha_update_xfer_mode(sc, sc->sc_actscb->target); 2551 2552 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2553 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2554 } 2555 2556 static void 2557 iha_sync_done(struct iha_softc *sc) 2558 { 2559 bus_space_tag_t iot = sc->sc_iot; 2560 bus_space_handle_t ioh = sc->sc_ioh; 2561 struct tcs *tcs = sc->sc_actscb->tcs; 2562 int i; 2563 2564 tcs->period = sc->sc_msg[2]; 2565 tcs->offset = sc->sc_msg[3]; 2566 if (tcs->offset != 0) { 2567 tcs->syncm |= tcs->offset; 2568 2569 /* pick the highest possible rate */ 2570 for (i = 0; i < sizeof(iha_rate_tbl); i++) 2571 if (iha_rate_tbl[i] >= tcs->period) 2572 break; 2573 2574 tcs->syncm |= (i << 4); 2575 tcs->sconfig0 |= ALTPD; 2576 } 2577 2578 tcs->flags |= FLAG_SYNC_DONE; 2579 2580 iha_update_xfer_mode(sc, sc->sc_actscb->target); 2581 2582 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2583 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2584 } 2585 2586 /* 2587 * iha_bad_seq - a SCSI bus phase was encountered out of the 2588 * correct/expected sequence. Reset the SCSI bus. 2589 */ 2590 static void 2591 iha_bad_seq(struct iha_softc *sc) 2592 { 2593 struct iha_scb *scb = sc->sc_actscb; 2594 2595 if (scb != NULL) 2596 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 2597 2598 iha_reset_scsi_bus(sc); 2599 iha_reset_chip(sc); 2600 } 2601 2602 /* 2603 * iha_read_eeprom - read Serial EEPROM value & set to defaults 2604 * if required. XXX - Writing does NOT work! 2605 */ 2606 static void 2607 iha_read_eeprom(struct iha_softc *sc, struct iha_eeprom *eeprom) 2608 { 2609 bus_space_tag_t iot = sc->sc_iot; 2610 bus_space_handle_t ioh = sc->sc_ioh; 2611 u_int16_t *buf = (u_int16_t *)eeprom; 2612 u_int8_t gctrl; 2613 2614 /* Enable EEProm programming */ 2615 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) | EEPRG; 2616 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2617 2618 /* Read EEProm */ 2619 if (iha_se2_rd_all(sc, buf) == 0) 2620 panic("%s: cannot read EEPROM", sc->sc_dev.dv_xname); 2621 2622 /* Disable EEProm programming */ 2623 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) & ~EEPRG; 2624 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2625 } 2626 2627 #ifdef notused 2628 /* 2629 * iha_se2_update_all - Update SCSI H/A configuration parameters from 2630 * serial EEPROM Setup default pattern. Only 2631 * change those values different from the values 2632 * in iha_eeprom. 2633 */ 2634 static void 2635 iha_se2_update_all(struct iha_softc *sc) 2636 { 2637 bus_space_tag_t iot = sc->sc_iot; 2638 bus_space_handle_t ioh = sc->sc_ioh; 2639 u_int16_t *np; 2640 u_int32_t chksum; 2641 int i; 2642 2643 /* Enable erase/write state of EEPROM */ 2644 iha_se2_instr(sc, ENABLE_ERASE); 2645 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2646 EEP_WAIT(); 2647 2648 np = (u_int16_t *)&eeprom_default; 2649 2650 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2651 iha_se2_wr(sc, i, *np); 2652 chksum += *np++; 2653 } 2654 2655 chksum &= 0x0000ffff; 2656 iha_se2_wr(sc, 31, chksum); 2657 2658 /* Disable erase/write state of EEPROM */ 2659 iha_se2_instr(sc, 0); 2660 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2661 EEP_WAIT(); 2662 } 2663 2664 /* 2665 * iha_se2_wr - write the given 16 bit value into the Serial EEPROM 2666 * at the specified offset 2667 */ 2668 static void 2669 iha_se2_wr(struct iha_softc *sc, int addr, u_int16_t writeword) 2670 { 2671 bus_space_tag_t iot = sc->sc_iot; 2672 bus_space_handle_t ioh = sc->sc_ioh; 2673 int i, bit; 2674 2675 /* send 'WRITE' Instruction == address | WRITE bit */ 2676 iha_se2_instr(sc, addr | WRITE); 2677 2678 for (i = 16; i > 0; i--) { 2679 if (writeword & (1 << (i - 1))) 2680 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRDO); 2681 else 2682 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2683 EEP_WAIT(); 2684 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2685 EEP_WAIT(); 2686 } 2687 2688 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2689 EEP_WAIT(); 2690 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2691 EEP_WAIT(); 2692 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2693 EEP_WAIT(); 2694 2695 for (;;) { 2696 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2697 EEP_WAIT(); 2698 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2699 EEP_WAIT(); 2700 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI; 2701 EEP_WAIT(); 2702 if (bit != 0) 2703 break; /* write complete */ 2704 } 2705 2706 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2707 } 2708 #endif 2709 2710 /* 2711 * iha_se2_rd - read & return the 16 bit value at the specified 2712 * offset in the Serial E2PROM 2713 * 2714 */ 2715 static u_int16_t 2716 iha_se2_rd(struct iha_softc *sc, int addr) 2717 { 2718 bus_space_tag_t iot = sc->sc_iot; 2719 bus_space_handle_t ioh = sc->sc_ioh; 2720 int i, bit; 2721 u_int16_t readword; 2722 2723 /* Send 'READ' instruction == address | READ bit */ 2724 iha_se2_instr(sc, addr | READ); 2725 2726 readword = 0; 2727 for (i = 16; i > 0; i--) { 2728 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2729 EEP_WAIT(); 2730 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2731 EEP_WAIT(); 2732 /* sample data after the following edge of clock */ 2733 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI ? 1 : 0; 2734 EEP_WAIT(); 2735 2736 readword |= bit << (i - 1); 2737 } 2738 2739 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2740 2741 return (readword); 2742 } 2743 2744 /* 2745 * iha_se2_rd_all - Read SCSI H/A config parameters from serial EEPROM 2746 */ 2747 static int 2748 iha_se2_rd_all(struct iha_softc *sc, u_int16_t *buf) 2749 { 2750 struct iha_eeprom *eeprom = (struct iha_eeprom *)buf; 2751 u_int32_t chksum; 2752 int i; 2753 2754 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2755 *buf = iha_se2_rd(sc, i); 2756 chksum += *buf++; 2757 } 2758 *buf = iha_se2_rd(sc, 31); /* read checksum from EEPROM */ 2759 2760 chksum &= 0x0000ffff; /* lower 16 bits */ 2761 2762 return (eeprom->signature == EEP_SIGNATURE) && 2763 (eeprom->checksum == chksum); 2764 } 2765 2766 /* 2767 * iha_se2_instr - write an octet to serial E2PROM one bit at a time 2768 */ 2769 static void 2770 iha_se2_instr(struct iha_softc *sc, int instr) 2771 { 2772 bus_space_tag_t iot = sc->sc_iot; 2773 bus_space_handle_t ioh = sc->sc_ioh; 2774 int b, i; 2775 2776 b = NVRCS | NVRDO; /* Write the start bit (== 1) */ 2777 2778 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2779 EEP_WAIT(); 2780 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2781 EEP_WAIT(); 2782 2783 for (i = 8; i > 0; i--) { 2784 if (instr & (1 << (i - 1))) 2785 b = NVRCS | NVRDO; /* Write a 1 bit */ 2786 else 2787 b = NVRCS; /* Write a 0 bit */ 2788 2789 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2790 EEP_WAIT(); 2791 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2792 EEP_WAIT(); 2793 } 2794 2795 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2796 } 2797
Indexes created Mon Sep 22 13:09:51 GMT 2025