iha.c revision 1.32
1 /* $NetBSD: iha.c,v 1.32 2006/03/19 06:22:45 rtr Exp $ */ 2 3 /*- 4 * Device driver for the INI-9XXXU/UW or INIC-940/950 PCI SCSI Controller. 5 * 6 * Written for 386bsd and FreeBSD by 7 * Winston Hung <winstonh (at) initio.com> 8 * 9 * Copyright (c) 1997-1999 Initio Corp. 10 * Copyright (c) 2000, 2001 Ken Westerback 11 * Copyright (c) 2001, 2002 Izumi Tsutsui 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer, 19 * without modification, immediately at the beginning of the file. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 32 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Ported to NetBSD by Izumi Tsutsui <tsutsui (at) ceres.dti.ne.jp> from OpenBSD: 38 * $OpenBSD: iha.c,v 1.3 2001/02/20 00:47:33 krw Exp $ 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: iha.c,v 1.32 2006/03/19 06:22:45 rtr Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/buf.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 56 #include <dev/scsipi/scsi_spc.h> 57 #include <dev/scsipi/scsi_all.h> 58 #include <dev/scsipi/scsipi_all.h> 59 #include <dev/scsipi/scsiconf.h> 60 #include <dev/scsipi/scsi_message.h> 61 62 #include <dev/ic/ihareg.h> 63 #include <dev/ic/ihavar.h> 64 65 /* 66 * SCSI Rate Table, indexed by FLAG_SCSI_RATE field of 67 * tcs flags. 68 */ 69 static const uint8_t iha_rate_tbl[] = { 70 /* fast 20 */ 71 /* nanosecond divide by 4 */ 72 12, /* 50ns, 20M */ 73 18, /* 75ns, 13.3M */ 74 25, /* 100ns, 10M */ 75 31, /* 125ns, 8M */ 76 37, /* 150ns, 6.6M */ 77 43, /* 175ns, 5.7M */ 78 50, /* 200ns, 5M */ 79 62 /* 250ns, 4M */ 80 }; 81 #define IHA_MAX_PERIOD 62 82 83 #ifdef notused 84 static uint16_t eeprom_default[EEPROM_SIZE] = { 85 /* -- Header ------------------------------------ */ 86 /* signature */ 87 EEP_SIGNATURE, 88 /* size, revision */ 89 EEP_WORD(EEPROM_SIZE * 2, 0x01), 90 /* -- Host Adapter Structure -------------------- */ 91 /* model */ 92 0x0095, 93 /* model info, number of channel */ 94 EEP_WORD(0x00, 1), 95 /* BIOS config */ 96 EEP_BIOSCFG_DEFAULT, 97 /* host adapter config */ 98 0, 99 100 /* -- eeprom_adapter[0] ------------------------------- */ 101 /* ID, adapter config 1 */ 102 EEP_WORD(7, CFG_DEFAULT), 103 /* adapter config 2, number of targets */ 104 EEP_WORD(0x00, 8), 105 /* target flags */ 106 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 107 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 108 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 109 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 110 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 111 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 112 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 113 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 114 115 /* -- eeprom_adapter[1] ------------------------------- */ 116 /* ID, adapter config 1 */ 117 EEP_WORD(7, CFG_DEFAULT), 118 /* adapter config 2, number of targets */ 119 EEP_WORD(0x00, 8), 120 /* target flags */ 121 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 122 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 123 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 124 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 125 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 126 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 127 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 128 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 129 /* reserved[5] */ 130 0, 0, 0, 0, 0, 131 /* checksum */ 132 0 133 }; 134 #endif 135 136 static void iha_append_free_scb(struct iha_softc *, struct iha_scb *); 137 static void iha_append_done_scb(struct iha_softc *, struct iha_scb *, uint8_t); 138 static inline struct iha_scb *iha_pop_done_scb(struct iha_softc *); 139 140 static struct iha_scb *iha_find_pend_scb(struct iha_softc *); 141 static inline void iha_append_pend_scb(struct iha_softc *, struct iha_scb *); 142 static inline void iha_push_pend_scb(struct iha_softc *, struct iha_scb *); 143 static inline void iha_del_pend_scb(struct iha_softc *, struct iha_scb *); 144 static inline void iha_mark_busy_scb(struct iha_scb *); 145 146 static inline void iha_set_ssig(struct iha_softc *, uint8_t, uint8_t); 147 148 static int iha_alloc_sglist(struct iha_softc *); 149 150 static void iha_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 151 void *); 152 static void iha_update_xfer_mode(struct iha_softc *, int); 153 154 static void iha_reset_scsi_bus(struct iha_softc *); 155 static void iha_reset_chip(struct iha_softc *); 156 static void iha_reset_dma(struct iha_softc *); 157 static void iha_reset_tcs(struct tcs *, uint8_t); 158 159 static void iha_main(struct iha_softc *); 160 static void iha_scsi(struct iha_softc *); 161 static void iha_select(struct iha_softc *, struct iha_scb *, uint8_t); 162 static int iha_wait(struct iha_softc *, uint8_t); 163 164 static void iha_exec_scb(struct iha_softc *, struct iha_scb *); 165 static void iha_done_scb(struct iha_softc *, struct iha_scb *); 166 static int iha_push_sense_request(struct iha_softc *, struct iha_scb *); 167 168 static void iha_timeout(void *); 169 static void iha_abort_xs(struct iha_softc *, struct scsipi_xfer *, uint8_t); 170 static uint8_t iha_data_over_run(struct iha_scb *); 171 172 static int iha_next_state(struct iha_softc *); 173 static int iha_state_1(struct iha_softc *); 174 static int iha_state_2(struct iha_softc *); 175 static int iha_state_3(struct iha_softc *); 176 static int iha_state_4(struct iha_softc *); 177 static int iha_state_5(struct iha_softc *); 178 static int iha_state_6(struct iha_softc *); 179 static int iha_state_8(struct iha_softc *); 180 181 static int iha_xfer_data(struct iha_softc *, struct iha_scb *, int); 182 static int iha_xpad_in(struct iha_softc *); 183 static int iha_xpad_out(struct iha_softc *); 184 185 static int iha_status_msg(struct iha_softc *); 186 static void iha_busfree(struct iha_softc *); 187 static int iha_resel(struct iha_softc *); 188 189 static int iha_msgin(struct iha_softc *); 190 static int iha_msgin_extended(struct iha_softc *); 191 static int iha_msgin_sdtr(struct iha_softc *); 192 static int iha_msgin_ignore_wid_resid(struct iha_softc *); 193 194 static int iha_msgout(struct iha_softc *, uint8_t); 195 static void iha_msgout_abort(struct iha_softc *, uint8_t); 196 static int iha_msgout_reject(struct iha_softc *); 197 static int iha_msgout_extended(struct iha_softc *); 198 static int iha_msgout_wdtr(struct iha_softc *); 199 static int iha_msgout_sdtr(struct iha_softc *); 200 201 static void iha_wide_done(struct iha_softc *); 202 static void iha_sync_done(struct iha_softc *); 203 204 static void iha_bad_seq(struct iha_softc *); 205 206 static void iha_read_eeprom(struct iha_softc *, struct iha_eeprom *); 207 static int iha_se2_rd_all(struct iha_softc *, uint16_t *); 208 static void iha_se2_instr(struct iha_softc *, int); 209 static uint16_t iha_se2_rd(struct iha_softc *, int); 210 #ifdef notused 211 static void iha_se2_update_all(struct iha_softc *); 212 static void iha_se2_wr(struct iha_softc *, int, uint16_t); 213 #endif 214 215 /* 216 * iha_append_free_scb - append the supplied SCB to the tail of the 217 * sc_freescb queue after clearing and resetting 218 * everything possible. 219 */ 220 static void 221 iha_append_free_scb(struct iha_softc *sc, struct iha_scb *scb) 222 { 223 int s; 224 225 s = splbio(); 226 227 if (scb == sc->sc_actscb) 228 sc->sc_actscb = NULL; 229 230 scb->status = STATUS_QUEUED; 231 scb->ha_stat = HOST_OK; 232 scb->ta_stat = SCSI_OK; 233 234 scb->nextstat = 0; 235 scb->scb_tagmsg = 0; 236 237 scb->xs = NULL; 238 scb->tcs = NULL; 239 240 /* 241 * scb_tagid, sg_addr, sglist 242 * SCB_SensePtr are set at initialization 243 * and never change 244 */ 245 246 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 247 248 splx(s); 249 } 250 251 static void 252 iha_append_done_scb(struct iha_softc *sc, struct iha_scb *scb, uint8_t hastat) 253 { 254 struct tcs *tcs; 255 int s; 256 257 s = splbio(); 258 259 if (scb->xs != NULL) 260 callout_stop(&scb->xs->xs_callout); 261 262 if (scb == sc->sc_actscb) 263 sc->sc_actscb = NULL; 264 265 tcs = scb->tcs; 266 267 if (scb->scb_tagmsg != 0) { 268 if (tcs->tagcnt) 269 tcs->tagcnt--; 270 } else if (tcs->ntagscb == scb) 271 tcs->ntagscb = NULL; 272 273 scb->status = STATUS_QUEUED; 274 scb->ha_stat = hastat; 275 276 TAILQ_INSERT_TAIL(&sc->sc_donescb, scb, chain); 277 278 splx(s); 279 } 280 281 static inline struct iha_scb * 282 iha_pop_done_scb(struct iha_softc *sc) 283 { 284 struct iha_scb *scb; 285 int s; 286 287 s = splbio(); 288 289 scb = TAILQ_FIRST(&sc->sc_donescb); 290 291 if (scb != NULL) { 292 scb->status = STATUS_RENT; 293 TAILQ_REMOVE(&sc->sc_donescb, scb, chain); 294 } 295 296 splx(s); 297 298 return (scb); 299 } 300 301 /* 302 * iha_find_pend_scb - scan the pending queue for a SCB that can be 303 * processed immediately. Return NULL if none found 304 * and a pointer to the SCB if one is found. If there 305 * is an active SCB, return NULL! 306 */ 307 static struct iha_scb * 308 iha_find_pend_scb(struct iha_softc *sc) 309 { 310 struct iha_scb *scb; 311 struct tcs *tcs; 312 int s; 313 314 s = splbio(); 315 316 if (sc->sc_actscb != NULL) 317 scb = NULL; 318 319 else 320 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) { 321 if ((scb->xs->xs_control & XS_CTL_RESET) != 0) 322 /* ALWAYS willing to reset a device */ 323 break; 324 325 tcs = scb->tcs; 326 327 if ((scb->scb_tagmsg) != 0) { 328 /* 329 * A Tagged I/O. OK to start If no 330 * non-tagged I/O is active on the same 331 * target 332 */ 333 if (tcs->ntagscb == NULL) 334 break; 335 336 } else if (scb->cmd[0] == SCSI_REQUEST_SENSE) { 337 /* 338 * OK to do a non-tagged request sense 339 * even if a non-tagged I/O has been 340 * started, 'cuz we don't allow any 341 * disconnect during a request sense op 342 */ 343 break; 344 345 } else if (tcs->tagcnt == 0) { 346 /* 347 * No tagged I/O active on this target, 348 * ok to start a non-tagged one if one 349 * is not already active 350 */ 351 if (tcs->ntagscb == NULL) 352 break; 353 } 354 } 355 356 splx(s); 357 358 return (scb); 359 } 360 361 static inline void 362 iha_append_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 363 { 364 /* ASSUMPTION: only called within a splbio()/splx() pair */ 365 366 if (scb == sc->sc_actscb) 367 sc->sc_actscb = NULL; 368 369 scb->status = STATUS_QUEUED; 370 371 TAILQ_INSERT_TAIL(&sc->sc_pendscb, scb, chain); 372 } 373 374 static inline void 375 iha_push_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 376 { 377 int s; 378 379 s = splbio(); 380 381 if (scb == sc->sc_actscb) 382 sc->sc_actscb = NULL; 383 384 scb->status = STATUS_QUEUED; 385 386 TAILQ_INSERT_HEAD(&sc->sc_pendscb, scb, chain); 387 388 splx(s); 389 } 390 391 /* 392 * iha_del_pend_scb - remove scb from sc_pendscb 393 */ 394 static inline void 395 iha_del_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 396 { 397 int s; 398 399 s = splbio(); 400 401 TAILQ_REMOVE(&sc->sc_pendscb, scb, chain); 402 403 splx(s); 404 } 405 406 static inline void 407 iha_mark_busy_scb(struct iha_scb *scb) 408 { 409 int s; 410 411 s = splbio(); 412 413 scb->status = STATUS_BUSY; 414 415 if (scb->scb_tagmsg == 0) 416 scb->tcs->ntagscb = scb; 417 else 418 scb->tcs->tagcnt++; 419 420 splx(s); 421 } 422 423 /* 424 * iha_set_ssig - read the current scsi signal mask, then write a new 425 * one which turns off/on the specified signals. 426 */ 427 static inline void 428 iha_set_ssig(struct iha_softc *sc, uint8_t offsigs, uint8_t onsigs) 429 { 430 bus_space_tag_t iot = sc->sc_iot; 431 bus_space_handle_t ioh = sc->sc_ioh; 432 uint8_t currsigs; 433 434 currsigs = bus_space_read_1(iot, ioh, TUL_SSIGI); 435 bus_space_write_1(iot, ioh, TUL_SSIGO, (currsigs & ~offsigs) | onsigs); 436 } 437 438 /* 439 * iha_intr - the interrupt service routine for the iha driver 440 */ 441 int 442 iha_intr(void *arg) 443 { 444 bus_space_tag_t iot; 445 bus_space_handle_t ioh; 446 struct iha_softc *sc; 447 int s; 448 449 sc = (struct iha_softc *)arg; 450 iot = sc->sc_iot; 451 ioh = sc->sc_ioh; 452 453 if ((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 454 return (0); 455 456 s = splbio(); /* XXX - Or are interrupts off when ISR's are called? */ 457 458 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 459 /* XXX - need these inside a splbio()/splx()? */ 460 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 461 sc->sc_semaph = SEMAPH_IN_MAIN; 462 463 iha_main(sc); 464 465 sc->sc_semaph = ~SEMAPH_IN_MAIN; 466 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 467 } 468 469 splx(s); 470 471 return (1); 472 } 473 474 void 475 iha_attach(struct iha_softc *sc) 476 { 477 bus_space_tag_t iot = sc->sc_iot; 478 bus_space_handle_t ioh = sc->sc_ioh; 479 struct iha_scb *scb; 480 struct iha_eeprom eeprom; 481 struct eeprom_adapter *conf; 482 int i, error, reg; 483 484 iha_read_eeprom(sc, &eeprom); 485 486 conf = &eeprom.adapter[0]; 487 488 /* 489 * fill in the rest of the iha_softc fields 490 */ 491 sc->sc_id = CFG_ID(conf->config1); 492 sc->sc_semaph = ~SEMAPH_IN_MAIN; 493 sc->sc_status0 = 0; 494 sc->sc_actscb = NULL; 495 496 TAILQ_INIT(&sc->sc_freescb); 497 TAILQ_INIT(&sc->sc_pendscb); 498 TAILQ_INIT(&sc->sc_donescb); 499 error = iha_alloc_sglist(sc); 500 if (error != 0) { 501 printf(": cannot allocate sglist\n"); 502 return; 503 } 504 505 sc->sc_scb = malloc(sizeof(struct iha_scb) * IHA_MAX_SCB, 506 M_DEVBUF, M_NOWAIT|M_ZERO); 507 if (sc->sc_scb == NULL) { 508 printf(": cannot allocate SCB\n"); 509 return; 510 } 511 512 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) { 513 scb->scb_tagid = i; 514 scb->sgoffset = IHA_SG_SIZE * i; 515 scb->sglist = sc->sc_sglist + IHA_MAX_SG_ENTRIES * i; 516 scb->sg_addr = 517 sc->sc_dmamap->dm_segs[0].ds_addr + scb->sgoffset; 518 519 error = bus_dmamap_create(sc->sc_dmat, 520 MAXPHYS, IHA_MAX_SG_ENTRIES, MAXPHYS, 0, 521 BUS_DMA_NOWAIT, &scb->dmap); 522 523 if (error != 0) { 524 printf(": couldn't create SCB DMA map, error = %d\n", 525 error); 526 return; 527 } 528 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 529 } 530 531 /* Mask all the interrupts */ 532 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 533 534 /* Stop any I/O and reset the scsi module */ 535 iha_reset_dma(sc); 536 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSMOD); 537 538 /* Program HBA's SCSI ID */ 539 bus_space_write_1(iot, ioh, TUL_SID, sc->sc_id << 4); 540 541 /* 542 * Configure the channel as requested by the NVRAM settings read 543 * by iha_read_eeprom() above. 544 */ 545 546 sc->sc_sconf1 = SCONFIG0DEFAULT; 547 if ((conf->config1 & CFG_EN_PAR) != 0) 548 sc->sc_sconf1 |= SPCHK; 549 bus_space_write_1(iot, ioh, TUL_SCONFIG0, sc->sc_sconf1); 550 551 /* set selection time out 250 ms */ 552 bus_space_write_1(iot, ioh, TUL_STIMO, STIMO_250MS); 553 554 /* Enable desired SCSI termination configuration read from eeprom */ 555 reg = 0; 556 if (conf->config1 & CFG_ACT_TERM1) 557 reg |= ENTMW; 558 if (conf->config1 & CFG_ACT_TERM2) 559 reg |= ENTM; 560 bus_space_write_1(iot, ioh, TUL_DCTRL0, reg); 561 562 reg = bus_space_read_1(iot, ioh, TUL_GCTRL1) & ~ATDEN; 563 if (conf->config1 & CFG_AUTO_TERM) 564 reg |= ATDEN; 565 bus_space_write_1(iot, ioh, TUL_GCTRL1, reg); 566 567 for (i = 0; i < IHA_MAX_TARGETS / 2; i++) { 568 sc->sc_tcs[i * 2 ].flags = EEP_LBYTE(conf->tflags[i]); 569 sc->sc_tcs[i * 2 + 1].flags = EEP_HBYTE(conf->tflags[i]); 570 iha_reset_tcs(&sc->sc_tcs[i * 2 ], sc->sc_sconf1); 571 iha_reset_tcs(&sc->sc_tcs[i * 2 + 1], sc->sc_sconf1); 572 } 573 574 iha_reset_chip(sc); 575 bus_space_write_1(iot, ioh, TUL_SIEN, ALL_INTERRUPTS); 576 577 /* 578 * fill in the adapter. 579 */ 580 sc->sc_adapter.adapt_dev = &sc->sc_dev; 581 sc->sc_adapter.adapt_nchannels = 1; 582 sc->sc_adapter.adapt_openings = IHA_MAX_SCB; 583 sc->sc_adapter.adapt_max_periph = IHA_MAX_SCB; 584 sc->sc_adapter.adapt_ioctl = NULL; 585 sc->sc_adapter.adapt_minphys = minphys; 586 sc->sc_adapter.adapt_request = iha_scsipi_request; 587 588 /* 589 * fill in the channel. 590 */ 591 sc->sc_channel.chan_adapter = &sc->sc_adapter; 592 sc->sc_channel.chan_bustype = &scsi_bustype; 593 sc->sc_channel.chan_channel = 0; 594 sc->sc_channel.chan_ntargets = CFG_TARGET(conf->config2); 595 sc->sc_channel.chan_nluns = 8; 596 sc->sc_channel.chan_id = sc->sc_id; 597 598 /* 599 * Now try to attach all the sub devices. 600 */ 601 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 602 } 603 604 /* 605 * iha_alloc_sglist - allocate and map sglist for SCB's 606 */ 607 static int 608 iha_alloc_sglist(struct iha_softc *sc) 609 { 610 bus_dma_segment_t seg; 611 int error, rseg; 612 613 /* 614 * Allocate DMA-safe memory for the SCB's sglist 615 */ 616 if ((error = bus_dmamem_alloc(sc->sc_dmat, 617 IHA_SG_SIZE * IHA_MAX_SCB, 618 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 619 printf(": unable to allocate sglist, error = %d\n", error); 620 return (error); 621 } 622 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 623 IHA_SG_SIZE * IHA_MAX_SCB, (caddr_t *)&sc->sc_sglist, 624 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 625 printf(": unable to map sglist, error = %d\n", error); 626 return (error); 627 } 628 629 /* 630 * Create and load the DMA map used for the SCBs 631 */ 632 if ((error = bus_dmamap_create(sc->sc_dmat, 633 IHA_SG_SIZE * IHA_MAX_SCB, 1, IHA_SG_SIZE * IHA_MAX_SCB, 634 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 635 printf(": unable to create control DMA map, error = %d\n", 636 error); 637 return (error); 638 } 639 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 640 sc->sc_sglist, IHA_SG_SIZE * IHA_MAX_SCB, 641 NULL, BUS_DMA_NOWAIT)) != 0) { 642 printf(": unable to load control DMA map, error = %d\n", error); 643 return (error); 644 } 645 646 memset(sc->sc_sglist, 0, IHA_SG_SIZE * IHA_MAX_SCB); 647 648 return (0); 649 } 650 651 void 652 iha_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 653 void *arg) 654 { 655 struct scsipi_xfer *xs; 656 struct scsipi_periph *periph; 657 struct iha_scb *scb; 658 struct iha_softc *sc; 659 int error, s; 660 661 sc = (struct iha_softc *)chan->chan_adapter->adapt_dev; 662 663 switch (req) { 664 case ADAPTER_REQ_RUN_XFER: 665 xs = arg; 666 periph = xs->xs_periph; 667 668 /* XXX This size isn't actually a hardware restriction. */ 669 if (xs->cmdlen > sizeof(scb->cmd) || 670 periph->periph_target >= IHA_MAX_TARGETS) { 671 xs->error = XS_DRIVER_STUFFUP; 672 scsipi_done(xs); 673 return; 674 } 675 676 s = splbio(); 677 scb = TAILQ_FIRST(&sc->sc_freescb); 678 if (scb != NULL) { 679 scb->status = STATUS_RENT; 680 TAILQ_REMOVE(&sc->sc_freescb, scb, chain); 681 } 682 #ifdef DIAGNOSTIC 683 else { 684 scsipi_printaddr(periph); 685 printf("unable to allocate scb\n"); 686 panic("iha_scsipi_request"); 687 } 688 #endif 689 splx(s); 690 691 scb->target = periph->periph_target; 692 scb->lun = periph->periph_lun; 693 scb->tcs = &sc->sc_tcs[scb->target]; 694 scb->scb_id = MSG_IDENTIFY(periph->periph_lun, 695 (xs->xs_control & XS_CTL_REQSENSE) == 0); 696 697 scb->xs = xs; 698 scb->cmdlen = xs->cmdlen; 699 memcpy(&scb->cmd, xs->cmd, xs->cmdlen); 700 scb->buflen = xs->datalen; 701 scb->flags = 0; 702 if (xs->xs_control & XS_CTL_DATA_OUT) 703 scb->flags |= FLAG_DATAOUT; 704 if (xs->xs_control & XS_CTL_DATA_IN) 705 scb->flags |= FLAG_DATAIN; 706 707 if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 708 error = bus_dmamap_load(sc->sc_dmat, scb->dmap, 709 xs->data, scb->buflen, NULL, 710 ((xs->xs_control & XS_CTL_NOSLEEP) ? 711 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 712 BUS_DMA_STREAMING | 713 ((scb->flags & FLAG_DATAIN) ? 714 BUS_DMA_READ : BUS_DMA_WRITE)); 715 716 if (error) { 717 printf("%s: error %d loading DMA map\n", 718 sc->sc_dev.dv_xname, error); 719 iha_append_free_scb(sc, scb); 720 xs->error = XS_DRIVER_STUFFUP; 721 scsipi_done(xs); 722 return; 723 } 724 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 725 0, scb->dmap->dm_mapsize, 726 (scb->flags & FLAG_DATAIN) ? 727 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 728 } 729 730 iha_exec_scb(sc, scb); 731 return; 732 733 case ADAPTER_REQ_GROW_RESOURCES: 734 return; /* XXX */ 735 736 case ADAPTER_REQ_SET_XFER_MODE: 737 { 738 struct tcs *tcs; 739 struct scsipi_xfer_mode *xm = arg; 740 741 tcs = &sc->sc_tcs[xm->xm_target]; 742 743 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 744 (tcs->flags & FLAG_NO_WIDE) == 0) 745 tcs->flags &= ~(FLAG_WIDE_DONE|FLAG_SYNC_DONE); 746 747 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 748 (tcs->flags & FLAG_NO_SYNC) == 0) 749 tcs->flags &= ~FLAG_SYNC_DONE; 750 751 /* 752 * If we're not going to negotiate, send the 753 * notification now, since it won't happen later. 754 */ 755 if ((tcs->flags & (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) == 756 (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) 757 iha_update_xfer_mode(sc, xm->xm_target); 758 759 return; 760 } 761 } 762 } 763 764 void 765 iha_update_xfer_mode(struct iha_softc *sc, int target) 766 { 767 struct tcs *tcs = &sc->sc_tcs[target]; 768 struct scsipi_xfer_mode xm; 769 770 xm.xm_target = target; 771 xm.xm_mode = 0; 772 xm.xm_period = 0; 773 xm.xm_offset = 0; 774 775 if (tcs->syncm & PERIOD_WIDE_SCSI) 776 xm.xm_mode |= PERIPH_CAP_WIDE16; 777 778 if (tcs->period) { 779 xm.xm_mode |= PERIPH_CAP_SYNC; 780 xm.xm_period = tcs->period; 781 xm.xm_offset = tcs->offset; 782 } 783 784 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 785 } 786 787 static void 788 iha_reset_scsi_bus(struct iha_softc *sc) 789 { 790 struct iha_scb *scb; 791 struct tcs *tcs; 792 int i, s; 793 794 s = splbio(); 795 796 iha_reset_dma(sc); 797 798 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 799 switch (scb->status) { 800 case STATUS_BUSY: 801 iha_append_done_scb(sc, scb, HOST_SCSI_RST); 802 break; 803 804 case STATUS_SELECT: 805 iha_push_pend_scb(sc, scb); 806 break; 807 808 default: 809 break; 810 } 811 812 for (i = 0, tcs = sc->sc_tcs; i < IHA_MAX_TARGETS; i++, tcs++) 813 iha_reset_tcs(tcs, sc->sc_sconf1); 814 815 splx(s); 816 } 817 818 void 819 iha_reset_chip(struct iha_softc *sc) 820 { 821 bus_space_tag_t iot = sc->sc_iot; 822 bus_space_handle_t ioh = sc->sc_ioh; 823 824 /* reset tulip chip */ 825 826 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSCSI); 827 828 do { 829 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 830 } while ((sc->sc_sistat & SRSTD) == 0); 831 832 iha_set_ssig(sc, 0, 0); 833 834 bus_space_read_1(iot, ioh, TUL_SISTAT); /* Clear any active interrupt*/ 835 } 836 837 /* 838 * iha_reset_dma - abort any active DMA xfer, reset tulip FIFO. 839 */ 840 static void 841 iha_reset_dma(struct iha_softc *sc) 842 { 843 bus_space_tag_t iot = sc->sc_iot; 844 bus_space_handle_t ioh = sc->sc_ioh; 845 846 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 847 /* if DMA xfer is pending, abort DMA xfer */ 848 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 849 /* wait Abort DMA xfer done */ 850 while ((bus_space_read_1(iot, ioh, TUL_ISTUS0) & DABT) == 0) 851 ; 852 } 853 854 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 855 } 856 857 /* 858 * iha_reset_tcs - reset the target control structure pointed 859 * to by tcs to default values. tcs flags 860 * only has the negotiation done bits reset as 861 * the other bits are fixed at initialization. 862 */ 863 static void 864 iha_reset_tcs(struct tcs *tcs, uint8_t config0) 865 { 866 867 tcs->flags &= ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 868 tcs->period = 0; 869 tcs->offset = 0; 870 tcs->tagcnt = 0; 871 tcs->ntagscb = NULL; 872 tcs->syncm = 0; 873 tcs->sconfig0 = config0; 874 } 875 876 /* 877 * iha_main - process the active SCB, taking one off pending and making it 878 * active if necessary, and any done SCB's created as 879 * a result until there are no interrupts pending and no pending 880 * SCB's that can be started. 881 */ 882 static void 883 iha_main(struct iha_softc *sc) 884 { 885 bus_space_tag_t iot = sc->sc_iot; 886 bus_space_handle_t ioh =sc->sc_ioh; 887 struct iha_scb *scb; 888 889 for (;;) { 890 iha_scsi(sc); 891 892 while ((scb = iha_pop_done_scb(sc)) != NULL) 893 iha_done_scb(sc, scb); 894 895 /* 896 * If there are no interrupts pending, or we can't start 897 * a pending sc, break out of the for(;;). Otherwise 898 * continue the good work with another call to 899 * iha_scsi(). 900 */ 901 if (((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 902 && (iha_find_pend_scb(sc) == NULL)) 903 break; 904 } 905 } 906 907 /* 908 * iha_scsi - service any outstanding interrupts. If there are none, try to 909 * start another SCB currently in the pending queue. 910 */ 911 static void 912 iha_scsi(struct iha_softc *sc) 913 { 914 bus_space_tag_t iot = sc->sc_iot; 915 bus_space_handle_t ioh = sc->sc_ioh; 916 struct iha_scb *scb; 917 struct tcs *tcs; 918 uint8_t stat; 919 920 /* service pending interrupts asap */ 921 922 stat = bus_space_read_1(iot, ioh, TUL_STAT0); 923 if ((stat & INTPD) != 0) { 924 sc->sc_status0 = stat; 925 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 926 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 927 928 sc->sc_phase = sc->sc_status0 & PH_MASK; 929 930 if ((sc->sc_sistat & SRSTD) != 0) { 931 iha_reset_scsi_bus(sc); 932 return; 933 } 934 935 if ((sc->sc_sistat & RSELED) != 0) { 936 iha_resel(sc); 937 return; 938 } 939 940 if ((sc->sc_sistat & (STIMEO | DISCD)) != 0) { 941 iha_busfree(sc); 942 return; 943 } 944 945 if ((sc->sc_sistat & (SCMDN | SBSRV)) != 0) { 946 iha_next_state(sc); 947 return; 948 } 949 950 if ((sc->sc_sistat & SELED) != 0) 951 iha_set_ssig(sc, 0, 0); 952 } 953 954 /* 955 * There were no interrupts pending which required action elsewhere, so 956 * see if it is possible to start the selection phase on a pending SCB 957 */ 958 if ((scb = iha_find_pend_scb(sc)) == NULL) 959 return; 960 961 tcs = scb->tcs; 962 963 /* program HBA's SCSI ID & target SCSI ID */ 964 bus_space_write_1(iot, ioh, TUL_SID, (sc->sc_id << 4) | scb->target); 965 966 if ((scb->xs->xs_control & XS_CTL_RESET) == 0) { 967 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 968 969 if ((tcs->flags & FLAG_NO_NEG_SYNC) == 0 || 970 (tcs->flags & FLAG_NO_NEG_WIDE) == 0) 971 iha_select(sc, scb, SELATNSTOP); 972 973 else if (scb->scb_tagmsg != 0) 974 iha_select(sc, scb, SEL_ATN3); 975 976 else 977 iha_select(sc, scb, SEL_ATN); 978 979 } else { 980 iha_select(sc, scb, SELATNSTOP); 981 scb->nextstat = 8; 982 } 983 984 if ((scb->xs->xs_control & XS_CTL_POLL) != 0) { 985 int timeout; 986 for (timeout = scb->xs->timeout; timeout > 0; timeout--) { 987 if (iha_wait(sc, NO_OP) == -1) 988 break; 989 if (iha_next_state(sc) == -1) 990 break; 991 delay(1000); /* Only happens in boot, so it's ok */ 992 } 993 994 /* 995 * Since done queue processing not done until AFTER this 996 * function returns, scb is on the done queue, not 997 * the free queue at this point and still has valid data 998 * 999 * Conversely, xs->error has not been set yet 1000 */ 1001 if (timeout == 0) 1002 iha_timeout(scb); 1003 } 1004 } 1005 1006 static void 1007 iha_select(struct iha_softc *sc, struct iha_scb *scb, uint8_t select_type) 1008 { 1009 bus_space_tag_t iot = sc->sc_iot; 1010 bus_space_handle_t ioh = sc->sc_ioh; 1011 1012 switch (select_type) { 1013 case SEL_ATN: 1014 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1015 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1016 scb->cmd, scb->cmdlen); 1017 1018 scb->nextstat = 2; 1019 break; 1020 1021 case SELATNSTOP: 1022 scb->nextstat = 1; 1023 break; 1024 1025 case SEL_ATN3: 1026 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1027 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagmsg); 1028 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagid); 1029 1030 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, scb->cmd, 1031 scb->cmdlen); 1032 1033 scb->nextstat = 2; 1034 break; 1035 1036 default: 1037 printf("[debug] iha_select() - unknown select type = 0x%02x\n", 1038 select_type); 1039 return; 1040 } 1041 1042 iha_del_pend_scb(sc, scb); 1043 scb->status = STATUS_SELECT; 1044 1045 sc->sc_actscb = scb; 1046 1047 bus_space_write_1(iot, ioh, TUL_SCMD, select_type); 1048 } 1049 1050 /* 1051 * iha_wait - wait for an interrupt to service or a SCSI bus phase change 1052 * after writing the supplied command to the tulip chip. If 1053 * the command is NO_OP, skip the command writing. 1054 */ 1055 static int 1056 iha_wait(struct iha_softc *sc, uint8_t cmd) 1057 { 1058 bus_space_tag_t iot = sc->sc_iot; 1059 bus_space_handle_t ioh = sc->sc_ioh; 1060 1061 if (cmd != NO_OP) 1062 bus_space_write_1(iot, ioh, TUL_SCMD, cmd); 1063 1064 /* 1065 * Have to do this here, in addition to in iha_isr, because 1066 * interrupts might be turned off when we get here. 1067 */ 1068 do { 1069 sc->sc_status0 = bus_space_read_1(iot, ioh, TUL_STAT0); 1070 } while ((sc->sc_status0 & INTPD) == 0); 1071 1072 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 1073 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 1074 1075 sc->sc_phase = sc->sc_status0 & PH_MASK; 1076 1077 if ((sc->sc_sistat & SRSTD) != 0) { 1078 /* SCSI bus reset interrupt */ 1079 iha_reset_scsi_bus(sc); 1080 return (-1); 1081 } 1082 1083 if ((sc->sc_sistat & RSELED) != 0) 1084 /* Reselection interrupt */ 1085 return (iha_resel(sc)); 1086 1087 if ((sc->sc_sistat & STIMEO) != 0) { 1088 /* selected/reselected timeout interrupt */ 1089 iha_busfree(sc); 1090 return (-1); 1091 } 1092 1093 if ((sc->sc_sistat & DISCD) != 0) { 1094 /* BUS disconnection interrupt */ 1095 if ((sc->sc_flags & FLAG_EXPECT_DONE_DISC) != 0) { 1096 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1097 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 1098 SCONFIG0DEFAULT); 1099 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1100 iha_append_done_scb(sc, sc->sc_actscb, HOST_OK); 1101 sc->sc_flags &= ~FLAG_EXPECT_DONE_DISC; 1102 1103 } else if ((sc->sc_flags & FLAG_EXPECT_DISC) != 0) { 1104 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1105 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 1106 SCONFIG0DEFAULT); 1107 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1108 sc->sc_actscb = NULL; 1109 sc->sc_flags &= ~FLAG_EXPECT_DISC; 1110 1111 } else 1112 iha_busfree(sc); 1113 1114 return (-1); 1115 } 1116 1117 return (sc->sc_phase); 1118 } 1119 1120 static void 1121 iha_exec_scb(struct iha_softc *sc, struct iha_scb *scb) 1122 { 1123 bus_space_tag_t iot; 1124 bus_space_handle_t ioh; 1125 bus_dmamap_t dm; 1126 struct scsipi_xfer *xs = scb->xs; 1127 int nseg, s; 1128 1129 dm = scb->dmap; 1130 nseg = dm->dm_nsegs; 1131 1132 if (nseg > 1) { 1133 struct iha_sg_element *sg = scb->sglist; 1134 int i; 1135 1136 for (i = 0; i < nseg; i++) { 1137 sg[i].sg_len = htole32(dm->dm_segs[i].ds_len); 1138 sg[i].sg_addr = htole32(dm->dm_segs[i].ds_addr); 1139 } 1140 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1141 scb->sgoffset, IHA_SG_SIZE, 1142 BUS_DMASYNC_PREWRITE); 1143 1144 scb->flags |= FLAG_SG; 1145 scb->sg_size = scb->sg_max = nseg; 1146 scb->sg_index = 0; 1147 1148 scb->bufaddr = scb->sg_addr; 1149 } else 1150 scb->bufaddr = dm->dm_segs[0].ds_addr; 1151 1152 if ((xs->xs_control & XS_CTL_POLL) == 0) { 1153 int timeout = mstohz(xs->timeout); 1154 if (timeout == 0) 1155 timeout = 1; 1156 callout_reset(&xs->xs_callout, timeout, iha_timeout, scb); 1157 } 1158 1159 s = splbio(); 1160 1161 if (((scb->xs->xs_control & XS_RESET) != 0) || 1162 (scb->cmd[0] == SCSI_REQUEST_SENSE)) 1163 iha_push_pend_scb(sc, scb); /* Insert SCB at head of Pend */ 1164 else 1165 iha_append_pend_scb(sc, scb); /* Append SCB to tail of Pend */ 1166 1167 /* 1168 * Run through iha_main() to ensure something is active, if 1169 * only this new SCB. 1170 */ 1171 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 1172 iot = sc->sc_iot; 1173 ioh = sc->sc_ioh; 1174 1175 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 1176 sc->sc_semaph = SEMAPH_IN_MAIN; 1177 1178 splx(s); 1179 iha_main(sc); 1180 s = splbio(); 1181 1182 sc->sc_semaph = ~SEMAPH_IN_MAIN; 1183 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 1184 } 1185 1186 splx(s); 1187 } 1188 1189 /* 1190 * iha_done_scb - We have a scb which has been processed by the 1191 * adaptor, now we look to see how the operation went. 1192 */ 1193 static void 1194 iha_done_scb(struct iha_softc *sc, struct iha_scb *scb) 1195 { 1196 struct scsipi_xfer *xs = scb->xs; 1197 1198 if (xs != NULL) { 1199 /* Cancel the timeout. */ 1200 callout_stop(&xs->xs_callout); 1201 1202 if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 1203 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 1204 0, scb->dmap->dm_mapsize, 1205 (scb->flags & FLAG_DATAIN) ? 1206 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1207 bus_dmamap_unload(sc->sc_dmat, scb->dmap); 1208 } 1209 1210 xs->status = scb->ta_stat; 1211 1212 switch (scb->ha_stat) { 1213 case HOST_OK: 1214 switch (scb->ta_stat) { 1215 case SCSI_OK: 1216 case SCSI_CONDITION_MET: 1217 case SCSI_INTERM: 1218 case SCSI_INTERM_COND_MET: 1219 xs->resid = scb->buflen; 1220 xs->error = XS_NOERROR; 1221 if ((scb->flags & FLAG_RSENS) != 0) 1222 xs->error = XS_SENSE; 1223 break; 1224 1225 case SCSI_RESV_CONFLICT: 1226 case SCSI_BUSY: 1227 case SCSI_QUEUE_FULL: 1228 xs->error = XS_BUSY; 1229 break; 1230 1231 case SCSI_TERMINATED: 1232 case SCSI_ACA_ACTIVE: 1233 case SCSI_CHECK: 1234 scb->tcs->flags &= 1235 ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 1236 1237 if ((scb->flags & FLAG_RSENS) != 0 || 1238 iha_push_sense_request(sc, scb) != 0) { 1239 scb->flags &= ~FLAG_RSENS; 1240 printf("%s: request sense failed\n", 1241 sc->sc_dev.dv_xname); 1242 xs->error = XS_DRIVER_STUFFUP; 1243 break; 1244 } 1245 1246 xs->error = XS_SENSE; 1247 return; 1248 1249 default: 1250 xs->error = XS_DRIVER_STUFFUP; 1251 break; 1252 } 1253 break; 1254 1255 case HOST_SEL_TOUT: 1256 xs->error = XS_SELTIMEOUT; 1257 break; 1258 1259 case HOST_SCSI_RST: 1260 case HOST_DEV_RST: 1261 xs->error = XS_RESET; 1262 break; 1263 1264 case HOST_SPERR: 1265 printf("%s: SCSI Parity error detected\n", 1266 sc->sc_dev.dv_xname); 1267 xs->error = XS_DRIVER_STUFFUP; 1268 break; 1269 1270 case HOST_TIMED_OUT: 1271 xs->error = XS_TIMEOUT; 1272 break; 1273 1274 case HOST_DO_DU: 1275 case HOST_BAD_PHAS: 1276 default: 1277 xs->error = XS_DRIVER_STUFFUP; 1278 break; 1279 } 1280 1281 scsipi_done(xs); 1282 } 1283 1284 iha_append_free_scb(sc, scb); 1285 } 1286 1287 /* 1288 * iha_push_sense_request - obtain auto sense data by pushing the 1289 * SCB needing it back onto the pending 1290 * queue with a REQUEST_SENSE CDB. 1291 */ 1292 static int 1293 iha_push_sense_request(struct iha_softc *sc, struct iha_scb *scb) 1294 { 1295 struct scsipi_xfer *xs = scb->xs; 1296 struct scsipi_periph *periph = xs->xs_periph; 1297 struct scsi_request_sense *ss = (struct scsi_request_sense *)scb->cmd; 1298 int lun = periph->periph_lun; 1299 int err; 1300 1301 memset(ss, 0, sizeof(*ss)); 1302 ss->opcode = SCSI_REQUEST_SENSE; 1303 ss->byte2 = lun << SCSI_CMD_LUN_SHIFT; 1304 ss->length = sizeof(struct scsi_sense_data); 1305 1306 scb->flags = FLAG_RSENS | FLAG_DATAIN; 1307 1308 scb->scb_id &= ~MSG_IDENTIFY_DISCFLAG; 1309 1310 scb->scb_tagmsg = 0; 1311 scb->ta_stat = SCSI_OK; 1312 1313 scb->cmdlen = sizeof(struct scsi_request_sense); 1314 scb->buflen = ss->length; 1315 1316 err = bus_dmamap_load(sc->sc_dmat, scb->dmap, 1317 &xs->sense.scsi_sense, scb->buflen, NULL, 1318 BUS_DMA_READ|BUS_DMA_NOWAIT); 1319 if (err != 0) { 1320 printf("iha_push_sense_request: cannot bus_dmamap_load()\n"); 1321 xs->error = XS_DRIVER_STUFFUP; 1322 return 1; 1323 } 1324 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 1325 0, scb->buflen, BUS_DMASYNC_PREREAD); 1326 1327 /* XXX What about queued command? */ 1328 iha_exec_scb(sc, scb); 1329 1330 return 0; 1331 } 1332 1333 static void 1334 iha_timeout(void *arg) 1335 { 1336 struct iha_scb *scb = (struct iha_scb *)arg; 1337 struct scsipi_xfer *xs = scb->xs; 1338 struct scsipi_periph *periph; 1339 struct iha_softc *sc; 1340 1341 if (xs == NULL) { 1342 printf("[debug] iha_timeout called with xs == NULL\n"); 1343 return; 1344 } 1345 1346 periph = xs->xs_periph; 1347 1348 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1349 1350 scsipi_printaddr(periph); 1351 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1352 iha_abort_xs(sc, xs, HOST_TIMED_OUT); 1353 } 1354 1355 /* 1356 * iha_abort_xs - find the SCB associated with the supplied xs and 1357 * stop all processing on it, moving it to the done 1358 * queue with the supplied host status value. 1359 */ 1360 static void 1361 iha_abort_xs(struct iha_softc *sc, struct scsipi_xfer *xs, uint8_t hastat) 1362 { 1363 struct iha_scb *scb; 1364 int i, s; 1365 1366 s = splbio(); 1367 1368 /* Check the pending queue for the SCB pointing to xs */ 1369 1370 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) 1371 if (scb->xs == xs) { 1372 iha_del_pend_scb(sc, scb); 1373 iha_append_done_scb(sc, scb, hastat); 1374 splx(s); 1375 return; 1376 } 1377 1378 /* 1379 * If that didn't work, check all BUSY/SELECTING SCB's for one 1380 * pointing to xs 1381 */ 1382 1383 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1384 switch (scb->status) { 1385 case STATUS_BUSY: 1386 case STATUS_SELECT: 1387 if (scb->xs == xs) { 1388 iha_append_done_scb(sc, scb, hastat); 1389 splx(s); 1390 return; 1391 } 1392 break; 1393 default: 1394 break; 1395 } 1396 1397 splx(s); 1398 } 1399 1400 /* 1401 * iha_data_over_run - return HOST_OK for all SCSI opcodes where BufLen 1402 * is an 'Allocation Length'. All other SCSI opcodes 1403 * get HOST_DO_DU as they SHOULD have xferred all the 1404 * data requested. 1405 * 1406 * The list of opcodes using 'Allocation Length' was 1407 * found by scanning all the SCSI-3 T10 drafts. See 1408 * www.t10.org for the curious with a .pdf reader. 1409 */ 1410 static uint8_t 1411 iha_data_over_run(struct iha_scb *scb) 1412 { 1413 switch (scb->cmd[0]) { 1414 case 0x03: /* Request Sense SPC-2 */ 1415 case 0x12: /* Inquiry SPC-2 */ 1416 case 0x1a: /* Mode Sense (6 byte version) SPC-2 */ 1417 case 0x1c: /* Receive Diagnostic Results SPC-2 */ 1418 case 0x23: /* Read Format Capacities MMC-2 */ 1419 case 0x29: /* Read Generation SBC */ 1420 case 0x34: /* Read Position SSC-2 */ 1421 case 0x37: /* Read Defect Data SBC */ 1422 case 0x3c: /* Read Buffer SPC-2 */ 1423 case 0x42: /* Read Sub Channel MMC-2 */ 1424 case 0x43: /* Read TOC/PMA/ATIP MMC */ 1425 1426 /* XXX - 2 with same opcode of 0x44? */ 1427 case 0x44: /* Read Header/Read Density Suprt MMC/SSC*/ 1428 1429 case 0x46: /* Get Configuration MMC-2 */ 1430 case 0x4a: /* Get Event/Status Notification MMC-2 */ 1431 case 0x4d: /* Log Sense SPC-2 */ 1432 case 0x51: /* Read Disc Information MMC */ 1433 case 0x52: /* Read Track Information MMC */ 1434 case 0x59: /* Read Master CUE MMC */ 1435 case 0x5a: /* Mode Sense (10 byte version) SPC-2 */ 1436 case 0x5c: /* Read Buffer Capacity MMC */ 1437 case 0x5e: /* Persistent Reserve In SPC-2 */ 1438 case 0x84: /* Receive Copy Results SPC-2 */ 1439 case 0xa0: /* Report LUNs SPC-2 */ 1440 case 0xa3: /* Various Report requests SBC-2/SCC-2*/ 1441 case 0xa4: /* Report Key MMC-2 */ 1442 case 0xad: /* Read DVD Structure MMC-2 */ 1443 case 0xb4: /* Read Element Status (Attached) SMC */ 1444 case 0xb5: /* Request Volume Element Address SMC */ 1445 case 0xb7: /* Read Defect Data (12 byte ver.) SBC */ 1446 case 0xb8: /* Read Element Status (Independ.) SMC */ 1447 case 0xba: /* Report Redundancy SCC-2 */ 1448 case 0xbd: /* Mechanism Status MMC */ 1449 case 0xbe: /* Report Basic Redundancy SCC-2 */ 1450 1451 return (HOST_OK); 1452 1453 default: 1454 return (HOST_DO_DU); 1455 } 1456 } 1457 1458 /* 1459 * iha_next_state - process the current SCB as requested in its 1460 * nextstat member. 1461 */ 1462 static int 1463 iha_next_state(struct iha_softc *sc) 1464 { 1465 1466 if (sc->sc_actscb == NULL) 1467 return (-1); 1468 1469 switch (sc->sc_actscb->nextstat) { 1470 case 1: 1471 if (iha_state_1(sc) == 3) 1472 goto state_3; 1473 break; 1474 1475 case 2: 1476 switch (iha_state_2(sc)) { 1477 case 3: 1478 goto state_3; 1479 case 4: 1480 goto state_4; 1481 default: 1482 break; 1483 } 1484 break; 1485 1486 case 3: 1487 state_3: 1488 if (iha_state_3(sc) == 4) 1489 goto state_4; 1490 break; 1491 1492 case 4: 1493 state_4: 1494 switch (iha_state_4(sc)) { 1495 case 0: 1496 return (0); 1497 case 6: 1498 goto state_6; 1499 default: 1500 break; 1501 } 1502 break; 1503 1504 case 5: 1505 switch (iha_state_5(sc)) { 1506 case 4: 1507 goto state_4; 1508 case 6: 1509 goto state_6; 1510 default: 1511 break; 1512 } 1513 break; 1514 1515 case 6: 1516 state_6: 1517 iha_state_6(sc); 1518 break; 1519 1520 case 8: 1521 iha_state_8(sc); 1522 break; 1523 1524 default: 1525 #ifdef IHA_DEBUG_STATE 1526 printf("[debug] -unknown state: %i-\n", 1527 sc->sc_actscb->nextstat); 1528 #endif 1529 iha_bad_seq(sc); 1530 break; 1531 } 1532 1533 return (-1); 1534 } 1535 1536 /* 1537 * iha_state_1 - selection is complete after a SELATNSTOP. If the target 1538 * has put the bus into MSG_OUT phase start wide/sync 1539 * negotiation. Otherwise clear the FIFO and go to state 3, 1540 * which will send the SCSI CDB to the target. 1541 */ 1542 static int 1543 iha_state_1(struct iha_softc *sc) 1544 { 1545 bus_space_tag_t iot = sc->sc_iot; 1546 bus_space_handle_t ioh = sc->sc_ioh; 1547 struct iha_scb *scb = sc->sc_actscb; 1548 struct tcs *tcs; 1549 int flags; 1550 1551 iha_mark_busy_scb(scb); 1552 1553 tcs = scb->tcs; 1554 1555 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 1556 1557 /* 1558 * If we are in PHASE_MSG_OUT, send 1559 * a) IDENT message (with tags if appropriate) 1560 * b) WDTR if the target is configured to negotiate wide xfers 1561 * ** OR ** 1562 * c) SDTR if the target is configured to negotiate sync xfers 1563 * but not wide ones 1564 * 1565 * If we are NOT, then the target is not asking for anything but 1566 * the data/command, so go straight to state 3. 1567 */ 1568 if (sc->sc_phase == PHASE_MSG_OUT) { 1569 bus_space_write_1(iot, ioh, TUL_SCTRL1, (ESBUSIN | EHRSL)); 1570 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1571 1572 if (scb->scb_tagmsg != 0) { 1573 bus_space_write_1(iot, ioh, TUL_SFIFO, 1574 scb->scb_tagmsg); 1575 bus_space_write_1(iot, ioh, TUL_SFIFO, 1576 scb->scb_tagid); 1577 } 1578 1579 flags = tcs->flags; 1580 if ((flags & FLAG_NO_NEG_WIDE) == 0) { 1581 if (iha_msgout_wdtr(sc) == -1) 1582 return (-1); 1583 } else if ((flags & FLAG_NO_NEG_SYNC) == 0) { 1584 if (iha_msgout_sdtr(sc) == -1) 1585 return (-1); 1586 } 1587 1588 } else { 1589 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1590 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1591 } 1592 1593 return (3); 1594 } 1595 1596 /* 1597 * iha_state_2 - selection is complete after a SEL_ATN or SEL_ATN3. If the SCSI 1598 * CDB has already been send, go to state 4 to start the data 1599 * xfer. Otherwise reset the FIFO and go to state 3, sending 1600 * the SCSI CDB. 1601 */ 1602 static int 1603 iha_state_2(struct iha_softc *sc) 1604 { 1605 bus_space_tag_t iot = sc->sc_iot; 1606 bus_space_handle_t ioh = sc->sc_ioh; 1607 struct iha_scb *scb = sc->sc_actscb; 1608 1609 iha_mark_busy_scb(scb); 1610 1611 bus_space_write_1(iot, ioh, TUL_SCONFIG0, scb->tcs->sconfig0); 1612 1613 if ((sc->sc_status1 & CPDNE) != 0) 1614 return (4); 1615 1616 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1617 1618 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1619 1620 return (3); 1621 } 1622 1623 /* 1624 * iha_state_3 - send the SCSI CDB to the target, processing any status 1625 * or other messages received until that is done or 1626 * abandoned. 1627 */ 1628 static int 1629 iha_state_3(struct iha_softc *sc) 1630 { 1631 bus_space_tag_t iot = sc->sc_iot; 1632 bus_space_handle_t ioh = sc->sc_ioh; 1633 struct iha_scb *scb = sc->sc_actscb; 1634 int flags; 1635 1636 for (;;) { 1637 switch (sc->sc_phase) { 1638 case PHASE_CMD_OUT: 1639 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1640 scb->cmd, scb->cmdlen); 1641 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1642 return (-1); 1643 else if (sc->sc_phase == PHASE_CMD_OUT) { 1644 iha_bad_seq(sc); 1645 return (-1); 1646 } else 1647 return (4); 1648 1649 case PHASE_MSG_IN: 1650 scb->nextstat = 3; 1651 if (iha_msgin(sc) == -1) 1652 return (-1); 1653 break; 1654 1655 case PHASE_STATUS_IN: 1656 if (iha_status_msg(sc) == -1) 1657 return (-1); 1658 break; 1659 1660 case PHASE_MSG_OUT: 1661 flags = scb->tcs->flags; 1662 if ((flags & FLAG_NO_NEG_SYNC) != 0) { 1663 if (iha_msgout(sc, MSG_NOOP) == -1) 1664 return (-1); 1665 } else if (iha_msgout_sdtr(sc) == -1) 1666 return (-1); 1667 break; 1668 1669 default: 1670 printf("[debug] -s3- bad phase = %d\n", sc->sc_phase); 1671 iha_bad_seq(sc); 1672 return (-1); 1673 } 1674 } 1675 } 1676 1677 /* 1678 * iha_state_4 - start a data xfer. Handle any bus state 1679 * transitions until PHASE_DATA_IN/_OUT 1680 * or the attempt is abandoned. If there is 1681 * no data to xfer, go to state 6 and finish 1682 * processing the current SCB. 1683 */ 1684 static int 1685 iha_state_4(struct iha_softc *sc) 1686 { 1687 struct iha_scb *scb = sc->sc_actscb; 1688 1689 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) == 1690 (FLAG_DATAIN | FLAG_DATAOUT)) 1691 return (6); /* Both dir flags set => NO xfer was requested */ 1692 1693 for (;;) { 1694 if (scb->buflen == 0) 1695 return (6); 1696 1697 switch (sc->sc_phase) { 1698 case PHASE_STATUS_IN: 1699 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1700 scb->ha_stat = iha_data_over_run(scb); 1701 if ((iha_status_msg(sc)) == -1) 1702 return (-1); 1703 break; 1704 1705 case PHASE_MSG_IN: 1706 scb->nextstat = 4; 1707 if (iha_msgin(sc) == -1) 1708 return (-1); 1709 break; 1710 1711 case PHASE_MSG_OUT: 1712 if ((sc->sc_status0 & SPERR) != 0) { 1713 scb->buflen = 0; 1714 scb->ha_stat = HOST_SPERR; 1715 if (iha_msgout(sc, MSG_INITIATOR_DET_ERR) == -1) 1716 return (-1); 1717 else 1718 return (6); 1719 } else { 1720 if (iha_msgout(sc, MSG_NOOP) == -1) 1721 return (-1); 1722 } 1723 break; 1724 1725 case PHASE_DATA_IN: 1726 return (iha_xfer_data(sc, scb, FLAG_DATAIN)); 1727 1728 case PHASE_DATA_OUT: 1729 return (iha_xfer_data(sc, scb, FLAG_DATAOUT)); 1730 1731 default: 1732 iha_bad_seq(sc); 1733 return (-1); 1734 } 1735 } 1736 } 1737 1738 /* 1739 * iha_state_5 - handle the partial or final completion of the current 1740 * data xfer. If DMA is still active stop it. If there is 1741 * more data to xfer, go to state 4 and start the xfer. 1742 * If not go to state 6 and finish the SCB. 1743 */ 1744 static int 1745 iha_state_5(struct iha_softc *sc) 1746 { 1747 bus_space_tag_t iot = sc->sc_iot; 1748 bus_space_handle_t ioh = sc->sc_ioh; 1749 struct iha_scb *scb = sc->sc_actscb; 1750 struct iha_sg_element *sg; 1751 uint32_t cnt; 1752 uint8_t period, stat; 1753 long xcnt; /* cannot use unsigned!! see code: if (xcnt < 0) */ 1754 int i; 1755 1756 cnt = bus_space_read_4(iot, ioh, TUL_STCNT0) & TCNT; 1757 1758 /* 1759 * Stop any pending DMA activity and check for parity error. 1760 */ 1761 1762 if ((bus_space_read_1(iot, ioh, TUL_DCMD) & XDIR) != 0) { 1763 /* Input Operation */ 1764 if ((sc->sc_status0 & SPERR) != 0) 1765 scb->ha_stat = HOST_SPERR; 1766 1767 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1768 bus_space_write_1(iot, ioh, TUL_DCTRL0, 1769 bus_space_read_1(iot, ioh, TUL_DCTRL0) | SXSTP); 1770 while (bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) 1771 ; 1772 } 1773 1774 } else { 1775 /* Output Operation */ 1776 if ((sc->sc_status1 & SXCMP) == 0) { 1777 period = scb->tcs->syncm; 1778 if ((period & PERIOD_WIDE_SCSI) != 0) 1779 cnt += (bus_space_read_1(iot, ioh, 1780 TUL_SFIFOCNT) & FIFOC) * 2; 1781 else 1782 cnt += bus_space_read_1(iot, ioh, 1783 TUL_SFIFOCNT) & FIFOC; 1784 } 1785 1786 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1787 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 1788 do 1789 stat = bus_space_read_1(iot, ioh, TUL_ISTUS0); 1790 while ((stat & DABT) == 0); 1791 } 1792 1793 if ((cnt == 1) && (sc->sc_phase == PHASE_DATA_OUT)) { 1794 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1795 return (-1); 1796 cnt = 0; 1797 1798 } else if ((sc->sc_status1 & SXCMP) == 0) 1799 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1800 } 1801 1802 if (cnt == 0) { 1803 scb->buflen = 0; 1804 return (6); 1805 } 1806 1807 /* Update active data pointer and restart the I/O at the new point */ 1808 1809 xcnt = scb->buflen - cnt; /* xcnt == bytes xferred */ 1810 scb->buflen = cnt; /* cnt == bytes left */ 1811 1812 if ((scb->flags & FLAG_SG) != 0) { 1813 sg = &scb->sglist[scb->sg_index]; 1814 for (i = scb->sg_index; i < scb->sg_max; sg++, i++) { 1815 xcnt -= le32toh(sg->sg_len); 1816 if (xcnt < 0) { 1817 xcnt += le32toh(sg->sg_len); 1818 1819 sg->sg_addr = 1820 htole32(le32toh(sg->sg_addr) + xcnt); 1821 sg->sg_len = 1822 htole32(le32toh(sg->sg_len) - xcnt); 1823 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1824 scb->sgoffset, IHA_SG_SIZE, 1825 BUS_DMASYNC_PREWRITE); 1826 1827 scb->bufaddr += (i - scb->sg_index) * 1828 sizeof(struct iha_sg_element); 1829 scb->sg_size = scb->sg_max - i; 1830 scb->sg_index = i; 1831 1832 return (4); 1833 } 1834 } 1835 return (6); 1836 1837 } else 1838 scb->bufaddr += xcnt; 1839 1840 return (4); 1841 } 1842 1843 /* 1844 * iha_state_6 - finish off the active scb (may require several 1845 * iterations if PHASE_MSG_IN) and return -1 to indicate 1846 * the bus is free. 1847 */ 1848 static int 1849 iha_state_6(struct iha_softc *sc) 1850 { 1851 1852 for (;;) { 1853 switch (sc->sc_phase) { 1854 case PHASE_STATUS_IN: 1855 if (iha_status_msg(sc) == -1) 1856 return (-1); 1857 break; 1858 1859 case PHASE_MSG_IN: 1860 sc->sc_actscb->nextstat = 6; 1861 if ((iha_msgin(sc)) == -1) 1862 return (-1); 1863 break; 1864 1865 case PHASE_MSG_OUT: 1866 if ((iha_msgout(sc, MSG_NOOP)) == -1) 1867 return (-1); 1868 break; 1869 1870 case PHASE_DATA_IN: 1871 if (iha_xpad_in(sc) == -1) 1872 return (-1); 1873 break; 1874 1875 case PHASE_DATA_OUT: 1876 if (iha_xpad_out(sc) == -1) 1877 return (-1); 1878 break; 1879 1880 default: 1881 iha_bad_seq(sc); 1882 return (-1); 1883 } 1884 } 1885 } 1886 1887 /* 1888 * iha_state_8 - reset the active device and all busy SCBs using it 1889 */ 1890 static int 1891 iha_state_8(struct iha_softc *sc) 1892 { 1893 bus_space_tag_t iot = sc->sc_iot; 1894 bus_space_handle_t ioh = sc->sc_ioh; 1895 struct iha_scb *scb; 1896 int i; 1897 uint8_t tar; 1898 1899 if (sc->sc_phase == PHASE_MSG_OUT) { 1900 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_BUS_DEV_RESET); 1901 1902 scb = sc->sc_actscb; 1903 1904 /* This SCB finished correctly -- resetting the device */ 1905 iha_append_done_scb(sc, scb, HOST_OK); 1906 1907 iha_reset_tcs(scb->tcs, sc->sc_sconf1); 1908 1909 tar = scb->target; 1910 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1911 if (scb->target == tar) 1912 switch (scb->status) { 1913 case STATUS_BUSY: 1914 iha_append_done_scb(sc, 1915 scb, HOST_DEV_RST); 1916 break; 1917 1918 case STATUS_SELECT: 1919 iha_push_pend_scb(sc, scb); 1920 break; 1921 1922 default: 1923 break; 1924 } 1925 1926 sc->sc_flags |= FLAG_EXPECT_DISC; 1927 1928 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1929 return (-1); 1930 } 1931 1932 iha_bad_seq(sc); 1933 return (-1); 1934 } 1935 1936 /* 1937 * iha_xfer_data - initiate the DMA xfer of the data 1938 */ 1939 static int 1940 iha_xfer_data(struct iha_softc *sc, struct iha_scb *scb, int direction) 1941 { 1942 bus_space_tag_t iot = sc->sc_iot; 1943 bus_space_handle_t ioh = sc->sc_ioh; 1944 uint32_t xferlen; 1945 uint8_t xfercmd; 1946 1947 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != direction) 1948 return (6); /* wrong direction, abandon I/O */ 1949 1950 bus_space_write_4(iot, ioh, TUL_STCNT0, scb->buflen); 1951 1952 xfercmd = STRXFR; 1953 if (direction == FLAG_DATAIN) 1954 xfercmd |= XDIR; 1955 1956 if (scb->flags & FLAG_SG) { 1957 xferlen = scb->sg_size * sizeof(struct iha_sg_element); 1958 xfercmd |= SGXFR; 1959 } else 1960 xferlen = scb->buflen; 1961 1962 bus_space_write_4(iot, ioh, TUL_DXC, xferlen); 1963 bus_space_write_4(iot, ioh, TUL_DXPA, scb->bufaddr); 1964 bus_space_write_1(iot, ioh, TUL_DCMD, xfercmd); 1965 1966 bus_space_write_1(iot, ioh, TUL_SCMD, 1967 (direction == FLAG_DATAIN) ? XF_DMA_IN : XF_DMA_OUT); 1968 1969 scb->nextstat = 5; 1970 1971 return (0); 1972 } 1973 1974 static int 1975 iha_xpad_in(struct iha_softc *sc) 1976 { 1977 bus_space_tag_t iot = sc->sc_iot; 1978 bus_space_handle_t ioh = sc->sc_ioh; 1979 struct iha_scb *scb = sc->sc_actscb; 1980 1981 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1982 scb->ha_stat = HOST_DO_DU; 1983 1984 for (;;) { 1985 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 1986 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 1987 else 1988 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1989 1990 switch (iha_wait(sc, XF_FIFO_IN)) { 1991 case -1: 1992 return (-1); 1993 1994 case PHASE_DATA_IN: 1995 bus_space_read_1(iot, ioh, TUL_SFIFO); 1996 break; 1997 1998 default: 1999 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2000 return (6); 2001 } 2002 } 2003 } 2004 2005 static int 2006 iha_xpad_out(struct iha_softc *sc) 2007 { 2008 bus_space_tag_t iot = sc->sc_iot; 2009 bus_space_handle_t ioh = sc->sc_ioh; 2010 struct iha_scb *scb = sc->sc_actscb; 2011 2012 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 2013 scb->ha_stat = HOST_DO_DU; 2014 2015 for (;;) { 2016 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 2017 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 2018 else 2019 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2020 2021 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 2022 2023 switch (iha_wait(sc, XF_FIFO_OUT)) { 2024 case -1: 2025 return (-1); 2026 2027 case PHASE_DATA_OUT: 2028 break; 2029 2030 default: 2031 /* Disable wide CPU to allow read 16 bits */ 2032 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2033 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2034 return (6); 2035 } 2036 } 2037 } 2038 2039 static int 2040 iha_status_msg(struct iha_softc *sc) 2041 { 2042 bus_space_tag_t iot = sc->sc_iot; 2043 bus_space_handle_t ioh = sc->sc_ioh; 2044 struct iha_scb *scb; 2045 uint8_t msg; 2046 int phase; 2047 2048 if ((phase = iha_wait(sc, CMD_COMP)) == -1) 2049 return (-1); 2050 2051 scb = sc->sc_actscb; 2052 2053 scb->ta_stat = bus_space_read_1(iot, ioh, TUL_SFIFO); 2054 2055 if (phase == PHASE_MSG_OUT) { 2056 if ((sc->sc_status0 & SPERR) == 0) 2057 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_NOOP); 2058 else 2059 bus_space_write_1(iot, ioh, TUL_SFIFO, 2060 MSG_PARITY_ERROR); 2061 2062 return (iha_wait(sc, XF_FIFO_OUT)); 2063 2064 } else if (phase == PHASE_MSG_IN) { 2065 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 2066 2067 if ((sc->sc_status0 & SPERR) != 0) 2068 switch (iha_wait(sc, MSG_ACCEPT)) { 2069 case -1: 2070 return (-1); 2071 case PHASE_MSG_OUT: 2072 bus_space_write_1(iot, ioh, TUL_SFIFO, 2073 MSG_PARITY_ERROR); 2074 return (iha_wait(sc, XF_FIFO_OUT)); 2075 default: 2076 iha_bad_seq(sc); 2077 return (-1); 2078 } 2079 2080 if (msg == MSG_CMDCOMPLETE) { 2081 if ((scb->ta_stat & 2082 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) { 2083 iha_bad_seq(sc); 2084 return (-1); 2085 } 2086 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 2087 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2088 return (iha_wait(sc, MSG_ACCEPT)); 2089 } 2090 2091 if ((msg == MSG_LINK_CMD_COMPLETE) 2092 || (msg == MSG_LINK_CMD_COMPLETEF)) { 2093 if ((scb->ta_stat & 2094 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) 2095 return (iha_wait(sc, MSG_ACCEPT)); 2096 } 2097 } 2098 2099 iha_bad_seq(sc); 2100 return (-1); 2101 } 2102 2103 /* 2104 * iha_busfree - SCSI bus free detected as a result of a TIMEOUT or 2105 * DISCONNECT interrupt. Reset the tulip FIFO and 2106 * SCONFIG0 and enable hardware reselect. Move any active 2107 * SCB to sc_donescb list. Return an appropriate host status 2108 * if an I/O was active. 2109 */ 2110 static void 2111 iha_busfree(struct iha_softc *sc) 2112 { 2113 bus_space_tag_t iot = sc->sc_iot; 2114 bus_space_handle_t ioh = sc->sc_ioh; 2115 struct iha_scb *scb; 2116 2117 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2118 bus_space_write_1(iot, ioh, TUL_SCONFIG0, SCONFIG0DEFAULT); 2119 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2120 2121 scb = sc->sc_actscb; 2122 2123 if (scb != NULL) { 2124 if (scb->status == STATUS_SELECT) 2125 /* selection timeout */ 2126 iha_append_done_scb(sc, scb, HOST_SEL_TOUT); 2127 else 2128 /* Unexpected bus free */ 2129 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 2130 } 2131 } 2132 2133 /* 2134 * iha_resel - handle a detected SCSI bus reselection request. 2135 */ 2136 static int 2137 iha_resel(struct iha_softc *sc) 2138 { 2139 bus_space_tag_t iot = sc->sc_iot; 2140 bus_space_handle_t ioh = sc->sc_ioh; 2141 struct iha_scb *scb; 2142 struct tcs *tcs; 2143 uint8_t tag, target, lun, msg, abortmsg; 2144 2145 if (sc->sc_actscb != NULL) { 2146 if ((sc->sc_actscb->status == STATUS_SELECT)) 2147 iha_push_pend_scb(sc, sc->sc_actscb); 2148 sc->sc_actscb = NULL; 2149 } 2150 2151 target = bus_space_read_1(iot, ioh, TUL_SBID); 2152 lun = bus_space_read_1(iot, ioh, TUL_SALVC) & IHA_MSG_IDENTIFY_LUNMASK; 2153 2154 tcs = &sc->sc_tcs[target]; 2155 2156 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2157 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2158 2159 abortmsg = MSG_ABORT; /* until a valid tag has been obtained */ 2160 2161 if (tcs->ntagscb != NULL) 2162 /* There is a non-tagged I/O active on the target */ 2163 scb = tcs->ntagscb; 2164 2165 else { 2166 /* 2167 * Since there is no active non-tagged operation 2168 * read the tag type, the tag itself, and find 2169 * the appropriate scb by indexing sc_scb with 2170 * the tag. 2171 */ 2172 2173 switch (iha_wait(sc, MSG_ACCEPT)) { 2174 case -1: 2175 return (-1); 2176 case PHASE_MSG_IN: 2177 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2178 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 2179 return (-1); 2180 break; 2181 default: 2182 goto abort; 2183 } 2184 2185 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag Msg */ 2186 2187 if ((msg < MSG_SIMPLE_Q_TAG) || (msg > MSG_ORDERED_Q_TAG)) 2188 goto abort; 2189 2190 switch (iha_wait(sc, MSG_ACCEPT)) { 2191 case -1: 2192 return (-1); 2193 case PHASE_MSG_IN: 2194 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2195 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 2196 return (-1); 2197 break; 2198 default: 2199 goto abort; 2200 } 2201 2202 tag = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag ID */ 2203 scb = &sc->sc_scb[tag]; 2204 2205 abortmsg = MSG_ABORT_TAG; /* Now that we have valdid tag! */ 2206 } 2207 2208 if ((scb->target != target) 2209 || (scb->lun != lun) 2210 || (scb->status != STATUS_BUSY)) { 2211 abort: 2212 iha_msgout_abort(sc, abortmsg); 2213 return (-1); 2214 } 2215 2216 sc->sc_actscb = scb; 2217 2218 if (iha_wait(sc, MSG_ACCEPT) == -1) 2219 return (-1); 2220 2221 return (iha_next_state(sc)); 2222 } 2223 2224 static int 2225 iha_msgin(struct iha_softc *sc) 2226 { 2227 bus_space_tag_t iot = sc->sc_iot; 2228 bus_space_handle_t ioh = sc->sc_ioh; 2229 int flags; 2230 int phase; 2231 uint8_t msg; 2232 2233 for (;;) { 2234 if ((bus_space_read_1(iot, ioh, TUL_SFIFOCNT) & FIFOC) > 0) 2235 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2236 2237 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2238 2239 phase = iha_wait(sc, XF_FIFO_IN); 2240 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 2241 2242 switch (msg) { 2243 case MSG_DISCONNECT: 2244 sc->sc_flags |= FLAG_EXPECT_DISC; 2245 if (iha_wait(sc, MSG_ACCEPT) != -1) 2246 iha_bad_seq(sc); 2247 phase = -1; 2248 break; 2249 case MSG_SAVEDATAPOINTER: 2250 case MSG_RESTOREPOINTERS: 2251 case MSG_NOOP: 2252 phase = iha_wait(sc, MSG_ACCEPT); 2253 break; 2254 case MSG_MESSAGE_REJECT: 2255 /* XXX - need to clear FIFO like other 'Clear ATN'?*/ 2256 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2257 flags = sc->sc_actscb->tcs->flags; 2258 if ((flags & FLAG_NO_NEG_SYNC) == 0) 2259 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2260 phase = iha_wait(sc, MSG_ACCEPT); 2261 break; 2262 case MSG_EXTENDED: 2263 phase = iha_msgin_extended(sc); 2264 break; 2265 case MSG_IGN_WIDE_RESIDUE: 2266 phase = iha_msgin_ignore_wid_resid(sc); 2267 break; 2268 case MSG_CMDCOMPLETE: 2269 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 2270 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2271 phase = iha_wait(sc, MSG_ACCEPT); 2272 if (phase != -1) { 2273 iha_bad_seq(sc); 2274 return (-1); 2275 } 2276 break; 2277 default: 2278 printf("[debug] iha_msgin: bad msg type: %d\n", msg); 2279 phase = iha_msgout_reject(sc); 2280 break; 2281 } 2282 2283 if (phase != PHASE_MSG_IN) 2284 return (phase); 2285 } 2286 /* NOTREACHED */ 2287 } 2288 2289 static int 2290 iha_msgin_extended(struct iha_softc *sc) 2291 { 2292 bus_space_tag_t iot = sc->sc_iot; 2293 bus_space_handle_t ioh = sc->sc_ioh; 2294 int flags, i, phase, msglen, msgcode; 2295 2296 /* 2297 * XXX - can we just stop reading and reject, or do we have to 2298 * read all input, discarding the excess, and then reject 2299 */ 2300 for (i = 0; i < IHA_MAX_EXTENDED_MSG; i++) { 2301 phase = iha_wait(sc, MSG_ACCEPT); 2302 2303 if (phase != PHASE_MSG_IN) 2304 return (phase); 2305 2306 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2307 2308 if (iha_wait(sc, XF_FIFO_IN) == -1) 2309 return (-1); 2310 2311 sc->sc_msg[i] = bus_space_read_1(iot, ioh, TUL_SFIFO); 2312 2313 if (sc->sc_msg[0] == i) 2314 break; 2315 } 2316 2317 msglen = sc->sc_msg[0]; 2318 msgcode = sc->sc_msg[1]; 2319 2320 if ((msglen == MSG_EXT_SDTR_LEN) && (msgcode == MSG_EXT_SDTR)) { 2321 if (iha_msgin_sdtr(sc) == 0) { 2322 iha_sync_done(sc); 2323 return (iha_wait(sc, MSG_ACCEPT)); 2324 } 2325 2326 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2327 2328 phase = iha_wait(sc, MSG_ACCEPT); 2329 if (phase != PHASE_MSG_OUT) 2330 return (phase); 2331 2332 /* Clear FIFO for important message - final SYNC offer */ 2333 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2334 2335 iha_sync_done(sc); /* This is our final offer */ 2336 2337 } else if ((msglen == MSG_EXT_WDTR_LEN) && (msgcode == MSG_EXT_WDTR)) { 2338 2339 flags = sc->sc_actscb->tcs->flags; 2340 2341 if ((flags & FLAG_NO_WIDE) != 0) 2342 /* Offer 8bit xfers only */ 2343 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_8_BIT; 2344 2345 else if (sc->sc_msg[2] > MSG_EXT_WDTR_BUS_32_BIT) 2346 /* BAD MSG */ 2347 return (iha_msgout_reject(sc)); 2348 2349 else if (sc->sc_msg[2] == MSG_EXT_WDTR_BUS_32_BIT) 2350 /* Offer 16bit instead */ 2351 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2352 2353 else { 2354 iha_wide_done(sc); 2355 if ((flags & FLAG_NO_NEG_SYNC) == 0) 2356 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2357 return (iha_wait(sc, MSG_ACCEPT)); 2358 } 2359 2360 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2361 2362 phase = iha_wait(sc, MSG_ACCEPT); 2363 if (phase != PHASE_MSG_OUT) 2364 return (phase); 2365 } else 2366 return (iha_msgout_reject(sc)); 2367 2368 return (iha_msgout_extended(sc)); 2369 } 2370 2371 /* 2372 * iha_msgin_sdtr - check SDTR msg in sc_msg. If the offer is 2373 * acceptable leave sc_msg as is and return 0. 2374 * If the negotiation must continue, modify sc_msg 2375 * as needed and return 1. Else return 0. 2376 */ 2377 static int 2378 iha_msgin_sdtr(struct iha_softc *sc) 2379 { 2380 int flags; 2381 int newoffer; 2382 uint8_t default_period; 2383 2384 flags = sc->sc_actscb->tcs->flags; 2385 2386 default_period = iha_rate_tbl[flags & FLAG_SCSI_RATE]; 2387 2388 if (sc->sc_msg[3] == 0) 2389 /* target offered async only. Accept it. */ 2390 return (0); 2391 2392 newoffer = 0; 2393 2394 if ((flags & FLAG_NO_SYNC) != 0) { 2395 sc->sc_msg[3] = 0; 2396 newoffer = 1; 2397 } 2398 2399 if (sc->sc_msg[3] > IHA_MAX_OFFSET) { 2400 sc->sc_msg[3] = IHA_MAX_OFFSET; 2401 newoffer = 1; 2402 } 2403 2404 if (sc->sc_msg[2] < default_period) { 2405 sc->sc_msg[2] = default_period; 2406 newoffer = 1; 2407 } 2408 2409 if (sc->sc_msg[2] > IHA_MAX_PERIOD) { 2410 /* Use async */ 2411 sc->sc_msg[3] = 0; 2412 newoffer = 1; 2413 } 2414 2415 return (newoffer); 2416 } 2417 2418 static int 2419 iha_msgin_ignore_wid_resid(struct iha_softc *sc) 2420 { 2421 bus_space_tag_t iot = sc->sc_iot; 2422 bus_space_handle_t ioh = sc->sc_ioh; 2423 int phase; 2424 2425 phase = iha_wait(sc, MSG_ACCEPT); 2426 2427 if (phase == PHASE_MSG_IN) { 2428 phase = iha_wait(sc, XF_FIFO_IN); 2429 2430 if (phase != -1) { 2431 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 2432 bus_space_read_1(iot, ioh, TUL_SFIFO); 2433 bus_space_read_1(iot, ioh, TUL_SFIFO); 2434 2435 phase = iha_wait(sc, MSG_ACCEPT); 2436 } 2437 } 2438 2439 return (phase); 2440 } 2441 2442 static int 2443 iha_msgout(struct iha_softc *sc, uint8_t msg) 2444 { 2445 2446 bus_space_write_1(sc->sc_iot, sc->sc_ioh, TUL_SFIFO, msg); 2447 2448 return (iha_wait(sc, XF_FIFO_OUT)); 2449 } 2450 2451 static void 2452 iha_msgout_abort(struct iha_softc *sc, uint8_t aborttype) 2453 { 2454 2455 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2456 2457 switch (iha_wait(sc, MSG_ACCEPT)) { 2458 case -1: 2459 break; 2460 2461 case PHASE_MSG_OUT: 2462 sc->sc_flags |= FLAG_EXPECT_DISC; 2463 if (iha_msgout(sc, aborttype) != -1) 2464 iha_bad_seq(sc); 2465 break; 2466 2467 default: 2468 iha_bad_seq(sc); 2469 break; 2470 } 2471 } 2472 2473 static int 2474 iha_msgout_reject(struct iha_softc *sc) 2475 { 2476 2477 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2478 2479 if (iha_wait(sc, MSG_ACCEPT) == PHASE_MSG_OUT) 2480 return (iha_msgout(sc, MSG_MESSAGE_REJECT)); 2481 2482 return (-1); 2483 } 2484 2485 static int 2486 iha_msgout_extended(struct iha_softc *sc) 2487 { 2488 bus_space_tag_t iot = sc->sc_iot; 2489 bus_space_handle_t ioh = sc->sc_ioh; 2490 int phase; 2491 2492 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXTENDED); 2493 2494 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 2495 sc->sc_msg, sc->sc_msg[0] + 1); 2496 2497 phase = iha_wait(sc, XF_FIFO_OUT); 2498 2499 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2500 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2501 2502 return (phase); 2503 } 2504 2505 static int 2506 iha_msgout_wdtr(struct iha_softc *sc) 2507 { 2508 2509 sc->sc_actscb->tcs->flags |= FLAG_WIDE_DONE; 2510 2511 sc->sc_msg[0] = MSG_EXT_WDTR_LEN; 2512 sc->sc_msg[1] = MSG_EXT_WDTR; 2513 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2514 2515 return (iha_msgout_extended(sc)); 2516 } 2517 2518 static int 2519 iha_msgout_sdtr(struct iha_softc *sc) 2520 { 2521 struct tcs *tcs = sc->sc_actscb->tcs; 2522 2523 tcs->flags |= FLAG_SYNC_DONE; 2524 2525 sc->sc_msg[0] = MSG_EXT_SDTR_LEN; 2526 sc->sc_msg[1] = MSG_EXT_SDTR; 2527 sc->sc_msg[2] = iha_rate_tbl[tcs->flags & FLAG_SCSI_RATE]; 2528 sc->sc_msg[3] = IHA_MAX_OFFSET; /* REQ/ACK */ 2529 2530 return (iha_msgout_extended(sc)); 2531 } 2532 2533 static void 2534 iha_wide_done(struct iha_softc *sc) 2535 { 2536 bus_space_tag_t iot = sc->sc_iot; 2537 bus_space_handle_t ioh = sc->sc_ioh; 2538 struct tcs *tcs = sc->sc_actscb->tcs; 2539 2540 tcs->syncm = 0; 2541 tcs->period = 0; 2542 tcs->offset = 0; 2543 2544 if (sc->sc_msg[2] != 0) 2545 tcs->syncm |= PERIOD_WIDE_SCSI; 2546 2547 tcs->sconfig0 &= ~ALTPD; 2548 tcs->flags &= ~FLAG_SYNC_DONE; 2549 tcs->flags |= FLAG_WIDE_DONE; 2550 2551 iha_update_xfer_mode(sc, sc->sc_actscb->target); 2552 2553 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2554 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2555 } 2556 2557 static void 2558 iha_sync_done(struct iha_softc *sc) 2559 { 2560 bus_space_tag_t iot = sc->sc_iot; 2561 bus_space_handle_t ioh = sc->sc_ioh; 2562 struct tcs *tcs = sc->sc_actscb->tcs; 2563 int i; 2564 2565 tcs->period = sc->sc_msg[2]; 2566 tcs->offset = sc->sc_msg[3]; 2567 if (tcs->offset != 0) { 2568 tcs->syncm |= tcs->offset; 2569 2570 /* pick the highest possible rate */ 2571 for (i = 0; i < sizeof(iha_rate_tbl); i++) 2572 if (iha_rate_tbl[i] >= tcs->period) 2573 break; 2574 2575 tcs->syncm |= (i << 4); 2576 tcs->sconfig0 |= ALTPD; 2577 } 2578 2579 tcs->flags |= FLAG_SYNC_DONE; 2580 2581 iha_update_xfer_mode(sc, sc->sc_actscb->target); 2582 2583 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2584 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2585 } 2586 2587 /* 2588 * iha_bad_seq - a SCSI bus phase was encountered out of the 2589 * correct/expected sequence. Reset the SCSI bus. 2590 */ 2591 static void 2592 iha_bad_seq(struct iha_softc *sc) 2593 { 2594 struct iha_scb *scb = sc->sc_actscb; 2595 2596 if (scb != NULL) 2597 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 2598 2599 iha_reset_scsi_bus(sc); 2600 iha_reset_chip(sc); 2601 } 2602 2603 /* 2604 * iha_read_eeprom - read Serial EEPROM value & set to defaults 2605 * if required. XXX - Writing does NOT work! 2606 */ 2607 static void 2608 iha_read_eeprom(struct iha_softc *sc, struct iha_eeprom *eeprom) 2609 { 2610 bus_space_tag_t iot = sc->sc_iot; 2611 bus_space_handle_t ioh = sc->sc_ioh; 2612 uint16_t *tbuf = (uint16_t *)eeprom; 2613 uint8_t gctrl; 2614 2615 /* Enable EEProm programming */ 2616 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) | EEPRG; 2617 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2618 2619 /* Read EEProm */ 2620 if (iha_se2_rd_all(sc, tbuf) == 0) 2621 panic("%s: cannot read EEPROM", sc->sc_dev.dv_xname); 2622 2623 /* Disable EEProm programming */ 2624 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) & ~EEPRG; 2625 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2626 } 2627 2628 #ifdef notused 2629 /* 2630 * iha_se2_update_all - Update SCSI H/A configuration parameters from 2631 * serial EEPROM Setup default pattern. Only 2632 * change those values different from the values 2633 * in iha_eeprom. 2634 */ 2635 static void 2636 iha_se2_update_all(struct iha_softc *sc) 2637 { 2638 bus_space_tag_t iot = sc->sc_iot; 2639 bus_space_handle_t ioh = sc->sc_ioh; 2640 uint16_t *np; 2641 uint32_t chksum; 2642 int i; 2643 2644 /* Enable erase/write state of EEPROM */ 2645 iha_se2_instr(sc, ENABLE_ERASE); 2646 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2647 EEP_WAIT(); 2648 2649 np = (uint16_t *)&eeprom_default; 2650 2651 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2652 iha_se2_wr(sc, i, *np); 2653 chksum += *np++; 2654 } 2655 2656 chksum &= 0x0000ffff; 2657 iha_se2_wr(sc, 31, chksum); 2658 2659 /* Disable erase/write state of EEPROM */ 2660 iha_se2_instr(sc, 0); 2661 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2662 EEP_WAIT(); 2663 } 2664 2665 /* 2666 * iha_se2_wr - write the given 16 bit value into the Serial EEPROM 2667 * at the specified offset 2668 */ 2669 static void 2670 iha_se2_wr(struct iha_softc *sc, int addr, uint16_t writeword) 2671 { 2672 bus_space_tag_t iot = sc->sc_iot; 2673 bus_space_handle_t ioh = sc->sc_ioh; 2674 int i, bit; 2675 2676 /* send 'WRITE' Instruction == address | WRITE bit */ 2677 iha_se2_instr(sc, addr | WRITE); 2678 2679 for (i = 16; i > 0; i--) { 2680 if (writeword & (1 << (i - 1))) 2681 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRDO); 2682 else 2683 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2684 EEP_WAIT(); 2685 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2686 EEP_WAIT(); 2687 } 2688 2689 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2690 EEP_WAIT(); 2691 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2692 EEP_WAIT(); 2693 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2694 EEP_WAIT(); 2695 2696 for (;;) { 2697 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2698 EEP_WAIT(); 2699 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2700 EEP_WAIT(); 2701 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI; 2702 EEP_WAIT(); 2703 if (bit != 0) 2704 break; /* write complete */ 2705 } 2706 2707 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2708 } 2709 #endif 2710 2711 /* 2712 * iha_se2_rd - read & return the 16 bit value at the specified 2713 * offset in the Serial E2PROM 2714 * 2715 */ 2716 static uint16_t 2717 iha_se2_rd(struct iha_softc *sc, int addr) 2718 { 2719 bus_space_tag_t iot = sc->sc_iot; 2720 bus_space_handle_t ioh = sc->sc_ioh; 2721 int i, bit; 2722 uint16_t readword; 2723 2724 /* Send 'READ' instruction == address | READ bit */ 2725 iha_se2_instr(sc, addr | READ); 2726 2727 readword = 0; 2728 for (i = 16; i > 0; i--) { 2729 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2730 EEP_WAIT(); 2731 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2732 EEP_WAIT(); 2733 /* sample data after the following edge of clock */ 2734 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI ? 1 : 0; 2735 EEP_WAIT(); 2736 2737 readword |= bit << (i - 1); 2738 } 2739 2740 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2741 2742 return (readword); 2743 } 2744 2745 /* 2746 * iha_se2_rd_all - Read SCSI H/A config parameters from serial EEPROM 2747 */ 2748 static int 2749 iha_se2_rd_all(struct iha_softc *sc, uint16_t *tbuf) 2750 { 2751 struct iha_eeprom *eeprom = (struct iha_eeprom *)tbuf; 2752 uint32_t chksum; 2753 int i; 2754 2755 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2756 *tbuf = iha_se2_rd(sc, i); 2757 chksum += *tbuf++; 2758 } 2759 *tbuf = iha_se2_rd(sc, 31); /* read checksum from EEPROM */ 2760 2761 chksum &= 0x0000ffff; /* lower 16 bits */ 2762 2763 return (eeprom->signature == EEP_SIGNATURE) && 2764 (eeprom->checksum == chksum); 2765 } 2766 2767 /* 2768 * iha_se2_instr - write an octet to serial E2PROM one bit at a time 2769 */ 2770 static void 2771 iha_se2_instr(struct iha_softc *sc, int instr) 2772 { 2773 bus_space_tag_t iot = sc->sc_iot; 2774 bus_space_handle_t ioh = sc->sc_ioh; 2775 int b, i; 2776 2777 b = NVRCS | NVRDO; /* Write the start bit (== 1) */ 2778 2779 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2780 EEP_WAIT(); 2781 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2782 EEP_WAIT(); 2783 2784 for (i = 8; i > 0; i--) { 2785 if (instr & (1 << (i - 1))) 2786 b = NVRCS | NVRDO; /* Write a 1 bit */ 2787 else 2788 b = NVRCS; /* Write a 0 bit */ 2789 2790 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2791 EEP_WAIT(); 2792 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2793 EEP_WAIT(); 2794 } 2795 2796 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2797 } 2798
Indexes created Thu Sep 25 08:09:54 GMT 2025