iha.c revision 1.33
1 /* $NetBSD: iha.c,v 1.33 2006/04/14 20:51:41 christos Exp $ */ 2 3 /*- 4 * Device driver for the INI-9XXXU/UW or INIC-940/950 PCI SCSI Controller. 5 * 6 * Written for 386bsd and FreeBSD by 7 * Winston Hung <winstonh (at) initio.com> 8 * 9 * Copyright (c) 1997-1999 Initio Corp. 10 * Copyright (c) 2000, 2001 Ken Westerback 11 * Copyright (c) 2001, 2002 Izumi Tsutsui 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer, 19 * without modification, immediately at the beginning of the file. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 32 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Ported to NetBSD by Izumi Tsutsui <tsutsui (at) ceres.dti.ne.jp> from OpenBSD: 38 * $OpenBSD: iha.c,v 1.3 2001/02/20 00:47:33 krw Exp $ 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: iha.c,v 1.33 2006/04/14 20:51:41 christos Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/buf.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 56 #include <dev/scsipi/scsi_spc.h> 57 #include <dev/scsipi/scsi_all.h> 58 #include <dev/scsipi/scsipi_all.h> 59 #include <dev/scsipi/scsiconf.h> 60 #include <dev/scsipi/scsi_message.h> 61 62 #include <dev/ic/ihareg.h> 63 #include <dev/ic/ihavar.h> 64 65 /* 66 * SCSI Rate Table, indexed by FLAG_SCSI_RATE field of 67 * tcs flags. 68 */ 69 static const uint8_t iha_rate_tbl[] = { 70 /* fast 20 */ 71 /* nanosecond divide by 4 */ 72 12, /* 50ns, 20M */ 73 18, /* 75ns, 13.3M */ 74 25, /* 100ns, 10M */ 75 31, /* 125ns, 8M */ 76 37, /* 150ns, 6.6M */ 77 43, /* 175ns, 5.7M */ 78 50, /* 200ns, 5M */ 79 62 /* 250ns, 4M */ 80 }; 81 #define IHA_MAX_PERIOD 62 82 83 #ifdef notused 84 static uint16_t eeprom_default[EEPROM_SIZE] = { 85 /* -- Header ------------------------------------ */ 86 /* signature */ 87 EEP_SIGNATURE, 88 /* size, revision */ 89 EEP_WORD(EEPROM_SIZE * 2, 0x01), 90 /* -- Host Adapter Structure -------------------- */ 91 /* model */ 92 0x0095, 93 /* model info, number of channel */ 94 EEP_WORD(0x00, 1), 95 /* BIOS config */ 96 EEP_BIOSCFG_DEFAULT, 97 /* host adapter config */ 98 0, 99 100 /* -- eeprom_adapter[0] ------------------------------- */ 101 /* ID, adapter config 1 */ 102 EEP_WORD(7, CFG_DEFAULT), 103 /* adapter config 2, number of targets */ 104 EEP_WORD(0x00, 8), 105 /* target flags */ 106 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 107 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 108 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 109 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 110 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 111 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 112 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 113 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 114 115 /* -- eeprom_adapter[1] ------------------------------- */ 116 /* ID, adapter config 1 */ 117 EEP_WORD(7, CFG_DEFAULT), 118 /* adapter config 2, number of targets */ 119 EEP_WORD(0x00, 8), 120 /* target flags */ 121 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 122 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 123 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 124 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 125 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 126 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 127 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 128 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 129 /* reserved[5] */ 130 0, 0, 0, 0, 0, 131 /* checksum */ 132 0 133 }; 134 #endif 135 136 static void iha_append_free_scb(struct iha_softc *, struct iha_scb *); 137 static void iha_append_done_scb(struct iha_softc *, struct iha_scb *, uint8_t); 138 static inline struct iha_scb *iha_pop_done_scb(struct iha_softc *); 139 140 static struct iha_scb *iha_find_pend_scb(struct iha_softc *); 141 static inline void iha_append_pend_scb(struct iha_softc *, struct iha_scb *); 142 static inline void iha_push_pend_scb(struct iha_softc *, struct iha_scb *); 143 static inline void iha_del_pend_scb(struct iha_softc *, struct iha_scb *); 144 static inline void iha_mark_busy_scb(struct iha_scb *); 145 146 static inline void iha_set_ssig(struct iha_softc *, uint8_t, uint8_t); 147 148 static int iha_alloc_sglist(struct iha_softc *); 149 150 static void iha_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 151 void *); 152 static void iha_update_xfer_mode(struct iha_softc *, int); 153 154 static void iha_reset_scsi_bus(struct iha_softc *); 155 static void iha_reset_chip(struct iha_softc *); 156 static void iha_reset_dma(struct iha_softc *); 157 static void iha_reset_tcs(struct tcs *, uint8_t); 158 159 static void iha_main(struct iha_softc *); 160 static void iha_scsi(struct iha_softc *); 161 static void iha_select(struct iha_softc *, struct iha_scb *, uint8_t); 162 static int iha_wait(struct iha_softc *, uint8_t); 163 164 static void iha_exec_scb(struct iha_softc *, struct iha_scb *); 165 static void iha_done_scb(struct iha_softc *, struct iha_scb *); 166 static int iha_push_sense_request(struct iha_softc *, struct iha_scb *); 167 168 static void iha_timeout(void *); 169 static void iha_abort_xs(struct iha_softc *, struct scsipi_xfer *, uint8_t); 170 static uint8_t iha_data_over_run(struct iha_scb *); 171 172 static int iha_next_state(struct iha_softc *); 173 static int iha_state_1(struct iha_softc *); 174 static int iha_state_2(struct iha_softc *); 175 static int iha_state_3(struct iha_softc *); 176 static int iha_state_4(struct iha_softc *); 177 static int iha_state_5(struct iha_softc *); 178 static int iha_state_6(struct iha_softc *); 179 static int iha_state_8(struct iha_softc *); 180 181 static int iha_xfer_data(struct iha_softc *, struct iha_scb *, int); 182 static int iha_xpad_in(struct iha_softc *); 183 static int iha_xpad_out(struct iha_softc *); 184 185 static int iha_status_msg(struct iha_softc *); 186 static void iha_busfree(struct iha_softc *); 187 static int iha_resel(struct iha_softc *); 188 189 static int iha_msgin(struct iha_softc *); 190 static int iha_msgin_extended(struct iha_softc *); 191 static int iha_msgin_sdtr(struct iha_softc *); 192 static int iha_msgin_ignore_wid_resid(struct iha_softc *); 193 194 static int iha_msgout(struct iha_softc *, uint8_t); 195 static void iha_msgout_abort(struct iha_softc *, uint8_t); 196 static int iha_msgout_reject(struct iha_softc *); 197 static int iha_msgout_extended(struct iha_softc *); 198 static int iha_msgout_wdtr(struct iha_softc *); 199 static int iha_msgout_sdtr(struct iha_softc *); 200 201 static void iha_wide_done(struct iha_softc *); 202 static void iha_sync_done(struct iha_softc *); 203 204 static void iha_bad_seq(struct iha_softc *); 205 206 static void iha_read_eeprom(struct iha_softc *, struct iha_eeprom *); 207 static int iha_se2_rd_all(struct iha_softc *, uint16_t *); 208 static void iha_se2_instr(struct iha_softc *, int); 209 static uint16_t iha_se2_rd(struct iha_softc *, int); 210 #ifdef notused 211 static void iha_se2_update_all(struct iha_softc *); 212 static void iha_se2_wr(struct iha_softc *, int, uint16_t); 213 #endif 214 215 /* 216 * iha_append_free_scb - append the supplied SCB to the tail of the 217 * sc_freescb queue after clearing and resetting 218 * everything possible. 219 */ 220 static void 221 iha_append_free_scb(struct iha_softc *sc, struct iha_scb *scb) 222 { 223 int s; 224 225 s = splbio(); 226 227 if (scb == sc->sc_actscb) 228 sc->sc_actscb = NULL; 229 230 scb->status = STATUS_QUEUED; 231 scb->ha_stat = HOST_OK; 232 scb->ta_stat = SCSI_OK; 233 234 scb->nextstat = 0; 235 scb->scb_tagmsg = 0; 236 237 scb->xs = NULL; 238 scb->tcs = NULL; 239 240 /* 241 * scb_tagid, sg_addr, sglist 242 * SCB_SensePtr are set at initialization 243 * and never change 244 */ 245 246 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 247 248 splx(s); 249 } 250 251 static void 252 iha_append_done_scb(struct iha_softc *sc, struct iha_scb *scb, uint8_t hastat) 253 { 254 struct tcs *tcs; 255 int s; 256 257 s = splbio(); 258 259 if (scb->xs != NULL) 260 callout_stop(&scb->xs->xs_callout); 261 262 if (scb == sc->sc_actscb) 263 sc->sc_actscb = NULL; 264 265 tcs = scb->tcs; 266 267 if (scb->scb_tagmsg != 0) { 268 if (tcs->tagcnt) 269 tcs->tagcnt--; 270 } else if (tcs->ntagscb == scb) 271 tcs->ntagscb = NULL; 272 273 scb->status = STATUS_QUEUED; 274 scb->ha_stat = hastat; 275 276 TAILQ_INSERT_TAIL(&sc->sc_donescb, scb, chain); 277 278 splx(s); 279 } 280 281 static inline struct iha_scb * 282 iha_pop_done_scb(struct iha_softc *sc) 283 { 284 struct iha_scb *scb; 285 int s; 286 287 s = splbio(); 288 289 scb = TAILQ_FIRST(&sc->sc_donescb); 290 291 if (scb != NULL) { 292 scb->status = STATUS_RENT; 293 TAILQ_REMOVE(&sc->sc_donescb, scb, chain); 294 } 295 296 splx(s); 297 298 return (scb); 299 } 300 301 /* 302 * iha_find_pend_scb - scan the pending queue for a SCB that can be 303 * processed immediately. Return NULL if none found 304 * and a pointer to the SCB if one is found. If there 305 * is an active SCB, return NULL! 306 */ 307 static struct iha_scb * 308 iha_find_pend_scb(struct iha_softc *sc) 309 { 310 struct iha_scb *scb; 311 struct tcs *tcs; 312 int s; 313 314 s = splbio(); 315 316 if (sc->sc_actscb != NULL) 317 scb = NULL; 318 319 else 320 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) { 321 if ((scb->xs->xs_control & XS_CTL_RESET) != 0) 322 /* ALWAYS willing to reset a device */ 323 break; 324 325 tcs = scb->tcs; 326 327 if ((scb->scb_tagmsg) != 0) { 328 /* 329 * A Tagged I/O. OK to start If no 330 * non-tagged I/O is active on the same 331 * target 332 */ 333 if (tcs->ntagscb == NULL) 334 break; 335 336 } else if (scb->cmd[0] == SCSI_REQUEST_SENSE) { 337 /* 338 * OK to do a non-tagged request sense 339 * even if a non-tagged I/O has been 340 * started, 'cuz we don't allow any 341 * disconnect during a request sense op 342 */ 343 break; 344 345 } else if (tcs->tagcnt == 0) { 346 /* 347 * No tagged I/O active on this target, 348 * ok to start a non-tagged one if one 349 * is not already active 350 */ 351 if (tcs->ntagscb == NULL) 352 break; 353 } 354 } 355 356 splx(s); 357 358 return (scb); 359 } 360 361 static inline void 362 iha_append_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 363 { 364 /* ASSUMPTION: only called within a splbio()/splx() pair */ 365 366 if (scb == sc->sc_actscb) 367 sc->sc_actscb = NULL; 368 369 scb->status = STATUS_QUEUED; 370 371 TAILQ_INSERT_TAIL(&sc->sc_pendscb, scb, chain); 372 } 373 374 static inline void 375 iha_push_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 376 { 377 int s; 378 379 s = splbio(); 380 381 if (scb == sc->sc_actscb) 382 sc->sc_actscb = NULL; 383 384 scb->status = STATUS_QUEUED; 385 386 TAILQ_INSERT_HEAD(&sc->sc_pendscb, scb, chain); 387 388 splx(s); 389 } 390 391 /* 392 * iha_del_pend_scb - remove scb from sc_pendscb 393 */ 394 static inline void 395 iha_del_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 396 { 397 int s; 398 399 s = splbio(); 400 401 TAILQ_REMOVE(&sc->sc_pendscb, scb, chain); 402 403 splx(s); 404 } 405 406 static inline void 407 iha_mark_busy_scb(struct iha_scb *scb) 408 { 409 int s; 410 411 s = splbio(); 412 413 scb->status = STATUS_BUSY; 414 415 if (scb->scb_tagmsg == 0) 416 scb->tcs->ntagscb = scb; 417 else 418 scb->tcs->tagcnt++; 419 420 splx(s); 421 } 422 423 /* 424 * iha_set_ssig - read the current scsi signal mask, then write a new 425 * one which turns off/on the specified signals. 426 */ 427 static inline void 428 iha_set_ssig(struct iha_softc *sc, uint8_t offsigs, uint8_t onsigs) 429 { 430 bus_space_tag_t iot = sc->sc_iot; 431 bus_space_handle_t ioh = sc->sc_ioh; 432 uint8_t currsigs; 433 434 currsigs = bus_space_read_1(iot, ioh, TUL_SSIGI); 435 bus_space_write_1(iot, ioh, TUL_SSIGO, (currsigs & ~offsigs) | onsigs); 436 } 437 438 /* 439 * iha_intr - the interrupt service routine for the iha driver 440 */ 441 int 442 iha_intr(void *arg) 443 { 444 bus_space_tag_t iot; 445 bus_space_handle_t ioh; 446 struct iha_softc *sc; 447 int s; 448 449 sc = (struct iha_softc *)arg; 450 iot = sc->sc_iot; 451 ioh = sc->sc_ioh; 452 453 if ((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 454 return (0); 455 456 s = splbio(); /* XXX - Or are interrupts off when ISR's are called? */ 457 458 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 459 /* XXX - need these inside a splbio()/splx()? */ 460 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 461 sc->sc_semaph = SEMAPH_IN_MAIN; 462 463 iha_main(sc); 464 465 sc->sc_semaph = ~SEMAPH_IN_MAIN; 466 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 467 } 468 469 splx(s); 470 471 return (1); 472 } 473 474 void 475 iha_attach(struct iha_softc *sc) 476 { 477 bus_space_tag_t iot = sc->sc_iot; 478 bus_space_handle_t ioh = sc->sc_ioh; 479 struct iha_scb *scb; 480 struct iha_eeprom eeprom; 481 struct eeprom_adapter *conf; 482 int i, error, reg; 483 484 iha_read_eeprom(sc, &eeprom); 485 486 conf = &eeprom.adapter[0]; 487 488 /* 489 * fill in the rest of the iha_softc fields 490 */ 491 sc->sc_id = CFG_ID(conf->config1); 492 sc->sc_semaph = ~SEMAPH_IN_MAIN; 493 sc->sc_status0 = 0; 494 sc->sc_actscb = NULL; 495 496 TAILQ_INIT(&sc->sc_freescb); 497 TAILQ_INIT(&sc->sc_pendscb); 498 TAILQ_INIT(&sc->sc_donescb); 499 error = iha_alloc_sglist(sc); 500 if (error != 0) { 501 printf(": cannot allocate sglist\n"); 502 return; 503 } 504 505 sc->sc_scb = malloc(sizeof(struct iha_scb) * IHA_MAX_SCB, 506 M_DEVBUF, M_NOWAIT|M_ZERO); 507 if (sc->sc_scb == NULL) { 508 printf(": cannot allocate SCB\n"); 509 return; 510 } 511 512 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) { 513 scb->scb_tagid = i; 514 scb->sgoffset = IHA_SG_SIZE * i; 515 scb->sglist = sc->sc_sglist + IHA_MAX_SG_ENTRIES * i; 516 scb->sg_addr = 517 sc->sc_dmamap->dm_segs[0].ds_addr + scb->sgoffset; 518 519 error = bus_dmamap_create(sc->sc_dmat, 520 MAXPHYS, IHA_MAX_SG_ENTRIES, MAXPHYS, 0, 521 BUS_DMA_NOWAIT, &scb->dmap); 522 523 if (error != 0) { 524 printf(": couldn't create SCB DMA map, error = %d\n", 525 error); 526 return; 527 } 528 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 529 } 530 531 /* Mask all the interrupts */ 532 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 533 534 /* Stop any I/O and reset the scsi module */ 535 iha_reset_dma(sc); 536 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSMOD); 537 538 /* Program HBA's SCSI ID */ 539 bus_space_write_1(iot, ioh, TUL_SID, sc->sc_id << 4); 540 541 /* 542 * Configure the channel as requested by the NVRAM settings read 543 * by iha_read_eeprom() above. 544 */ 545 546 sc->sc_sconf1 = SCONFIG0DEFAULT; 547 if ((conf->config1 & CFG_EN_PAR) != 0) 548 sc->sc_sconf1 |= SPCHK; 549 bus_space_write_1(iot, ioh, TUL_SCONFIG0, sc->sc_sconf1); 550 551 /* set selection time out 250 ms */ 552 bus_space_write_1(iot, ioh, TUL_STIMO, STIMO_250MS); 553 554 /* Enable desired SCSI termination configuration read from eeprom */ 555 reg = 0; 556 if (conf->config1 & CFG_ACT_TERM1) 557 reg |= ENTMW; 558 if (conf->config1 & CFG_ACT_TERM2) 559 reg |= ENTM; 560 bus_space_write_1(iot, ioh, TUL_DCTRL0, reg); 561 562 reg = bus_space_read_1(iot, ioh, TUL_GCTRL1) & ~ATDEN; 563 if (conf->config1 & CFG_AUTO_TERM) 564 reg |= ATDEN; 565 bus_space_write_1(iot, ioh, TUL_GCTRL1, reg); 566 567 for (i = 0; i < IHA_MAX_TARGETS / 2; i++) { 568 sc->sc_tcs[i * 2 ].flags = EEP_LBYTE(conf->tflags[i]); 569 sc->sc_tcs[i * 2 + 1].flags = EEP_HBYTE(conf->tflags[i]); 570 iha_reset_tcs(&sc->sc_tcs[i * 2 ], sc->sc_sconf1); 571 iha_reset_tcs(&sc->sc_tcs[i * 2 + 1], sc->sc_sconf1); 572 } 573 574 iha_reset_chip(sc); 575 bus_space_write_1(iot, ioh, TUL_SIEN, ALL_INTERRUPTS); 576 577 /* 578 * fill in the adapter. 579 */ 580 sc->sc_adapter.adapt_dev = &sc->sc_dev; 581 sc->sc_adapter.adapt_nchannels = 1; 582 sc->sc_adapter.adapt_openings = IHA_MAX_SCB; 583 sc->sc_adapter.adapt_max_periph = IHA_MAX_SCB; 584 sc->sc_adapter.adapt_ioctl = NULL; 585 sc->sc_adapter.adapt_minphys = minphys; 586 sc->sc_adapter.adapt_request = iha_scsipi_request; 587 588 /* 589 * fill in the channel. 590 */ 591 sc->sc_channel.chan_adapter = &sc->sc_adapter; 592 sc->sc_channel.chan_bustype = &scsi_bustype; 593 sc->sc_channel.chan_channel = 0; 594 sc->sc_channel.chan_ntargets = CFG_TARGET(conf->config2); 595 sc->sc_channel.chan_nluns = 8; 596 sc->sc_channel.chan_id = sc->sc_id; 597 598 /* 599 * Now try to attach all the sub devices. 600 */ 601 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 602 } 603 604 /* 605 * iha_alloc_sglist - allocate and map sglist for SCB's 606 */ 607 static int 608 iha_alloc_sglist(struct iha_softc *sc) 609 { 610 bus_dma_segment_t seg; 611 int error, rseg; 612 613 /* 614 * Allocate DMA-safe memory for the SCB's sglist 615 */ 616 if ((error = bus_dmamem_alloc(sc->sc_dmat, 617 IHA_SG_SIZE * IHA_MAX_SCB, 618 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 619 printf(": unable to allocate sglist, error = %d\n", error); 620 return (error); 621 } 622 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 623 IHA_SG_SIZE * IHA_MAX_SCB, (caddr_t *)&sc->sc_sglist, 624 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 625 printf(": unable to map sglist, error = %d\n", error); 626 return (error); 627 } 628 629 /* 630 * Create and load the DMA map used for the SCBs 631 */ 632 if ((error = bus_dmamap_create(sc->sc_dmat, 633 IHA_SG_SIZE * IHA_MAX_SCB, 1, IHA_SG_SIZE * IHA_MAX_SCB, 634 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 635 printf(": unable to create control DMA map, error = %d\n", 636 error); 637 return (error); 638 } 639 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 640 sc->sc_sglist, IHA_SG_SIZE * IHA_MAX_SCB, 641 NULL, BUS_DMA_NOWAIT)) != 0) { 642 printf(": unable to load control DMA map, error = %d\n", error); 643 return (error); 644 } 645 646 memset(sc->sc_sglist, 0, IHA_SG_SIZE * IHA_MAX_SCB); 647 648 return (0); 649 } 650 651 void 652 iha_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 653 void *arg) 654 { 655 struct scsipi_xfer *xs; 656 struct scsipi_periph *periph; 657 struct iha_scb *scb; 658 struct iha_softc *sc; 659 int error, s; 660 661 sc = (struct iha_softc *)chan->chan_adapter->adapt_dev; 662 663 switch (req) { 664 case ADAPTER_REQ_RUN_XFER: 665 xs = arg; 666 periph = xs->xs_periph; 667 668 /* XXX This size isn't actually a hardware restriction. */ 669 if (xs->cmdlen > sizeof(scb->cmd) || 670 periph->periph_target >= IHA_MAX_TARGETS) { 671 xs->error = XS_DRIVER_STUFFUP; 672 scsipi_done(xs); 673 return; 674 } 675 676 s = splbio(); 677 scb = TAILQ_FIRST(&sc->sc_freescb); 678 if (scb != NULL) { 679 scb->status = STATUS_RENT; 680 TAILQ_REMOVE(&sc->sc_freescb, scb, chain); 681 } 682 else { 683 printf("unable to allocate scb\n"); 684 #ifdef DIAGNOSTIC 685 scsipi_printaddr(periph); 686 panic("iha_scsipi_request"); 687 #else 688 splx(s); 689 return; 690 #endif 691 } 692 splx(s); 693 694 scb->target = periph->periph_target; 695 scb->lun = periph->periph_lun; 696 scb->tcs = &sc->sc_tcs[scb->target]; 697 scb->scb_id = MSG_IDENTIFY(periph->periph_lun, 698 (xs->xs_control & XS_CTL_REQSENSE) == 0); 699 700 scb->xs = xs; 701 scb->cmdlen = xs->cmdlen; 702 memcpy(&scb->cmd, xs->cmd, xs->cmdlen); 703 scb->buflen = xs->datalen; 704 scb->flags = 0; 705 if (xs->xs_control & XS_CTL_DATA_OUT) 706 scb->flags |= FLAG_DATAOUT; 707 if (xs->xs_control & XS_CTL_DATA_IN) 708 scb->flags |= FLAG_DATAIN; 709 710 if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 711 error = bus_dmamap_load(sc->sc_dmat, scb->dmap, 712 xs->data, scb->buflen, NULL, 713 ((xs->xs_control & XS_CTL_NOSLEEP) ? 714 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 715 BUS_DMA_STREAMING | 716 ((scb->flags & FLAG_DATAIN) ? 717 BUS_DMA_READ : BUS_DMA_WRITE)); 718 719 if (error) { 720 printf("%s: error %d loading DMA map\n", 721 sc->sc_dev.dv_xname, error); 722 iha_append_free_scb(sc, scb); 723 xs->error = XS_DRIVER_STUFFUP; 724 scsipi_done(xs); 725 return; 726 } 727 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 728 0, scb->dmap->dm_mapsize, 729 (scb->flags & FLAG_DATAIN) ? 730 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 731 } 732 733 iha_exec_scb(sc, scb); 734 return; 735 736 case ADAPTER_REQ_GROW_RESOURCES: 737 return; /* XXX */ 738 739 case ADAPTER_REQ_SET_XFER_MODE: 740 { 741 struct tcs *tcs; 742 struct scsipi_xfer_mode *xm = arg; 743 744 tcs = &sc->sc_tcs[xm->xm_target]; 745 746 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 747 (tcs->flags & FLAG_NO_WIDE) == 0) 748 tcs->flags &= ~(FLAG_WIDE_DONE|FLAG_SYNC_DONE); 749 750 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 751 (tcs->flags & FLAG_NO_SYNC) == 0) 752 tcs->flags &= ~FLAG_SYNC_DONE; 753 754 /* 755 * If we're not going to negotiate, send the 756 * notification now, since it won't happen later. 757 */ 758 if ((tcs->flags & (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) == 759 (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) 760 iha_update_xfer_mode(sc, xm->xm_target); 761 762 return; 763 } 764 } 765 } 766 767 void 768 iha_update_xfer_mode(struct iha_softc *sc, int target) 769 { 770 struct tcs *tcs = &sc->sc_tcs[target]; 771 struct scsipi_xfer_mode xm; 772 773 xm.xm_target = target; 774 xm.xm_mode = 0; 775 xm.xm_period = 0; 776 xm.xm_offset = 0; 777 778 if (tcs->syncm & PERIOD_WIDE_SCSI) 779 xm.xm_mode |= PERIPH_CAP_WIDE16; 780 781 if (tcs->period) { 782 xm.xm_mode |= PERIPH_CAP_SYNC; 783 xm.xm_period = tcs->period; 784 xm.xm_offset = tcs->offset; 785 } 786 787 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 788 } 789 790 static void 791 iha_reset_scsi_bus(struct iha_softc *sc) 792 { 793 struct iha_scb *scb; 794 struct tcs *tcs; 795 int i, s; 796 797 s = splbio(); 798 799 iha_reset_dma(sc); 800 801 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 802 switch (scb->status) { 803 case STATUS_BUSY: 804 iha_append_done_scb(sc, scb, HOST_SCSI_RST); 805 break; 806 807 case STATUS_SELECT: 808 iha_push_pend_scb(sc, scb); 809 break; 810 811 default: 812 break; 813 } 814 815 for (i = 0, tcs = sc->sc_tcs; i < IHA_MAX_TARGETS; i++, tcs++) 816 iha_reset_tcs(tcs, sc->sc_sconf1); 817 818 splx(s); 819 } 820 821 void 822 iha_reset_chip(struct iha_softc *sc) 823 { 824 bus_space_tag_t iot = sc->sc_iot; 825 bus_space_handle_t ioh = sc->sc_ioh; 826 827 /* reset tulip chip */ 828 829 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSCSI); 830 831 do { 832 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 833 } while ((sc->sc_sistat & SRSTD) == 0); 834 835 iha_set_ssig(sc, 0, 0); 836 837 bus_space_read_1(iot, ioh, TUL_SISTAT); /* Clear any active interrupt*/ 838 } 839 840 /* 841 * iha_reset_dma - abort any active DMA xfer, reset tulip FIFO. 842 */ 843 static void 844 iha_reset_dma(struct iha_softc *sc) 845 { 846 bus_space_tag_t iot = sc->sc_iot; 847 bus_space_handle_t ioh = sc->sc_ioh; 848 849 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 850 /* if DMA xfer is pending, abort DMA xfer */ 851 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 852 /* wait Abort DMA xfer done */ 853 while ((bus_space_read_1(iot, ioh, TUL_ISTUS0) & DABT) == 0) 854 ; 855 } 856 857 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 858 } 859 860 /* 861 * iha_reset_tcs - reset the target control structure pointed 862 * to by tcs to default values. tcs flags 863 * only has the negotiation done bits reset as 864 * the other bits are fixed at initialization. 865 */ 866 static void 867 iha_reset_tcs(struct tcs *tcs, uint8_t config0) 868 { 869 870 tcs->flags &= ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 871 tcs->period = 0; 872 tcs->offset = 0; 873 tcs->tagcnt = 0; 874 tcs->ntagscb = NULL; 875 tcs->syncm = 0; 876 tcs->sconfig0 = config0; 877 } 878 879 /* 880 * iha_main - process the active SCB, taking one off pending and making it 881 * active if necessary, and any done SCB's created as 882 * a result until there are no interrupts pending and no pending 883 * SCB's that can be started. 884 */ 885 static void 886 iha_main(struct iha_softc *sc) 887 { 888 bus_space_tag_t iot = sc->sc_iot; 889 bus_space_handle_t ioh =sc->sc_ioh; 890 struct iha_scb *scb; 891 892 for (;;) { 893 iha_scsi(sc); 894 895 while ((scb = iha_pop_done_scb(sc)) != NULL) 896 iha_done_scb(sc, scb); 897 898 /* 899 * If there are no interrupts pending, or we can't start 900 * a pending sc, break out of the for(;;). Otherwise 901 * continue the good work with another call to 902 * iha_scsi(). 903 */ 904 if (((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 905 && (iha_find_pend_scb(sc) == NULL)) 906 break; 907 } 908 } 909 910 /* 911 * iha_scsi - service any outstanding interrupts. If there are none, try to 912 * start another SCB currently in the pending queue. 913 */ 914 static void 915 iha_scsi(struct iha_softc *sc) 916 { 917 bus_space_tag_t iot = sc->sc_iot; 918 bus_space_handle_t ioh = sc->sc_ioh; 919 struct iha_scb *scb; 920 struct tcs *tcs; 921 uint8_t stat; 922 923 /* service pending interrupts asap */ 924 925 stat = bus_space_read_1(iot, ioh, TUL_STAT0); 926 if ((stat & INTPD) != 0) { 927 sc->sc_status0 = stat; 928 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 929 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 930 931 sc->sc_phase = sc->sc_status0 & PH_MASK; 932 933 if ((sc->sc_sistat & SRSTD) != 0) { 934 iha_reset_scsi_bus(sc); 935 return; 936 } 937 938 if ((sc->sc_sistat & RSELED) != 0) { 939 iha_resel(sc); 940 return; 941 } 942 943 if ((sc->sc_sistat & (STIMEO | DISCD)) != 0) { 944 iha_busfree(sc); 945 return; 946 } 947 948 if ((sc->sc_sistat & (SCMDN | SBSRV)) != 0) { 949 iha_next_state(sc); 950 return; 951 } 952 953 if ((sc->sc_sistat & SELED) != 0) 954 iha_set_ssig(sc, 0, 0); 955 } 956 957 /* 958 * There were no interrupts pending which required action elsewhere, so 959 * see if it is possible to start the selection phase on a pending SCB 960 */ 961 if ((scb = iha_find_pend_scb(sc)) == NULL) 962 return; 963 964 tcs = scb->tcs; 965 966 /* program HBA's SCSI ID & target SCSI ID */ 967 bus_space_write_1(iot, ioh, TUL_SID, (sc->sc_id << 4) | scb->target); 968 969 if ((scb->xs->xs_control & XS_CTL_RESET) == 0) { 970 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 971 972 if ((tcs->flags & FLAG_NO_NEG_SYNC) == 0 || 973 (tcs->flags & FLAG_NO_NEG_WIDE) == 0) 974 iha_select(sc, scb, SELATNSTOP); 975 976 else if (scb->scb_tagmsg != 0) 977 iha_select(sc, scb, SEL_ATN3); 978 979 else 980 iha_select(sc, scb, SEL_ATN); 981 982 } else { 983 iha_select(sc, scb, SELATNSTOP); 984 scb->nextstat = 8; 985 } 986 987 if ((scb->xs->xs_control & XS_CTL_POLL) != 0) { 988 int timeout; 989 for (timeout = scb->xs->timeout; timeout > 0; timeout--) { 990 if (iha_wait(sc, NO_OP) == -1) 991 break; 992 if (iha_next_state(sc) == -1) 993 break; 994 delay(1000); /* Only happens in boot, so it's ok */ 995 } 996 997 /* 998 * Since done queue processing not done until AFTER this 999 * function returns, scb is on the done queue, not 1000 * the free queue at this point and still has valid data 1001 * 1002 * Conversely, xs->error has not been set yet 1003 */ 1004 if (timeout == 0) 1005 iha_timeout(scb); 1006 } 1007 } 1008 1009 static void 1010 iha_select(struct iha_softc *sc, struct iha_scb *scb, uint8_t select_type) 1011 { 1012 bus_space_tag_t iot = sc->sc_iot; 1013 bus_space_handle_t ioh = sc->sc_ioh; 1014 1015 switch (select_type) { 1016 case SEL_ATN: 1017 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1018 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1019 scb->cmd, scb->cmdlen); 1020 1021 scb->nextstat = 2; 1022 break; 1023 1024 case SELATNSTOP: 1025 scb->nextstat = 1; 1026 break; 1027 1028 case SEL_ATN3: 1029 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1030 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagmsg); 1031 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagid); 1032 1033 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, scb->cmd, 1034 scb->cmdlen); 1035 1036 scb->nextstat = 2; 1037 break; 1038 1039 default: 1040 printf("[debug] iha_select() - unknown select type = 0x%02x\n", 1041 select_type); 1042 return; 1043 } 1044 1045 iha_del_pend_scb(sc, scb); 1046 scb->status = STATUS_SELECT; 1047 1048 sc->sc_actscb = scb; 1049 1050 bus_space_write_1(iot, ioh, TUL_SCMD, select_type); 1051 } 1052 1053 /* 1054 * iha_wait - wait for an interrupt to service or a SCSI bus phase change 1055 * after writing the supplied command to the tulip chip. If 1056 * the command is NO_OP, skip the command writing. 1057 */ 1058 static int 1059 iha_wait(struct iha_softc *sc, uint8_t cmd) 1060 { 1061 bus_space_tag_t iot = sc->sc_iot; 1062 bus_space_handle_t ioh = sc->sc_ioh; 1063 1064 if (cmd != NO_OP) 1065 bus_space_write_1(iot, ioh, TUL_SCMD, cmd); 1066 1067 /* 1068 * Have to do this here, in addition to in iha_isr, because 1069 * interrupts might be turned off when we get here. 1070 */ 1071 do { 1072 sc->sc_status0 = bus_space_read_1(iot, ioh, TUL_STAT0); 1073 } while ((sc->sc_status0 & INTPD) == 0); 1074 1075 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 1076 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 1077 1078 sc->sc_phase = sc->sc_status0 & PH_MASK; 1079 1080 if ((sc->sc_sistat & SRSTD) != 0) { 1081 /* SCSI bus reset interrupt */ 1082 iha_reset_scsi_bus(sc); 1083 return (-1); 1084 } 1085 1086 if ((sc->sc_sistat & RSELED) != 0) 1087 /* Reselection interrupt */ 1088 return (iha_resel(sc)); 1089 1090 if ((sc->sc_sistat & STIMEO) != 0) { 1091 /* selected/reselected timeout interrupt */ 1092 iha_busfree(sc); 1093 return (-1); 1094 } 1095 1096 if ((sc->sc_sistat & DISCD) != 0) { 1097 /* BUS disconnection interrupt */ 1098 if ((sc->sc_flags & FLAG_EXPECT_DONE_DISC) != 0) { 1099 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1100 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 1101 SCONFIG0DEFAULT); 1102 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1103 iha_append_done_scb(sc, sc->sc_actscb, HOST_OK); 1104 sc->sc_flags &= ~FLAG_EXPECT_DONE_DISC; 1105 1106 } else if ((sc->sc_flags & FLAG_EXPECT_DISC) != 0) { 1107 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1108 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 1109 SCONFIG0DEFAULT); 1110 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1111 sc->sc_actscb = NULL; 1112 sc->sc_flags &= ~FLAG_EXPECT_DISC; 1113 1114 } else 1115 iha_busfree(sc); 1116 1117 return (-1); 1118 } 1119 1120 return (sc->sc_phase); 1121 } 1122 1123 static void 1124 iha_exec_scb(struct iha_softc *sc, struct iha_scb *scb) 1125 { 1126 bus_space_tag_t iot; 1127 bus_space_handle_t ioh; 1128 bus_dmamap_t dm; 1129 struct scsipi_xfer *xs = scb->xs; 1130 int nseg, s; 1131 1132 dm = scb->dmap; 1133 nseg = dm->dm_nsegs; 1134 1135 if (nseg > 1) { 1136 struct iha_sg_element *sg = scb->sglist; 1137 int i; 1138 1139 for (i = 0; i < nseg; i++) { 1140 sg[i].sg_len = htole32(dm->dm_segs[i].ds_len); 1141 sg[i].sg_addr = htole32(dm->dm_segs[i].ds_addr); 1142 } 1143 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1144 scb->sgoffset, IHA_SG_SIZE, 1145 BUS_DMASYNC_PREWRITE); 1146 1147 scb->flags |= FLAG_SG; 1148 scb->sg_size = scb->sg_max = nseg; 1149 scb->sg_index = 0; 1150 1151 scb->bufaddr = scb->sg_addr; 1152 } else 1153 scb->bufaddr = dm->dm_segs[0].ds_addr; 1154 1155 if ((xs->xs_control & XS_CTL_POLL) == 0) { 1156 int timeout = mstohz(xs->timeout); 1157 if (timeout == 0) 1158 timeout = 1; 1159 callout_reset(&xs->xs_callout, timeout, iha_timeout, scb); 1160 } 1161 1162 s = splbio(); 1163 1164 if (((scb->xs->xs_control & XS_RESET) != 0) || 1165 (scb->cmd[0] == SCSI_REQUEST_SENSE)) 1166 iha_push_pend_scb(sc, scb); /* Insert SCB at head of Pend */ 1167 else 1168 iha_append_pend_scb(sc, scb); /* Append SCB to tail of Pend */ 1169 1170 /* 1171 * Run through iha_main() to ensure something is active, if 1172 * only this new SCB. 1173 */ 1174 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 1175 iot = sc->sc_iot; 1176 ioh = sc->sc_ioh; 1177 1178 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 1179 sc->sc_semaph = SEMAPH_IN_MAIN; 1180 1181 splx(s); 1182 iha_main(sc); 1183 s = splbio(); 1184 1185 sc->sc_semaph = ~SEMAPH_IN_MAIN; 1186 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 1187 } 1188 1189 splx(s); 1190 } 1191 1192 /* 1193 * iha_done_scb - We have a scb which has been processed by the 1194 * adaptor, now we look to see how the operation went. 1195 */ 1196 static void 1197 iha_done_scb(struct iha_softc *sc, struct iha_scb *scb) 1198 { 1199 struct scsipi_xfer *xs = scb->xs; 1200 1201 if (xs != NULL) { 1202 /* Cancel the timeout. */ 1203 callout_stop(&xs->xs_callout); 1204 1205 if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 1206 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 1207 0, scb->dmap->dm_mapsize, 1208 (scb->flags & FLAG_DATAIN) ? 1209 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1210 bus_dmamap_unload(sc->sc_dmat, scb->dmap); 1211 } 1212 1213 xs->status = scb->ta_stat; 1214 1215 switch (scb->ha_stat) { 1216 case HOST_OK: 1217 switch (scb->ta_stat) { 1218 case SCSI_OK: 1219 case SCSI_CONDITION_MET: 1220 case SCSI_INTERM: 1221 case SCSI_INTERM_COND_MET: 1222 xs->resid = scb->buflen; 1223 xs->error = XS_NOERROR; 1224 if ((scb->flags & FLAG_RSENS) != 0) 1225 xs->error = XS_SENSE; 1226 break; 1227 1228 case SCSI_RESV_CONFLICT: 1229 case SCSI_BUSY: 1230 case SCSI_QUEUE_FULL: 1231 xs->error = XS_BUSY; 1232 break; 1233 1234 case SCSI_TERMINATED: 1235 case SCSI_ACA_ACTIVE: 1236 case SCSI_CHECK: 1237 scb->tcs->flags &= 1238 ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 1239 1240 if ((scb->flags & FLAG_RSENS) != 0 || 1241 iha_push_sense_request(sc, scb) != 0) { 1242 scb->flags &= ~FLAG_RSENS; 1243 printf("%s: request sense failed\n", 1244 sc->sc_dev.dv_xname); 1245 xs->error = XS_DRIVER_STUFFUP; 1246 break; 1247 } 1248 1249 xs->error = XS_SENSE; 1250 return; 1251 1252 default: 1253 xs->error = XS_DRIVER_STUFFUP; 1254 break; 1255 } 1256 break; 1257 1258 case HOST_SEL_TOUT: 1259 xs->error = XS_SELTIMEOUT; 1260 break; 1261 1262 case HOST_SCSI_RST: 1263 case HOST_DEV_RST: 1264 xs->error = XS_RESET; 1265 break; 1266 1267 case HOST_SPERR: 1268 printf("%s: SCSI Parity error detected\n", 1269 sc->sc_dev.dv_xname); 1270 xs->error = XS_DRIVER_STUFFUP; 1271 break; 1272 1273 case HOST_TIMED_OUT: 1274 xs->error = XS_TIMEOUT; 1275 break; 1276 1277 case HOST_DO_DU: 1278 case HOST_BAD_PHAS: 1279 default: 1280 xs->error = XS_DRIVER_STUFFUP; 1281 break; 1282 } 1283 1284 scsipi_done(xs); 1285 } 1286 1287 iha_append_free_scb(sc, scb); 1288 } 1289 1290 /* 1291 * iha_push_sense_request - obtain auto sense data by pushing the 1292 * SCB needing it back onto the pending 1293 * queue with a REQUEST_SENSE CDB. 1294 */ 1295 static int 1296 iha_push_sense_request(struct iha_softc *sc, struct iha_scb *scb) 1297 { 1298 struct scsipi_xfer *xs = scb->xs; 1299 struct scsipi_periph *periph = xs->xs_periph; 1300 struct scsi_request_sense *ss = (struct scsi_request_sense *)scb->cmd; 1301 int lun = periph->periph_lun; 1302 int err; 1303 1304 memset(ss, 0, sizeof(*ss)); 1305 ss->opcode = SCSI_REQUEST_SENSE; 1306 ss->byte2 = lun << SCSI_CMD_LUN_SHIFT; 1307 ss->length = sizeof(struct scsi_sense_data); 1308 1309 scb->flags = FLAG_RSENS | FLAG_DATAIN; 1310 1311 scb->scb_id &= ~MSG_IDENTIFY_DISCFLAG; 1312 1313 scb->scb_tagmsg = 0; 1314 scb->ta_stat = SCSI_OK; 1315 1316 scb->cmdlen = sizeof(struct scsi_request_sense); 1317 scb->buflen = ss->length; 1318 1319 err = bus_dmamap_load(sc->sc_dmat, scb->dmap, 1320 &xs->sense.scsi_sense, scb->buflen, NULL, 1321 BUS_DMA_READ|BUS_DMA_NOWAIT); 1322 if (err != 0) { 1323 printf("iha_push_sense_request: cannot bus_dmamap_load()\n"); 1324 xs->error = XS_DRIVER_STUFFUP; 1325 return 1; 1326 } 1327 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 1328 0, scb->buflen, BUS_DMASYNC_PREREAD); 1329 1330 /* XXX What about queued command? */ 1331 iha_exec_scb(sc, scb); 1332 1333 return 0; 1334 } 1335 1336 static void 1337 iha_timeout(void *arg) 1338 { 1339 struct iha_scb *scb = (struct iha_scb *)arg; 1340 struct scsipi_xfer *xs = scb->xs; 1341 struct scsipi_periph *periph; 1342 struct iha_softc *sc; 1343 1344 if (xs == NULL) { 1345 printf("[debug] iha_timeout called with xs == NULL\n"); 1346 return; 1347 } 1348 1349 periph = xs->xs_periph; 1350 1351 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1352 1353 scsipi_printaddr(periph); 1354 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1355 iha_abort_xs(sc, xs, HOST_TIMED_OUT); 1356 } 1357 1358 /* 1359 * iha_abort_xs - find the SCB associated with the supplied xs and 1360 * stop all processing on it, moving it to the done 1361 * queue with the supplied host status value. 1362 */ 1363 static void 1364 iha_abort_xs(struct iha_softc *sc, struct scsipi_xfer *xs, uint8_t hastat) 1365 { 1366 struct iha_scb *scb; 1367 int i, s; 1368 1369 s = splbio(); 1370 1371 /* Check the pending queue for the SCB pointing to xs */ 1372 1373 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) 1374 if (scb->xs == xs) { 1375 iha_del_pend_scb(sc, scb); 1376 iha_append_done_scb(sc, scb, hastat); 1377 splx(s); 1378 return; 1379 } 1380 1381 /* 1382 * If that didn't work, check all BUSY/SELECTING SCB's for one 1383 * pointing to xs 1384 */ 1385 1386 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1387 switch (scb->status) { 1388 case STATUS_BUSY: 1389 case STATUS_SELECT: 1390 if (scb->xs == xs) { 1391 iha_append_done_scb(sc, scb, hastat); 1392 splx(s); 1393 return; 1394 } 1395 break; 1396 default: 1397 break; 1398 } 1399 1400 splx(s); 1401 } 1402 1403 /* 1404 * iha_data_over_run - return HOST_OK for all SCSI opcodes where BufLen 1405 * is an 'Allocation Length'. All other SCSI opcodes 1406 * get HOST_DO_DU as they SHOULD have xferred all the 1407 * data requested. 1408 * 1409 * The list of opcodes using 'Allocation Length' was 1410 * found by scanning all the SCSI-3 T10 drafts. See 1411 * www.t10.org for the curious with a .pdf reader. 1412 */ 1413 static uint8_t 1414 iha_data_over_run(struct iha_scb *scb) 1415 { 1416 switch (scb->cmd[0]) { 1417 case 0x03: /* Request Sense SPC-2 */ 1418 case 0x12: /* Inquiry SPC-2 */ 1419 case 0x1a: /* Mode Sense (6 byte version) SPC-2 */ 1420 case 0x1c: /* Receive Diagnostic Results SPC-2 */ 1421 case 0x23: /* Read Format Capacities MMC-2 */ 1422 case 0x29: /* Read Generation SBC */ 1423 case 0x34: /* Read Position SSC-2 */ 1424 case 0x37: /* Read Defect Data SBC */ 1425 case 0x3c: /* Read Buffer SPC-2 */ 1426 case 0x42: /* Read Sub Channel MMC-2 */ 1427 case 0x43: /* Read TOC/PMA/ATIP MMC */ 1428 1429 /* XXX - 2 with same opcode of 0x44? */ 1430 case 0x44: /* Read Header/Read Density Suprt MMC/SSC*/ 1431 1432 case 0x46: /* Get Configuration MMC-2 */ 1433 case 0x4a: /* Get Event/Status Notification MMC-2 */ 1434 case 0x4d: /* Log Sense SPC-2 */ 1435 case 0x51: /* Read Disc Information MMC */ 1436 case 0x52: /* Read Track Information MMC */ 1437 case 0x59: /* Read Master CUE MMC */ 1438 case 0x5a: /* Mode Sense (10 byte version) SPC-2 */ 1439 case 0x5c: /* Read Buffer Capacity MMC */ 1440 case 0x5e: /* Persistent Reserve In SPC-2 */ 1441 case 0x84: /* Receive Copy Results SPC-2 */ 1442 case 0xa0: /* Report LUNs SPC-2 */ 1443 case 0xa3: /* Various Report requests SBC-2/SCC-2*/ 1444 case 0xa4: /* Report Key MMC-2 */ 1445 case 0xad: /* Read DVD Structure MMC-2 */ 1446 case 0xb4: /* Read Element Status (Attached) SMC */ 1447 case 0xb5: /* Request Volume Element Address SMC */ 1448 case 0xb7: /* Read Defect Data (12 byte ver.) SBC */ 1449 case 0xb8: /* Read Element Status (Independ.) SMC */ 1450 case 0xba: /* Report Redundancy SCC-2 */ 1451 case 0xbd: /* Mechanism Status MMC */ 1452 case 0xbe: /* Report Basic Redundancy SCC-2 */ 1453 1454 return (HOST_OK); 1455 1456 default: 1457 return (HOST_DO_DU); 1458 } 1459 } 1460 1461 /* 1462 * iha_next_state - process the current SCB as requested in its 1463 * nextstat member. 1464 */ 1465 static int 1466 iha_next_state(struct iha_softc *sc) 1467 { 1468 1469 if (sc->sc_actscb == NULL) 1470 return (-1); 1471 1472 switch (sc->sc_actscb->nextstat) { 1473 case 1: 1474 if (iha_state_1(sc) == 3) 1475 goto state_3; 1476 break; 1477 1478 case 2: 1479 switch (iha_state_2(sc)) { 1480 case 3: 1481 goto state_3; 1482 case 4: 1483 goto state_4; 1484 default: 1485 break; 1486 } 1487 break; 1488 1489 case 3: 1490 state_3: 1491 if (iha_state_3(sc) == 4) 1492 goto state_4; 1493 break; 1494 1495 case 4: 1496 state_4: 1497 switch (iha_state_4(sc)) { 1498 case 0: 1499 return (0); 1500 case 6: 1501 goto state_6; 1502 default: 1503 break; 1504 } 1505 break; 1506 1507 case 5: 1508 switch (iha_state_5(sc)) { 1509 case 4: 1510 goto state_4; 1511 case 6: 1512 goto state_6; 1513 default: 1514 break; 1515 } 1516 break; 1517 1518 case 6: 1519 state_6: 1520 iha_state_6(sc); 1521 break; 1522 1523 case 8: 1524 iha_state_8(sc); 1525 break; 1526 1527 default: 1528 #ifdef IHA_DEBUG_STATE 1529 printf("[debug] -unknown state: %i-\n", 1530 sc->sc_actscb->nextstat); 1531 #endif 1532 iha_bad_seq(sc); 1533 break; 1534 } 1535 1536 return (-1); 1537 } 1538 1539 /* 1540 * iha_state_1 - selection is complete after a SELATNSTOP. If the target 1541 * has put the bus into MSG_OUT phase start wide/sync 1542 * negotiation. Otherwise clear the FIFO and go to state 3, 1543 * which will send the SCSI CDB to the target. 1544 */ 1545 static int 1546 iha_state_1(struct iha_softc *sc) 1547 { 1548 bus_space_tag_t iot = sc->sc_iot; 1549 bus_space_handle_t ioh = sc->sc_ioh; 1550 struct iha_scb *scb = sc->sc_actscb; 1551 struct tcs *tcs; 1552 int flags; 1553 1554 iha_mark_busy_scb(scb); 1555 1556 tcs = scb->tcs; 1557 1558 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 1559 1560 /* 1561 * If we are in PHASE_MSG_OUT, send 1562 * a) IDENT message (with tags if appropriate) 1563 * b) WDTR if the target is configured to negotiate wide xfers 1564 * ** OR ** 1565 * c) SDTR if the target is configured to negotiate sync xfers 1566 * but not wide ones 1567 * 1568 * If we are NOT, then the target is not asking for anything but 1569 * the data/command, so go straight to state 3. 1570 */ 1571 if (sc->sc_phase == PHASE_MSG_OUT) { 1572 bus_space_write_1(iot, ioh, TUL_SCTRL1, (ESBUSIN | EHRSL)); 1573 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1574 1575 if (scb->scb_tagmsg != 0) { 1576 bus_space_write_1(iot, ioh, TUL_SFIFO, 1577 scb->scb_tagmsg); 1578 bus_space_write_1(iot, ioh, TUL_SFIFO, 1579 scb->scb_tagid); 1580 } 1581 1582 flags = tcs->flags; 1583 if ((flags & FLAG_NO_NEG_WIDE) == 0) { 1584 if (iha_msgout_wdtr(sc) == -1) 1585 return (-1); 1586 } else if ((flags & FLAG_NO_NEG_SYNC) == 0) { 1587 if (iha_msgout_sdtr(sc) == -1) 1588 return (-1); 1589 } 1590 1591 } else { 1592 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1593 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1594 } 1595 1596 return (3); 1597 } 1598 1599 /* 1600 * iha_state_2 - selection is complete after a SEL_ATN or SEL_ATN3. If the SCSI 1601 * CDB has already been send, go to state 4 to start the data 1602 * xfer. Otherwise reset the FIFO and go to state 3, sending 1603 * the SCSI CDB. 1604 */ 1605 static int 1606 iha_state_2(struct iha_softc *sc) 1607 { 1608 bus_space_tag_t iot = sc->sc_iot; 1609 bus_space_handle_t ioh = sc->sc_ioh; 1610 struct iha_scb *scb = sc->sc_actscb; 1611 1612 iha_mark_busy_scb(scb); 1613 1614 bus_space_write_1(iot, ioh, TUL_SCONFIG0, scb->tcs->sconfig0); 1615 1616 if ((sc->sc_status1 & CPDNE) != 0) 1617 return (4); 1618 1619 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1620 1621 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1622 1623 return (3); 1624 } 1625 1626 /* 1627 * iha_state_3 - send the SCSI CDB to the target, processing any status 1628 * or other messages received until that is done or 1629 * abandoned. 1630 */ 1631 static int 1632 iha_state_3(struct iha_softc *sc) 1633 { 1634 bus_space_tag_t iot = sc->sc_iot; 1635 bus_space_handle_t ioh = sc->sc_ioh; 1636 struct iha_scb *scb = sc->sc_actscb; 1637 int flags; 1638 1639 for (;;) { 1640 switch (sc->sc_phase) { 1641 case PHASE_CMD_OUT: 1642 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1643 scb->cmd, scb->cmdlen); 1644 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1645 return (-1); 1646 else if (sc->sc_phase == PHASE_CMD_OUT) { 1647 iha_bad_seq(sc); 1648 return (-1); 1649 } else 1650 return (4); 1651 1652 case PHASE_MSG_IN: 1653 scb->nextstat = 3; 1654 if (iha_msgin(sc) == -1) 1655 return (-1); 1656 break; 1657 1658 case PHASE_STATUS_IN: 1659 if (iha_status_msg(sc) == -1) 1660 return (-1); 1661 break; 1662 1663 case PHASE_MSG_OUT: 1664 flags = scb->tcs->flags; 1665 if ((flags & FLAG_NO_NEG_SYNC) != 0) { 1666 if (iha_msgout(sc, MSG_NOOP) == -1) 1667 return (-1); 1668 } else if (iha_msgout_sdtr(sc) == -1) 1669 return (-1); 1670 break; 1671 1672 default: 1673 printf("[debug] -s3- bad phase = %d\n", sc->sc_phase); 1674 iha_bad_seq(sc); 1675 return (-1); 1676 } 1677 } 1678 } 1679 1680 /* 1681 * iha_state_4 - start a data xfer. Handle any bus state 1682 * transitions until PHASE_DATA_IN/_OUT 1683 * or the attempt is abandoned. If there is 1684 * no data to xfer, go to state 6 and finish 1685 * processing the current SCB. 1686 */ 1687 static int 1688 iha_state_4(struct iha_softc *sc) 1689 { 1690 struct iha_scb *scb = sc->sc_actscb; 1691 1692 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) == 1693 (FLAG_DATAIN | FLAG_DATAOUT)) 1694 return (6); /* Both dir flags set => NO xfer was requested */ 1695 1696 for (;;) { 1697 if (scb->buflen == 0) 1698 return (6); 1699 1700 switch (sc->sc_phase) { 1701 case PHASE_STATUS_IN: 1702 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1703 scb->ha_stat = iha_data_over_run(scb); 1704 if ((iha_status_msg(sc)) == -1) 1705 return (-1); 1706 break; 1707 1708 case PHASE_MSG_IN: 1709 scb->nextstat = 4; 1710 if (iha_msgin(sc) == -1) 1711 return (-1); 1712 break; 1713 1714 case PHASE_MSG_OUT: 1715 if ((sc->sc_status0 & SPERR) != 0) { 1716 scb->buflen = 0; 1717 scb->ha_stat = HOST_SPERR; 1718 if (iha_msgout(sc, MSG_INITIATOR_DET_ERR) == -1) 1719 return (-1); 1720 else 1721 return (6); 1722 } else { 1723 if (iha_msgout(sc, MSG_NOOP) == -1) 1724 return (-1); 1725 } 1726 break; 1727 1728 case PHASE_DATA_IN: 1729 return (iha_xfer_data(sc, scb, FLAG_DATAIN)); 1730 1731 case PHASE_DATA_OUT: 1732 return (iha_xfer_data(sc, scb, FLAG_DATAOUT)); 1733 1734 default: 1735 iha_bad_seq(sc); 1736 return (-1); 1737 } 1738 } 1739 } 1740 1741 /* 1742 * iha_state_5 - handle the partial or final completion of the current 1743 * data xfer. If DMA is still active stop it. If there is 1744 * more data to xfer, go to state 4 and start the xfer. 1745 * If not go to state 6 and finish the SCB. 1746 */ 1747 static int 1748 iha_state_5(struct iha_softc *sc) 1749 { 1750 bus_space_tag_t iot = sc->sc_iot; 1751 bus_space_handle_t ioh = sc->sc_ioh; 1752 struct iha_scb *scb = sc->sc_actscb; 1753 struct iha_sg_element *sg; 1754 uint32_t cnt; 1755 uint8_t period, stat; 1756 long xcnt; /* cannot use unsigned!! see code: if (xcnt < 0) */ 1757 int i; 1758 1759 cnt = bus_space_read_4(iot, ioh, TUL_STCNT0) & TCNT; 1760 1761 /* 1762 * Stop any pending DMA activity and check for parity error. 1763 */ 1764 1765 if ((bus_space_read_1(iot, ioh, TUL_DCMD) & XDIR) != 0) { 1766 /* Input Operation */ 1767 if ((sc->sc_status0 & SPERR) != 0) 1768 scb->ha_stat = HOST_SPERR; 1769 1770 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1771 bus_space_write_1(iot, ioh, TUL_DCTRL0, 1772 bus_space_read_1(iot, ioh, TUL_DCTRL0) | SXSTP); 1773 while (bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) 1774 ; 1775 } 1776 1777 } else { 1778 /* Output Operation */ 1779 if ((sc->sc_status1 & SXCMP) == 0) { 1780 period = scb->tcs->syncm; 1781 if ((period & PERIOD_WIDE_SCSI) != 0) 1782 cnt += (bus_space_read_1(iot, ioh, 1783 TUL_SFIFOCNT) & FIFOC) * 2; 1784 else 1785 cnt += bus_space_read_1(iot, ioh, 1786 TUL_SFIFOCNT) & FIFOC; 1787 } 1788 1789 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1790 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 1791 do 1792 stat = bus_space_read_1(iot, ioh, TUL_ISTUS0); 1793 while ((stat & DABT) == 0); 1794 } 1795 1796 if ((cnt == 1) && (sc->sc_phase == PHASE_DATA_OUT)) { 1797 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1798 return (-1); 1799 cnt = 0; 1800 1801 } else if ((sc->sc_status1 & SXCMP) == 0) 1802 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1803 } 1804 1805 if (cnt == 0) { 1806 scb->buflen = 0; 1807 return (6); 1808 } 1809 1810 /* Update active data pointer and restart the I/O at the new point */ 1811 1812 xcnt = scb->buflen - cnt; /* xcnt == bytes xferred */ 1813 scb->buflen = cnt; /* cnt == bytes left */ 1814 1815 if ((scb->flags & FLAG_SG) != 0) { 1816 sg = &scb->sglist[scb->sg_index]; 1817 for (i = scb->sg_index; i < scb->sg_max; sg++, i++) { 1818 xcnt -= le32toh(sg->sg_len); 1819 if (xcnt < 0) { 1820 xcnt += le32toh(sg->sg_len); 1821 1822 sg->sg_addr = 1823 htole32(le32toh(sg->sg_addr) + xcnt); 1824 sg->sg_len = 1825 htole32(le32toh(sg->sg_len) - xcnt); 1826 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1827 scb->sgoffset, IHA_SG_SIZE, 1828 BUS_DMASYNC_PREWRITE); 1829 1830 scb->bufaddr += (i - scb->sg_index) * 1831 sizeof(struct iha_sg_element); 1832 scb->sg_size = scb->sg_max - i; 1833 scb->sg_index = i; 1834 1835 return (4); 1836 } 1837 } 1838 return (6); 1839 1840 } else 1841 scb->bufaddr += xcnt; 1842 1843 return (4); 1844 } 1845 1846 /* 1847 * iha_state_6 - finish off the active scb (may require several 1848 * iterations if PHASE_MSG_IN) and return -1 to indicate 1849 * the bus is free. 1850 */ 1851 static int 1852 iha_state_6(struct iha_softc *sc) 1853 { 1854 1855 for (;;) { 1856 switch (sc->sc_phase) { 1857 case PHASE_STATUS_IN: 1858 if (iha_status_msg(sc) == -1) 1859 return (-1); 1860 break; 1861 1862 case PHASE_MSG_IN: 1863 sc->sc_actscb->nextstat = 6; 1864 if ((iha_msgin(sc)) == -1) 1865 return (-1); 1866 break; 1867 1868 case PHASE_MSG_OUT: 1869 if ((iha_msgout(sc, MSG_NOOP)) == -1) 1870 return (-1); 1871 break; 1872 1873 case PHASE_DATA_IN: 1874 if (iha_xpad_in(sc) == -1) 1875 return (-1); 1876 break; 1877 1878 case PHASE_DATA_OUT: 1879 if (iha_xpad_out(sc) == -1) 1880 return (-1); 1881 break; 1882 1883 default: 1884 iha_bad_seq(sc); 1885 return (-1); 1886 } 1887 } 1888 } 1889 1890 /* 1891 * iha_state_8 - reset the active device and all busy SCBs using it 1892 */ 1893 static int 1894 iha_state_8(struct iha_softc *sc) 1895 { 1896 bus_space_tag_t iot = sc->sc_iot; 1897 bus_space_handle_t ioh = sc->sc_ioh; 1898 struct iha_scb *scb; 1899 int i; 1900 uint8_t tar; 1901 1902 if (sc->sc_phase == PHASE_MSG_OUT) { 1903 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_BUS_DEV_RESET); 1904 1905 scb = sc->sc_actscb; 1906 1907 /* This SCB finished correctly -- resetting the device */ 1908 iha_append_done_scb(sc, scb, HOST_OK); 1909 1910 iha_reset_tcs(scb->tcs, sc->sc_sconf1); 1911 1912 tar = scb->target; 1913 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1914 if (scb->target == tar) 1915 switch (scb->status) { 1916 case STATUS_BUSY: 1917 iha_append_done_scb(sc, 1918 scb, HOST_DEV_RST); 1919 break; 1920 1921 case STATUS_SELECT: 1922 iha_push_pend_scb(sc, scb); 1923 break; 1924 1925 default: 1926 break; 1927 } 1928 1929 sc->sc_flags |= FLAG_EXPECT_DISC; 1930 1931 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1932 return (-1); 1933 } 1934 1935 iha_bad_seq(sc); 1936 return (-1); 1937 } 1938 1939 /* 1940 * iha_xfer_data - initiate the DMA xfer of the data 1941 */ 1942 static int 1943 iha_xfer_data(struct iha_softc *sc, struct iha_scb *scb, int direction) 1944 { 1945 bus_space_tag_t iot = sc->sc_iot; 1946 bus_space_handle_t ioh = sc->sc_ioh; 1947 uint32_t xferlen; 1948 uint8_t xfercmd; 1949 1950 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != direction) 1951 return (6); /* wrong direction, abandon I/O */ 1952 1953 bus_space_write_4(iot, ioh, TUL_STCNT0, scb->buflen); 1954 1955 xfercmd = STRXFR; 1956 if (direction == FLAG_DATAIN) 1957 xfercmd |= XDIR; 1958 1959 if (scb->flags & FLAG_SG) { 1960 xferlen = scb->sg_size * sizeof(struct iha_sg_element); 1961 xfercmd |= SGXFR; 1962 } else 1963 xferlen = scb->buflen; 1964 1965 bus_space_write_4(iot, ioh, TUL_DXC, xferlen); 1966 bus_space_write_4(iot, ioh, TUL_DXPA, scb->bufaddr); 1967 bus_space_write_1(iot, ioh, TUL_DCMD, xfercmd); 1968 1969 bus_space_write_1(iot, ioh, TUL_SCMD, 1970 (direction == FLAG_DATAIN) ? XF_DMA_IN : XF_DMA_OUT); 1971 1972 scb->nextstat = 5; 1973 1974 return (0); 1975 } 1976 1977 static int 1978 iha_xpad_in(struct iha_softc *sc) 1979 { 1980 bus_space_tag_t iot = sc->sc_iot; 1981 bus_space_handle_t ioh = sc->sc_ioh; 1982 struct iha_scb *scb = sc->sc_actscb; 1983 1984 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1985 scb->ha_stat = HOST_DO_DU; 1986 1987 for (;;) { 1988 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 1989 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 1990 else 1991 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1992 1993 switch (iha_wait(sc, XF_FIFO_IN)) { 1994 case -1: 1995 return (-1); 1996 1997 case PHASE_DATA_IN: 1998 bus_space_read_1(iot, ioh, TUL_SFIFO); 1999 break; 2000 2001 default: 2002 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2003 return (6); 2004 } 2005 } 2006 } 2007 2008 static int 2009 iha_xpad_out(struct iha_softc *sc) 2010 { 2011 bus_space_tag_t iot = sc->sc_iot; 2012 bus_space_handle_t ioh = sc->sc_ioh; 2013 struct iha_scb *scb = sc->sc_actscb; 2014 2015 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 2016 scb->ha_stat = HOST_DO_DU; 2017 2018 for (;;) { 2019 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 2020 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 2021 else 2022 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2023 2024 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 2025 2026 switch (iha_wait(sc, XF_FIFO_OUT)) { 2027 case -1: 2028 return (-1); 2029 2030 case PHASE_DATA_OUT: 2031 break; 2032 2033 default: 2034 /* Disable wide CPU to allow read 16 bits */ 2035 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2036 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2037 return (6); 2038 } 2039 } 2040 } 2041 2042 static int 2043 iha_status_msg(struct iha_softc *sc) 2044 { 2045 bus_space_tag_t iot = sc->sc_iot; 2046 bus_space_handle_t ioh = sc->sc_ioh; 2047 struct iha_scb *scb; 2048 uint8_t msg; 2049 int phase; 2050 2051 if ((phase = iha_wait(sc, CMD_COMP)) == -1) 2052 return (-1); 2053 2054 scb = sc->sc_actscb; 2055 2056 scb->ta_stat = bus_space_read_1(iot, ioh, TUL_SFIFO); 2057 2058 if (phase == PHASE_MSG_OUT) { 2059 if ((sc->sc_status0 & SPERR) == 0) 2060 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_NOOP); 2061 else 2062 bus_space_write_1(iot, ioh, TUL_SFIFO, 2063 MSG_PARITY_ERROR); 2064 2065 return (iha_wait(sc, XF_FIFO_OUT)); 2066 2067 } else if (phase == PHASE_MSG_IN) { 2068 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 2069 2070 if ((sc->sc_status0 & SPERR) != 0) 2071 switch (iha_wait(sc, MSG_ACCEPT)) { 2072 case -1: 2073 return (-1); 2074 case PHASE_MSG_OUT: 2075 bus_space_write_1(iot, ioh, TUL_SFIFO, 2076 MSG_PARITY_ERROR); 2077 return (iha_wait(sc, XF_FIFO_OUT)); 2078 default: 2079 iha_bad_seq(sc); 2080 return (-1); 2081 } 2082 2083 if (msg == MSG_CMDCOMPLETE) { 2084 if ((scb->ta_stat & 2085 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) { 2086 iha_bad_seq(sc); 2087 return (-1); 2088 } 2089 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 2090 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2091 return (iha_wait(sc, MSG_ACCEPT)); 2092 } 2093 2094 if ((msg == MSG_LINK_CMD_COMPLETE) 2095 || (msg == MSG_LINK_CMD_COMPLETEF)) { 2096 if ((scb->ta_stat & 2097 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) 2098 return (iha_wait(sc, MSG_ACCEPT)); 2099 } 2100 } 2101 2102 iha_bad_seq(sc); 2103 return (-1); 2104 } 2105 2106 /* 2107 * iha_busfree - SCSI bus free detected as a result of a TIMEOUT or 2108 * DISCONNECT interrupt. Reset the tulip FIFO and 2109 * SCONFIG0 and enable hardware reselect. Move any active 2110 * SCB to sc_donescb list. Return an appropriate host status 2111 * if an I/O was active. 2112 */ 2113 static void 2114 iha_busfree(struct iha_softc *sc) 2115 { 2116 bus_space_tag_t iot = sc->sc_iot; 2117 bus_space_handle_t ioh = sc->sc_ioh; 2118 struct iha_scb *scb; 2119 2120 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2121 bus_space_write_1(iot, ioh, TUL_SCONFIG0, SCONFIG0DEFAULT); 2122 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2123 2124 scb = sc->sc_actscb; 2125 2126 if (scb != NULL) { 2127 if (scb->status == STATUS_SELECT) 2128 /* selection timeout */ 2129 iha_append_done_scb(sc, scb, HOST_SEL_TOUT); 2130 else 2131 /* Unexpected bus free */ 2132 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 2133 } 2134 } 2135 2136 /* 2137 * iha_resel - handle a detected SCSI bus reselection request. 2138 */ 2139 static int 2140 iha_resel(struct iha_softc *sc) 2141 { 2142 bus_space_tag_t iot = sc->sc_iot; 2143 bus_space_handle_t ioh = sc->sc_ioh; 2144 struct iha_scb *scb; 2145 struct tcs *tcs; 2146 uint8_t tag, target, lun, msg, abortmsg; 2147 2148 if (sc->sc_actscb != NULL) { 2149 if ((sc->sc_actscb->status == STATUS_SELECT)) 2150 iha_push_pend_scb(sc, sc->sc_actscb); 2151 sc->sc_actscb = NULL; 2152 } 2153 2154 target = bus_space_read_1(iot, ioh, TUL_SBID); 2155 lun = bus_space_read_1(iot, ioh, TUL_SALVC) & IHA_MSG_IDENTIFY_LUNMASK; 2156 2157 tcs = &sc->sc_tcs[target]; 2158 2159 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2160 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2161 2162 abortmsg = MSG_ABORT; /* until a valid tag has been obtained */ 2163 2164 if (tcs->ntagscb != NULL) 2165 /* There is a non-tagged I/O active on the target */ 2166 scb = tcs->ntagscb; 2167 2168 else { 2169 /* 2170 * Since there is no active non-tagged operation 2171 * read the tag type, the tag itself, and find 2172 * the appropriate scb by indexing sc_scb with 2173 * the tag. 2174 */ 2175 2176 switch (iha_wait(sc, MSG_ACCEPT)) { 2177 case -1: 2178 return (-1); 2179 case PHASE_MSG_IN: 2180 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2181 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 2182 return (-1); 2183 break; 2184 default: 2185 goto abort; 2186 } 2187 2188 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag Msg */ 2189 2190 if ((msg < MSG_SIMPLE_Q_TAG) || (msg > MSG_ORDERED_Q_TAG)) 2191 goto abort; 2192 2193 switch (iha_wait(sc, MSG_ACCEPT)) { 2194 case -1: 2195 return (-1); 2196 case PHASE_MSG_IN: 2197 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2198 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 2199 return (-1); 2200 break; 2201 default: 2202 goto abort; 2203 } 2204 2205 tag = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag ID */ 2206 scb = &sc->sc_scb[tag]; 2207 2208 abortmsg = MSG_ABORT_TAG; /* Now that we have valdid tag! */ 2209 } 2210 2211 if ((scb->target != target) 2212 || (scb->lun != lun) 2213 || (scb->status != STATUS_BUSY)) { 2214 abort: 2215 iha_msgout_abort(sc, abortmsg); 2216 return (-1); 2217 } 2218 2219 sc->sc_actscb = scb; 2220 2221 if (iha_wait(sc, MSG_ACCEPT) == -1) 2222 return (-1); 2223 2224 return (iha_next_state(sc)); 2225 } 2226 2227 static int 2228 iha_msgin(struct iha_softc *sc) 2229 { 2230 bus_space_tag_t iot = sc->sc_iot; 2231 bus_space_handle_t ioh = sc->sc_ioh; 2232 int flags; 2233 int phase; 2234 uint8_t msg; 2235 2236 for (;;) { 2237 if ((bus_space_read_1(iot, ioh, TUL_SFIFOCNT) & FIFOC) > 0) 2238 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2239 2240 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2241 2242 phase = iha_wait(sc, XF_FIFO_IN); 2243 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 2244 2245 switch (msg) { 2246 case MSG_DISCONNECT: 2247 sc->sc_flags |= FLAG_EXPECT_DISC; 2248 if (iha_wait(sc, MSG_ACCEPT) != -1) 2249 iha_bad_seq(sc); 2250 phase = -1; 2251 break; 2252 case MSG_SAVEDATAPOINTER: 2253 case MSG_RESTOREPOINTERS: 2254 case MSG_NOOP: 2255 phase = iha_wait(sc, MSG_ACCEPT); 2256 break; 2257 case MSG_MESSAGE_REJECT: 2258 /* XXX - need to clear FIFO like other 'Clear ATN'?*/ 2259 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2260 flags = sc->sc_actscb->tcs->flags; 2261 if ((flags & FLAG_NO_NEG_SYNC) == 0) 2262 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2263 phase = iha_wait(sc, MSG_ACCEPT); 2264 break; 2265 case MSG_EXTENDED: 2266 phase = iha_msgin_extended(sc); 2267 break; 2268 case MSG_IGN_WIDE_RESIDUE: 2269 phase = iha_msgin_ignore_wid_resid(sc); 2270 break; 2271 case MSG_CMDCOMPLETE: 2272 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 2273 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2274 phase = iha_wait(sc, MSG_ACCEPT); 2275 if (phase != -1) { 2276 iha_bad_seq(sc); 2277 return (-1); 2278 } 2279 break; 2280 default: 2281 printf("[debug] iha_msgin: bad msg type: %d\n", msg); 2282 phase = iha_msgout_reject(sc); 2283 break; 2284 } 2285 2286 if (phase != PHASE_MSG_IN) 2287 return (phase); 2288 } 2289 /* NOTREACHED */ 2290 } 2291 2292 static int 2293 iha_msgin_extended(struct iha_softc *sc) 2294 { 2295 bus_space_tag_t iot = sc->sc_iot; 2296 bus_space_handle_t ioh = sc->sc_ioh; 2297 int flags, i, phase, msglen, msgcode; 2298 2299 /* 2300 * XXX - can we just stop reading and reject, or do we have to 2301 * read all input, discarding the excess, and then reject 2302 */ 2303 for (i = 0; i < IHA_MAX_EXTENDED_MSG; i++) { 2304 phase = iha_wait(sc, MSG_ACCEPT); 2305 2306 if (phase != PHASE_MSG_IN) 2307 return (phase); 2308 2309 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2310 2311 if (iha_wait(sc, XF_FIFO_IN) == -1) 2312 return (-1); 2313 2314 sc->sc_msg[i] = bus_space_read_1(iot, ioh, TUL_SFIFO); 2315 2316 if (sc->sc_msg[0] == i) 2317 break; 2318 } 2319 2320 msglen = sc->sc_msg[0]; 2321 msgcode = sc->sc_msg[1]; 2322 2323 if ((msglen == MSG_EXT_SDTR_LEN) && (msgcode == MSG_EXT_SDTR)) { 2324 if (iha_msgin_sdtr(sc) == 0) { 2325 iha_sync_done(sc); 2326 return (iha_wait(sc, MSG_ACCEPT)); 2327 } 2328 2329 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2330 2331 phase = iha_wait(sc, MSG_ACCEPT); 2332 if (phase != PHASE_MSG_OUT) 2333 return (phase); 2334 2335 /* Clear FIFO for important message - final SYNC offer */ 2336 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2337 2338 iha_sync_done(sc); /* This is our final offer */ 2339 2340 } else if ((msglen == MSG_EXT_WDTR_LEN) && (msgcode == MSG_EXT_WDTR)) { 2341 2342 flags = sc->sc_actscb->tcs->flags; 2343 2344 if ((flags & FLAG_NO_WIDE) != 0) 2345 /* Offer 8bit xfers only */ 2346 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_8_BIT; 2347 2348 else if (sc->sc_msg[2] > MSG_EXT_WDTR_BUS_32_BIT) 2349 /* BAD MSG */ 2350 return (iha_msgout_reject(sc)); 2351 2352 else if (sc->sc_msg[2] == MSG_EXT_WDTR_BUS_32_BIT) 2353 /* Offer 16bit instead */ 2354 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2355 2356 else { 2357 iha_wide_done(sc); 2358 if ((flags & FLAG_NO_NEG_SYNC) == 0) 2359 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2360 return (iha_wait(sc, MSG_ACCEPT)); 2361 } 2362 2363 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2364 2365 phase = iha_wait(sc, MSG_ACCEPT); 2366 if (phase != PHASE_MSG_OUT) 2367 return (phase); 2368 } else 2369 return (iha_msgout_reject(sc)); 2370 2371 return (iha_msgout_extended(sc)); 2372 } 2373 2374 /* 2375 * iha_msgin_sdtr - check SDTR msg in sc_msg. If the offer is 2376 * acceptable leave sc_msg as is and return 0. 2377 * If the negotiation must continue, modify sc_msg 2378 * as needed and return 1. Else return 0. 2379 */ 2380 static int 2381 iha_msgin_sdtr(struct iha_softc *sc) 2382 { 2383 int flags; 2384 int newoffer; 2385 uint8_t default_period; 2386 2387 flags = sc->sc_actscb->tcs->flags; 2388 2389 default_period = iha_rate_tbl[flags & FLAG_SCSI_RATE]; 2390 2391 if (sc->sc_msg[3] == 0) 2392 /* target offered async only. Accept it. */ 2393 return (0); 2394 2395 newoffer = 0; 2396 2397 if ((flags & FLAG_NO_SYNC) != 0) { 2398 sc->sc_msg[3] = 0; 2399 newoffer = 1; 2400 } 2401 2402 if (sc->sc_msg[3] > IHA_MAX_OFFSET) { 2403 sc->sc_msg[3] = IHA_MAX_OFFSET; 2404 newoffer = 1; 2405 } 2406 2407 if (sc->sc_msg[2] < default_period) { 2408 sc->sc_msg[2] = default_period; 2409 newoffer = 1; 2410 } 2411 2412 if (sc->sc_msg[2] > IHA_MAX_PERIOD) { 2413 /* Use async */ 2414 sc->sc_msg[3] = 0; 2415 newoffer = 1; 2416 } 2417 2418 return (newoffer); 2419 } 2420 2421 static int 2422 iha_msgin_ignore_wid_resid(struct iha_softc *sc) 2423 { 2424 bus_space_tag_t iot = sc->sc_iot; 2425 bus_space_handle_t ioh = sc->sc_ioh; 2426 int phase; 2427 2428 phase = iha_wait(sc, MSG_ACCEPT); 2429 2430 if (phase == PHASE_MSG_IN) { 2431 phase = iha_wait(sc, XF_FIFO_IN); 2432 2433 if (phase != -1) { 2434 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 2435 bus_space_read_1(iot, ioh, TUL_SFIFO); 2436 bus_space_read_1(iot, ioh, TUL_SFIFO); 2437 2438 phase = iha_wait(sc, MSG_ACCEPT); 2439 } 2440 } 2441 2442 return (phase); 2443 } 2444 2445 static int 2446 iha_msgout(struct iha_softc *sc, uint8_t msg) 2447 { 2448 2449 bus_space_write_1(sc->sc_iot, sc->sc_ioh, TUL_SFIFO, msg); 2450 2451 return (iha_wait(sc, XF_FIFO_OUT)); 2452 } 2453 2454 static void 2455 iha_msgout_abort(struct iha_softc *sc, uint8_t aborttype) 2456 { 2457 2458 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2459 2460 switch (iha_wait(sc, MSG_ACCEPT)) { 2461 case -1: 2462 break; 2463 2464 case PHASE_MSG_OUT: 2465 sc->sc_flags |= FLAG_EXPECT_DISC; 2466 if (iha_msgout(sc, aborttype) != -1) 2467 iha_bad_seq(sc); 2468 break; 2469 2470 default: 2471 iha_bad_seq(sc); 2472 break; 2473 } 2474 } 2475 2476 static int 2477 iha_msgout_reject(struct iha_softc *sc) 2478 { 2479 2480 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2481 2482 if (iha_wait(sc, MSG_ACCEPT) == PHASE_MSG_OUT) 2483 return (iha_msgout(sc, MSG_MESSAGE_REJECT)); 2484 2485 return (-1); 2486 } 2487 2488 static int 2489 iha_msgout_extended(struct iha_softc *sc) 2490 { 2491 bus_space_tag_t iot = sc->sc_iot; 2492 bus_space_handle_t ioh = sc->sc_ioh; 2493 int phase; 2494 2495 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXTENDED); 2496 2497 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 2498 sc->sc_msg, sc->sc_msg[0] + 1); 2499 2500 phase = iha_wait(sc, XF_FIFO_OUT); 2501 2502 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2503 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2504 2505 return (phase); 2506 } 2507 2508 static int 2509 iha_msgout_wdtr(struct iha_softc *sc) 2510 { 2511 2512 sc->sc_actscb->tcs->flags |= FLAG_WIDE_DONE; 2513 2514 sc->sc_msg[0] = MSG_EXT_WDTR_LEN; 2515 sc->sc_msg[1] = MSG_EXT_WDTR; 2516 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2517 2518 return (iha_msgout_extended(sc)); 2519 } 2520 2521 static int 2522 iha_msgout_sdtr(struct iha_softc *sc) 2523 { 2524 struct tcs *tcs = sc->sc_actscb->tcs; 2525 2526 tcs->flags |= FLAG_SYNC_DONE; 2527 2528 sc->sc_msg[0] = MSG_EXT_SDTR_LEN; 2529 sc->sc_msg[1] = MSG_EXT_SDTR; 2530 sc->sc_msg[2] = iha_rate_tbl[tcs->flags & FLAG_SCSI_RATE]; 2531 sc->sc_msg[3] = IHA_MAX_OFFSET; /* REQ/ACK */ 2532 2533 return (iha_msgout_extended(sc)); 2534 } 2535 2536 static void 2537 iha_wide_done(struct iha_softc *sc) 2538 { 2539 bus_space_tag_t iot = sc->sc_iot; 2540 bus_space_handle_t ioh = sc->sc_ioh; 2541 struct tcs *tcs = sc->sc_actscb->tcs; 2542 2543 tcs->syncm = 0; 2544 tcs->period = 0; 2545 tcs->offset = 0; 2546 2547 if (sc->sc_msg[2] != 0) 2548 tcs->syncm |= PERIOD_WIDE_SCSI; 2549 2550 tcs->sconfig0 &= ~ALTPD; 2551 tcs->flags &= ~FLAG_SYNC_DONE; 2552 tcs->flags |= FLAG_WIDE_DONE; 2553 2554 iha_update_xfer_mode(sc, sc->sc_actscb->target); 2555 2556 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2557 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2558 } 2559 2560 static void 2561 iha_sync_done(struct iha_softc *sc) 2562 { 2563 bus_space_tag_t iot = sc->sc_iot; 2564 bus_space_handle_t ioh = sc->sc_ioh; 2565 struct tcs *tcs = sc->sc_actscb->tcs; 2566 int i; 2567 2568 tcs->period = sc->sc_msg[2]; 2569 tcs->offset = sc->sc_msg[3]; 2570 if (tcs->offset != 0) { 2571 tcs->syncm |= tcs->offset; 2572 2573 /* pick the highest possible rate */ 2574 for (i = 0; i < sizeof(iha_rate_tbl); i++) 2575 if (iha_rate_tbl[i] >= tcs->period) 2576 break; 2577 2578 tcs->syncm |= (i << 4); 2579 tcs->sconfig0 |= ALTPD; 2580 } 2581 2582 tcs->flags |= FLAG_SYNC_DONE; 2583 2584 iha_update_xfer_mode(sc, sc->sc_actscb->target); 2585 2586 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2587 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2588 } 2589 2590 /* 2591 * iha_bad_seq - a SCSI bus phase was encountered out of the 2592 * correct/expected sequence. Reset the SCSI bus. 2593 */ 2594 static void 2595 iha_bad_seq(struct iha_softc *sc) 2596 { 2597 struct iha_scb *scb = sc->sc_actscb; 2598 2599 if (scb != NULL) 2600 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 2601 2602 iha_reset_scsi_bus(sc); 2603 iha_reset_chip(sc); 2604 } 2605 2606 /* 2607 * iha_read_eeprom - read Serial EEPROM value & set to defaults 2608 * if required. XXX - Writing does NOT work! 2609 */ 2610 static void 2611 iha_read_eeprom(struct iha_softc *sc, struct iha_eeprom *eeprom) 2612 { 2613 bus_space_tag_t iot = sc->sc_iot; 2614 bus_space_handle_t ioh = sc->sc_ioh; 2615 uint16_t *tbuf = (uint16_t *)eeprom; 2616 uint8_t gctrl; 2617 2618 /* Enable EEProm programming */ 2619 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) | EEPRG; 2620 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2621 2622 /* Read EEProm */ 2623 if (iha_se2_rd_all(sc, tbuf) == 0) 2624 panic("%s: cannot read EEPROM", sc->sc_dev.dv_xname); 2625 2626 /* Disable EEProm programming */ 2627 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) & ~EEPRG; 2628 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2629 } 2630 2631 #ifdef notused 2632 /* 2633 * iha_se2_update_all - Update SCSI H/A configuration parameters from 2634 * serial EEPROM Setup default pattern. Only 2635 * change those values different from the values 2636 * in iha_eeprom. 2637 */ 2638 static void 2639 iha_se2_update_all(struct iha_softc *sc) 2640 { 2641 bus_space_tag_t iot = sc->sc_iot; 2642 bus_space_handle_t ioh = sc->sc_ioh; 2643 uint16_t *np; 2644 uint32_t chksum; 2645 int i; 2646 2647 /* Enable erase/write state of EEPROM */ 2648 iha_se2_instr(sc, ENABLE_ERASE); 2649 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2650 EEP_WAIT(); 2651 2652 np = (uint16_t *)&eeprom_default; 2653 2654 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2655 iha_se2_wr(sc, i, *np); 2656 chksum += *np++; 2657 } 2658 2659 chksum &= 0x0000ffff; 2660 iha_se2_wr(sc, 31, chksum); 2661 2662 /* Disable erase/write state of EEPROM */ 2663 iha_se2_instr(sc, 0); 2664 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2665 EEP_WAIT(); 2666 } 2667 2668 /* 2669 * iha_se2_wr - write the given 16 bit value into the Serial EEPROM 2670 * at the specified offset 2671 */ 2672 static void 2673 iha_se2_wr(struct iha_softc *sc, int addr, uint16_t writeword) 2674 { 2675 bus_space_tag_t iot = sc->sc_iot; 2676 bus_space_handle_t ioh = sc->sc_ioh; 2677 int i, bit; 2678 2679 /* send 'WRITE' Instruction == address | WRITE bit */ 2680 iha_se2_instr(sc, addr | WRITE); 2681 2682 for (i = 16; i > 0; i--) { 2683 if (writeword & (1 << (i - 1))) 2684 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRDO); 2685 else 2686 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2687 EEP_WAIT(); 2688 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2689 EEP_WAIT(); 2690 } 2691 2692 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2693 EEP_WAIT(); 2694 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2695 EEP_WAIT(); 2696 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2697 EEP_WAIT(); 2698 2699 for (;;) { 2700 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2701 EEP_WAIT(); 2702 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2703 EEP_WAIT(); 2704 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI; 2705 EEP_WAIT(); 2706 if (bit != 0) 2707 break; /* write complete */ 2708 } 2709 2710 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2711 } 2712 #endif 2713 2714 /* 2715 * iha_se2_rd - read & return the 16 bit value at the specified 2716 * offset in the Serial E2PROM 2717 * 2718 */ 2719 static uint16_t 2720 iha_se2_rd(struct iha_softc *sc, int addr) 2721 { 2722 bus_space_tag_t iot = sc->sc_iot; 2723 bus_space_handle_t ioh = sc->sc_ioh; 2724 int i, bit; 2725 uint16_t readword; 2726 2727 /* Send 'READ' instruction == address | READ bit */ 2728 iha_se2_instr(sc, addr | READ); 2729 2730 readword = 0; 2731 for (i = 16; i > 0; i--) { 2732 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2733 EEP_WAIT(); 2734 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2735 EEP_WAIT(); 2736 /* sample data after the following edge of clock */ 2737 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI ? 1 : 0; 2738 EEP_WAIT(); 2739 2740 readword |= bit << (i - 1); 2741 } 2742 2743 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2744 2745 return (readword); 2746 } 2747 2748 /* 2749 * iha_se2_rd_all - Read SCSI H/A config parameters from serial EEPROM 2750 */ 2751 static int 2752 iha_se2_rd_all(struct iha_softc *sc, uint16_t *tbuf) 2753 { 2754 struct iha_eeprom *eeprom = (struct iha_eeprom *)tbuf; 2755 uint32_t chksum; 2756 int i; 2757 2758 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2759 *tbuf = iha_se2_rd(sc, i); 2760 chksum += *tbuf++; 2761 } 2762 *tbuf = iha_se2_rd(sc, 31); /* read checksum from EEPROM */ 2763 2764 chksum &= 0x0000ffff; /* lower 16 bits */ 2765 2766 return (eeprom->signature == EEP_SIGNATURE) && 2767 (eeprom->checksum == chksum); 2768 } 2769 2770 /* 2771 * iha_se2_instr - write an octet to serial E2PROM one bit at a time 2772 */ 2773 static void 2774 iha_se2_instr(struct iha_softc *sc, int instr) 2775 { 2776 bus_space_tag_t iot = sc->sc_iot; 2777 bus_space_handle_t ioh = sc->sc_ioh; 2778 int b, i; 2779 2780 b = NVRCS | NVRDO; /* Write the start bit (== 1) */ 2781 2782 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2783 EEP_WAIT(); 2784 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2785 EEP_WAIT(); 2786 2787 for (i = 8; i > 0; i--) { 2788 if (instr & (1 << (i - 1))) 2789 b = NVRCS | NVRDO; /* Write a 1 bit */ 2790 else 2791 b = NVRCS; /* Write a 0 bit */ 2792 2793 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2794 EEP_WAIT(); 2795 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2796 EEP_WAIT(); 2797 } 2798 2799 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2800 } 2801
Indexes created Fri Sep 26 20:09:58 GMT 2025