iha.c revision 1.36
1 /* $NetBSD: iha.c,v 1.36 2007/10/19 11:59:53 ad Exp $ */ 2 3 /*- 4 * Device driver for the INI-9XXXU/UW or INIC-940/950 PCI SCSI Controller. 5 * 6 * Written for 386bsd and FreeBSD by 7 * Winston Hung <winstonh (at) initio.com> 8 * 9 * Copyright (c) 1997-1999 Initio Corp. 10 * Copyright (c) 2000, 2001 Ken Westerback 11 * Copyright (c) 2001, 2002 Izumi Tsutsui 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer, 19 * without modification, immediately at the beginning of the file. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 32 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * Ported to NetBSD by Izumi Tsutsui <tsutsui (at) ceres.dti.ne.jp> from OpenBSD: 38 * $OpenBSD: iha.c,v 1.3 2001/02/20 00:47:33 krw Exp $ 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: iha.c,v 1.36 2007/10/19 11:59:53 ad Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/buf.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <sys/bus.h> 54 #include <sys/intr.h> 55 56 #include <dev/scsipi/scsi_spc.h> 57 #include <dev/scsipi/scsi_all.h> 58 #include <dev/scsipi/scsipi_all.h> 59 #include <dev/scsipi/scsiconf.h> 60 #include <dev/scsipi/scsi_message.h> 61 62 #include <dev/ic/ihareg.h> 63 #include <dev/ic/ihavar.h> 64 65 /* 66 * SCSI Rate Table, indexed by FLAG_SCSI_RATE field of 67 * tcs flags. 68 */ 69 static const uint8_t iha_rate_tbl[] = { 70 /* fast 20 */ 71 /* nanosecond divide by 4 */ 72 12, /* 50ns, 20M */ 73 18, /* 75ns, 13.3M */ 74 25, /* 100ns, 10M */ 75 31, /* 125ns, 8M */ 76 37, /* 150ns, 6.6M */ 77 43, /* 175ns, 5.7M */ 78 50, /* 200ns, 5M */ 79 62 /* 250ns, 4M */ 80 }; 81 #define IHA_MAX_PERIOD 62 82 83 #ifdef notused 84 static uint16_t eeprom_default[EEPROM_SIZE] = { 85 /* -- Header ------------------------------------ */ 86 /* signature */ 87 EEP_SIGNATURE, 88 /* size, revision */ 89 EEP_WORD(EEPROM_SIZE * 2, 0x01), 90 /* -- Host Adapter Structure -------------------- */ 91 /* model */ 92 0x0095, 93 /* model info, number of channel */ 94 EEP_WORD(0x00, 1), 95 /* BIOS config */ 96 EEP_BIOSCFG_DEFAULT, 97 /* host adapter config */ 98 0, 99 100 /* -- eeprom_adapter[0] ------------------------------- */ 101 /* ID, adapter config 1 */ 102 EEP_WORD(7, CFG_DEFAULT), 103 /* adapter config 2, number of targets */ 104 EEP_WORD(0x00, 8), 105 /* target flags */ 106 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 107 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 108 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 109 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 110 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 111 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 112 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 113 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 114 115 /* -- eeprom_adapter[1] ------------------------------- */ 116 /* ID, adapter config 1 */ 117 EEP_WORD(7, CFG_DEFAULT), 118 /* adapter config 2, number of targets */ 119 EEP_WORD(0x00, 8), 120 /* target flags */ 121 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 122 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 123 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 124 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 125 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 126 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 127 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 128 EEP_WORD(FLAG_DEFAULT, FLAG_DEFAULT), 129 /* reserved[5] */ 130 0, 0, 0, 0, 0, 131 /* checksum */ 132 0 133 }; 134 #endif 135 136 static void iha_append_free_scb(struct iha_softc *, struct iha_scb *); 137 static void iha_append_done_scb(struct iha_softc *, struct iha_scb *, uint8_t); 138 static inline struct iha_scb *iha_pop_done_scb(struct iha_softc *); 139 140 static struct iha_scb *iha_find_pend_scb(struct iha_softc *); 141 static inline void iha_append_pend_scb(struct iha_softc *, struct iha_scb *); 142 static inline void iha_push_pend_scb(struct iha_softc *, struct iha_scb *); 143 static inline void iha_del_pend_scb(struct iha_softc *, struct iha_scb *); 144 static inline void iha_mark_busy_scb(struct iha_scb *); 145 146 static inline void iha_set_ssig(struct iha_softc *, uint8_t, uint8_t); 147 148 static int iha_alloc_sglist(struct iha_softc *); 149 150 static void iha_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 151 void *); 152 static void iha_update_xfer_mode(struct iha_softc *, int); 153 154 static void iha_reset_scsi_bus(struct iha_softc *); 155 static void iha_reset_chip(struct iha_softc *); 156 static void iha_reset_dma(struct iha_softc *); 157 static void iha_reset_tcs(struct tcs *, uint8_t); 158 159 static void iha_main(struct iha_softc *); 160 static void iha_scsi(struct iha_softc *); 161 static void iha_select(struct iha_softc *, struct iha_scb *, uint8_t); 162 static int iha_wait(struct iha_softc *, uint8_t); 163 164 static void iha_exec_scb(struct iha_softc *, struct iha_scb *); 165 static void iha_done_scb(struct iha_softc *, struct iha_scb *); 166 static int iha_push_sense_request(struct iha_softc *, struct iha_scb *); 167 168 static void iha_timeout(void *); 169 static void iha_abort_xs(struct iha_softc *, struct scsipi_xfer *, uint8_t); 170 static uint8_t iha_data_over_run(struct iha_scb *); 171 172 static int iha_next_state(struct iha_softc *); 173 static int iha_state_1(struct iha_softc *); 174 static int iha_state_2(struct iha_softc *); 175 static int iha_state_3(struct iha_softc *); 176 static int iha_state_4(struct iha_softc *); 177 static int iha_state_5(struct iha_softc *); 178 static int iha_state_6(struct iha_softc *); 179 static int iha_state_8(struct iha_softc *); 180 181 static int iha_xfer_data(struct iha_softc *, struct iha_scb *, int); 182 static int iha_xpad_in(struct iha_softc *); 183 static int iha_xpad_out(struct iha_softc *); 184 185 static int iha_status_msg(struct iha_softc *); 186 static void iha_busfree(struct iha_softc *); 187 static int iha_resel(struct iha_softc *); 188 189 static int iha_msgin(struct iha_softc *); 190 static int iha_msgin_extended(struct iha_softc *); 191 static int iha_msgin_sdtr(struct iha_softc *); 192 static int iha_msgin_ignore_wid_resid(struct iha_softc *); 193 194 static int iha_msgout(struct iha_softc *, uint8_t); 195 static void iha_msgout_abort(struct iha_softc *, uint8_t); 196 static int iha_msgout_reject(struct iha_softc *); 197 static int iha_msgout_extended(struct iha_softc *); 198 static int iha_msgout_wdtr(struct iha_softc *); 199 static int iha_msgout_sdtr(struct iha_softc *); 200 201 static void iha_wide_done(struct iha_softc *); 202 static void iha_sync_done(struct iha_softc *); 203 204 static void iha_bad_seq(struct iha_softc *); 205 206 static void iha_read_eeprom(struct iha_softc *, struct iha_eeprom *); 207 static int iha_se2_rd_all(struct iha_softc *, uint16_t *); 208 static void iha_se2_instr(struct iha_softc *, int); 209 static uint16_t iha_se2_rd(struct iha_softc *, int); 210 #ifdef notused 211 static void iha_se2_update_all(struct iha_softc *); 212 static void iha_se2_wr(struct iha_softc *, int, uint16_t); 213 #endif 214 215 /* 216 * iha_append_free_scb - append the supplied SCB to the tail of the 217 * sc_freescb queue after clearing and resetting 218 * everything possible. 219 */ 220 static void 221 iha_append_free_scb(struct iha_softc *sc, struct iha_scb *scb) 222 { 223 int s; 224 225 s = splbio(); 226 227 if (scb == sc->sc_actscb) 228 sc->sc_actscb = NULL; 229 230 scb->status = STATUS_QUEUED; 231 scb->ha_stat = HOST_OK; 232 scb->ta_stat = SCSI_OK; 233 234 scb->nextstat = 0; 235 scb->scb_tagmsg = 0; 236 237 scb->xs = NULL; 238 scb->tcs = NULL; 239 240 /* 241 * scb_tagid, sg_addr, sglist 242 * SCB_SensePtr are set at initialization 243 * and never change 244 */ 245 246 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 247 248 splx(s); 249 } 250 251 static void 252 iha_append_done_scb(struct iha_softc *sc, struct iha_scb *scb, uint8_t hastat) 253 { 254 struct tcs *tcs; 255 int s; 256 257 s = splbio(); 258 259 if (scb->xs != NULL) 260 callout_stop(&scb->xs->xs_callout); 261 262 if (scb == sc->sc_actscb) 263 sc->sc_actscb = NULL; 264 265 tcs = scb->tcs; 266 267 if (scb->scb_tagmsg != 0) { 268 if (tcs->tagcnt) 269 tcs->tagcnt--; 270 } else if (tcs->ntagscb == scb) 271 tcs->ntagscb = NULL; 272 273 scb->status = STATUS_QUEUED; 274 scb->ha_stat = hastat; 275 276 TAILQ_INSERT_TAIL(&sc->sc_donescb, scb, chain); 277 278 splx(s); 279 } 280 281 static inline struct iha_scb * 282 iha_pop_done_scb(struct iha_softc *sc) 283 { 284 struct iha_scb *scb; 285 int s; 286 287 s = splbio(); 288 289 scb = TAILQ_FIRST(&sc->sc_donescb); 290 291 if (scb != NULL) { 292 scb->status = STATUS_RENT; 293 TAILQ_REMOVE(&sc->sc_donescb, scb, chain); 294 } 295 296 splx(s); 297 298 return (scb); 299 } 300 301 /* 302 * iha_find_pend_scb - scan the pending queue for a SCB that can be 303 * processed immediately. Return NULL if none found 304 * and a pointer to the SCB if one is found. If there 305 * is an active SCB, return NULL! 306 */ 307 static struct iha_scb * 308 iha_find_pend_scb(struct iha_softc *sc) 309 { 310 struct iha_scb *scb; 311 struct tcs *tcs; 312 int s; 313 314 s = splbio(); 315 316 if (sc->sc_actscb != NULL) 317 scb = NULL; 318 319 else 320 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) { 321 if ((scb->xs->xs_control & XS_CTL_RESET) != 0) 322 /* ALWAYS willing to reset a device */ 323 break; 324 325 tcs = scb->tcs; 326 327 if ((scb->scb_tagmsg) != 0) { 328 /* 329 * A Tagged I/O. OK to start If no 330 * non-tagged I/O is active on the same 331 * target 332 */ 333 if (tcs->ntagscb == NULL) 334 break; 335 336 } else if (scb->cmd[0] == SCSI_REQUEST_SENSE) { 337 /* 338 * OK to do a non-tagged request sense 339 * even if a non-tagged I/O has been 340 * started, 'cuz we don't allow any 341 * disconnect during a request sense op 342 */ 343 break; 344 345 } else if (tcs->tagcnt == 0) { 346 /* 347 * No tagged I/O active on this target, 348 * ok to start a non-tagged one if one 349 * is not already active 350 */ 351 if (tcs->ntagscb == NULL) 352 break; 353 } 354 } 355 356 splx(s); 357 358 return (scb); 359 } 360 361 static inline void 362 iha_append_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 363 { 364 /* ASSUMPTION: only called within a splbio()/splx() pair */ 365 366 if (scb == sc->sc_actscb) 367 sc->sc_actscb = NULL; 368 369 scb->status = STATUS_QUEUED; 370 371 TAILQ_INSERT_TAIL(&sc->sc_pendscb, scb, chain); 372 } 373 374 static inline void 375 iha_push_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 376 { 377 int s; 378 379 s = splbio(); 380 381 if (scb == sc->sc_actscb) 382 sc->sc_actscb = NULL; 383 384 scb->status = STATUS_QUEUED; 385 386 TAILQ_INSERT_HEAD(&sc->sc_pendscb, scb, chain); 387 388 splx(s); 389 } 390 391 /* 392 * iha_del_pend_scb - remove scb from sc_pendscb 393 */ 394 static inline void 395 iha_del_pend_scb(struct iha_softc *sc, struct iha_scb *scb) 396 { 397 int s; 398 399 s = splbio(); 400 401 TAILQ_REMOVE(&sc->sc_pendscb, scb, chain); 402 403 splx(s); 404 } 405 406 static inline void 407 iha_mark_busy_scb(struct iha_scb *scb) 408 { 409 int s; 410 411 s = splbio(); 412 413 scb->status = STATUS_BUSY; 414 415 if (scb->scb_tagmsg == 0) 416 scb->tcs->ntagscb = scb; 417 else 418 scb->tcs->tagcnt++; 419 420 splx(s); 421 } 422 423 /* 424 * iha_set_ssig - read the current scsi signal mask, then write a new 425 * one which turns off/on the specified signals. 426 */ 427 static inline void 428 iha_set_ssig(struct iha_softc *sc, uint8_t offsigs, uint8_t onsigs) 429 { 430 bus_space_tag_t iot = sc->sc_iot; 431 bus_space_handle_t ioh = sc->sc_ioh; 432 uint8_t currsigs; 433 434 currsigs = bus_space_read_1(iot, ioh, TUL_SSIGI); 435 bus_space_write_1(iot, ioh, TUL_SSIGO, (currsigs & ~offsigs) | onsigs); 436 } 437 438 /* 439 * iha_intr - the interrupt service routine for the iha driver 440 */ 441 int 442 iha_intr(void *arg) 443 { 444 bus_space_tag_t iot; 445 bus_space_handle_t ioh; 446 struct iha_softc *sc; 447 int s; 448 449 sc = (struct iha_softc *)arg; 450 iot = sc->sc_iot; 451 ioh = sc->sc_ioh; 452 453 if ((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 454 return (0); 455 456 s = splbio(); /* XXX - Or are interrupts off when ISR's are called? */ 457 458 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 459 /* XXX - need these inside a splbio()/splx()? */ 460 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 461 sc->sc_semaph = SEMAPH_IN_MAIN; 462 463 iha_main(sc); 464 465 sc->sc_semaph = ~SEMAPH_IN_MAIN; 466 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 467 } 468 469 splx(s); 470 471 return (1); 472 } 473 474 void 475 iha_attach(struct iha_softc *sc) 476 { 477 bus_space_tag_t iot = sc->sc_iot; 478 bus_space_handle_t ioh = sc->sc_ioh; 479 struct iha_scb *scb; 480 struct iha_eeprom eeprom; 481 struct eeprom_adapter *conf; 482 int i, error, reg; 483 484 iha_read_eeprom(sc, &eeprom); 485 486 conf = &eeprom.adapter[0]; 487 488 /* 489 * fill in the rest of the iha_softc fields 490 */ 491 sc->sc_id = CFG_ID(conf->config1); 492 sc->sc_semaph = ~SEMAPH_IN_MAIN; 493 sc->sc_status0 = 0; 494 sc->sc_actscb = NULL; 495 496 TAILQ_INIT(&sc->sc_freescb); 497 TAILQ_INIT(&sc->sc_pendscb); 498 TAILQ_INIT(&sc->sc_donescb); 499 error = iha_alloc_sglist(sc); 500 if (error != 0) { 501 printf(": cannot allocate sglist\n"); 502 return; 503 } 504 505 sc->sc_scb = malloc(sizeof(struct iha_scb) * IHA_MAX_SCB, 506 M_DEVBUF, M_NOWAIT|M_ZERO); 507 if (sc->sc_scb == NULL) { 508 printf(": cannot allocate SCB\n"); 509 return; 510 } 511 512 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) { 513 scb->scb_tagid = i; 514 scb->sgoffset = IHA_SG_SIZE * i; 515 scb->sglist = sc->sc_sglist + IHA_MAX_SG_ENTRIES * i; 516 scb->sg_addr = 517 sc->sc_dmamap->dm_segs[0].ds_addr + scb->sgoffset; 518 519 error = bus_dmamap_create(sc->sc_dmat, 520 MAXPHYS, IHA_MAX_SG_ENTRIES, MAXPHYS, 0, 521 BUS_DMA_NOWAIT, &scb->dmap); 522 523 if (error != 0) { 524 printf(": couldn't create SCB DMA map, error = %d\n", 525 error); 526 return; 527 } 528 TAILQ_INSERT_TAIL(&sc->sc_freescb, scb, chain); 529 } 530 531 /* Mask all the interrupts */ 532 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 533 534 /* Stop any I/O and reset the scsi module */ 535 iha_reset_dma(sc); 536 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSMOD); 537 538 /* Program HBA's SCSI ID */ 539 bus_space_write_1(iot, ioh, TUL_SID, sc->sc_id << 4); 540 541 /* 542 * Configure the channel as requested by the NVRAM settings read 543 * by iha_read_eeprom() above. 544 */ 545 546 sc->sc_sconf1 = SCONFIG0DEFAULT; 547 if ((conf->config1 & CFG_EN_PAR) != 0) 548 sc->sc_sconf1 |= SPCHK; 549 bus_space_write_1(iot, ioh, TUL_SCONFIG0, sc->sc_sconf1); 550 551 /* set selection time out 250 ms */ 552 bus_space_write_1(iot, ioh, TUL_STIMO, STIMO_250MS); 553 554 /* Enable desired SCSI termination configuration read from eeprom */ 555 reg = 0; 556 if (conf->config1 & CFG_ACT_TERM1) 557 reg |= ENTMW; 558 if (conf->config1 & CFG_ACT_TERM2) 559 reg |= ENTM; 560 bus_space_write_1(iot, ioh, TUL_DCTRL0, reg); 561 562 reg = bus_space_read_1(iot, ioh, TUL_GCTRL1) & ~ATDEN; 563 if (conf->config1 & CFG_AUTO_TERM) 564 reg |= ATDEN; 565 bus_space_write_1(iot, ioh, TUL_GCTRL1, reg); 566 567 for (i = 0; i < IHA_MAX_TARGETS / 2; i++) { 568 sc->sc_tcs[i * 2 ].flags = EEP_LBYTE(conf->tflags[i]); 569 sc->sc_tcs[i * 2 + 1].flags = EEP_HBYTE(conf->tflags[i]); 570 iha_reset_tcs(&sc->sc_tcs[i * 2 ], sc->sc_sconf1); 571 iha_reset_tcs(&sc->sc_tcs[i * 2 + 1], sc->sc_sconf1); 572 } 573 574 iha_reset_chip(sc); 575 bus_space_write_1(iot, ioh, TUL_SIEN, ALL_INTERRUPTS); 576 577 /* 578 * fill in the adapter. 579 */ 580 sc->sc_adapter.adapt_dev = &sc->sc_dev; 581 sc->sc_adapter.adapt_nchannels = 1; 582 sc->sc_adapter.adapt_openings = IHA_MAX_SCB; 583 sc->sc_adapter.adapt_max_periph = IHA_MAX_SCB; 584 sc->sc_adapter.adapt_ioctl = NULL; 585 sc->sc_adapter.adapt_minphys = minphys; 586 sc->sc_adapter.adapt_request = iha_scsipi_request; 587 588 /* 589 * fill in the channel. 590 */ 591 sc->sc_channel.chan_adapter = &sc->sc_adapter; 592 sc->sc_channel.chan_bustype = &scsi_bustype; 593 sc->sc_channel.chan_channel = 0; 594 sc->sc_channel.chan_ntargets = CFG_TARGET(conf->config2); 595 sc->sc_channel.chan_nluns = 8; 596 sc->sc_channel.chan_id = sc->sc_id; 597 598 /* 599 * Now try to attach all the sub devices. 600 */ 601 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 602 } 603 604 /* 605 * iha_alloc_sglist - allocate and map sglist for SCB's 606 */ 607 static int 608 iha_alloc_sglist(struct iha_softc *sc) 609 { 610 bus_dma_segment_t seg; 611 int error, rseg; 612 613 /* 614 * Allocate DMA-safe memory for the SCB's sglist 615 */ 616 if ((error = bus_dmamem_alloc(sc->sc_dmat, 617 IHA_SG_SIZE * IHA_MAX_SCB, 618 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 619 printf(": unable to allocate sglist, error = %d\n", error); 620 return (error); 621 } 622 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 623 IHA_SG_SIZE * IHA_MAX_SCB, (void **)&sc->sc_sglist, 624 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 625 printf(": unable to map sglist, error = %d\n", error); 626 return (error); 627 } 628 629 /* 630 * Create and load the DMA map used for the SCBs 631 */ 632 if ((error = bus_dmamap_create(sc->sc_dmat, 633 IHA_SG_SIZE * IHA_MAX_SCB, 1, IHA_SG_SIZE * IHA_MAX_SCB, 634 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 635 printf(": unable to create control DMA map, error = %d\n", 636 error); 637 return (error); 638 } 639 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 640 sc->sc_sglist, IHA_SG_SIZE * IHA_MAX_SCB, 641 NULL, BUS_DMA_NOWAIT)) != 0) { 642 printf(": unable to load control DMA map, error = %d\n", error); 643 return (error); 644 } 645 646 memset(sc->sc_sglist, 0, IHA_SG_SIZE * IHA_MAX_SCB); 647 648 return (0); 649 } 650 651 void 652 iha_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 653 void *arg) 654 { 655 struct scsipi_xfer *xs; 656 struct scsipi_periph *periph; 657 struct iha_scb *scb; 658 struct iha_softc *sc; 659 int error, s; 660 661 sc = (struct iha_softc *)chan->chan_adapter->adapt_dev; 662 663 switch (req) { 664 case ADAPTER_REQ_RUN_XFER: 665 xs = arg; 666 periph = xs->xs_periph; 667 668 /* XXX This size isn't actually a hardware restriction. */ 669 if (xs->cmdlen > sizeof(scb->cmd) || 670 periph->periph_target >= IHA_MAX_TARGETS) { 671 xs->error = XS_DRIVER_STUFFUP; 672 scsipi_done(xs); 673 return; 674 } 675 676 s = splbio(); 677 scb = TAILQ_FIRST(&sc->sc_freescb); 678 if (scb != NULL) { 679 scb->status = STATUS_RENT; 680 TAILQ_REMOVE(&sc->sc_freescb, scb, chain); 681 } 682 else { 683 printf("unable to allocate scb\n"); 684 #ifdef DIAGNOSTIC 685 scsipi_printaddr(periph); 686 panic("iha_scsipi_request"); 687 #else 688 splx(s); 689 return; 690 #endif 691 } 692 splx(s); 693 694 scb->target = periph->periph_target; 695 scb->lun = periph->periph_lun; 696 scb->tcs = &sc->sc_tcs[scb->target]; 697 scb->scb_id = MSG_IDENTIFY(periph->periph_lun, 698 (xs->xs_control & XS_CTL_REQSENSE) == 0); 699 700 scb->xs = xs; 701 scb->cmdlen = xs->cmdlen; 702 memcpy(&scb->cmd, xs->cmd, xs->cmdlen); 703 scb->buflen = xs->datalen; 704 scb->flags = 0; 705 if (xs->xs_control & XS_CTL_DATA_OUT) 706 scb->flags |= FLAG_DATAOUT; 707 if (xs->xs_control & XS_CTL_DATA_IN) 708 scb->flags |= FLAG_DATAIN; 709 710 if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 711 error = bus_dmamap_load(sc->sc_dmat, scb->dmap, 712 xs->data, scb->buflen, NULL, 713 ((xs->xs_control & XS_CTL_NOSLEEP) ? 714 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 715 BUS_DMA_STREAMING | 716 ((scb->flags & FLAG_DATAIN) ? 717 BUS_DMA_READ : BUS_DMA_WRITE)); 718 719 if (error) { 720 printf("%s: error %d loading DMA map\n", 721 sc->sc_dev.dv_xname, error); 722 iha_append_free_scb(sc, scb); 723 xs->error = XS_DRIVER_STUFFUP; 724 scsipi_done(xs); 725 return; 726 } 727 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 728 0, scb->dmap->dm_mapsize, 729 (scb->flags & FLAG_DATAIN) ? 730 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 731 } 732 733 iha_exec_scb(sc, scb); 734 return; 735 736 case ADAPTER_REQ_GROW_RESOURCES: 737 return; /* XXX */ 738 739 case ADAPTER_REQ_SET_XFER_MODE: 740 { 741 struct tcs *tcs; 742 struct scsipi_xfer_mode *xm = arg; 743 744 tcs = &sc->sc_tcs[xm->xm_target]; 745 746 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 747 (tcs->flags & FLAG_NO_WIDE) == 0) 748 tcs->flags &= ~(FLAG_WIDE_DONE|FLAG_SYNC_DONE); 749 750 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 751 (tcs->flags & FLAG_NO_SYNC) == 0) 752 tcs->flags &= ~FLAG_SYNC_DONE; 753 754 /* 755 * If we're not going to negotiate, send the 756 * notification now, since it won't happen later. 757 */ 758 if ((tcs->flags & (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) == 759 (FLAG_WIDE_DONE|FLAG_SYNC_DONE)) 760 iha_update_xfer_mode(sc, xm->xm_target); 761 762 return; 763 } 764 } 765 } 766 767 void 768 iha_update_xfer_mode(struct iha_softc *sc, int target) 769 { 770 struct tcs *tcs = &sc->sc_tcs[target]; 771 struct scsipi_xfer_mode xm; 772 773 xm.xm_target = target; 774 xm.xm_mode = 0; 775 xm.xm_period = 0; 776 xm.xm_offset = 0; 777 778 if (tcs->syncm & PERIOD_WIDE_SCSI) 779 xm.xm_mode |= PERIPH_CAP_WIDE16; 780 781 if (tcs->period) { 782 xm.xm_mode |= PERIPH_CAP_SYNC; 783 xm.xm_period = tcs->period; 784 xm.xm_offset = tcs->offset; 785 } 786 787 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 788 } 789 790 static void 791 iha_reset_scsi_bus(struct iha_softc *sc) 792 { 793 struct iha_scb *scb; 794 struct tcs *tcs; 795 int i, s; 796 797 s = splbio(); 798 799 iha_reset_dma(sc); 800 801 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 802 switch (scb->status) { 803 case STATUS_BUSY: 804 iha_append_done_scb(sc, scb, HOST_SCSI_RST); 805 break; 806 807 case STATUS_SELECT: 808 iha_push_pend_scb(sc, scb); 809 break; 810 811 default: 812 break; 813 } 814 815 for (i = 0, tcs = sc->sc_tcs; i < IHA_MAX_TARGETS; i++, tcs++) 816 iha_reset_tcs(tcs, sc->sc_sconf1); 817 818 splx(s); 819 } 820 821 void 822 iha_reset_chip(struct iha_softc *sc) 823 { 824 bus_space_tag_t iot = sc->sc_iot; 825 bus_space_handle_t ioh = sc->sc_ioh; 826 827 /* reset tulip chip */ 828 829 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSCSI); 830 831 do { 832 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 833 } while ((sc->sc_sistat & SRSTD) == 0); 834 835 iha_set_ssig(sc, 0, 0); 836 837 /* Clear any active interrupt*/ 838 (void)bus_space_read_1(iot, ioh, TUL_SISTAT); 839 } 840 841 /* 842 * iha_reset_dma - abort any active DMA xfer, reset tulip FIFO. 843 */ 844 static void 845 iha_reset_dma(struct iha_softc *sc) 846 { 847 bus_space_tag_t iot = sc->sc_iot; 848 bus_space_handle_t ioh = sc->sc_ioh; 849 850 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 851 /* if DMA xfer is pending, abort DMA xfer */ 852 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 853 /* wait Abort DMA xfer done */ 854 while ((bus_space_read_1(iot, ioh, TUL_ISTUS0) & DABT) == 0) 855 ; 856 } 857 858 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 859 } 860 861 /* 862 * iha_reset_tcs - reset the target control structure pointed 863 * to by tcs to default values. tcs flags 864 * only has the negotiation done bits reset as 865 * the other bits are fixed at initialization. 866 */ 867 static void 868 iha_reset_tcs(struct tcs *tcs, uint8_t config0) 869 { 870 871 tcs->flags &= ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 872 tcs->period = 0; 873 tcs->offset = 0; 874 tcs->tagcnt = 0; 875 tcs->ntagscb = NULL; 876 tcs->syncm = 0; 877 tcs->sconfig0 = config0; 878 } 879 880 /* 881 * iha_main - process the active SCB, taking one off pending and making it 882 * active if necessary, and any done SCB's created as 883 * a result until there are no interrupts pending and no pending 884 * SCB's that can be started. 885 */ 886 static void 887 iha_main(struct iha_softc *sc) 888 { 889 bus_space_tag_t iot = sc->sc_iot; 890 bus_space_handle_t ioh =sc->sc_ioh; 891 struct iha_scb *scb; 892 893 for (;;) { 894 iha_scsi(sc); 895 896 while ((scb = iha_pop_done_scb(sc)) != NULL) 897 iha_done_scb(sc, scb); 898 899 /* 900 * If there are no interrupts pending, or we can't start 901 * a pending sc, break out of the for(;;). Otherwise 902 * continue the good work with another call to 903 * iha_scsi(). 904 */ 905 if (((bus_space_read_1(iot, ioh, TUL_STAT0) & INTPD) == 0) 906 && (iha_find_pend_scb(sc) == NULL)) 907 break; 908 } 909 } 910 911 /* 912 * iha_scsi - service any outstanding interrupts. If there are none, try to 913 * start another SCB currently in the pending queue. 914 */ 915 static void 916 iha_scsi(struct iha_softc *sc) 917 { 918 bus_space_tag_t iot = sc->sc_iot; 919 bus_space_handle_t ioh = sc->sc_ioh; 920 struct iha_scb *scb; 921 struct tcs *tcs; 922 uint8_t stat; 923 924 /* service pending interrupts asap */ 925 926 stat = bus_space_read_1(iot, ioh, TUL_STAT0); 927 if ((stat & INTPD) != 0) { 928 sc->sc_status0 = stat; 929 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 930 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 931 932 sc->sc_phase = sc->sc_status0 & PH_MASK; 933 934 if ((sc->sc_sistat & SRSTD) != 0) { 935 iha_reset_scsi_bus(sc); 936 return; 937 } 938 939 if ((sc->sc_sistat & RSELED) != 0) { 940 iha_resel(sc); 941 return; 942 } 943 944 if ((sc->sc_sistat & (STIMEO | DISCD)) != 0) { 945 iha_busfree(sc); 946 return; 947 } 948 949 if ((sc->sc_sistat & (SCMDN | SBSRV)) != 0) { 950 iha_next_state(sc); 951 return; 952 } 953 954 if ((sc->sc_sistat & SELED) != 0) 955 iha_set_ssig(sc, 0, 0); 956 } 957 958 /* 959 * There were no interrupts pending which required action elsewhere, so 960 * see if it is possible to start the selection phase on a pending SCB 961 */ 962 if ((scb = iha_find_pend_scb(sc)) == NULL) 963 return; 964 965 tcs = scb->tcs; 966 967 /* program HBA's SCSI ID & target SCSI ID */ 968 bus_space_write_1(iot, ioh, TUL_SID, (sc->sc_id << 4) | scb->target); 969 970 if ((scb->xs->xs_control & XS_CTL_RESET) == 0) { 971 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 972 973 if ((tcs->flags & FLAG_NO_NEG_SYNC) == 0 || 974 (tcs->flags & FLAG_NO_NEG_WIDE) == 0) 975 iha_select(sc, scb, SELATNSTOP); 976 977 else if (scb->scb_tagmsg != 0) 978 iha_select(sc, scb, SEL_ATN3); 979 980 else 981 iha_select(sc, scb, SEL_ATN); 982 983 } else { 984 iha_select(sc, scb, SELATNSTOP); 985 scb->nextstat = 8; 986 } 987 988 if ((scb->xs->xs_control & XS_CTL_POLL) != 0) { 989 int timeout; 990 for (timeout = scb->xs->timeout; timeout > 0; timeout--) { 991 if (iha_wait(sc, NO_OP) == -1) 992 break; 993 if (iha_next_state(sc) == -1) 994 break; 995 delay(1000); /* Only happens in boot, so it's ok */ 996 } 997 998 /* 999 * Since done queue processing not done until AFTER this 1000 * function returns, scb is on the done queue, not 1001 * the free queue at this point and still has valid data 1002 * 1003 * Conversely, xs->error has not been set yet 1004 */ 1005 if (timeout == 0) 1006 iha_timeout(scb); 1007 } 1008 } 1009 1010 static void 1011 iha_select(struct iha_softc *sc, struct iha_scb *scb, uint8_t select_type) 1012 { 1013 bus_space_tag_t iot = sc->sc_iot; 1014 bus_space_handle_t ioh = sc->sc_ioh; 1015 1016 switch (select_type) { 1017 case SEL_ATN: 1018 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1019 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1020 scb->cmd, scb->cmdlen); 1021 1022 scb->nextstat = 2; 1023 break; 1024 1025 case SELATNSTOP: 1026 scb->nextstat = 1; 1027 break; 1028 1029 case SEL_ATN3: 1030 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1031 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagmsg); 1032 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_tagid); 1033 1034 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, scb->cmd, 1035 scb->cmdlen); 1036 1037 scb->nextstat = 2; 1038 break; 1039 1040 default: 1041 printf("[debug] iha_select() - unknown select type = 0x%02x\n", 1042 select_type); 1043 return; 1044 } 1045 1046 iha_del_pend_scb(sc, scb); 1047 scb->status = STATUS_SELECT; 1048 1049 sc->sc_actscb = scb; 1050 1051 bus_space_write_1(iot, ioh, TUL_SCMD, select_type); 1052 } 1053 1054 /* 1055 * iha_wait - wait for an interrupt to service or a SCSI bus phase change 1056 * after writing the supplied command to the tulip chip. If 1057 * the command is NO_OP, skip the command writing. 1058 */ 1059 static int 1060 iha_wait(struct iha_softc *sc, uint8_t cmd) 1061 { 1062 bus_space_tag_t iot = sc->sc_iot; 1063 bus_space_handle_t ioh = sc->sc_ioh; 1064 1065 if (cmd != NO_OP) 1066 bus_space_write_1(iot, ioh, TUL_SCMD, cmd); 1067 1068 /* 1069 * Have to do this here, in addition to in iha_isr, because 1070 * interrupts might be turned off when we get here. 1071 */ 1072 do { 1073 sc->sc_status0 = bus_space_read_1(iot, ioh, TUL_STAT0); 1074 } while ((sc->sc_status0 & INTPD) == 0); 1075 1076 sc->sc_status1 = bus_space_read_1(iot, ioh, TUL_STAT1); 1077 sc->sc_sistat = bus_space_read_1(iot, ioh, TUL_SISTAT); 1078 1079 sc->sc_phase = sc->sc_status0 & PH_MASK; 1080 1081 if ((sc->sc_sistat & SRSTD) != 0) { 1082 /* SCSI bus reset interrupt */ 1083 iha_reset_scsi_bus(sc); 1084 return (-1); 1085 } 1086 1087 if ((sc->sc_sistat & RSELED) != 0) 1088 /* Reselection interrupt */ 1089 return (iha_resel(sc)); 1090 1091 if ((sc->sc_sistat & STIMEO) != 0) { 1092 /* selected/reselected timeout interrupt */ 1093 iha_busfree(sc); 1094 return (-1); 1095 } 1096 1097 if ((sc->sc_sistat & DISCD) != 0) { 1098 /* BUS disconnection interrupt */ 1099 if ((sc->sc_flags & FLAG_EXPECT_DONE_DISC) != 0) { 1100 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1101 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 1102 SCONFIG0DEFAULT); 1103 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1104 iha_append_done_scb(sc, sc->sc_actscb, HOST_OK); 1105 sc->sc_flags &= ~FLAG_EXPECT_DONE_DISC; 1106 1107 } else if ((sc->sc_flags & FLAG_EXPECT_DISC) != 0) { 1108 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1109 bus_space_write_1(iot, ioh, TUL_SCONFIG0, 1110 SCONFIG0DEFAULT); 1111 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 1112 sc->sc_actscb = NULL; 1113 sc->sc_flags &= ~FLAG_EXPECT_DISC; 1114 1115 } else 1116 iha_busfree(sc); 1117 1118 return (-1); 1119 } 1120 1121 return (sc->sc_phase); 1122 } 1123 1124 static void 1125 iha_exec_scb(struct iha_softc *sc, struct iha_scb *scb) 1126 { 1127 bus_space_tag_t iot; 1128 bus_space_handle_t ioh; 1129 bus_dmamap_t dm; 1130 struct scsipi_xfer *xs = scb->xs; 1131 int nseg, s; 1132 1133 dm = scb->dmap; 1134 nseg = dm->dm_nsegs; 1135 1136 if (nseg > 1) { 1137 struct iha_sg_element *sg = scb->sglist; 1138 int i; 1139 1140 for (i = 0; i < nseg; i++) { 1141 sg[i].sg_len = htole32(dm->dm_segs[i].ds_len); 1142 sg[i].sg_addr = htole32(dm->dm_segs[i].ds_addr); 1143 } 1144 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1145 scb->sgoffset, IHA_SG_SIZE, 1146 BUS_DMASYNC_PREWRITE); 1147 1148 scb->flags |= FLAG_SG; 1149 scb->sg_size = scb->sg_max = nseg; 1150 scb->sg_index = 0; 1151 1152 scb->bufaddr = scb->sg_addr; 1153 } else 1154 scb->bufaddr = dm->dm_segs[0].ds_addr; 1155 1156 if ((xs->xs_control & XS_CTL_POLL) == 0) { 1157 int timeout = mstohz(xs->timeout); 1158 if (timeout == 0) 1159 timeout = 1; 1160 callout_reset(&xs->xs_callout, timeout, iha_timeout, scb); 1161 } 1162 1163 s = splbio(); 1164 1165 if (((scb->xs->xs_control & XS_RESET) != 0) || 1166 (scb->cmd[0] == SCSI_REQUEST_SENSE)) 1167 iha_push_pend_scb(sc, scb); /* Insert SCB at head of Pend */ 1168 else 1169 iha_append_pend_scb(sc, scb); /* Append SCB to tail of Pend */ 1170 1171 /* 1172 * Run through iha_main() to ensure something is active, if 1173 * only this new SCB. 1174 */ 1175 if (sc->sc_semaph != SEMAPH_IN_MAIN) { 1176 iot = sc->sc_iot; 1177 ioh = sc->sc_ioh; 1178 1179 bus_space_write_1(iot, ioh, TUL_IMSK, MASK_ALL); 1180 sc->sc_semaph = SEMAPH_IN_MAIN; 1181 1182 splx(s); 1183 iha_main(sc); 1184 s = splbio(); 1185 1186 sc->sc_semaph = ~SEMAPH_IN_MAIN; 1187 bus_space_write_1(iot, ioh, TUL_IMSK, (MASK_ALL & ~MSCMP)); 1188 } 1189 1190 splx(s); 1191 } 1192 1193 /* 1194 * iha_done_scb - We have a scb which has been processed by the 1195 * adaptor, now we look to see how the operation went. 1196 */ 1197 static void 1198 iha_done_scb(struct iha_softc *sc, struct iha_scb *scb) 1199 { 1200 struct scsipi_xfer *xs = scb->xs; 1201 1202 if (xs != NULL) { 1203 /* Cancel the timeout. */ 1204 callout_stop(&xs->xs_callout); 1205 1206 if (scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) { 1207 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 1208 0, scb->dmap->dm_mapsize, 1209 (scb->flags & FLAG_DATAIN) ? 1210 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1211 bus_dmamap_unload(sc->sc_dmat, scb->dmap); 1212 } 1213 1214 xs->status = scb->ta_stat; 1215 1216 switch (scb->ha_stat) { 1217 case HOST_OK: 1218 switch (scb->ta_stat) { 1219 case SCSI_OK: 1220 case SCSI_CONDITION_MET: 1221 case SCSI_INTERM: 1222 case SCSI_INTERM_COND_MET: 1223 xs->resid = scb->buflen; 1224 xs->error = XS_NOERROR; 1225 if ((scb->flags & FLAG_RSENS) != 0) 1226 xs->error = XS_SENSE; 1227 break; 1228 1229 case SCSI_RESV_CONFLICT: 1230 case SCSI_BUSY: 1231 case SCSI_QUEUE_FULL: 1232 xs->error = XS_BUSY; 1233 break; 1234 1235 case SCSI_TERMINATED: 1236 case SCSI_ACA_ACTIVE: 1237 case SCSI_CHECK: 1238 scb->tcs->flags &= 1239 ~(FLAG_SYNC_DONE | FLAG_WIDE_DONE); 1240 1241 if ((scb->flags & FLAG_RSENS) != 0 || 1242 iha_push_sense_request(sc, scb) != 0) { 1243 scb->flags &= ~FLAG_RSENS; 1244 printf("%s: request sense failed\n", 1245 sc->sc_dev.dv_xname); 1246 xs->error = XS_DRIVER_STUFFUP; 1247 break; 1248 } 1249 1250 xs->error = XS_SENSE; 1251 return; 1252 1253 default: 1254 xs->error = XS_DRIVER_STUFFUP; 1255 break; 1256 } 1257 break; 1258 1259 case HOST_SEL_TOUT: 1260 xs->error = XS_SELTIMEOUT; 1261 break; 1262 1263 case HOST_SCSI_RST: 1264 case HOST_DEV_RST: 1265 xs->error = XS_RESET; 1266 break; 1267 1268 case HOST_SPERR: 1269 printf("%s: SCSI Parity error detected\n", 1270 sc->sc_dev.dv_xname); 1271 xs->error = XS_DRIVER_STUFFUP; 1272 break; 1273 1274 case HOST_TIMED_OUT: 1275 xs->error = XS_TIMEOUT; 1276 break; 1277 1278 case HOST_DO_DU: 1279 case HOST_BAD_PHAS: 1280 default: 1281 xs->error = XS_DRIVER_STUFFUP; 1282 break; 1283 } 1284 1285 scsipi_done(xs); 1286 } 1287 1288 iha_append_free_scb(sc, scb); 1289 } 1290 1291 /* 1292 * iha_push_sense_request - obtain auto sense data by pushing the 1293 * SCB needing it back onto the pending 1294 * queue with a REQUEST_SENSE CDB. 1295 */ 1296 static int 1297 iha_push_sense_request(struct iha_softc *sc, struct iha_scb *scb) 1298 { 1299 struct scsipi_xfer *xs = scb->xs; 1300 struct scsipi_periph *periph = xs->xs_periph; 1301 struct scsi_request_sense *ss = (struct scsi_request_sense *)scb->cmd; 1302 int lun = periph->periph_lun; 1303 int err; 1304 1305 memset(ss, 0, sizeof(*ss)); 1306 ss->opcode = SCSI_REQUEST_SENSE; 1307 ss->byte2 = lun << SCSI_CMD_LUN_SHIFT; 1308 ss->length = sizeof(struct scsi_sense_data); 1309 1310 scb->flags = FLAG_RSENS | FLAG_DATAIN; 1311 1312 scb->scb_id &= ~MSG_IDENTIFY_DISCFLAG; 1313 1314 scb->scb_tagmsg = 0; 1315 scb->ta_stat = SCSI_OK; 1316 1317 scb->cmdlen = sizeof(struct scsi_request_sense); 1318 scb->buflen = ss->length; 1319 1320 err = bus_dmamap_load(sc->sc_dmat, scb->dmap, 1321 &xs->sense.scsi_sense, scb->buflen, NULL, 1322 BUS_DMA_READ|BUS_DMA_NOWAIT); 1323 if (err != 0) { 1324 printf("iha_push_sense_request: cannot bus_dmamap_load()\n"); 1325 xs->error = XS_DRIVER_STUFFUP; 1326 return 1; 1327 } 1328 bus_dmamap_sync(sc->sc_dmat, scb->dmap, 1329 0, scb->buflen, BUS_DMASYNC_PREREAD); 1330 1331 /* XXX What about queued command? */ 1332 iha_exec_scb(sc, scb); 1333 1334 return 0; 1335 } 1336 1337 static void 1338 iha_timeout(void *arg) 1339 { 1340 struct iha_scb *scb = (struct iha_scb *)arg; 1341 struct scsipi_xfer *xs = scb->xs; 1342 struct scsipi_periph *periph; 1343 struct iha_softc *sc; 1344 1345 if (xs == NULL) { 1346 printf("[debug] iha_timeout called with xs == NULL\n"); 1347 return; 1348 } 1349 1350 periph = xs->xs_periph; 1351 1352 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1353 1354 scsipi_printaddr(periph); 1355 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1356 iha_abort_xs(sc, xs, HOST_TIMED_OUT); 1357 } 1358 1359 /* 1360 * iha_abort_xs - find the SCB associated with the supplied xs and 1361 * stop all processing on it, moving it to the done 1362 * queue with the supplied host status value. 1363 */ 1364 static void 1365 iha_abort_xs(struct iha_softc *sc, struct scsipi_xfer *xs, uint8_t hastat) 1366 { 1367 struct iha_scb *scb; 1368 int i, s; 1369 1370 s = splbio(); 1371 1372 /* Check the pending queue for the SCB pointing to xs */ 1373 1374 TAILQ_FOREACH(scb, &sc->sc_pendscb, chain) 1375 if (scb->xs == xs) { 1376 iha_del_pend_scb(sc, scb); 1377 iha_append_done_scb(sc, scb, hastat); 1378 splx(s); 1379 return; 1380 } 1381 1382 /* 1383 * If that didn't work, check all BUSY/SELECTING SCB's for one 1384 * pointing to xs 1385 */ 1386 1387 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1388 switch (scb->status) { 1389 case STATUS_BUSY: 1390 case STATUS_SELECT: 1391 if (scb->xs == xs) { 1392 iha_append_done_scb(sc, scb, hastat); 1393 splx(s); 1394 return; 1395 } 1396 break; 1397 default: 1398 break; 1399 } 1400 1401 splx(s); 1402 } 1403 1404 /* 1405 * iha_data_over_run - return HOST_OK for all SCSI opcodes where BufLen 1406 * is an 'Allocation Length'. All other SCSI opcodes 1407 * get HOST_DO_DU as they SHOULD have xferred all the 1408 * data requested. 1409 * 1410 * The list of opcodes using 'Allocation Length' was 1411 * found by scanning all the SCSI-3 T10 drafts. See 1412 * www.t10.org for the curious with a .pdf reader. 1413 */ 1414 static uint8_t 1415 iha_data_over_run(struct iha_scb *scb) 1416 { 1417 switch (scb->cmd[0]) { 1418 case 0x03: /* Request Sense SPC-2 */ 1419 case 0x12: /* Inquiry SPC-2 */ 1420 case 0x1a: /* Mode Sense (6 byte version) SPC-2 */ 1421 case 0x1c: /* Receive Diagnostic Results SPC-2 */ 1422 case 0x23: /* Read Format Capacities MMC-2 */ 1423 case 0x29: /* Read Generation SBC */ 1424 case 0x34: /* Read Position SSC-2 */ 1425 case 0x37: /* Read Defect Data SBC */ 1426 case 0x3c: /* Read Buffer SPC-2 */ 1427 case 0x42: /* Read Sub Channel MMC-2 */ 1428 case 0x43: /* Read TOC/PMA/ATIP MMC */ 1429 1430 /* XXX - 2 with same opcode of 0x44? */ 1431 case 0x44: /* Read Header/Read Density Suprt MMC/SSC*/ 1432 1433 case 0x46: /* Get Configuration MMC-2 */ 1434 case 0x4a: /* Get Event/Status Notification MMC-2 */ 1435 case 0x4d: /* Log Sense SPC-2 */ 1436 case 0x51: /* Read Disc Information MMC */ 1437 case 0x52: /* Read Track Information MMC */ 1438 case 0x59: /* Read Master CUE MMC */ 1439 case 0x5a: /* Mode Sense (10 byte version) SPC-2 */ 1440 case 0x5c: /* Read Buffer Capacity MMC */ 1441 case 0x5e: /* Persistent Reserve In SPC-2 */ 1442 case 0x84: /* Receive Copy Results SPC-2 */ 1443 case 0xa0: /* Report LUNs SPC-2 */ 1444 case 0xa3: /* Various Report requests SBC-2/SCC-2*/ 1445 case 0xa4: /* Report Key MMC-2 */ 1446 case 0xad: /* Read DVD Structure MMC-2 */ 1447 case 0xb4: /* Read Element Status (Attached) SMC */ 1448 case 0xb5: /* Request Volume Element Address SMC */ 1449 case 0xb7: /* Read Defect Data (12 byte ver.) SBC */ 1450 case 0xb8: /* Read Element Status (Independ.) SMC */ 1451 case 0xba: /* Report Redundancy SCC-2 */ 1452 case 0xbd: /* Mechanism Status MMC */ 1453 case 0xbe: /* Report Basic Redundancy SCC-2 */ 1454 1455 return (HOST_OK); 1456 1457 default: 1458 return (HOST_DO_DU); 1459 } 1460 } 1461 1462 /* 1463 * iha_next_state - process the current SCB as requested in its 1464 * nextstat member. 1465 */ 1466 static int 1467 iha_next_state(struct iha_softc *sc) 1468 { 1469 1470 if (sc->sc_actscb == NULL) 1471 return (-1); 1472 1473 switch (sc->sc_actscb->nextstat) { 1474 case 1: 1475 if (iha_state_1(sc) == 3) 1476 goto state_3; 1477 break; 1478 1479 case 2: 1480 switch (iha_state_2(sc)) { 1481 case 3: 1482 goto state_3; 1483 case 4: 1484 goto state_4; 1485 default: 1486 break; 1487 } 1488 break; 1489 1490 case 3: 1491 state_3: 1492 if (iha_state_3(sc) == 4) 1493 goto state_4; 1494 break; 1495 1496 case 4: 1497 state_4: 1498 switch (iha_state_4(sc)) { 1499 case 0: 1500 return (0); 1501 case 6: 1502 goto state_6; 1503 default: 1504 break; 1505 } 1506 break; 1507 1508 case 5: 1509 switch (iha_state_5(sc)) { 1510 case 4: 1511 goto state_4; 1512 case 6: 1513 goto state_6; 1514 default: 1515 break; 1516 } 1517 break; 1518 1519 case 6: 1520 state_6: 1521 iha_state_6(sc); 1522 break; 1523 1524 case 8: 1525 iha_state_8(sc); 1526 break; 1527 1528 default: 1529 #ifdef IHA_DEBUG_STATE 1530 printf("[debug] -unknown state: %i-\n", 1531 sc->sc_actscb->nextstat); 1532 #endif 1533 iha_bad_seq(sc); 1534 break; 1535 } 1536 1537 return (-1); 1538 } 1539 1540 /* 1541 * iha_state_1 - selection is complete after a SELATNSTOP. If the target 1542 * has put the bus into MSG_OUT phase start wide/sync 1543 * negotiation. Otherwise clear the FIFO and go to state 3, 1544 * which will send the SCSI CDB to the target. 1545 */ 1546 static int 1547 iha_state_1(struct iha_softc *sc) 1548 { 1549 bus_space_tag_t iot = sc->sc_iot; 1550 bus_space_handle_t ioh = sc->sc_ioh; 1551 struct iha_scb *scb = sc->sc_actscb; 1552 struct tcs *tcs; 1553 int flags; 1554 1555 iha_mark_busy_scb(scb); 1556 1557 tcs = scb->tcs; 1558 1559 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 1560 1561 /* 1562 * If we are in PHASE_MSG_OUT, send 1563 * a) IDENT message (with tags if appropriate) 1564 * b) WDTR if the target is configured to negotiate wide xfers 1565 * ** OR ** 1566 * c) SDTR if the target is configured to negotiate sync xfers 1567 * but not wide ones 1568 * 1569 * If we are NOT, then the target is not asking for anything but 1570 * the data/command, so go straight to state 3. 1571 */ 1572 if (sc->sc_phase == PHASE_MSG_OUT) { 1573 bus_space_write_1(iot, ioh, TUL_SCTRL1, (ESBUSIN | EHRSL)); 1574 bus_space_write_1(iot, ioh, TUL_SFIFO, scb->scb_id); 1575 1576 if (scb->scb_tagmsg != 0) { 1577 bus_space_write_1(iot, ioh, TUL_SFIFO, 1578 scb->scb_tagmsg); 1579 bus_space_write_1(iot, ioh, TUL_SFIFO, 1580 scb->scb_tagid); 1581 } 1582 1583 flags = tcs->flags; 1584 if ((flags & FLAG_NO_NEG_WIDE) == 0) { 1585 if (iha_msgout_wdtr(sc) == -1) 1586 return (-1); 1587 } else if ((flags & FLAG_NO_NEG_SYNC) == 0) { 1588 if (iha_msgout_sdtr(sc) == -1) 1589 return (-1); 1590 } 1591 1592 } else { 1593 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1594 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1595 } 1596 1597 return (3); 1598 } 1599 1600 /* 1601 * iha_state_2 - selection is complete after a SEL_ATN or SEL_ATN3. If the SCSI 1602 * CDB has already been send, go to state 4 to start the data 1603 * xfer. Otherwise reset the FIFO and go to state 3, sending 1604 * the SCSI CDB. 1605 */ 1606 static int 1607 iha_state_2(struct iha_softc *sc) 1608 { 1609 bus_space_tag_t iot = sc->sc_iot; 1610 bus_space_handle_t ioh = sc->sc_ioh; 1611 struct iha_scb *scb = sc->sc_actscb; 1612 1613 iha_mark_busy_scb(scb); 1614 1615 bus_space_write_1(iot, ioh, TUL_SCONFIG0, scb->tcs->sconfig0); 1616 1617 if ((sc->sc_status1 & CPDNE) != 0) 1618 return (4); 1619 1620 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1621 1622 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 1623 1624 return (3); 1625 } 1626 1627 /* 1628 * iha_state_3 - send the SCSI CDB to the target, processing any status 1629 * or other messages received until that is done or 1630 * abandoned. 1631 */ 1632 static int 1633 iha_state_3(struct iha_softc *sc) 1634 { 1635 bus_space_tag_t iot = sc->sc_iot; 1636 bus_space_handle_t ioh = sc->sc_ioh; 1637 struct iha_scb *scb = sc->sc_actscb; 1638 int flags; 1639 1640 for (;;) { 1641 switch (sc->sc_phase) { 1642 case PHASE_CMD_OUT: 1643 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 1644 scb->cmd, scb->cmdlen); 1645 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1646 return (-1); 1647 else if (sc->sc_phase == PHASE_CMD_OUT) { 1648 iha_bad_seq(sc); 1649 return (-1); 1650 } else 1651 return (4); 1652 1653 case PHASE_MSG_IN: 1654 scb->nextstat = 3; 1655 if (iha_msgin(sc) == -1) 1656 return (-1); 1657 break; 1658 1659 case PHASE_STATUS_IN: 1660 if (iha_status_msg(sc) == -1) 1661 return (-1); 1662 break; 1663 1664 case PHASE_MSG_OUT: 1665 flags = scb->tcs->flags; 1666 if ((flags & FLAG_NO_NEG_SYNC) != 0) { 1667 if (iha_msgout(sc, MSG_NOOP) == -1) 1668 return (-1); 1669 } else if (iha_msgout_sdtr(sc) == -1) 1670 return (-1); 1671 break; 1672 1673 default: 1674 printf("[debug] -s3- bad phase = %d\n", sc->sc_phase); 1675 iha_bad_seq(sc); 1676 return (-1); 1677 } 1678 } 1679 } 1680 1681 /* 1682 * iha_state_4 - start a data xfer. Handle any bus state 1683 * transitions until PHASE_DATA_IN/_OUT 1684 * or the attempt is abandoned. If there is 1685 * no data to xfer, go to state 6 and finish 1686 * processing the current SCB. 1687 */ 1688 static int 1689 iha_state_4(struct iha_softc *sc) 1690 { 1691 struct iha_scb *scb = sc->sc_actscb; 1692 1693 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) == 1694 (FLAG_DATAIN | FLAG_DATAOUT)) 1695 return (6); /* Both dir flags set => NO xfer was requested */ 1696 1697 for (;;) { 1698 if (scb->buflen == 0) 1699 return (6); 1700 1701 switch (sc->sc_phase) { 1702 case PHASE_STATUS_IN: 1703 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1704 scb->ha_stat = iha_data_over_run(scb); 1705 if ((iha_status_msg(sc)) == -1) 1706 return (-1); 1707 break; 1708 1709 case PHASE_MSG_IN: 1710 scb->nextstat = 4; 1711 if (iha_msgin(sc) == -1) 1712 return (-1); 1713 break; 1714 1715 case PHASE_MSG_OUT: 1716 if ((sc->sc_status0 & SPERR) != 0) { 1717 scb->buflen = 0; 1718 scb->ha_stat = HOST_SPERR; 1719 if (iha_msgout(sc, MSG_INITIATOR_DET_ERR) == -1) 1720 return (-1); 1721 else 1722 return (6); 1723 } else { 1724 if (iha_msgout(sc, MSG_NOOP) == -1) 1725 return (-1); 1726 } 1727 break; 1728 1729 case PHASE_DATA_IN: 1730 return (iha_xfer_data(sc, scb, FLAG_DATAIN)); 1731 1732 case PHASE_DATA_OUT: 1733 return (iha_xfer_data(sc, scb, FLAG_DATAOUT)); 1734 1735 default: 1736 iha_bad_seq(sc); 1737 return (-1); 1738 } 1739 } 1740 } 1741 1742 /* 1743 * iha_state_5 - handle the partial or final completion of the current 1744 * data xfer. If DMA is still active stop it. If there is 1745 * more data to xfer, go to state 4 and start the xfer. 1746 * If not go to state 6 and finish the SCB. 1747 */ 1748 static int 1749 iha_state_5(struct iha_softc *sc) 1750 { 1751 bus_space_tag_t iot = sc->sc_iot; 1752 bus_space_handle_t ioh = sc->sc_ioh; 1753 struct iha_scb *scb = sc->sc_actscb; 1754 struct iha_sg_element *sg; 1755 uint32_t cnt; 1756 uint8_t period, stat; 1757 long xcnt; /* cannot use unsigned!! see code: if (xcnt < 0) */ 1758 int i; 1759 1760 cnt = bus_space_read_4(iot, ioh, TUL_STCNT0) & TCNT; 1761 1762 /* 1763 * Stop any pending DMA activity and check for parity error. 1764 */ 1765 1766 if ((bus_space_read_1(iot, ioh, TUL_DCMD) & XDIR) != 0) { 1767 /* Input Operation */ 1768 if ((sc->sc_status0 & SPERR) != 0) 1769 scb->ha_stat = HOST_SPERR; 1770 1771 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1772 bus_space_write_1(iot, ioh, TUL_DCTRL0, 1773 bus_space_read_1(iot, ioh, TUL_DCTRL0) | SXSTP); 1774 while (bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) 1775 ; 1776 } 1777 1778 } else { 1779 /* Output Operation */ 1780 if ((sc->sc_status1 & SXCMP) == 0) { 1781 period = scb->tcs->syncm; 1782 if ((period & PERIOD_WIDE_SCSI) != 0) 1783 cnt += (bus_space_read_1(iot, ioh, 1784 TUL_SFIFOCNT) & FIFOC) * 2; 1785 else 1786 cnt += bus_space_read_1(iot, ioh, 1787 TUL_SFIFOCNT) & FIFOC; 1788 } 1789 1790 if ((bus_space_read_1(iot, ioh, TUL_ISTUS1) & XPEND) != 0) { 1791 bus_space_write_1(iot, ioh, TUL_DCMD, ABTXFR); 1792 do 1793 stat = bus_space_read_1(iot, ioh, TUL_ISTUS0); 1794 while ((stat & DABT) == 0); 1795 } 1796 1797 if ((cnt == 1) && (sc->sc_phase == PHASE_DATA_OUT)) { 1798 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1799 return (-1); 1800 cnt = 0; 1801 1802 } else if ((sc->sc_status1 & SXCMP) == 0) 1803 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 1804 } 1805 1806 if (cnt == 0) { 1807 scb->buflen = 0; 1808 return (6); 1809 } 1810 1811 /* Update active data pointer and restart the I/O at the new point */ 1812 1813 xcnt = scb->buflen - cnt; /* xcnt == bytes xferred */ 1814 scb->buflen = cnt; /* cnt == bytes left */ 1815 1816 if ((scb->flags & FLAG_SG) != 0) { 1817 sg = &scb->sglist[scb->sg_index]; 1818 for (i = scb->sg_index; i < scb->sg_max; sg++, i++) { 1819 xcnt -= le32toh(sg->sg_len); 1820 if (xcnt < 0) { 1821 xcnt += le32toh(sg->sg_len); 1822 1823 sg->sg_addr = 1824 htole32(le32toh(sg->sg_addr) + xcnt); 1825 sg->sg_len = 1826 htole32(le32toh(sg->sg_len) - xcnt); 1827 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1828 scb->sgoffset, IHA_SG_SIZE, 1829 BUS_DMASYNC_PREWRITE); 1830 1831 scb->bufaddr += (i - scb->sg_index) * 1832 sizeof(struct iha_sg_element); 1833 scb->sg_size = scb->sg_max - i; 1834 scb->sg_index = i; 1835 1836 return (4); 1837 } 1838 } 1839 return (6); 1840 1841 } else 1842 scb->bufaddr += xcnt; 1843 1844 return (4); 1845 } 1846 1847 /* 1848 * iha_state_6 - finish off the active scb (may require several 1849 * iterations if PHASE_MSG_IN) and return -1 to indicate 1850 * the bus is free. 1851 */ 1852 static int 1853 iha_state_6(struct iha_softc *sc) 1854 { 1855 1856 for (;;) { 1857 switch (sc->sc_phase) { 1858 case PHASE_STATUS_IN: 1859 if (iha_status_msg(sc) == -1) 1860 return (-1); 1861 break; 1862 1863 case PHASE_MSG_IN: 1864 sc->sc_actscb->nextstat = 6; 1865 if ((iha_msgin(sc)) == -1) 1866 return (-1); 1867 break; 1868 1869 case PHASE_MSG_OUT: 1870 if ((iha_msgout(sc, MSG_NOOP)) == -1) 1871 return (-1); 1872 break; 1873 1874 case PHASE_DATA_IN: 1875 if (iha_xpad_in(sc) == -1) 1876 return (-1); 1877 break; 1878 1879 case PHASE_DATA_OUT: 1880 if (iha_xpad_out(sc) == -1) 1881 return (-1); 1882 break; 1883 1884 default: 1885 iha_bad_seq(sc); 1886 return (-1); 1887 } 1888 } 1889 } 1890 1891 /* 1892 * iha_state_8 - reset the active device and all busy SCBs using it 1893 */ 1894 static int 1895 iha_state_8(struct iha_softc *sc) 1896 { 1897 bus_space_tag_t iot = sc->sc_iot; 1898 bus_space_handle_t ioh = sc->sc_ioh; 1899 struct iha_scb *scb; 1900 int i; 1901 uint8_t tar; 1902 1903 if (sc->sc_phase == PHASE_MSG_OUT) { 1904 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_BUS_DEV_RESET); 1905 1906 scb = sc->sc_actscb; 1907 1908 /* This SCB finished correctly -- resetting the device */ 1909 iha_append_done_scb(sc, scb, HOST_OK); 1910 1911 iha_reset_tcs(scb->tcs, sc->sc_sconf1); 1912 1913 tar = scb->target; 1914 for (i = 0, scb = sc->sc_scb; i < IHA_MAX_SCB; i++, scb++) 1915 if (scb->target == tar) 1916 switch (scb->status) { 1917 case STATUS_BUSY: 1918 iha_append_done_scb(sc, 1919 scb, HOST_DEV_RST); 1920 break; 1921 1922 case STATUS_SELECT: 1923 iha_push_pend_scb(sc, scb); 1924 break; 1925 1926 default: 1927 break; 1928 } 1929 1930 sc->sc_flags |= FLAG_EXPECT_DISC; 1931 1932 if (iha_wait(sc, XF_FIFO_OUT) == -1) 1933 return (-1); 1934 } 1935 1936 iha_bad_seq(sc); 1937 return (-1); 1938 } 1939 1940 /* 1941 * iha_xfer_data - initiate the DMA xfer of the data 1942 */ 1943 static int 1944 iha_xfer_data(struct iha_softc *sc, struct iha_scb *scb, int direction) 1945 { 1946 bus_space_tag_t iot = sc->sc_iot; 1947 bus_space_handle_t ioh = sc->sc_ioh; 1948 uint32_t xferlen; 1949 uint8_t xfercmd; 1950 1951 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != direction) 1952 return (6); /* wrong direction, abandon I/O */ 1953 1954 bus_space_write_4(iot, ioh, TUL_STCNT0, scb->buflen); 1955 1956 xfercmd = STRXFR; 1957 if (direction == FLAG_DATAIN) 1958 xfercmd |= XDIR; 1959 1960 if (scb->flags & FLAG_SG) { 1961 xferlen = scb->sg_size * sizeof(struct iha_sg_element); 1962 xfercmd |= SGXFR; 1963 } else 1964 xferlen = scb->buflen; 1965 1966 bus_space_write_4(iot, ioh, TUL_DXC, xferlen); 1967 bus_space_write_4(iot, ioh, TUL_DXPA, scb->bufaddr); 1968 bus_space_write_1(iot, ioh, TUL_DCMD, xfercmd); 1969 1970 bus_space_write_1(iot, ioh, TUL_SCMD, 1971 (direction == FLAG_DATAIN) ? XF_DMA_IN : XF_DMA_OUT); 1972 1973 scb->nextstat = 5; 1974 1975 return (0); 1976 } 1977 1978 static int 1979 iha_xpad_in(struct iha_softc *sc) 1980 { 1981 bus_space_tag_t iot = sc->sc_iot; 1982 bus_space_handle_t ioh = sc->sc_ioh; 1983 struct iha_scb *scb = sc->sc_actscb; 1984 1985 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 1986 scb->ha_stat = HOST_DO_DU; 1987 1988 for (;;) { 1989 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 1990 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 1991 else 1992 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 1993 1994 switch (iha_wait(sc, XF_FIFO_IN)) { 1995 case -1: 1996 return (-1); 1997 1998 case PHASE_DATA_IN: 1999 (void)bus_space_read_1(iot, ioh, TUL_SFIFO); 2000 break; 2001 2002 default: 2003 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2004 return (6); 2005 } 2006 } 2007 } 2008 2009 static int 2010 iha_xpad_out(struct iha_softc *sc) 2011 { 2012 bus_space_tag_t iot = sc->sc_iot; 2013 bus_space_handle_t ioh = sc->sc_ioh; 2014 struct iha_scb *scb = sc->sc_actscb; 2015 2016 if ((scb->flags & (FLAG_DATAIN | FLAG_DATAOUT)) != 0) 2017 scb->ha_stat = HOST_DO_DU; 2018 2019 for (;;) { 2020 if ((scb->tcs->syncm & PERIOD_WIDE_SCSI) != 0) 2021 bus_space_write_4(iot, ioh, TUL_STCNT0, 2); 2022 else 2023 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2024 2025 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 2026 2027 switch (iha_wait(sc, XF_FIFO_OUT)) { 2028 case -1: 2029 return (-1); 2030 2031 case PHASE_DATA_OUT: 2032 break; 2033 2034 default: 2035 /* Disable wide CPU to allow read 16 bits */ 2036 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2037 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2038 return (6); 2039 } 2040 } 2041 } 2042 2043 static int 2044 iha_status_msg(struct iha_softc *sc) 2045 { 2046 bus_space_tag_t iot = sc->sc_iot; 2047 bus_space_handle_t ioh = sc->sc_ioh; 2048 struct iha_scb *scb; 2049 uint8_t msg; 2050 int phase; 2051 2052 if ((phase = iha_wait(sc, CMD_COMP)) == -1) 2053 return (-1); 2054 2055 scb = sc->sc_actscb; 2056 2057 scb->ta_stat = bus_space_read_1(iot, ioh, TUL_SFIFO); 2058 2059 if (phase == PHASE_MSG_OUT) { 2060 if ((sc->sc_status0 & SPERR) == 0) 2061 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_NOOP); 2062 else 2063 bus_space_write_1(iot, ioh, TUL_SFIFO, 2064 MSG_PARITY_ERROR); 2065 2066 return (iha_wait(sc, XF_FIFO_OUT)); 2067 2068 } else if (phase == PHASE_MSG_IN) { 2069 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 2070 2071 if ((sc->sc_status0 & SPERR) != 0) 2072 switch (iha_wait(sc, MSG_ACCEPT)) { 2073 case -1: 2074 return (-1); 2075 case PHASE_MSG_OUT: 2076 bus_space_write_1(iot, ioh, TUL_SFIFO, 2077 MSG_PARITY_ERROR); 2078 return (iha_wait(sc, XF_FIFO_OUT)); 2079 default: 2080 iha_bad_seq(sc); 2081 return (-1); 2082 } 2083 2084 if (msg == MSG_CMDCOMPLETE) { 2085 if ((scb->ta_stat & 2086 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) { 2087 iha_bad_seq(sc); 2088 return (-1); 2089 } 2090 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 2091 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2092 return (iha_wait(sc, MSG_ACCEPT)); 2093 } 2094 2095 if ((msg == MSG_LINK_CMD_COMPLETE) 2096 || (msg == MSG_LINK_CMD_COMPLETEF)) { 2097 if ((scb->ta_stat & 2098 (SCSI_INTERM | SCSI_BUSY)) == SCSI_INTERM) 2099 return (iha_wait(sc, MSG_ACCEPT)); 2100 } 2101 } 2102 2103 iha_bad_seq(sc); 2104 return (-1); 2105 } 2106 2107 /* 2108 * iha_busfree - SCSI bus free detected as a result of a TIMEOUT or 2109 * DISCONNECT interrupt. Reset the tulip FIFO and 2110 * SCONFIG0 and enable hardware reselect. Move any active 2111 * SCB to sc_donescb list. Return an appropriate host status 2112 * if an I/O was active. 2113 */ 2114 static void 2115 iha_busfree(struct iha_softc *sc) 2116 { 2117 bus_space_tag_t iot = sc->sc_iot; 2118 bus_space_handle_t ioh = sc->sc_ioh; 2119 struct iha_scb *scb; 2120 2121 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2122 bus_space_write_1(iot, ioh, TUL_SCONFIG0, SCONFIG0DEFAULT); 2123 bus_space_write_1(iot, ioh, TUL_SCTRL1, EHRSL); 2124 2125 scb = sc->sc_actscb; 2126 2127 if (scb != NULL) { 2128 if (scb->status == STATUS_SELECT) 2129 /* selection timeout */ 2130 iha_append_done_scb(sc, scb, HOST_SEL_TOUT); 2131 else 2132 /* Unexpected bus free */ 2133 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 2134 } 2135 } 2136 2137 /* 2138 * iha_resel - handle a detected SCSI bus reselection request. 2139 */ 2140 static int 2141 iha_resel(struct iha_softc *sc) 2142 { 2143 bus_space_tag_t iot = sc->sc_iot; 2144 bus_space_handle_t ioh = sc->sc_ioh; 2145 struct iha_scb *scb; 2146 struct tcs *tcs; 2147 uint8_t tag, target, lun, msg, abortmsg; 2148 2149 if (sc->sc_actscb != NULL) { 2150 if ((sc->sc_actscb->status == STATUS_SELECT)) 2151 iha_push_pend_scb(sc, sc->sc_actscb); 2152 sc->sc_actscb = NULL; 2153 } 2154 2155 target = bus_space_read_1(iot, ioh, TUL_SBID); 2156 lun = bus_space_read_1(iot, ioh, TUL_SALVC) & IHA_MSG_IDENTIFY_LUNMASK; 2157 2158 tcs = &sc->sc_tcs[target]; 2159 2160 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2161 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2162 2163 abortmsg = MSG_ABORT; /* until a valid tag has been obtained */ 2164 2165 if (tcs->ntagscb != NULL) 2166 /* There is a non-tagged I/O active on the target */ 2167 scb = tcs->ntagscb; 2168 2169 else { 2170 /* 2171 * Since there is no active non-tagged operation 2172 * read the tag type, the tag itself, and find 2173 * the appropriate scb by indexing sc_scb with 2174 * the tag. 2175 */ 2176 2177 switch (iha_wait(sc, MSG_ACCEPT)) { 2178 case -1: 2179 return (-1); 2180 case PHASE_MSG_IN: 2181 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2182 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 2183 return (-1); 2184 break; 2185 default: 2186 goto abort; 2187 } 2188 2189 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag Msg */ 2190 2191 if ((msg < MSG_SIMPLE_Q_TAG) || (msg > MSG_ORDERED_Q_TAG)) 2192 goto abort; 2193 2194 switch (iha_wait(sc, MSG_ACCEPT)) { 2195 case -1: 2196 return (-1); 2197 case PHASE_MSG_IN: 2198 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2199 if ((iha_wait(sc, XF_FIFO_IN)) == -1) 2200 return (-1); 2201 break; 2202 default: 2203 goto abort; 2204 } 2205 2206 tag = bus_space_read_1(iot, ioh, TUL_SFIFO); /* Read Tag ID */ 2207 scb = &sc->sc_scb[tag]; 2208 2209 abortmsg = MSG_ABORT_TAG; /* Now that we have valdid tag! */ 2210 } 2211 2212 if ((scb->target != target) 2213 || (scb->lun != lun) 2214 || (scb->status != STATUS_BUSY)) { 2215 abort: 2216 iha_msgout_abort(sc, abortmsg); 2217 return (-1); 2218 } 2219 2220 sc->sc_actscb = scb; 2221 2222 if (iha_wait(sc, MSG_ACCEPT) == -1) 2223 return (-1); 2224 2225 return (iha_next_state(sc)); 2226 } 2227 2228 static int 2229 iha_msgin(struct iha_softc *sc) 2230 { 2231 bus_space_tag_t iot = sc->sc_iot; 2232 bus_space_handle_t ioh = sc->sc_ioh; 2233 int flags; 2234 int phase; 2235 uint8_t msg; 2236 2237 for (;;) { 2238 if ((bus_space_read_1(iot, ioh, TUL_SFIFOCNT) & FIFOC) > 0) 2239 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2240 2241 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2242 2243 phase = iha_wait(sc, XF_FIFO_IN); 2244 msg = bus_space_read_1(iot, ioh, TUL_SFIFO); 2245 2246 switch (msg) { 2247 case MSG_DISCONNECT: 2248 sc->sc_flags |= FLAG_EXPECT_DISC; 2249 if (iha_wait(sc, MSG_ACCEPT) != -1) 2250 iha_bad_seq(sc); 2251 phase = -1; 2252 break; 2253 case MSG_SAVEDATAPOINTER: 2254 case MSG_RESTOREPOINTERS: 2255 case MSG_NOOP: 2256 phase = iha_wait(sc, MSG_ACCEPT); 2257 break; 2258 case MSG_MESSAGE_REJECT: 2259 /* XXX - need to clear FIFO like other 'Clear ATN'?*/ 2260 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2261 flags = sc->sc_actscb->tcs->flags; 2262 if ((flags & FLAG_NO_NEG_SYNC) == 0) 2263 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2264 phase = iha_wait(sc, MSG_ACCEPT); 2265 break; 2266 case MSG_EXTENDED: 2267 phase = iha_msgin_extended(sc); 2268 break; 2269 case MSG_IGN_WIDE_RESIDUE: 2270 phase = iha_msgin_ignore_wid_resid(sc); 2271 break; 2272 case MSG_CMDCOMPLETE: 2273 sc->sc_flags |= FLAG_EXPECT_DONE_DISC; 2274 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2275 phase = iha_wait(sc, MSG_ACCEPT); 2276 if (phase != -1) { 2277 iha_bad_seq(sc); 2278 return (-1); 2279 } 2280 break; 2281 default: 2282 printf("[debug] iha_msgin: bad msg type: %d\n", msg); 2283 phase = iha_msgout_reject(sc); 2284 break; 2285 } 2286 2287 if (phase != PHASE_MSG_IN) 2288 return (phase); 2289 } 2290 /* NOTREACHED */ 2291 } 2292 2293 static int 2294 iha_msgin_extended(struct iha_softc *sc) 2295 { 2296 bus_space_tag_t iot = sc->sc_iot; 2297 bus_space_handle_t ioh = sc->sc_ioh; 2298 int flags, i, phase, msglen, msgcode; 2299 2300 /* 2301 * XXX - can we just stop reading and reject, or do we have to 2302 * read all input, discarding the excess, and then reject 2303 */ 2304 for (i = 0; i < IHA_MAX_EXTENDED_MSG; i++) { 2305 phase = iha_wait(sc, MSG_ACCEPT); 2306 2307 if (phase != PHASE_MSG_IN) 2308 return (phase); 2309 2310 bus_space_write_4(iot, ioh, TUL_STCNT0, 1); 2311 2312 if (iha_wait(sc, XF_FIFO_IN) == -1) 2313 return (-1); 2314 2315 sc->sc_msg[i] = bus_space_read_1(iot, ioh, TUL_SFIFO); 2316 2317 if (sc->sc_msg[0] == i) 2318 break; 2319 } 2320 2321 msglen = sc->sc_msg[0]; 2322 msgcode = sc->sc_msg[1]; 2323 2324 if ((msglen == MSG_EXT_SDTR_LEN) && (msgcode == MSG_EXT_SDTR)) { 2325 if (iha_msgin_sdtr(sc) == 0) { 2326 iha_sync_done(sc); 2327 return (iha_wait(sc, MSG_ACCEPT)); 2328 } 2329 2330 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2331 2332 phase = iha_wait(sc, MSG_ACCEPT); 2333 if (phase != PHASE_MSG_OUT) 2334 return (phase); 2335 2336 /* Clear FIFO for important message - final SYNC offer */ 2337 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2338 2339 iha_sync_done(sc); /* This is our final offer */ 2340 2341 } else if ((msglen == MSG_EXT_WDTR_LEN) && (msgcode == MSG_EXT_WDTR)) { 2342 2343 flags = sc->sc_actscb->tcs->flags; 2344 2345 if ((flags & FLAG_NO_WIDE) != 0) 2346 /* Offer 8bit xfers only */ 2347 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_8_BIT; 2348 2349 else if (sc->sc_msg[2] > MSG_EXT_WDTR_BUS_32_BIT) 2350 /* BAD MSG */ 2351 return (iha_msgout_reject(sc)); 2352 2353 else if (sc->sc_msg[2] == MSG_EXT_WDTR_BUS_32_BIT) 2354 /* Offer 16bit instead */ 2355 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2356 2357 else { 2358 iha_wide_done(sc); 2359 if ((flags & FLAG_NO_NEG_SYNC) == 0) 2360 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2361 return (iha_wait(sc, MSG_ACCEPT)); 2362 } 2363 2364 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2365 2366 phase = iha_wait(sc, MSG_ACCEPT); 2367 if (phase != PHASE_MSG_OUT) 2368 return (phase); 2369 } else 2370 return (iha_msgout_reject(sc)); 2371 2372 return (iha_msgout_extended(sc)); 2373 } 2374 2375 /* 2376 * iha_msgin_sdtr - check SDTR msg in sc_msg. If the offer is 2377 * acceptable leave sc_msg as is and return 0. 2378 * If the negotiation must continue, modify sc_msg 2379 * as needed and return 1. Else return 0. 2380 */ 2381 static int 2382 iha_msgin_sdtr(struct iha_softc *sc) 2383 { 2384 int flags; 2385 int newoffer; 2386 uint8_t default_period; 2387 2388 flags = sc->sc_actscb->tcs->flags; 2389 2390 default_period = iha_rate_tbl[flags & FLAG_SCSI_RATE]; 2391 2392 if (sc->sc_msg[3] == 0) 2393 /* target offered async only. Accept it. */ 2394 return (0); 2395 2396 newoffer = 0; 2397 2398 if ((flags & FLAG_NO_SYNC) != 0) { 2399 sc->sc_msg[3] = 0; 2400 newoffer = 1; 2401 } 2402 2403 if (sc->sc_msg[3] > IHA_MAX_OFFSET) { 2404 sc->sc_msg[3] = IHA_MAX_OFFSET; 2405 newoffer = 1; 2406 } 2407 2408 if (sc->sc_msg[2] < default_period) { 2409 sc->sc_msg[2] = default_period; 2410 newoffer = 1; 2411 } 2412 2413 if (sc->sc_msg[2] > IHA_MAX_PERIOD) { 2414 /* Use async */ 2415 sc->sc_msg[3] = 0; 2416 newoffer = 1; 2417 } 2418 2419 return (newoffer); 2420 } 2421 2422 static int 2423 iha_msgin_ignore_wid_resid(struct iha_softc *sc) 2424 { 2425 bus_space_tag_t iot = sc->sc_iot; 2426 bus_space_handle_t ioh = sc->sc_ioh; 2427 int phase; 2428 2429 phase = iha_wait(sc, MSG_ACCEPT); 2430 2431 if (phase == PHASE_MSG_IN) { 2432 phase = iha_wait(sc, XF_FIFO_IN); 2433 2434 if (phase != -1) { 2435 bus_space_write_1(iot, ioh, TUL_SFIFO, 0); 2436 (void)bus_space_read_1(iot, ioh, TUL_SFIFO); 2437 (void)bus_space_read_1(iot, ioh, TUL_SFIFO); 2438 2439 phase = iha_wait(sc, MSG_ACCEPT); 2440 } 2441 } 2442 2443 return (phase); 2444 } 2445 2446 static int 2447 iha_msgout(struct iha_softc *sc, uint8_t msg) 2448 { 2449 2450 bus_space_write_1(sc->sc_iot, sc->sc_ioh, TUL_SFIFO, msg); 2451 2452 return (iha_wait(sc, XF_FIFO_OUT)); 2453 } 2454 2455 static void 2456 iha_msgout_abort(struct iha_softc *sc, uint8_t aborttype) 2457 { 2458 2459 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2460 2461 switch (iha_wait(sc, MSG_ACCEPT)) { 2462 case -1: 2463 break; 2464 2465 case PHASE_MSG_OUT: 2466 sc->sc_flags |= FLAG_EXPECT_DISC; 2467 if (iha_msgout(sc, aborttype) != -1) 2468 iha_bad_seq(sc); 2469 break; 2470 2471 default: 2472 iha_bad_seq(sc); 2473 break; 2474 } 2475 } 2476 2477 static int 2478 iha_msgout_reject(struct iha_softc *sc) 2479 { 2480 2481 iha_set_ssig(sc, REQ | BSY | SEL, ATN); 2482 2483 if (iha_wait(sc, MSG_ACCEPT) == PHASE_MSG_OUT) 2484 return (iha_msgout(sc, MSG_MESSAGE_REJECT)); 2485 2486 return (-1); 2487 } 2488 2489 static int 2490 iha_msgout_extended(struct iha_softc *sc) 2491 { 2492 bus_space_tag_t iot = sc->sc_iot; 2493 bus_space_handle_t ioh = sc->sc_ioh; 2494 int phase; 2495 2496 bus_space_write_1(iot, ioh, TUL_SFIFO, MSG_EXTENDED); 2497 2498 bus_space_write_multi_1(iot, ioh, TUL_SFIFO, 2499 sc->sc_msg, sc->sc_msg[0] + 1); 2500 2501 phase = iha_wait(sc, XF_FIFO_OUT); 2502 2503 bus_space_write_1(iot, ioh, TUL_SCTRL0, RSFIFO); 2504 iha_set_ssig(sc, REQ | BSY | SEL | ATN, 0); 2505 2506 return (phase); 2507 } 2508 2509 static int 2510 iha_msgout_wdtr(struct iha_softc *sc) 2511 { 2512 2513 sc->sc_actscb->tcs->flags |= FLAG_WIDE_DONE; 2514 2515 sc->sc_msg[0] = MSG_EXT_WDTR_LEN; 2516 sc->sc_msg[1] = MSG_EXT_WDTR; 2517 sc->sc_msg[2] = MSG_EXT_WDTR_BUS_16_BIT; 2518 2519 return (iha_msgout_extended(sc)); 2520 } 2521 2522 static int 2523 iha_msgout_sdtr(struct iha_softc *sc) 2524 { 2525 struct tcs *tcs = sc->sc_actscb->tcs; 2526 2527 tcs->flags |= FLAG_SYNC_DONE; 2528 2529 sc->sc_msg[0] = MSG_EXT_SDTR_LEN; 2530 sc->sc_msg[1] = MSG_EXT_SDTR; 2531 sc->sc_msg[2] = iha_rate_tbl[tcs->flags & FLAG_SCSI_RATE]; 2532 sc->sc_msg[3] = IHA_MAX_OFFSET; /* REQ/ACK */ 2533 2534 return (iha_msgout_extended(sc)); 2535 } 2536 2537 static void 2538 iha_wide_done(struct iha_softc *sc) 2539 { 2540 bus_space_tag_t iot = sc->sc_iot; 2541 bus_space_handle_t ioh = sc->sc_ioh; 2542 struct tcs *tcs = sc->sc_actscb->tcs; 2543 2544 tcs->syncm = 0; 2545 tcs->period = 0; 2546 tcs->offset = 0; 2547 2548 if (sc->sc_msg[2] != 0) 2549 tcs->syncm |= PERIOD_WIDE_SCSI; 2550 2551 tcs->sconfig0 &= ~ALTPD; 2552 tcs->flags &= ~FLAG_SYNC_DONE; 2553 tcs->flags |= FLAG_WIDE_DONE; 2554 2555 iha_update_xfer_mode(sc, sc->sc_actscb->target); 2556 2557 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2558 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2559 } 2560 2561 static void 2562 iha_sync_done(struct iha_softc *sc) 2563 { 2564 bus_space_tag_t iot = sc->sc_iot; 2565 bus_space_handle_t ioh = sc->sc_ioh; 2566 struct tcs *tcs = sc->sc_actscb->tcs; 2567 int i; 2568 2569 tcs->period = sc->sc_msg[2]; 2570 tcs->offset = sc->sc_msg[3]; 2571 if (tcs->offset != 0) { 2572 tcs->syncm |= tcs->offset; 2573 2574 /* pick the highest possible rate */ 2575 for (i = 0; i < sizeof(iha_rate_tbl); i++) 2576 if (iha_rate_tbl[i] >= tcs->period) 2577 break; 2578 2579 tcs->syncm |= (i << 4); 2580 tcs->sconfig0 |= ALTPD; 2581 } 2582 2583 tcs->flags |= FLAG_SYNC_DONE; 2584 2585 iha_update_xfer_mode(sc, sc->sc_actscb->target); 2586 2587 bus_space_write_1(iot, ioh, TUL_SCONFIG0, tcs->sconfig0); 2588 bus_space_write_1(iot, ioh, TUL_SYNCM, tcs->syncm); 2589 } 2590 2591 /* 2592 * iha_bad_seq - a SCSI bus phase was encountered out of the 2593 * correct/expected sequence. Reset the SCSI bus. 2594 */ 2595 static void 2596 iha_bad_seq(struct iha_softc *sc) 2597 { 2598 struct iha_scb *scb = sc->sc_actscb; 2599 2600 if (scb != NULL) 2601 iha_append_done_scb(sc, scb, HOST_BAD_PHAS); 2602 2603 iha_reset_scsi_bus(sc); 2604 iha_reset_chip(sc); 2605 } 2606 2607 /* 2608 * iha_read_eeprom - read Serial EEPROM value & set to defaults 2609 * if required. XXX - Writing does NOT work! 2610 */ 2611 static void 2612 iha_read_eeprom(struct iha_softc *sc, struct iha_eeprom *eeprom) 2613 { 2614 bus_space_tag_t iot = sc->sc_iot; 2615 bus_space_handle_t ioh = sc->sc_ioh; 2616 uint16_t *tbuf = (uint16_t *)eeprom; 2617 uint8_t gctrl; 2618 2619 /* Enable EEProm programming */ 2620 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) | EEPRG; 2621 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2622 2623 /* Read EEProm */ 2624 if (iha_se2_rd_all(sc, tbuf) == 0) 2625 panic("%s: cannot read EEPROM", sc->sc_dev.dv_xname); 2626 2627 /* Disable EEProm programming */ 2628 gctrl = bus_space_read_1(iot, ioh, TUL_GCTRL0) & ~EEPRG; 2629 bus_space_write_1(iot, ioh, TUL_GCTRL0, gctrl); 2630 } 2631 2632 #ifdef notused 2633 /* 2634 * iha_se2_update_all - Update SCSI H/A configuration parameters from 2635 * serial EEPROM Setup default pattern. Only 2636 * change those values different from the values 2637 * in iha_eeprom. 2638 */ 2639 static void 2640 iha_se2_update_all(struct iha_softc *sc) 2641 { 2642 bus_space_tag_t iot = sc->sc_iot; 2643 bus_space_handle_t ioh = sc->sc_ioh; 2644 uint16_t *np; 2645 uint32_t chksum; 2646 int i; 2647 2648 /* Enable erase/write state of EEPROM */ 2649 iha_se2_instr(sc, ENABLE_ERASE); 2650 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2651 EEP_WAIT(); 2652 2653 np = (uint16_t *)&eeprom_default; 2654 2655 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2656 iha_se2_wr(sc, i, *np); 2657 chksum += *np++; 2658 } 2659 2660 chksum &= 0x0000ffff; 2661 iha_se2_wr(sc, 31, chksum); 2662 2663 /* Disable erase/write state of EEPROM */ 2664 iha_se2_instr(sc, 0); 2665 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2666 EEP_WAIT(); 2667 } 2668 2669 /* 2670 * iha_se2_wr - write the given 16 bit value into the Serial EEPROM 2671 * at the specified offset 2672 */ 2673 static void 2674 iha_se2_wr(struct iha_softc *sc, int addr, uint16_t writeword) 2675 { 2676 bus_space_tag_t iot = sc->sc_iot; 2677 bus_space_handle_t ioh = sc->sc_ioh; 2678 int i, bit; 2679 2680 /* send 'WRITE' Instruction == address | WRITE bit */ 2681 iha_se2_instr(sc, addr | WRITE); 2682 2683 for (i = 16; i > 0; i--) { 2684 if (writeword & (1 << (i - 1))) 2685 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRDO); 2686 else 2687 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2688 EEP_WAIT(); 2689 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2690 EEP_WAIT(); 2691 } 2692 2693 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2694 EEP_WAIT(); 2695 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2696 EEP_WAIT(); 2697 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2698 EEP_WAIT(); 2699 2700 for (;;) { 2701 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2702 EEP_WAIT(); 2703 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2704 EEP_WAIT(); 2705 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI; 2706 EEP_WAIT(); 2707 if (bit != 0) 2708 break; /* write complete */ 2709 } 2710 2711 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2712 } 2713 #endif 2714 2715 /* 2716 * iha_se2_rd - read & return the 16 bit value at the specified 2717 * offset in the Serial E2PROM 2718 * 2719 */ 2720 static uint16_t 2721 iha_se2_rd(struct iha_softc *sc, int addr) 2722 { 2723 bus_space_tag_t iot = sc->sc_iot; 2724 bus_space_handle_t ioh = sc->sc_ioh; 2725 int i, bit; 2726 uint16_t readword; 2727 2728 /* Send 'READ' instruction == address | READ bit */ 2729 iha_se2_instr(sc, addr | READ); 2730 2731 readword = 0; 2732 for (i = 16; i > 0; i--) { 2733 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS | NVRCK); 2734 EEP_WAIT(); 2735 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2736 EEP_WAIT(); 2737 /* sample data after the following edge of clock */ 2738 bit = bus_space_read_1(iot, ioh, TUL_NVRAM) & NVRDI ? 1 : 0; 2739 EEP_WAIT(); 2740 2741 readword |= bit << (i - 1); 2742 } 2743 2744 bus_space_write_1(iot, ioh, TUL_NVRAM, 0); 2745 2746 return (readword); 2747 } 2748 2749 /* 2750 * iha_se2_rd_all - Read SCSI H/A config parameters from serial EEPROM 2751 */ 2752 static int 2753 iha_se2_rd_all(struct iha_softc *sc, uint16_t *tbuf) 2754 { 2755 struct iha_eeprom *eeprom = (struct iha_eeprom *)tbuf; 2756 uint32_t chksum; 2757 int i; 2758 2759 for (i = 0, chksum = 0; i < EEPROM_SIZE - 1; i++) { 2760 *tbuf = iha_se2_rd(sc, i); 2761 chksum += *tbuf++; 2762 } 2763 *tbuf = iha_se2_rd(sc, 31); /* read checksum from EEPROM */ 2764 2765 chksum &= 0x0000ffff; /* lower 16 bits */ 2766 2767 return (eeprom->signature == EEP_SIGNATURE) && 2768 (eeprom->checksum == chksum); 2769 } 2770 2771 /* 2772 * iha_se2_instr - write an octet to serial E2PROM one bit at a time 2773 */ 2774 static void 2775 iha_se2_instr(struct iha_softc *sc, int instr) 2776 { 2777 bus_space_tag_t iot = sc->sc_iot; 2778 bus_space_handle_t ioh = sc->sc_ioh; 2779 int b, i; 2780 2781 b = NVRCS | NVRDO; /* Write the start bit (== 1) */ 2782 2783 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2784 EEP_WAIT(); 2785 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2786 EEP_WAIT(); 2787 2788 for (i = 8; i > 0; i--) { 2789 if (instr & (1 << (i - 1))) 2790 b = NVRCS | NVRDO; /* Write a 1 bit */ 2791 else 2792 b = NVRCS; /* Write a 0 bit */ 2793 2794 bus_space_write_1(iot, ioh, TUL_NVRAM, b); 2795 EEP_WAIT(); 2796 bus_space_write_1(iot, ioh, TUL_NVRAM, b | NVRCK); 2797 EEP_WAIT(); 2798 } 2799 2800 bus_space_write_1(iot, ioh, TUL_NVRAM, NVRCS); 2801 } 2802
Indexes created Wed Sep 24 05:09:52 GMT 2025