1 1.3 christos /* $NetBSD: ims332reg.h,v 1.3 2005/12/11 12:21:27 christos Exp $ */ 2 1.1 nisimura 3 1.2 perry /* 4 1.1 nisimura * Mach Operating System 5 1.1 nisimura * Copyright (c) 1991,1990,1989 Carnegie Mellon University 6 1.1 nisimura * All Rights Reserved. 7 1.2 perry * 8 1.1 nisimura * Permission to use, copy, modify and distribute this software and its 9 1.1 nisimura * documentation is hereby granted, provided that both the copyright 10 1.1 nisimura * notice and this permission notice appear in all copies of the 11 1.1 nisimura * software, derivative works or modified versions, and any portions 12 1.1 nisimura * thereof, and that both notices appear in supporting documentation. 13 1.2 perry * 14 1.1 nisimura * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 15 1.1 nisimura * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 16 1.1 nisimura * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 17 1.2 perry * 18 1.1 nisimura * Carnegie Mellon requests users of this software to return to 19 1.2 perry * 20 1.1 nisimura * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 21 1.1 nisimura * School of Computer Science 22 1.1 nisimura * Carnegie Mellon University 23 1.1 nisimura * Pittsburgh PA 15213-3890 24 1.2 perry * 25 1.1 nisimura * any improvements or extensions that they make and grant Carnegie Mellon 26 1.1 nisimura * the rights to redistribute these changes. 27 1.1 nisimura */ 28 1.1 nisimura 29 1.1 nisimura /* 30 1.1 nisimura * Defines for the Inmos IMS-G332 Colour video controller 31 1.1 nisimura * Author: Alessandro Forin, Carnegie Mellon University 32 1.1 nisimura * See: IMS G332 Colour Video Controller, 1990 Databook, pg 139-163, 33 1.1 nisimura * Inmos, Ltd. 34 1.1 nisimura */ 35 1.1 nisimura 36 1.1 nisimura /* 37 1.1 nisimura * Although the chip is built to be memory-mapped 38 1.1 nisimura * it can be programmed for 32 or 64 bit addressing. 39 1.1 nisimura * Moreover, the hardware bits have been twisted 40 1.1 nisimura * even more on the machine I am writing this for. 41 1.1 nisimura * So I'll just define the chip's offsets and leave 42 1.1 nisimura * it to the implementation to define the rest. 43 1.1 nisimura */ 44 1.1 nisimura 45 1.1 nisimura #define IMS332_REG_BOOT 0x000 /* boot time config */ 46 1.1 nisimura 47 1.1 nisimura #define IMS332_REG_HALF_SYNCH 0x021 /* datapath registers */ 48 1.1 nisimura #define IMS332_REG_BACK_PORCH 0x022 49 1.1 nisimura #define IMS332_REG_DISPLAY 0x023 50 1.1 nisimura #define IMS332_REG_SHORT_DIS 0x024 51 1.1 nisimura #define IMS332_REG_BROAD_PULSE 0x025 52 1.1 nisimura #define IMS332_REG_V_SYNC 0x026 53 1.1 nisimura #define IMS332_REG_V_PRE_EQUALIZE 0x027 54 1.1 nisimura #define IMS332_REG_V_POST_EQUALIZE 0x028 55 1.1 nisimura #define IMS332_REG_V_BLANK 0x029 56 1.1 nisimura #define IMS332_REG_V_DISPLAY 0x02a 57 1.1 nisimura #define IMS332_REG_LINE_TIME 0x02b 58 1.1 nisimura #define IMS332_REG_LINE_START 0x02c 59 1.1 nisimura #define IMS332_REG_MEM_INIT 0x02d 60 1.1 nisimura #define IMS332_REG_XFER_DELAY 0x02e 61 1.1 nisimura 62 1.1 nisimura #define IMS332_REG_COLOR_MASK 0x040 /* color mask register */ 63 1.1 nisimura 64 1.1 nisimura #define IMS332_REG_CSR_A 0x060 65 1.1 nisimura 66 1.1 nisimura #define IMS332_REG_CSR_B 0x070 67 1.1 nisimura 68 1.1 nisimura #define IMS332_REG_TOP_SCREEN 0x080 /* top-of-screen offset */ 69 1.1 nisimura 70 1.1 nisimura #define IMS332_REG_CURSOR_LUT_0 0x0a1 /* cursor palette */ 71 1.1 nisimura #define IMS332_REG_CURSOR_LUT_1 0x0a2 72 1.1 nisimura #define IMS332_REG_CURSOR_LUT_2 0x0a3 73 1.1 nisimura 74 1.1 nisimura #define IMS332_REG_RGB_CKSUM_0 0x0c0 /* test registers */ 75 1.1 nisimura #define IMS332_REG_RGB_CKSUM_1 0x0c1 76 1.1 nisimura #define IMS332_REG_RGB_CKSUM_2 0x0c2 77 1.1 nisimura 78 1.1 nisimura #define IMS332_REG_CURSOR_LOC 0x0c7 /* cursor location */ 79 1.1 nisimura 80 1.1 nisimura #define IMS332_REG_LUT_BASE 0x100 /* color palette */ 81 1.1 nisimura #define IMS332_REG_LUT_END 0x1ff 82 1.1 nisimura 83 1.1 nisimura #define IMS332_REG_CURSOR_RAM 0x200 /* cursor bitmap */ 84 1.1 nisimura #define IMS332_REG_CURSOR_RAM_END 0x3ff 85 1.1 nisimura 86 1.1 nisimura /* 87 1.1 nisimura * Control register A 88 1.1 nisimura */ 89 1.1 nisimura 90 1.1 nisimura #define IMS332_CSR_A_VTG_ENABLE 0x000001 /* vertical timing generator */ 91 1.1 nisimura #define IMS332_CSR_A_INTERLACED 0x000002 /* screen format */ 92 1.1 nisimura #define IMS332_CSR_A_CCIR 0x000004 /* default is EIA */ 93 1.1 nisimura #define IMS332_CSR_A_SLAVE_SYNC 0x000008 /* else from our pll */ 94 1.1 nisimura #define IMS332_CSR_A_PLAIN_SYNC 0x000010 /* else tesselated */ 95 1.1 nisimura #define IMS332_CSR_A_SEPARATE_SYNC 0x000020 /* else composite */ 96 1.1 nisimura #define IMS332_CSR_A_VIDEO_ONLY 0x000040 /* else video+sync */ 97 1.1 nisimura #define IMS332_CSR_A_BLANK_PEDESTAL 0x000080 /* blank level */ 98 1.1 nisimura #define IMS332_CSR_A_CBLANK_IS_OUT 0x000100 99 1.1 nisimura #define IMS332_CSR_A_CBLANK_NO_DELAY 0x000200 100 1.1 nisimura #define IMS332_CSR_A_FORCE_BLANK 0x000400 101 1.1 nisimura #define IMS332_CSR_A_BLANK_DISABLE 0x000800 102 1.1 nisimura #define IMS332_CSR_A_VRAM_INCREMENT 0x003000 103 1.1 nisimura # define IMS332_VRAM_INC_1 0x000000 104 1.1 nisimura # define IMS332_VRAM_INC_256 0x001000 /* except interlaced->2 */ 105 1.1 nisimura # define IMS332_VRAM_INC_512 0x002000 106 1.1 nisimura # define IMS332_VRAM_INC_1024 0x003000 107 1.1 nisimura #define IMS332_CSR_A_DMA_DISABLE 0x004000 108 1.1 nisimura #define IMS332_CSR_A_SYNC_DELAY_MASK 0x038000 /* 0-7 VTG clk delays */ 109 1.1 nisimura #define IMS332_CSR_A_PIXEL_INTERLEAVE 0x040000 110 1.1 nisimura #define IMS332_CSR_A_DELAYED_SAMPLING 0x080000 111 1.1 nisimura #define IMS332_CSR_A_BITS_PER_PIXEL 0x700000 112 1.1 nisimura # define IMS332_BPP_1 0x000000 113 1.1 nisimura # define IMS332_BPP_2 0x100000 114 1.1 nisimura # define IMS332_BPP_4 0x200000 115 1.1 nisimura # define IMS332_BPP_8 0x300000 116 1.1 nisimura # define IMS332_BPP_15 0x400000 117 1.1 nisimura # define IMS332_BPP_16 0x500000 118 1.1 nisimura #define IMS332_CSR_A_DISABLE_CURSOR 0x800000 119 1.1 nisimura 120 1.1 nisimura 121 1.1 nisimura /* 122 1.1 nisimura * Control register B is mbz 123 1.1 nisimura */ 124 1.1 nisimura 125 1.1 nisimura /* 126 1.1 nisimura * Boot register 127 1.1 nisimura */ 128 1.1 nisimura 129 1.1 nisimura #define IMS332_BOOT_PLL 0x00001f /* xPLL, binary */ 130 1.1 nisimura #define IMS332_BOOT_CLOCK_PLL 0x000020 /* else xternal */ 131 1.1 nisimura #define IMS332_BOOT_64_BIT_MODE 0x000040 /* else 32 */ 132 1.1 nisimura #define IMS332_BOOT_xxx 0xffff80 /* reserved, mbz */ 133