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interwavereg.h revision 1.8.70.1
      1       1.1  augustss #ifndef INTERWAVEREG_H
      2       1.1  augustss #define INTERWAVEREG_H
      3       1.1  augustss 
      4  1.8.70.1       mjf /*	$NetBSD: interwavereg.h,v 1.8.70.1 2008/06/02 13:23:23 mjf Exp $	*/
      5       1.1  augustss 
      6       1.1  augustss /*
      7       1.1  augustss  * Copyright (c) 1997 The NetBSD Foundation, Inc.
      8       1.1  augustss  * All rights reserved.
      9       1.1  augustss  *
     10       1.1  augustss  * Author: Kari Mettinen
     11       1.1  augustss  *
     12       1.1  augustss  * Redistribution and use in source and binary forms, with or without
     13       1.1  augustss  * modification, are permitted provided that the following conditions
     14       1.1  augustss  * are met:
     15       1.1  augustss  * 1. Redistributions of source code must retain the above copyright
     16       1.1  augustss  *    notice, this list of conditions and the following disclaimer.
     17       1.1  augustss  * 2. Redistributions in binary form must reproduce the above copyright
     18       1.1  augustss  *    notice, this list of conditions and the following disclaimer in the
     19       1.1  augustss  *    documentation and/or other materials provided with the distribution.
     20       1.1  augustss  *
     21       1.1  augustss  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     22       1.1  augustss  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     23       1.1  augustss  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     24       1.2       jtc  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     25       1.2       jtc  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     26       1.1  augustss  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     27       1.1  augustss  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     28       1.1  augustss  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     29       1.1  augustss  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     30       1.1  augustss  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     31       1.1  augustss  * POSSIBILITY OF SUCH DAMAGE.
     32       1.1  augustss  */
     33       1.1  augustss 
     34       1.1  augustss 
     35       1.7      kent #define IW_LINELEVEL_MAX	((1L << 10) - 1)
     36       1.7      kent #define IW_LINELEVEL_CODEC_MAX	((1L << 10) - 1)
     37       1.1  augustss 
     38       1.7      kent #define IW_OUTPUT_CLASS		10
     39       1.7      kent #define IW_INPUT_CLASS		11
     40       1.7      kent #define IW_RECORD_CLASS		12
     41       1.1  augustss 
     42       1.1  augustss 
     43       1.7      kent #define IW_MIC_IN		11
     44       1.7      kent #define IW_MIC_IN_LVL		0
     45       1.1  augustss 
     46       1.1  augustss /* these 2 are hw dependent values */
     47       1.7      kent #define IW_RIGHT_MIC_IN_PORT	0x16
     48       1.7      kent #define IW_LEFT_MIC_IN_PORT	0x17
     49       1.1  augustss 
     50       1.7      kent #define IW_AUX1			12
     51       1.7      kent #define IW_AUX1_LVL		1
     52       1.1  augustss 
     53       1.7      kent #define IW_RIGHT_AUX1_PORT	0x02
     54       1.7      kent #define IW_LEFT_AUX1_PORT	0x03
     55       1.1  augustss 
     56       1.7      kent #define IW_AUX2			13
     57       1.7      kent #define IW_AUX2_LVL		2
     58       1.1  augustss 
     59       1.7      kent #define IW_RIGHT_AUX2_PORT	0x04
     60       1.7      kent #define IW_LEFT_AUX2_PORT	0x05
     61       1.1  augustss 
     62       1.7      kent #define IW_LINE_IN		14
     63       1.7      kent #define IW_LINE_IN_LVL		3
     64       1.1  augustss 
     65       1.7      kent #define IW_RIGHT_LINE_IN_PORT	0x12
     66       1.7      kent #define IW_LEFT_LINE_IN_PORT	0x13
     67       1.1  augustss 
     68       1.7      kent #define IW_LINE_OUT		15
     69       1.7      kent #define IW_LINE_OUT_LVL		4
     70       1.1  augustss 
     71       1.7      kent #define IW_RIGHT_LINE_OUT_PORT	0x19
     72       1.7      kent #define IW_LEFT_LINE_OUT_PORT	0x1b
     73       1.1  augustss 
     74       1.7      kent #define IW_RECORD_SOURCE	5
     75       1.1  augustss 
     76       1.7      kent #define IW_REC			16
     77       1.7      kent #define IW_REC_LVL		6
     78       1.7      kent #define IW_REC_LEFT_PORT	0x00
     79       1.7      kent #define IW_REC_RIGHT_PORT	0x01
     80       1.1  augustss 
     81       1.7      kent #define IW_DAC			18
     82       1.7      kent #define IW_DAC_LVL		7
     83       1.7      kent #define IW_LEFT_DAC_PORT	0x06
     84       1.7      kent #define IW_RIGHT_DAC_PORT	0x07
     85       1.1  augustss 
     86       1.7      kent #define IW_LOOPBACK		19
     87       1.7      kent #define IW_LOOPBACK_LVL		8
     88       1.7      kent #define IW_LOOPBACK_PORT	0x0d
     89       1.1  augustss 
     90       1.7      kent #define IW_MONO_IN		20
     91       1.7      kent #define IW_MONO_IN_LVL		9
     92       1.7      kent #define IW_MONO_IN_PORT		0x1a
     93       1.1  augustss 
     94       1.7      kent #define IW_LINE_IN_SRC		0
     95       1.7      kent #define IW_AUX1_SRC		1
     96       1.7      kent #define IW_MIC_IN_SRC		2
     97       1.7      kent #define IW_MIX_OUT_SRC		3
     98       1.1  augustss 
     99       1.1  augustss 
    100       1.6       wiz /* DMA flags */
    101       1.1  augustss 
    102       1.1  augustss #define IW_PLAYBACK 1L
    103       1.1  augustss #define IW_RECORD   2L
    104       1.1  augustss 
    105       1.1  augustss #define ADDR_HIGH(a)  (u_short)((a) >> 7)
    106       1.1  augustss #define ADDR_LOW(a)   (u_short)((a) << 9)
    107       1.1  augustss 
    108       1.7      kent #define MIDI_TX_IRQ	  0x01
    109       1.7      kent #define MIDI_RX_IRQ	  0x02
    110       1.7      kent #define ALIB_TIMER1_IRQ	  0x04
    111       1.7      kent #define ALIB_TIMER2_IRQ	  0x08
    112       1.7      kent #define UASBCI		  0x45		/* UASBCI index */
    113       1.7      kent #define SAMPLE_CONTROL	  0x49		/* Not used by IW */
    114       1.7      kent #define SET_VOICES	  0x0E
    115       1.7      kent #define SAVI_WR		  0x0E
    116       1.7      kent #define WAVETABLE_IRQ	  0x20
    117       1.7      kent #define ENVELOPE_IRQ	  0x40
    118       1.7      kent #define DMA_TC_IRQ	  0x80
    119       1.7      kent 
    120       1.7      kent #define GEN_INDEX	  0x03		 /* IGIDX offset into p3xr */
    121       1.7      kent #define VOICE_SELECT	  0x02		 /* SVSR offset into p3xr */
    122       1.7      kent #define VOICE_IRQS	  0x8F		 /* SVII index (read) */
    123       1.7      kent #define URSTI		  0x4C		 /* URSTI index */
    124       1.7      kent #define GF1_SET		  0x01		 /* URSTI[0] */
    125       1.7      kent #define GF1_OUT_ENABLE	  0x02		 /* URSTI[1] */
    126       1.7      kent #define GF1_IRQ_ENABLE	  0x04		 /* URSTI[2] */
    127       1.7      kent #define GF1_RESET	  0xFE		 /* URSTI[0]=0 */
    128       1.7      kent #define VOICE_VOLUME_IRQ  0x04		 /* SVII[2] */
    129       1.7      kent #define VOICE_WAVE_IRQ	  0x08		 /* SVII[3] */
    130       1.7      kent #define VC_IRQ_ENABLE	  0x20		 /* SACI[5] or SVCI[5]*/
    131       1.7      kent #define VOICE_NUMBER	  0x1F		 /* Mask for SVII[4:0] */
    132       1.7      kent #define VC_IRQ_PENDING	  0x80		 /* SACI[7] or SVCI[7] */
    133       1.7      kent #define VC_DIRECT	  0x40		 /* SACI[6] or SVCI[6]*/
    134       1.7      kent #define VC_DATA_WIDTH	  0x04		 /* SACI[2] */
    135       1.7      kent #define VOICE_STOP	  0x02		 /* SACI[1] */
    136       1.7      kent #define VOICE_STOPPED	  0x01		 /* SACI[0] */
    137       1.7      kent #define VOLUME_STOP	  0x02		 /* SVCI[1] */
    138       1.7      kent #define VOLUME_STOPPED	  0x01		 /* SVCI[0] */
    139       1.7      kent #define VC_ROLLOVER	  0x04		 /* SVCI[2] */
    140       1.7      kent #define VC_LOOP_ENABLE	  0x08		 /* SVCI[3] or SACI[3]*/
    141       1.7      kent #define VC_BI_LOOP	  0x10		 /* SVCI[4] or SACI[4]*/
    142       1.7      kent #define VOICE_OFFSET	  0x20		 /* SMSI[5] */
    143       1.7      kent #define VOLUME_RATE0	  0x00		 /* SVRI[7:6]=(0,0) */
    144       1.7      kent #define VOLUME_RATE1	  0x40		 /* SVRI[7:6]=(0,1) */
    145       1.7      kent #define VOLUME_RATE2	  0x80		 /* SVRI[7:6]=(1,0) */
    146       1.7      kent #define VOLUME_RATE3	  0xC0		 /* SVRI[7:6]=(1,1) */
    147       1.7      kent 
    148       1.7      kent #define CSR1R		  0x02
    149       1.7      kent #define CPDR		  0x03
    150       1.7      kent #define CRDR		  0x03
    151       1.7      kent 
    152       1.7      kent #define SHUT_DOWN	  0x7E		 /* shuts InterWave down */
    153       1.7      kent #define POWER_UP	  0xFE		 /* enables all modules */
    154       1.7      kent #define CODEC_PWR_UP	  0x81		 /* enables Codec Analog Ckts */
    155       1.7      kent #define CODEC_PWR_DOWN	  0x01		 /* disables Codec Analog Ckts */
    156       1.7      kent #define CODEC_REC_UP	  0x82		 /* Enables Record Path */
    157       1.7      kent #define CODEC_REC_DOWN	  0x02		 /* Disables Record Path */
    158       1.7      kent #define CODEC_PLAY_UP	  0x84		 /* Enables Playback Path */
    159       1.7      kent #define CODEC_PLAY_DOWN	  0x04		 /* Disables Playback Path */
    160       1.7      kent #define CODEC_IRQ_ENABLE  0x02		 /* CEXTI[2] */
    161       1.7      kent #define CODEC_TIMER_IRQ	  0x40		 /* CSR3I[6] */
    162       1.7      kent #define CODEC_REC_IRQ	  0x20		 /* CSR3I[5] */
    163       1.7      kent #define CODEC_PLAY_IRQ	  0x10		 /* CSR3I[4] */
    164       1.7      kent #define CODEC_INT	  0x01		 /* CSR1R[0] */
    165       1.7      kent #define MONO_INPUT	  0x80		 /* CMONOI[7] */
    166       1.7      kent #define MONO_OUTPUT	  0x40		 /* CMONOI[6] */
    167       1.7      kent #define MIDI_UP		  0x88		 /* Enables MIDI ports */
    168       1.7      kent #define MIDI_DOWN	  0x08		 /* Disables MIDI ports */
    169       1.7      kent #define SYNTH_UP	  0x90		 /* Enables Synthesizer */
    170       1.7      kent #define SYNTH_DOWN	  0x10		 /* Disables Synthesizer */
    171       1.7      kent #define LMC_UP		  0xA0		 /* Enables LM Module */
    172       1.7      kent #define LMC_DOWN	  0x20		 /* Disbales LM Module */
    173       1.7      kent #define XTAL24_UP	  0xC0		 /* Enables 24MHz Osc */
    174       1.7      kent #define XTAL24_DOWN	  0x40		 /* Disables 24MHz Osc */
    175       1.7      kent #define PPWRI		  0xF2		 /* PPWRI index */
    176       1.7      kent #define PLAY		  0x0F
    177       1.7      kent #define REC		  0x1F
    178       1.7      kent #define LEFT_AUX1_INPUT	  0x02
    179       1.1  augustss #define RIGHT_AUX1_INPUT  0x03
    180       1.7      kent #define LEFT_AUX2_INPUT	  0x04
    181       1.1  augustss #define RIGHT_AUX2_INPUT  0x05
    182       1.7      kent #define LEFT_LINE_IN	  0x12
    183       1.7      kent #define RIGHT_LINE_IN	  0x13
    184       1.7      kent #define LEFT_LINE_OUT	  0x19
    185       1.7      kent #define RIGHT_LINE_OUT	  0x1B
    186       1.7      kent #define LEFT_SOURCE	  0x00
    187       1.7      kent #define RIGHT_SOURCE	  0x01
    188       1.7      kent #define LINE_IN		  0x00
    189       1.7      kent #define AUX1_IN		  0x40
    190       1.7      kent #define MIC_IN		  0x80
    191       1.7      kent #define MIX_IN		  0xC0
    192       1.7      kent #define LEFT_DAC	  0x06
    193       1.7      kent #define RIGHT_DAC	  0x07
    194       1.7      kent #define LEFT_MIC_IN	  0x16
    195       1.7      kent #define RIGHT_MIC_IN	  0x17
    196       1.7      kent #define CUPCTI		  0x0E
    197       1.7      kent #define CLPCTI		  0x0F
    198       1.7      kent #define CURCTI		  0x1E
    199       1.7      kent #define CLRCTI		  0x1F
    200       1.7      kent #define CLAX1I		  0x02
    201       1.7      kent #define CRAX1I		  0x03
    202       1.7      kent #define CLAX2I		  0x04
    203       1.7      kent #define CRAX2I		  0x05
    204       1.7      kent #define CLLICI		  0x12
    205       1.7      kent #define CRLICI		  0x13
    206       1.7      kent #define CLOAI		  0x19
    207       1.7      kent #define CROAI		  0x1B
    208       1.7      kent #define CLICI		  0x00
    209       1.7      kent #define CRICI		  0x01
    210       1.7      kent #define CLDACI		  0x06
    211       1.7      kent #define CRDACI		  0x07
    212       1.7      kent #define CPVFI		  0x1D
    213       1.7      kent 
    214       1.7      kent #define MAX_DMA		  0x07
    215       1.7      kent #define DMA_DECREMENT	  0x20
    216       1.7      kent #define AUTO_INIT	  0x10
    217       1.7      kent #define DMA_READ	  0x01
    218       1.7      kent #define DMA_WRITE	  0x02
    219       1.7      kent #define AUTO_READ	  0x03
    220       1.7      kent #define AUTO_WRITE	  0x04
    221       1.7      kent #define IDMA_INV	  0x0400
    222       1.7      kent #define IDMA_WIDTH_16	  0x0100
    223       1.7      kent 
    224       1.7      kent #define LDMACI		  0x41	/* Index */
    225       1.7      kent #define DMA_INV		  0x80
    226       1.7      kent #define DMA_IRQ_ENABLE	  0x20
    227       1.7      kent #define DMA_IRQ_PENDING	  0x40	/* on reads of LDMACI[6] */
    228       1.7      kent #define DMA_DATA_16	  0x40	/* on writes to LDMACI[6] */
    229       1.7      kent #define DMA_WIDTH_16	  0x04	/* 1=16-bit, 0=8-bit (DMA channel) */
    230       1.7      kent #define DMA_RATE	  0x18	/* 00=fastest,...,11=slowest */
    231       1.7      kent #define DMA_UPLOAD	  0x02	/* From LM to PC */
    232       1.7      kent #define DMA_ENABLE	  0x01
    233       1.7      kent 
    234       1.7      kent #define GUS_MODE	  0x00	/* SGMI[0]=0 */
    235       1.7      kent #define ENH_MODE	  0x01	/* SGMI[0]=1 */
    236       1.7      kent #define ENABLE_LFOS	  0x02	/* SGMI[1] */
    237       1.7      kent #define NO_WAVETABLE	  0x04	/* SGMI[2] */
    238       1.7      kent #define RAM_TEST	  0x08	/* SGMI[3] */
    239       1.7      kent 
    240       1.7      kent #define DMA_SET_MASK	  0x04
    241       1.7      kent 
    242       1.7      kent #define VOICE_STOP	  0x02		 /* SACI[1] */
    243       1.7      kent #define VOICE_STOPPED	  0x01		 /* SACI[0] */
    244       1.7      kent 
    245       1.7      kent #define LDSALI		  0x42
    246       1.7      kent #define LDSAHI		  0x50
    247       1.7      kent #define LMALI		  0x43
    248       1.7      kent #define LMAHI		  0x44
    249       1.7      kent #define LMCFI		  0x52
    250       1.7      kent #define LMCI		  0x53
    251       1.7      kent #define LMFSI		  0x56
    252       1.7      kent #define LDIBI		  0x58
    253       1.7      kent #define LDICI		  0x57
    254       1.7      kent #define LMSBAI		  0x51
    255       1.7      kent #define LMRFAI		  0x54
    256       1.7      kent #define LMPFAI		  0x55
    257       1.7      kent #define SVCI_RD		  0x8D
    258       1.7      kent #define SVCI_WR		  0x0D
    259       1.7      kent #define SACI_RD		  0x80
    260       1.7      kent #define SACI_WR		  0x00
    261       1.7      kent #define SALI_RD		  0x8B
    262       1.7      kent #define SALI_WR		  0x0B
    263       1.7      kent #define SAHI_RD		  0x8A
    264       1.7      kent #define SAHI_WR		  0x0A
    265       1.7      kent #define SASHI_RD	  0x82
    266       1.7      kent #define SASHI_WR	  0x02
    267       1.7      kent #define SASLI_RD	  0x83
    268       1.7      kent #define SASLI_WR	  0x03
    269       1.7      kent #define SAEHI_RD	  0x84
    270       1.7      kent #define SAEHI_WR	  0x04
    271       1.7      kent #define SAELI_RD	  0x85
    272       1.7      kent #define SAELI_WR	  0x05
    273       1.7      kent #define SVRI_RD		  0x86
    274       1.7      kent #define SVRI_WR		  0x06
    275       1.7      kent #define SVSI_RD		  0x87
    276       1.7      kent #define SVSI_WR		  0x07
    277       1.7      kent #define SVEI_RD		  0x88
    278       1.7      kent #define SVEI_WR		  0x08
    279       1.7      kent #define SVLI_RD		  0x89
    280       1.7      kent #define SVLI_WR		  0x09
    281       1.7      kent #define SROI_RD		  0x8C
    282       1.7      kent #define SROI_WR		  0x0C
    283       1.7      kent #define SLOI_RD		  0x93
    284       1.7      kent #define SLOI_WR		  0x13
    285       1.7      kent #define SMSI_RD		  0x95
    286       1.7      kent #define SMSI_WR		  0x15
    287       1.7      kent #define SGMI_RD		  0x99
    288       1.7      kent #define SGMI_WR		  0x19
    289       1.7      kent #define SFCI_RD		  0x81
    290       1.7      kent #define SFCI_WR		  0x01
    291       1.7      kent #define SUAI_RD		  0x90
    292       1.7      kent #define SUAI_WR		  0x10
    293       1.7      kent #define SVII		  0x8F
    294       1.7      kent #define CMODEI		  0x0C	      /* index for CMODEI */
    295       1.7      kent #define CMONOI		  0x1A
    296       1.7      kent #define CFIG3I		  0x11
    297       1.7      kent #define CFIG2I		  0x10
    298       1.7      kent #define CLTIMI		  0x14
    299       1.7      kent #define CUTIMI		  0x15
    300       1.7      kent #define CSR3I		  0x18	      /* Index to CSR3I (Interrupt Status) */
    301       1.7      kent #define CEXTI		  0x0A	      /* Index to External Control Register */
    302       1.7      kent #define CFIG1I		  0x09	      /* Index to Codec Conf Reg 1 */
    303       1.7      kent #define CSR2I		  0x0B	      /* Index to Codec Stat Reg 2 */
    304       1.7      kent #define CPDFI		  0x08	      /* Index to Play Data Format Reg */
    305       1.7      kent #define CRDFI		  0x1C	      /* Index to Rec Data Format Reg */
    306       1.7      kent #define CLMICI		  0x16	      /* Index to Left Mic Input Ctrl Register */
    307       1.7      kent #define CRMICI		  0x17	      /* Index to Right Mic Input Ctrl Register */
    308       1.7      kent #define CLCI		  0x0D	      /* Index to Loopback Ctrl Register */
    309       1.7      kent #define IVERI		  0x5B	      /* Index to register IVERI */
    310       1.7      kent #define IDECI		  0x5A
    311       1.7      kent #define ICMPTI		  0x59
    312       1.7      kent #define CODEC_MODE1	  0x00
    313       1.7      kent #define CODEC_MODE2	  0x40
    314       1.7      kent #define CODEC_MODE3	  0x6C	      /* Enhanced Mode */
    315       1.7      kent #define CODEC_STATUS1	  0x01
    316       1.7      kent #define CODEC_STATUS2	  0x0B	      /* Index to CSR2I */
    317       1.7      kent #define CODEC_STATUS3	  0x18	      /* Index to CSR3I */
    318       1.7      kent #define PLAYBACK	  0x01	      /* Enable playback path CFIG1I[0]=1*/
    319       1.7      kent #define RECORD		  0x02	      /* Enable Record path CFIG1I[1]=1*/
    320       1.7      kent #define TIMER_ENABLE	  0x40	      /* CFIG2I[6] */
    321       1.7      kent #define CODEC_MCE	  0x40	      /* CIDXR[6] */
    322       1.7      kent #define CALIB_IN_PROGRESS 0x20	      /* CSR2I[5] */
    323       1.7      kent #define CODEC_INIT	  0x80	      /* CIDXR[7] */
    324       1.7      kent #define BIT16_BIG	  0xC0	      /* 16-bit signed, big endian */
    325       1.7      kent #define IMA_ADPCM	  0xA0	      /* IMA-compliant ADPCM */
    326       1.7      kent #define BIT8_ALAW	  0x60	      /* 8-bit A-law */
    327       1.7      kent #define BIT16_LITTLE	  0x40	      /* 16-bit signed, little endian */
    328       1.7      kent #define BIT8_ULAW	  0x20	      /* 8-bit mu-law */
    329       1.7      kent #define BIT8_LINEAR	  0x00	      /* 8-bit unsigned */
    330       1.7      kent #define REC_DFORMAT	  0x1C
    331       1.7      kent #define PLAY_DFORMAT	  0x08
    332       1.7      kent #define DMA_ACCESS	  0x00
    333       1.7      kent #define PIO_ACCESS	  0xC0
    334       1.7      kent #define DMA_SIMPLEX	  0x04
    335       1.7      kent #define STEREO		  0x10	      /* CxDFI[4] */
    336       1.7      kent #define AUTOCALIB	  0x08	      /* CFIG1I[3] */
    337       1.7      kent #define ROM_IO		  0x02	      /* ROM I/O cycles - LMCI[1]=1 */
    338       1.7      kent #define DRAM_IO		  0x4D	      /* DRAM I/O cycles - LMCI[1]=0 */
    339       1.7      kent #define AUTOI		  0x01	      /* LMCI[0]=1 */
    340       1.7      kent #define PLDNI		  0x07
    341       1.7      kent #define ACTIVATE_DEV	  0x30
    342       1.7      kent #define PWAKEI		  0x03	      /* Index for PWAKEI */
    343       1.7      kent #define PISOCI		  0x01	      /* Index for PISOCI */
    344       1.7      kent #define PSECI		  0xF1	      /* Index for PSECI */
    345       1.7      kent #define RANGE_IOCHK	  0x31	      /* PURCI or PRRCI Index */
    346       1.7      kent #define MIDI_RESET	  0x03
    347       1.1  augustss 
    348       1.7      kent #define IW_DMA_RECORD	  0x02
    349       1.7      kent #define IW_DMA_PLAYBACK	  0x01
    350       1.1  augustss 
    351       1.7      kent #define IW_MCE		  0x40
    352       1.1  augustss 
    353       1.7      kent #define IN		  0
    354       1.7      kent #define OUT		  1
    355       1.1  augustss 
    356       1.1  augustss /* codec indirect register access */
    357       1.1  augustss 
    358       1.7      kent #define IW_WRITE_CODEC_1(reg, val) \
    359       1.7      kent do {\
    360       1.7      kent 	bus_space_write_1(sc->sc_iot, sc->codec_index_h, 0, (u_char)(reg));\
    361       1.7      kent 	bus_space_write_1(sc->sc_iot, sc->codec_index_h, sc->cdatap, (u_char)val);\
    362       1.7      kent 	bus_space_write_1(sc->sc_iot, sc->codec_index_h, 0, 0);\
    363       1.7      kent } while (0)\
    364       1.7      kent 
    365       1.7      kent #define IW_READ_CODEC_1(reg, ret) \
    366       1.7      kent do {\
    367       1.7      kent 	bus_space_write_1(sc->sc_iot, sc->codec_index_h, sc->codec_index, (u_char)(reg));\
    368       1.7      kent 	ret = bus_space_read_1(sc->sc_iot, sc->codec_index_h, sc->cdatap);\
    369       1.7      kent 	bus_space_write_1(sc->sc_iot, sc->codec_index_h, 0, 0);\
    370       1.7      kent } while (0)\
    371       1.1  augustss 
    372       1.1  augustss /* iw direct register access */
    373       1.1  augustss 
    374       1.7      kent #define IW_WRITE_DIRECT_1(reg, h, val) \
    375       1.7      kent do {\
    376       1.7      kent 	bus_space_write_1(sc->sc_iot, h, reg, (u_char)val);\
    377       1.7      kent } while (0)\
    378       1.7      kent 
    379       1.7      kent #define IW_READ_DIRECT_1(reg, h, ret) \
    380       1.7      kent do {\
    381       1.7      kent 	ret = bus_space_read_1(sc->sc_iot, h, (u_char)reg);\
    382       1.7      kent } while (0)\
    383       1.1  augustss 
    384       1.1  augustss /* general indexed regs access */
    385       1.1  augustss 
    386       1.7      kent #define IW_WRITE_GENERAL_1(reg, val) \
    387       1.7      kent do {\
    388       1.7      kent 	bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\
    389       1.7      kent 	bus_space_write_1(sc->sc_iot, sc->p3xr_h, 5, (u_char)val);\
    390       1.7      kent } while (0)\
    391       1.7      kent 
    392       1.7      kent #define IW_WRITE_GENERAL_2(reg, val) \
    393       1.7      kent do {\
    394       1.7      kent 	bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\
    395       1.7      kent 	bus_space_write_2(sc->sc_iot, sc->p3xr_h, 4, (u_short)val);\
    396       1.7      kent } while (0)\
    397       1.1  augustss 
    398       1.7      kent #define IW_READ_GENERAL_1(reg, ret) \
    399       1.1  augustss do{\
    400       1.7      kent 	bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\
    401       1.7      kent 	ret = bus_space_read_1(sc->sc_iot, sc->p3xr_h, 5);\
    402       1.7      kent } while (0)\
    403       1.1  augustss 
    404       1.7      kent #define IW_READ_GENERAL_2(reg, ret) \
    405       1.1  augustss do{\
    406       1.7      kent 	bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\
    407       1.7      kent 	ret = bus_space_read_2(sc->sc_iot, sc->p3xr_h, 4);\
    408       1.7      kent } while (0)\
    409       1.1  augustss 
    410       1.1  augustss 
    411       1.1  augustss #endif /* INTERWAVEREG_H */
    412