interwavereg.h revision 1.2
1 #ifndef INTERWAVEREG_H 2 #define INTERWAVEREG_H 3 4 /* $NetBSD: interwavereg.h,v 1.2 1997/10/09 08:03:48 jtc Exp $ */ 5 6 /* 7 * Copyright (c) 1997 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Kari Mettinen 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 42 #define IW_LINELEVEL_MAX ((1L << 10) - 1) 43 #define IW_LINELEVEL_CODEC_MAX ((1L << 10) - 1) 44 45 #define IW_OUTPUT_CLASS 10 46 #define IW_INPUT_CLASS 11 47 #define IW_RECORD_CLASS 12 48 49 50 #define IW_MIC_IN 11 51 #define IW_MIC_IN_LVL 0 52 53 /* these 2 are hw dependent values */ 54 #define IW_RIGHT_MIC_IN_PORT 0x16 55 #define IW_LEFT_MIC_IN_PORT 0x17 56 57 #define IW_AUX1 12 58 #define IW_AUX1_LVL 1 59 60 #define IW_RIGHT_AUX1_PORT 0x02 61 #define IW_LEFT_AUX1_PORT 0x03 62 63 #define IW_AUX2 13 64 #define IW_AUX2_LVL 2 65 66 #define IW_RIGHT_AUX2_PORT 0x04 67 #define IW_LEFT_AUX2_PORT 0x05 68 69 #define IW_LINE_IN 14 70 #define IW_LINE_IN_LVL 3 71 72 #define IW_RIGHT_LINE_IN_PORT 0x12 73 #define IW_LEFT_LINE_IN_PORT 0x13 74 75 #define IW_LINE_OUT 15 76 #define IW_LINE_OUT_LVL 4 77 78 #define IW_RIGHT_LINE_OUT_PORT 0x19 79 #define IW_LEFT_LINE_OUT_PORT 0x1b 80 81 #define IW_RECORD_SOURCE 5 82 83 #define IW_REC 16 84 #define IW_REC_LVL 6 85 #define IW_REC_LEFT_PORT 0x00 86 #define IW_REC_RIGHT_PORT 0x01 87 88 #define IW_DAC 18 89 #define IW_DAC_LVL 7 90 #define IW_LEFT_DAC_PORT 0x06 91 #define IW_RIGHT_DAC_PORT 0x07 92 93 #define IW_LOOPBACK 19 94 #define IW_LOOPBACK_LVL 8 95 #define IW_LOOPBACK_PORT 0x0d 96 97 #define IW_MONO_IN 20 98 #define IW_MONO_IN_LVL 9 99 #define IW_MONO_IN_PORT 0x1a 100 101 #define IW_LINE_IN_SRC 0 102 #define IW_AUX1_SRC 1 103 #define IW_MIC_IN_SRC 2 104 #define IW_MIX_OUT_SRC 3 105 106 107 #define IW_OUTPORT IW_MIC_IN_SRC 108 109 /* dma flags */ 110 111 #define IW_PLAYBACK 1L 112 #define IW_RECORD 2L 113 114 #define ADDR_HIGH(a) (u_short)((a) >> 7) 115 #define ADDR_LOW(a) (u_short)((a) << 9) 116 117 #define MIDI_TX_IRQ 0x01 118 #define MIDI_RX_IRQ 0x02 119 #define ALIB_TIMER1_IRQ 0x04 120 #define ALIB_TIMER2_IRQ 0x08 121 #define UASBCI 0x45 /* UASBCI index */ 122 #define SAMPLE_CONTROL 0x49 /* Not used by IW */ 123 #define SET_VOICES 0x0E 124 #define SAVI_WR 0x0E 125 #define WAVETABLE_IRQ 0x20 126 #define ENVELOPE_IRQ 0x40 127 #define DMA_TC_IRQ 0x80 128 129 #define GEN_INDEX 0x03 /* IGIDX offset into p3xr */ 130 #define VOICE_SELECT 0x02 /* SVSR offset into p3xr */ 131 #define VOICE_IRQS 0x8F /* SVII index (read) */ 132 #define URSTI 0x4C /* URSTI index */ 133 #define GF1_SET 0x01 /* URSTI[0] */ 134 #define GF1_OUT_ENABLE 0x02 /* URSTI[1] */ 135 #define GF1_IRQ_ENABLE 0x04 /* URSTI[2] */ 136 #define GF1_RESET 0xFE /* URSTI[0]=0 */ 137 #define VOICE_VOLUME_IRQ 0x04 /* SVII[2] */ 138 #define VOICE_WAVE_IRQ 0x08 /* SVII[3] */ 139 #define VC_IRQ_ENABLE 0x20 /* SACI[5] or SVCI[5]*/ 140 #define VOICE_NUMBER 0x1F /* Mask for SVII[4:0] */ 141 #define VC_IRQ_PENDING 0x80 /* SACI[7] or SVCI[7] */ 142 #define VC_DIRECT 0x40 /* SACI[6] or SVCI[6]*/ 143 #define VC_DATA_WIDTH 0x04 /* SACI[2] */ 144 #define VOICE_STOP 0x02 /* SACI[1] */ 145 #define VOICE_STOPPED 0x01 /* SACI[0] */ 146 #define VOLUME_STOP 0x02 /* SVCI[1] */ 147 #define VOLUME_STOPPED 0x01 /* SVCI[0] */ 148 #define VC_ROLLOVER 0x04 /* SVCI[2] */ 149 #define VC_LOOP_ENABLE 0x08 /* SVCI[3] or SACI[3]*/ 150 #define VC_BI_LOOP 0x10 /* SVCI[4] or SACI[4]*/ 151 #define VOICE_OFFSET 0x20 /* SMSI[5] */ 152 #define VOLUME_RATE0 0x00 /* SVRI[7:6]=(0,0) */ 153 #define VOLUME_RATE1 0x40 /* SVRI[7:6]=(0,1) */ 154 #define VOLUME_RATE2 0x80 /* SVRI[7:6]=(1,0) */ 155 #define VOLUME_RATE3 0xC0 /* SVRI[7:6]=(1,1) */ 156 157 #define CSR1R 0x02 158 #define CPDR 0x03 159 #define CRDR 0x03 160 161 #define SHUT_DOWN 0x7E /* shuts InterWave down */ 162 #define POWER_UP 0xFE /* enables all modules */ 163 #define CODEC_PWR_UP 0x81 /* enables Codec Analog Ckts */ 164 #define CODEC_PWR_DOWN 0x01 /* disables Codec Analog Ckts */ 165 #define CODEC_REC_UP 0x82 /* Enables Record Path */ 166 #define CODEC_REC_DOWN 0x02 /* Disables Record Path */ 167 #define CODEC_PLAY_UP 0x84 /* Enables Playback Path */ 168 #define CODEC_PLAY_DOWN 0x04 /* Disables Playback Path */ 169 #define CODEC_IRQ_ENABLE 0x02 /* CEXTI[2] */ 170 #define CODEC_TIMER_IRQ 0x40 /* CSR3I[6] */ 171 #define CODEC_REC_IRQ 0x20 /* CSR3I[5] */ 172 #define CODEC_PLAY_IRQ 0x10 /* CSR3I[4] */ 173 #define CODEC_INT 0x01 /* CSR1R[0] */ 174 #define MONO_INPUT 0x80 /* CMONOI[7] */ 175 #define MONO_OUTPUT 0x40 /* CMONOI[6] */ 176 #define MIDI_UP 0x88 /* Enables MIDI ports */ 177 #define MIDI_DOWN 0x08 /* Disables MIDI ports */ 178 #define SYNTH_UP 0x90 /* Enables Synthesizer */ 179 #define SYNTH_DOWN 0x10 /* Disables Synthesizer */ 180 #define LMC_UP 0xA0 /* Enables LM Module */ 181 #define LMC_DOWN 0x20 /* Disbales LM Module */ 182 #define XTAL24_UP 0xC0 /* Enables 24MHz Osc */ 183 #define XTAL24_DOWN 0x40 /* Disables 24MHz Osc */ 184 #define PPWRI 0xF2 /* PPWRI index */ 185 #define PLAY 0x0F 186 #define REC 0x1F 187 #define LEFT_AUX1_INPUT 0x02 188 #define RIGHT_AUX1_INPUT 0x03 189 #define LEFT_AUX2_INPUT 0x04 190 #define RIGHT_AUX2_INPUT 0x05 191 #define LEFT_LINE_IN 0x12 192 #define RIGHT_LINE_IN 0x13 193 #define LEFT_LINE_OUT 0x19 194 #define RIGHT_LINE_OUT 0x1B 195 #define LEFT_SOURCE 0x00 196 #define RIGHT_SOURCE 0x01 197 #define LINE_IN 0x00 198 #define AUX1_IN 0x40 199 #define MIC_IN 0x80 200 #define MIX_IN 0xC0 201 #define LEFT_DAC 0x06 202 #define RIGHT_DAC 0x07 203 #define LEFT_MIC_IN 0x16 204 #define RIGHT_MIC_IN 0x17 205 #define CUPCTI 0x0E 206 #define CLPCTI 0x0F 207 #define CURCTI 0x1E 208 #define CLRCTI 0x1F 209 #define CLAX1I 0x02 210 #define CRAX1I 0x03 211 #define CLAX2I 0x04 212 #define CRAX2I 0x05 213 #define CLLICI 0x12 214 #define CRLICI 0x13 215 #define CLOAI 0x19 216 #define CROAI 0x1B 217 #define CLICI 0x00 218 #define CRICI 0x01 219 #define CLDACI 0x06 220 #define CRDACI 0x07 221 #define CPVFI 0x1D 222 223 #define MAX_DMA 0x07 224 #define DMA_DECREMENT 0x20 225 #define AUTO_INIT 0x10 226 #define DMA_READ 0x01 227 #define DMA_WRITE 0x02 228 #define AUTO_READ 0x03 229 #define AUTO_WRITE 0x04 230 #define IDMA_INV 0x0400 231 #define IDMA_WIDTH_16 0x0100 232 233 #define LDMACI 0x41 /* Index */ 234 #define DMA_INV 0x80 235 #define DMA_IRQ_ENABLE 0x20 236 #define DMA_IRQ_PENDING 0x40 /* on reads of LDMACI[6] */ 237 #define DMA_DATA_16 0x40 /* on writes to LDMACI[6] */ 238 #define DMA_WIDTH_16 0x04 /* 1=16-bit, 0=8-bit (DMA channel) */ 239 #define DMA_RATE 0x18 /* 00=fastest,...,11=slowest */ 240 #define DMA_UPLOAD 0x02 /* From LM to PC */ 241 #define DMA_ENABLE 0x01 242 243 #define GUS_MODE 0x00 // SGMI[0]=0 244 #define ENH_MODE 0x01 // SGMI[0]=1 245 #define ENABLE_LFOS 0x02 // SGMI[1] 246 #define NO_WAVETABLE 0x04 // SGMI[2] 247 #define RAM_TEST 0x08 // SGMI[3] 248 249 #define DMA_SET_MASK 0x04 250 251 #define VOICE_STOP 0x02 /* SACI[1] */ 252 #define VOICE_STOPPED 0x01 /* SACI[0] */ 253 254 #define LDSALI 0x42 255 #define LDSAHI 0x50 256 #define LMALI 0x43 257 #define LMAHI 0x44 258 #define LMCFI 0x52 259 #define LMCI 0x53 260 #define LMFSI 0x56 261 #define LDIBI 0x58 262 #define LDICI 0x57 263 #define LMSBAI 0x51 264 #define LMRFAI 0x54 265 #define LMPFAI 0x55 266 #define SVCI_RD 0x8D 267 #define SVCI_WR 0x0D 268 #define SACI_RD 0x80 269 #define SACI_WR 0x00 270 #define SALI_RD 0x8B 271 #define SALI_WR 0x0B 272 #define SAHI_RD 0x8A 273 #define SAHI_WR 0x0A 274 #define SASHI_RD 0x82 275 #define SASHI_WR 0x02 276 #define SASLI_RD 0x83 277 #define SASLI_WR 0x03 278 #define SAEHI_RD 0x84 279 #define SAEHI_WR 0x04 280 #define SAELI_RD 0x85 281 #define SAELI_WR 0x05 282 #define SVRI_RD 0x86 283 #define SVRI_WR 0x06 284 #define SVSI_RD 0x87 285 #define SVSI_WR 0x07 286 #define SVEI_RD 0x88 287 #define SVEI_WR 0x08 288 #define SVLI_RD 0x89 289 #define SVLI_WR 0x09 290 #define SROI_RD 0x8C 291 #define SROI_WR 0x0C 292 #define SLOI_RD 0x93 293 #define SLOI_WR 0x13 294 #define SMSI_RD 0x95 295 #define SMSI_WR 0x15 296 #define SGMI_RD 0x99 297 #define SGMI_WR 0x19 298 #define SFCI_RD 0x81 299 #define SFCI_WR 0x01 300 #define SUAI_RD 0x90 301 #define SUAI_WR 0x10 302 #define SVII 0x8F 303 #define CMODEI 0x0C /* index for CMODEI */ 304 #define CMONOI 0x1A 305 #define CFIG3I 0x11 306 #define CFIG2I 0x10 307 #define CLTIMI 0x14 308 #define CUTIMI 0x15 309 #define CSR3I 0x18 /* Index to CSR3I (Interrupt Status) */ 310 #define CEXTI 0x0A /* Index to External Control Register */ 311 #define CFIG1I 0x09 /* Index to Codec Conf Reg 1 */ 312 #define CSR2I 0x0B /* Index to Codec Stat Reg 2 */ 313 #define CPDFI 0x08 /* Index to Play Data Format Reg */ 314 #define CRDFI 0x1C /* Index to Rec Data Format Reg */ 315 #define CLMICI 0x16 /* Index to Left Mic Input Ctrl Register */ 316 #define CRMICI 0x17 /* Index to Right Mic Input Ctrl Register */ 317 #define CLCI 0x0D /* Index to Loopback Ctrl Register */ 318 #define IVERI 0x5B /* Index to register IVERI */ 319 #define IDECI 0x5A 320 #define ICMPTI 0x59 321 #define CODEC_MODE1 0x00 322 #define CODEC_MODE2 0x40 323 #define CODEC_MODE3 0x6C /* Enhanced Mode */ 324 #define CODEC_STATUS1 0x01 325 #define CODEC_STATUS2 0x0B /* Index to CSR2I */ 326 #define CODEC_STATUS3 0x18 /* Index to CSR3I */ 327 #define PLAYBACK 0x01 /* Enable playback path CFIG1I[0]=1*/ 328 #define RECORD 0x02 /* Enable Record path CFIG1I[1]=1*/ 329 #define TIMER_ENABLE 0x40 /* CFIG2I[6] */ 330 #define CODEC_MCE 0x40 /* CIDXR[6] */ 331 #define CALIB_IN_PROGRESS 0x20 /* CSR2I[5] */ 332 #define CODEC_INIT 0x80 /* CIDXR[7] */ 333 #define BIT16_BIG 0xC0 /* 16-bit signed, big endian */ 334 #define IMA_ADPCM 0xA0 /* IMA-compliant ADPCM */ 335 #define BIT8_ALAW 0x60 /* 8-bit A-law */ 336 #define BIT16_LITTLE 0x40 /* 16-bit signed, lillte endian */ 337 #define BIT8_ULAW 0x20 /* 8-bit u-law */ 338 #define BIT8_LINEAR 0x00 /* 8-bit unsigned */ 339 #define REC_DFORMAT 0x1C 340 #define PLAY_DFORMAT 0x08 341 #define DMA_ACCESS 0x00 342 #define PIO_ACCESS 0xC0 343 #define DMA_SIMPLEX 0x04 344 #define STEREO 0x10 /* CxDFI[4] */ 345 #define AUTOCALIB 0x08 /* CFIG1I[3] */ 346 #define ROM_IO 0x02 /* ROM I/O cycles - LMCI[1]=1 */ 347 #define DRAM_IO 0x4D /* DRAM I/O cycles - LMCI[1]=0 */ 348 #define AUTOI 0x01 /* LMCI[0]=1 */ 349 #define PLDNI 0x07 350 #define ACTIVATE_DEV 0x30 351 #define PWAKEI 0x03 /* Index for PWAKEI */ 352 #define PISOCI 0x01 /* Index for PISOCI */ 353 #define PSECI 0xF1 /* Index for PSECI */ 354 #define RANGE_IOCHK 0x31 /* PURCI or PRRCI Index */ 355 #define MIDI_RESET 0x03 356 357 #define IW_DMA_RECORD 0x02 358 #define IW_DMA_PLAYBACK 0x01 359 360 #define IW_MCE 0x40 361 362 #define IN 0 363 #define OUT 1 364 365 /* codec indirect register access */ 366 367 #define IW_WRITE_CODEC_1(reg,val) \ 368 do{\ 369 bus_space_write_1(sc->sc_iot,sc->codec_index_h, 0, (u_char)(reg));\ 370 bus_space_write_1(sc->sc_iot,sc->codec_index_h,sc->cdatap,(u_char)val);\ 371 bus_space_write_1(sc->sc_iot,sc->codec_index_h, 0,0);\ 372 }while(0)\ 373 374 #define IW_READ_CODEC_1(reg,ret) \ 375 do{\ 376 bus_space_write_1(sc->sc_iot,sc->codec_index_h,sc->codec_index,(u_char)(reg));\ 377 ret=bus_space_read_1(sc->sc_iot,sc->codec_index_h,sc->cdatap);\ 378 bus_space_write_1(sc->sc_iot,sc->codec_index_h, 0,0);\ 379 }while(0)\ 380 381 /* iw direct register access */ 382 383 #define IW_WRITE_DIRECT_1(reg,h,val) \ 384 do{\ 385 bus_space_write_1(sc->sc_iot,h,reg,(u_char)val);\ 386 }while(0)\ 387 388 #define IW_READ_DIRECT_1(reg,h,ret) \ 389 do{\ 390 ret=bus_space_read_1(sc->sc_iot,h,(u_char)reg);\ 391 }while(0)\ 392 393 /* general indexed regs access */ 394 395 #define IW_WRITE_GENERAL_1(reg,val) \ 396 do{\ 397 bus_space_write_1(sc->sc_iot,sc->p3xr_h,3,(u_char)reg);\ 398 bus_space_write_1(sc->sc_iot,sc->p3xr_h,5,(u_char)val);\ 399 }while(0)\ 400 401 #define IW_WRITE_GENERAL_2(reg,val) \ 402 do{\ 403 bus_space_write_1(sc->sc_iot,sc->p3xr_h,3,(u_char)reg);\ 404 bus_space_write_2(sc->sc_iot,sc->p3xr_h,4,(u_short)val);\ 405 }while(0)\ 406 407 #define IW_READ_GENERAL_1(reg,ret) \ 408 do{\ 409 bus_space_write_1(sc->sc_iot,sc->p3xr_h,3,(u_char)reg);\ 410 ret=bus_space_read_1(sc->sc_iot,sc->p3xr_h,5);\ 411 }while(0)\ 412 413 #define IW_READ_GENERAL_2(reg,ret) \ 414 do{\ 415 bus_space_write_1(sc->sc_iot,sc->p3xr_h,3,(u_char)reg);\ 416 ret=bus_space_read_2(sc->sc_iot,sc->p3xr_h,4);\ 417 }while(0)\ 418 419 420 #endif /* INTERWAVEREG_H */ 421
Indexes created Wed Sep 24 15:09:51 GMT 2025