ispmbox.h revision 1.10
1 /* $NetBSD: ispmbox.h,v 1.10 1998/12/05 19:48:23 mjacob Exp $ */ 2 /* ispmbox.h 1.10 */ 3 /* 4 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters. 5 * 6 *--------------------------------------- 7 * Copyright (c) 1997, 1998 by Matthew Jacob 8 * NASA/Ames Research Center 9 * All rights reserved. 10 *--------------------------------------- 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice immediately at the beginning of the file, without modification, 17 * this list of conditions, and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 #ifndef _ISPMBOX_H 38 #define _ISPMBOX_H 39 40 /* 41 * Mailbox Command Opcodes 42 */ 43 44 #define MBOX_NO_OP 0x0000 45 #define MBOX_LOAD_RAM 0x0001 46 #define MBOX_EXEC_FIRMWARE 0x0002 47 #define MBOX_DUMP_RAM 0x0003 48 #define MBOX_WRITE_RAM_WORD 0x0004 49 #define MBOX_READ_RAM_WORD 0x0005 50 #define MBOX_MAILBOX_REG_TEST 0x0006 51 #define MBOX_VERIFY_CHECKSUM 0x0007 52 #define MBOX_ABOUT_FIRMWARE 0x0008 53 /* 9 */ 54 /* a */ 55 /* b */ 56 /* c */ 57 /* d */ 58 #define MBOX_CHECK_FIRMWARE 0x000e 59 /* f */ 60 #define MBOX_INIT_REQ_QUEUE 0x0010 61 #define MBOX_INIT_RES_QUEUE 0x0011 62 #define MBOX_EXECUTE_IOCB 0x0012 63 #define MBOX_WAKE_UP 0x0013 64 #define MBOX_STOP_FIRMWARE 0x0014 65 #define MBOX_ABORT 0x0015 66 #define MBOX_ABORT_DEVICE 0x0016 67 #define MBOX_ABORT_TARGET 0x0017 68 #define MBOX_BUS_RESET 0x0018 69 #define MBOX_STOP_QUEUE 0x0019 70 #define MBOX_START_QUEUE 0x001a 71 #define MBOX_SINGLE_STEP_QUEUE 0x001b 72 #define MBOX_ABORT_QUEUE 0x001c 73 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 74 /* 1e */ 75 #define MBOX_GET_FIRMWARE_STATUS 0x001f 76 #define MBOX_GET_INIT_SCSI_ID 0x0020 77 #define MBOX_GET_SELECT_TIMEOUT 0x0021 78 #define MBOX_GET_RETRY_COUNT 0x0022 79 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 80 #define MBOX_GET_CLOCK_RATE 0x0024 81 #define MBOX_GET_ACT_NEG_STATE 0x0025 82 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 83 #define MBOX_GET_SBUS_PARAMS 0x0027 84 #define MBOX_GET_TARGET_PARAMS 0x0028 85 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 86 /* 2a */ 87 /* 2b */ 88 /* 2c */ 89 /* 2d */ 90 /* 2e */ 91 /* 2f */ 92 #define MBOX_SET_INIT_SCSI_ID 0x0030 93 #define MBOX_SET_SELECT_TIMEOUT 0x0031 94 #define MBOX_SET_RETRY_COUNT 0x0032 95 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 96 #define MBOX_SET_CLOCK_RATE 0x0034 97 #define MBOX_SET_ACTIVE_NEG_STATE 0x0035 98 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 99 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 100 #define MBOX_SET_PCI_PARAMETERS 0x0037 101 #define MBOX_SET_TARGET_PARAMS 0x0038 102 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 103 /* 3a */ 104 /* 3b */ 105 /* 3c */ 106 /* 3d */ 107 /* 3e */ 108 /* 3f */ 109 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 110 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 111 #define MBOX_EXEC_BIOS_IOCB 0x0042 112 113 /* These are for the ISP2100 FC cards */ 114 #define MBOX_GET_LOOP_ID 0x20 115 #define MBOX_EXEC_COMMAND_IOCB_A64 0x54 116 #define MBOX_INIT_FIRMWARE 0x60 117 #define MBOX_GET_INIT_CONTROL_BLOCK 0x61 118 #define MBOX_INIT_LIP 0x62 119 #define MBOX_GET_FC_AL_POSITION_MAP 0x63 120 #define MBOX_GET_PORT_DB 0x64 121 #define MBOX_CLEAR_ACA 0x65 122 #define MBOX_TARGET_RESET 0x66 123 #define MBOX_CLEAR_TASK_SET 0x67 124 #define MBOX_ABORT_TASK_SET 0x68 125 #define MBOX_GET_FW_STATE 0x69 126 #define MBOX_GET_LINK_STATUS 0x6a 127 #define MBOX_INIT_LIP_RESET 0x6c 128 #define MBOX_INIT_LIP_LOGIN 0x72 129 130 #define ISP2100_SET_PCI_PARAM 0x00ff 131 132 #define MBOX_BUSY 0x04 133 134 typedef struct { 135 u_int16_t param[8]; 136 } mbreg_t; 137 138 /* 139 * Mailbox Command Complete Status Codes 140 */ 141 #define MBOX_COMMAND_COMPLETE 0x4000 142 #define MBOX_INVALID_COMMAND 0x4001 143 #define MBOX_HOST_INTERFACE_ERROR 0x4002 144 #define MBOX_TEST_FAILED 0x4003 145 #define MBOX_COMMAND_ERROR 0x4005 146 #define MBOX_COMMAND_PARAM_ERROR 0x4006 147 148 /* 149 * Asynchronous event status codes 150 */ 151 #define ASYNC_BUS_RESET 0x8001 152 #define ASYNC_SYSTEM_ERROR 0x8002 153 #define ASYNC_RQS_XFER_ERR 0x8003 154 #define ASYNC_RSP_XFER_ERR 0x8004 155 #define ASYNC_QWAKEUP 0x8005 156 #define ASYNC_TIMEOUT_RESET 0x8006 157 #define ASYNC_DEVICE_RESET 0x8007 158 #define ASYNC_EXTMSG_UNDERRUN 0x800A 159 #define ASYNC_SCAM_INT 0x800B 160 #define ASYNC_HUNG_SCSI 0x800C 161 #define ASYNC_KILLED_BUS 0x800D 162 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 163 #define ASYNC_CMD_CMPLT 0x8020 164 #define ASYNC_CTIO_DONE 0x8021 165 166 /* for ISP2100 only */ 167 #define ASYNC_LIP_OCCURRED 0x8010 168 #define ASYNC_LOOP_UP 0x8011 169 #define ASYNC_LOOP_DOWN 0x8012 170 #define ASYNC_LOOP_RESET 0x8013 171 #define ASYNC_PDB_CHANGED 0x8014 172 #define ASYNC_CHANGE_NOTIFY 0x8015 173 174 /* 175 * Command Structure Definitions 176 */ 177 178 typedef struct { 179 u_int32_t ds_base; 180 u_int32_t ds_count; 181 } ispds_t; 182 183 typedef struct { 184 #if BYTE_ORDER == BIG_ENDIAN 185 u_int8_t rqs_entry_count; 186 u_int8_t rqs_entry_type; 187 u_int8_t rqs_flags; 188 u_int8_t rqs_seqno; 189 #else 190 u_int8_t rqs_entry_type; 191 u_int8_t rqs_entry_count; 192 u_int8_t rqs_seqno; 193 u_int8_t rqs_flags; 194 #endif 195 } isphdr_t; 196 197 /* RQS Flag definitions */ 198 #define RQSFLAG_CONTINUATION 0x01 199 #define RQSFLAG_FULL 0x02 200 #define RQSFLAG_BADHEADER 0x04 201 #define RQSFLAG_BADPACKET 0x08 202 203 /* RQS entry_type definitions */ 204 #define RQSTYPE_REQUEST 0x01 205 #define RQSTYPE_DATASEG 0x02 206 #define RQSTYPE_RESPONSE 0x03 207 #define RQSTYPE_MARKER 0x04 208 #define RQSTYPE_CMDONLY 0x05 209 #define RQSTYPE_ATIO 0x06 /* Target Mode */ 210 #define RQSTYPE_CTIO0 0x07 /* Target Mode */ 211 #define RQSTYPE_SCAM 0x08 212 #define RQSTYPE_A64 0x09 213 #define RQSTYPE_A64_CONT 0x0a 214 #define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */ 215 #define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */ 216 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 217 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 218 #define RQSTYPE_CTIO1 0x0f /* Target Mode */ 219 #define RQSTYPE_STATUS_CONT 0x10 220 #define RQSTYPE_T2RQS 0x11 221 222 #define RQSTYPE_T4RQS 0x15 223 #define RQSTYPE_ATIO2 0x16 224 #define RQSTYPE_CTIO2 0x17 225 #define RQSTYPE_CSET0 0x18 226 #define RQSTYPE_T3RQS 0x19 227 228 #define RQSTYPE_CTIO3 0x1f 229 230 231 #define ISP_RQDSEG 4 232 typedef struct { 233 isphdr_t req_header; 234 u_int32_t req_handle; 235 #if BYTE_ORDER == BIG_ENDIAN 236 u_int8_t req_target; 237 u_int8_t req_lun_trn; 238 #else 239 u_int8_t req_lun_trn; 240 u_int8_t req_target; 241 #endif 242 u_int16_t req_cdblen; 243 #define req_modifier req_cdblen /* marker packet */ 244 u_int16_t req_flags; 245 u_int16_t req_reserved; 246 u_int16_t req_time; 247 u_int16_t req_seg_count; 248 u_int8_t req_cdb[12]; 249 ispds_t req_dataseg[ISP_RQDSEG]; 250 } ispreq_t; 251 252 #define ISP_RQDSEG_T2 3 253 typedef struct { 254 isphdr_t req_header; 255 u_int32_t req_handle; 256 #if BYTE_ORDER == BIG_ENDIAN 257 u_int8_t req_target; 258 u_int8_t req_lun_trn; 259 #else 260 u_int8_t req_lun_trn; 261 u_int8_t req_target; 262 #endif 263 u_int16_t req_scclun; 264 u_int16_t req_flags; 265 u_int16_t _res2; 266 u_int16_t req_time; 267 u_int16_t req_seg_count; 268 u_int32_t req_cdb[4]; 269 u_int32_t req_totalcnt; 270 ispds_t req_dataseg[ISP_RQDSEG_T2]; 271 } ispreqt2_t; 272 273 /* req_flag values */ 274 #define REQFLAG_NODISCON 0x0001 275 #define REQFLAG_HTAG 0x0002 276 #define REQFLAG_OTAG 0x0004 277 #define REQFLAG_STAG 0x0008 278 #define REQFLAG_TARGET_RTN 0x0010 279 280 #define REQFLAG_NODATA 0x0000 281 #define REQFLAG_DATA_IN 0x0020 282 #define REQFLAG_DATA_OUT 0x0040 283 #define REQFLAG_DATA_UNKNOWN 0x0060 284 285 #define REQFLAG_DISARQ 0x0100 286 #define REQFLAG_FRC_ASYNC 0x0200 287 #define REQFLAG_FRC_SYNC 0x0400 288 #define REQFLAG_FRC_WIDE 0x0800 289 #define REQFLAG_NOPARITY 0x1000 290 #define REQFLAG_STOPQ 0x2000 291 #define REQFLAG_XTRASNS 0x4000 292 #define REQFLAG_PRIORITY 0x8000 293 294 typedef struct { 295 isphdr_t req_header; 296 u_int32_t req_handle; 297 #if BYTE_ORDER == BIG_ENDIAN 298 u_int8_t req_target; 299 u_int8_t req_lun_trn; 300 #else 301 u_int8_t req_lun_trn; 302 u_int8_t req_target; 303 #endif 304 u_int16_t req_cdblen; 305 u_int16_t req_flags; 306 u_int16_t _res1; 307 u_int16_t req_time; 308 u_int16_t req_seg_count; 309 u_int8_t req_cdb[44]; 310 } ispextreq_t; 311 312 #define ISP_CDSEG 7 313 typedef struct { 314 isphdr_t req_header; 315 u_int32_t _res1; 316 ispds_t req_dataseg[ISP_CDSEG]; 317 } ispcontreq_t; 318 319 typedef struct { 320 isphdr_t req_header; 321 u_int32_t _res1; 322 #if BYTE_ORDER == BIG_ENDIAN 323 u_int8_t req_target; 324 u_int8_t req_lun_trn; 325 u_int8_t _res2; 326 u_int8_t req_modifier; 327 #else 328 u_int8_t req_lun_trn; 329 u_int8_t req_target; 330 u_int8_t req_modifier; 331 u_int8_t _res2; 332 #endif 333 } ispmarkreq_t; 334 335 #define SYNC_DEVICE 0 336 #define SYNC_TARGET 1 337 #define SYNC_ALL 2 338 339 typedef struct { 340 isphdr_t req_header; 341 u_int32_t req_handle; 342 u_int16_t req_scsi_status; 343 u_int16_t req_completion_status; 344 u_int16_t req_state_flags; 345 u_int16_t req_status_flags; 346 u_int16_t req_time; 347 u_int16_t req_sense_len; 348 u_int32_t req_resid; 349 u_int8_t _res1[8]; 350 u_int8_t req_sense_data[32]; 351 } ispstatusreq_t; 352 353 /* 354 * For Qlogic 2100, the high order byte of SCSI status has 355 * additional meaning. 356 */ 357 #define RQCS_RU 0x800 /* Residual Under */ 358 #define RQCS_RO 0x400 /* Residual Over */ 359 #define RQCS_SV 0x200 /* Sense Length Valid */ 360 #define RQCS_RV 0x100 /* Residual Valid */ 361 362 /* 363 * Completion Status Codes. 364 */ 365 #define RQCS_COMPLETE 0x0000 366 #define RQCS_INCOMPLETE 0x0001 367 #define RQCS_DMA_ERROR 0x0002 368 #define RQCS_TRANSPORT_ERROR 0x0003 369 #define RQCS_RESET_OCCURRED 0x0004 370 #define RQCS_ABORTED 0x0005 371 #define RQCS_TIMEOUT 0x0006 372 #define RQCS_DATA_OVERRUN 0x0007 373 #define RQCS_COMMAND_OVERRUN 0x0008 374 #define RQCS_STATUS_OVERRUN 0x0009 375 #define RQCS_BAD_MESSAGE 0x000a 376 #define RQCS_NO_MESSAGE_OUT 0x000b 377 #define RQCS_EXT_ID_FAILED 0x000c 378 #define RQCS_IDE_MSG_FAILED 0x000d 379 #define RQCS_ABORT_MSG_FAILED 0x000e 380 #define RQCS_REJECT_MSG_FAILED 0x000f 381 #define RQCS_NOP_MSG_FAILED 0x0010 382 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 383 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 384 #define RQCS_ID_MSG_FAILED 0x0013 385 #define RQCS_UNEXP_BUS_FREE 0x0014 386 #define RQCS_DATA_UNDERRUN 0x0015 387 #define RQCS_XACT_ERR1 0x0018 388 #define RQCS_XACT_ERR2 0x0019 389 #define RQCS_XACT_ERR3 0x001A 390 #define RQCS_BAD_ENTRY 0x001B 391 #define RQCS_QUEUE_FULL 0x001C 392 #define RQCS_PHASE_SKIPPED 0x001D 393 #define RQCS_ARQS_FAILED 0x001E 394 #define RQCS_WIDE_FAILED 0x001F 395 #define RQCS_SYNCXFER_FAILED 0x0020 396 #define RQCS_LVD_BUSERR 0x0021 397 398 /* 2100 Only Completion Codes */ 399 #define RQCS_PORT_UNAVAILABLE 0x0028 400 #define RQCS_PORT_LOGGED_OUT 0x0029 401 #define RQCS_PORT_CHANGED 0x002A 402 #define RQCS_PORT_BUSY 0x002B 403 404 /* 405 * State Flags (not applicable to 2100) 406 */ 407 #define RQSF_GOT_BUS 0x0100 408 #define RQSF_GOT_TARGET 0x0200 409 #define RQSF_SENT_CDB 0x0400 410 #define RQSF_XFRD_DATA 0x0800 411 #define RQSF_GOT_STATUS 0x1000 412 #define RQSF_GOT_SENSE 0x2000 413 #define RQSF_XFER_COMPLETE 0x4000 414 415 /* 416 * Status Flags (not applicable to 2100) 417 */ 418 #define RQSTF_DISCONNECT 0x0001 419 #define RQSTF_SYNCHRONOUS 0x0002 420 #define RQSTF_PARITY_ERROR 0x0004 421 #define RQSTF_BUS_RESET 0x0008 422 #define RQSTF_DEVICE_RESET 0x0010 423 #define RQSTF_ABORTED 0x0020 424 #define RQSTF_TIMEOUT 0x0040 425 #define RQSTF_NEGOTIATION 0x0080 426 427 /* 428 * FC (ISP2100) specific initialization data structures 429 */ 430 431 /* 432 * Initialization Control Block 433 * 434 * Version One format. 435 */ 436 typedef struct { 437 #if BYTE_ORDER == BIG_ENDIAN 438 u_int8_t _reserved0; 439 u_int8_t icb_version; 440 #else 441 u_int8_t icb_version; 442 u_int8_t _reserved0; 443 #endif 444 u_int16_t icb_fwoptions; 445 u_int16_t icb_maxfrmlen; 446 u_int16_t icb_maxalloc; 447 u_int16_t icb_execthrottle; 448 #if BYTE_ORDER == BIG_ENDIAN 449 u_int8_t icb_retry_delay; 450 u_int8_t icb_retry_count; 451 #else 452 u_int8_t icb_retry_count; 453 u_int8_t icb_retry_delay; 454 #endif 455 u_int8_t icb_nodename[8]; 456 u_int16_t icb_hardaddr; 457 #if BYTE_ORDER == BIG_ENDIAN 458 u_int8_t _reserved1; 459 u_int8_t icb_iqdevtype; 460 #else 461 u_int8_t icb_iqdevtype; 462 u_int8_t _reserved1; 463 #endif 464 u_int8_t icb_portname[8]; 465 u_int16_t icb_rqstout; 466 u_int16_t icb_rspnsin; 467 u_int16_t icb_rqstqlen; 468 u_int16_t icb_rsltqlen; 469 u_int16_t icb_rqstaddr[4]; 470 u_int16_t icb_respaddr[4]; 471 } isp_icb_t; 472 #define ICB_VERSION1 1 473 474 #define ICBOPT_HARD_ADDRESS (1<<0) 475 #define ICBOPT_FAIRNESS (1<<1) 476 #define ICBOPT_FULL_DUPLEX (1<<2) 477 #define ICBOPT_FAST_POST (1<<3) 478 #define ICBOPT_TGT_ENABLE (1<<4) 479 #define ICBOPT_INI_DISABLE (1<<5) 480 #define ICBOPT_INI_ADISC (1<<6) 481 #define ICBOPT_INI_TGTTYPE (1<<7) 482 #define ICBOPT_PDBCHANGE_AE (1<<8) 483 #define ICBOPT_NOLIP (1<<9) 484 #define ICBOPT_SRCHDOWN (1<<10) 485 #define ICBOPT_PREVLOOP (1<<11) 486 #define ICBOPT_STOP_ON_QFULL (1<<12) 487 #define ICBOPT_FULL_LOGIN (1<<13) 488 #define ICBOPT_USE_PORTNAME (1<<14) 489 490 491 #define ICB_MIN_FRMLEN 256 492 #define ICB_MAX_FRMLEN 2112 493 #define ICB_DFLT_FRMLEN 1024 494 495 #define RQRSP_ADDR0015 0 496 #define RQRSP_ADDR1631 1 497 #define RQRSP_ADDR3247 2 498 #define RQRSP_ADDR4863 3 499 500 501 #define ICB_NNM0 7 502 #define ICB_NNM1 6 503 #define ICB_NNM2 5 504 #define ICB_NNM3 4 505 #define ICB_NNM4 3 506 #define ICB_NNM5 2 507 #define ICB_NNM6 1 508 #define ICB_NNM7 0 509 510 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 511 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \ 512 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \ 513 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \ 514 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \ 515 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \ 516 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \ 517 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \ 518 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff) 519 520 /* 521 * Target Mode Structures 522 */ 523 #define TGTSVALID 0x80 /* scsi status & sense data valid */ 524 #define SUGGSENSELEN 18 525 526 /* 527 * Structure for Enable Lun and Modify Lun queue entries 528 */ 529 typedef struct { 530 isphdr_t le_header; 531 u_int32_t le_reserved2; 532 #if BYTE_ORDER == BIG_ENDIAN 533 #else 534 u_int8_t le_lun; 535 u_int8_t le_rsvd; 536 u_int8_t le_ops; /* Modify LUN only */ 537 u_int8_t le_tgt; /* Not for FC */ 538 #endif 539 u_int32_t le_flags; /* Not for FC */ 540 #if BYTE_ORDER == BIG_ENDIAN 541 #else 542 u_int8_t le_status; 543 u_int8_t le_rsvd2; 544 u_int8_t le_cmd_count; 545 u_int8_t le_in_count; 546 u_int8_t le_cdb6len; /* Not for FC */ 547 u_int8_t le_cdb7len; /* Not for FC */ 548 #endif 549 u_int16_t le_timeout; 550 u_int16_t le_reserved[20]; 551 } lun_entry_t; 552 553 /* 554 * le_flags values 555 */ 556 #define LUN_TQAE 0x00000001 /* Tagged Queue Action Enable */ 557 #define LUN_DSSM 0x01000000 /* Disable Sending SDP Message */ 558 #define LUN_DM 0x40000000 /* Disconnects Mandatory */ 559 560 /* 561 * le_ops values 562 */ 563 #define LUN_CCINCR 0x01 /* increment command count */ 564 #define LUN_CCDECR 0x02 /* decrement command count */ 565 #define LUN_ININCR 0x40 /* increment immed. notify count */ 566 #define LUN_INDECR 0x80 /* decrement immed. notify count */ 567 568 /* 569 * le_status values 570 */ 571 #define LUN_ERR 0x04 /* request completed with error */ 572 #define LUN_INVAL 0x06 /* invalid request */ 573 #define LUN_NOCAP 0x16 /* can't provide requested capability */ 574 #define LUN_ENABLED 0x3E /* LUN already enabled */ 575 576 /* 577 * Immediate Notify Entry structure 578 */ 579 #define IN_MSGLEN 8 /* 8 bytes */ 580 #define IN_RSVDLEN 8 /* 8 words */ 581 typedef struct { 582 isphdr_t in_header; 583 u_int32_t in_reserved2; 584 #if BYTE_ORDER == BIG_ENDIAN 585 #else 586 u_int8_t in_lun; /* lun */ 587 u_int8_t in_iid; /* initiator */ 588 u_int8_t in_rsvd; 589 u_int8_t in_tgt; /* target */ 590 #endif 591 u_int32_t in_flags; 592 #if BYTE_ORDER == BIG_ENDIAN 593 #else 594 u_int8_t in_status; 595 u_int8_t in_rsvd2; 596 u_int8_t in_tag_val; /* tag value */ 597 u_int8_t in_tag_type; /* tag type */ 598 #endif 599 u_int16_t in_seqid; /* sequence id */ 600 u_int8_t in_msg[IN_MSGLEN]; /* SCSI message bytes */ 601 u_int16_t in_reserved[IN_RSVDLEN]; 602 u_int8_t in_sense[SUGGSENSELEN]; /* suggested sense data */ 603 } in_entry_t; 604 605 typedef struct { 606 isphdr_t in_header; 607 u_int32_t in_reserved2; 608 #if BYTE_ORDER == BIG_ENDIAN 609 #else 610 u_int8_t in_lun; /* lun */ 611 u_int8_t in_iid; /* initiator */ 612 #endif 613 u_int16_t in_rsvd; 614 u_int32_t in_rsvd2; 615 u_int16_t in_status; 616 u_int16_t in_task_flags; 617 u_int16_t in_seqid; /* sequence id */ 618 } in_fcentry_t; 619 620 /* 621 * Values for the in_status field 622 */ 623 #define IN_NO_RCAP 0x16 /* requested capability not available */ 624 #define IN_IDE_RECEIVED 0x33 /* Initiator Detected Error msg received */ 625 #define IN_RSRC_UNAVAIL 0x34 /* resource unavailable */ 626 #define IN_MSG_RECEIVED 0x36 /* SCSI message received */ 627 #define IN_PORT_LOGOUT 0x29 /* port has logged out (FC) */ 628 #define IN_ABORT_TASK 0x20 /* task named in RX_ID is being aborted (FC) */ 629 630 /* 631 * Notify Acknowledge Entry structure 632 */ 633 #define NA_RSVDLEN 22 634 typedef struct { 635 isphdr_t na_header; 636 u_int32_t na_reserved2; 637 #if BYTE_ORDER == BIG_ENDIAN 638 #else 639 u_int8_t na_lun; /* lun */ 640 u_int8_t na_iid; /* initiator */ 641 u_int8_t na_rsvd; 642 u_int8_t na_tgt; /* target */ 643 #endif 644 u_int32_t na_flags; 645 #if BYTE_ORDER == BIG_ENDIAN 646 #else 647 u_int8_t na_status; 648 u_int8_t na_event; 649 #endif 650 u_int16_t na_seqid; /* sequence id */ 651 u_int16_t na_reserved[NA_RSVDLEN]; 652 } na_entry_t; 653 654 /* 655 * Value for the na_event field 656 */ 657 #define NA_RST_CLRD 0x80 /* Clear an async event notification */ 658 659 #define NA2_RSVDLEN 21 660 typedef struct { 661 isphdr_t na_header; 662 u_int32_t na_reserved2; 663 #if BYTE_ORDER == BIG_ENDIAN 664 #else 665 u_int8_t na_lun; /* lun */ 666 u_int8_t na_iid; /* initiator */ 667 #endif 668 u_int16_t na_rsvd; 669 u_int16_t na_flags; 670 u_int16_t na_rsvd2; 671 u_int16_t na_status; 672 u_int16_t na_task_flags; 673 u_int16_t na_seqid; /* sequence id */ 674 u_int16_t na_reserved[NA2_RSVDLEN]; 675 } na_fcentry_t; 676 #define NAFC_RST_CLRD 0x40 677 678 /* 679 * Value for the na_event field 680 */ 681 #define NA_RST_CLRD 0x80 /* Clear an async event notification */ 682 /* 683 * Accept Target I/O Entry structure 684 */ 685 #define ATIO_CDBLEN 26 686 687 typedef struct { 688 isphdr_t at_header; 689 u_int32_t at_reserved2; 690 #if BYTE_ORDER == BIG_ENDIAN 691 #else 692 u_int8_t at_lun; /* lun */ 693 u_int8_t at_iid; /* initiator */ 694 u_int8_t at_cdblen; /* cdb length */ 695 u_int8_t at_tgt; /* target */ 696 #endif 697 u_int32_t at_flags; 698 #if BYTE_ORDER == BIG_ENDIAN 699 #else 700 u_int8_t at_status; /* firmware status */ 701 u_int8_t at_scsi_status; /* scsi status */ 702 u_int8_t at_tag_val; /* tag value */ 703 u_int8_t at_tag_type; /* tag type */ 704 #endif 705 u_int8_t at_cdb[ATIO_CDBLEN]; /* received CDB */ 706 u_int8_t at_sense[SUGGSENSELEN]; /* suggested sense data */ 707 } at_entry_t; 708 709 /* 710 * at_flags values 711 */ 712 #define AT_NODISC 0x00008000 /* disconnect disabled */ 713 #define AT_TQAE 0x00000001 /* Tagged Queue Action enabled */ 714 715 /* 716 * at_status values 717 */ 718 #define AT_PATH_INVALID 0x07 /* ATIO sent to firmware for disabled lun */ 719 #define AT_PHASE_ERROR 0x14 /* Bus phase sequence error */ 720 #define AT_NOCAP 0x16 /* Requested capability not available */ 721 #define AT_BDR_MSG 0x17 /* Bus Device Reset msg received */ 722 #define AT_CDB 0x3D /* CDB received */ 723 724 /* 725 * Accept Target I/O Entry structure, Type 2 726 */ 727 #define ATIO2_CDBLEN 16 728 729 typedef struct { 730 isphdr_t at_header; 731 u_int32_t at_reserved2; 732 #if BYTE_ORDER == BIG_ENDIAN 733 #else 734 u_int8_t at_lun; /* lun */ 735 u_int8_t at_iid; /* initiator */ 736 #endif 737 u_int16_t at_rxid; /* response ID */ 738 u_int16_t at_flags; 739 u_int16_t at_status; /* firmware status */ 740 #if BYTE_ORDER == BIG_ENDIAN 741 #else 742 u_int8_t at_reserved1; 743 u_int8_t at_taskcodes; 744 u_int8_t at_taskflags; 745 u_int8_t at_execodes; 746 #endif 747 u_int8_t at_cdb[ATIO2_CDBLEN]; /* received CDB */ 748 u_int32_t at_datalen; /* allocated data len */ 749 u_int16_t at_scclun; 750 u_int16_t at_reserved3; 751 u_int16_t at_scsi_status; 752 u_int8_t at_sense[SUGGSENSELEN]; /* suggested sense data */ 753 } at2_entry_t; 754 755 #define ATIO2_TC_ATTR_MASK 0x7 756 #define ATIO2_TC_ATTR_SIMPLEQ 0 757 #define ATIO2_TC_ATTR_HEADOFQ 1 758 #define ATIO2_TC_ATTR_ORDERED 2 759 #define ATIO2_TC_ATTR_ACAQ 4 760 #define ATIO2_TC_ATTR_UNTAGGED 5 761 #define TC2TT(code) \ 762 (((code) == ATIO2_TC_ATTR_SIMPLEQ)? 0x20 : \ 763 (((code) == ATIO2_TC_ATTR_HEADOFQ)? 0x21 : \ 764 (((code) == ATIO2_TC_ATTR_ORDERED)? 0x22 : \ 765 (((code) == ATIO2_TC_ATTR_ACAQ)? 0x24 : 0)))) 766 767 768 /* 769 * Continue Target I/O Entry structure 770 * Request from driver. The response from the 771 * ISP firmware is the same except that the last 18 772 * bytes are overwritten by suggested sense data if 773 * the 'autosense valid' bit is set in the status byte. 774 */ 775 typedef struct { 776 isphdr_t ct_header; 777 u_int32_t ct_reserved; 778 #if BYTE_ORDER == BIG_ENDIAN 779 #else 780 u_int8_t ct_lun; /* lun */ 781 u_int8_t ct_iid; /* initiator id */ 782 u_int8_t ct_rsvd; 783 u_int8_t ct_tgt; /* our target id */ 784 #endif 785 u_int32_t ct_flags; 786 #if BYTE_ORDER == BIG_ENDIAN 787 #else 788 u_int8_t ct_status; /* isp status */ 789 u_int8_t ct_scsi_status; /* scsi status */ 790 u_int8_t ct_tag_val; /* tag value */ 791 u_int8_t ct_tag_type; /* tag type */ 792 #endif 793 u_int32_t ct_xfrlen; /* transfer length */ 794 u_int32_t ct_resid; /* residual length */ 795 u_int16_t ct_timeout; 796 u_int16_t ct_seg_count; 797 ispds_t ct_dataseg[ISP_RQDSEG]; 798 } ct_entry_t; 799 800 /* 801 * ct_flags values 802 */ 803 #define CT_TQAE 0x00000001 /* Tagged Queue Action enable */ 804 #define CT_DATA_IN 0x00000040 /* Data direction */ 805 #define CT_DATA_OUT 0x00000080 /* Data direction */ 806 #define CT_NO_DATA 0x000000C0 /* Data direction */ 807 #define CT_DATAMASK 0x000000C0 /* Data direction */ 808 #define CT_NODISC 0x00008000 /* Disconnects disabled */ 809 #define CT_DSDP 0x01000000 /* Disable Save Data Pointers */ 810 #define CT_SENDRDP 0x04000000 /* Send Restore Pointers msg */ 811 #define CT_SENDSTATUS 0x80000000 /* Send SCSI status byte */ 812 813 /* 814 * ct_status values 815 * - set by the firmware when it returns the CTIO 816 */ 817 #define CT_OK 0x01 /* completed without error */ 818 #define CT_ABORTED 0x02 /* aborted by host */ 819 #define CT_ERR 0x04 /* see sense data for error */ 820 #define CT_INVAL 0x06 /* request for disabled lun */ 821 #define CT_NOPATH 0x07 /* invalid ITL nexus */ 822 #define CT_INVRXID 0x08 /* (FC only) Invalid RX_ID */ 823 #define CT_RSELTMO 0x0A /* reselection timeout after 2 tries */ 824 #define CT_TIMEOUT 0x0B /* timed out */ 825 #define CT_RESET 0x0E /* SCSI Bus Reset occurred */ 826 #define CT_PHASE_ERROR 0x14 /* Bus phase sequence error */ 827 #define CT_BDR_MSG 0x17 /* Bus Device Reset msg received */ 828 #define CT_TERMINATED 0x19 /* due to Terminate Transfer mbox cmd */ 829 #define CT_LOGOUT 0x29 /* port logout not acknowledged yet */ 830 #define CT_NOACK 0x35 /* Outstanding Immed. Notify. entry */ 831 832 /* 833 * When the firmware returns a CTIO entry, it may overwrite the last 834 * part of the structure with sense data. This starts at offset 0x2E 835 * into the entry, which is in the middle of ct_dataseg[1]. Rather 836 * than define a new struct for this, I'm just using the sense data 837 * offset. 838 */ 839 #define CTIO_SENSE_OFFSET 0x2E 840 841 /* 842 * Entry length in u_longs. All entries are the same size so 843 * any one will do as the numerator. 844 */ 845 #define UINT32_ENTRY_SIZE (sizeof(at_entry_t)/sizeof(u_int32_t)) 846 847 /* 848 * QLA2100 CTIO (type 2) entry 849 */ 850 #define MAXRESPLEN 26 851 typedef struct { 852 isphdr_t ct_header; 853 u_int32_t ct_reserved; 854 #if BYTE_ORDER == BIG_ENDIAN 855 #else 856 u_int8_t ct_lun; /* lun */ 857 u_int8_t ct_iid; /* initiator id */ 858 #endif 859 u_int16_t ct_rxid; /* response ID */ 860 u_int16_t ct_flags; 861 u_int16_t ct_status; /* isp status */ 862 u_int16_t ct_timeout; 863 u_int16_t ct_seg_count; 864 u_int32_t ct_reloff; /* relative offset */ 865 u_int32_t ct_resid; /* residual length */ 866 union { 867 /* 868 * The three different modes that the target driver 869 * can set the CTIO2 up as. 870 * 871 * The first is for sending FCP_DATA_IUs as well as 872 * (optionally) sending a terminal SCSI status FCP_RSP_IU. 873 * 874 * The second is for sending SCSI sense data in an FCP_RSP_IU. 875 * Note that no FCP_DATA_IUs will be sent. 876 * 877 * The third is for sending FCP_RSP_IUs as built specifically 878 * in system memory as located by the isp_dataseg. 879 */ 880 struct { 881 u_int32_t _reserved; 882 u_int16_t _reserved2; 883 u_int16_t ct_scsi_status; 884 u_int32_t ct_xfrlen; 885 ispds_t ct_dataseg[ISP_RQDSEG_T2]; 886 } m0; 887 struct { 888 u_int16_t _reserved; 889 u_int16_t _reserved2; 890 u_int16_t ct_senselen; 891 u_int16_t ct_scsi_status; 892 u_int16_t ct_resplen; 893 u_int8_t ct_resp[MAXRESPLEN]; 894 } m1; 895 struct { 896 u_int32_t _reserved; 897 u_int16_t _reserved2; 898 u_int16_t _reserved3; 899 u_int32_t ct_datalen; 900 ispds_t ct_fcp_rsp_iudata; 901 } m2; 902 /* 903 * CTIO2 returned from F/W... 904 */ 905 struct { 906 u_int32_t _reserved[4]; 907 u_int16_t ct_scsi_status; 908 u_int8_t ct_sense[SUGGSENSELEN]; 909 } fw; 910 } rsp; 911 } ct2_entry_t; 912 /* 913 * ct_flags values for CTIO2 914 */ 915 #define CT2_FLAG_MMASK 0x0003 916 #define CT2_FLAG_MODE0 0x0000 917 #define CT2_FLAG_MODE1 0x0001 918 #define CT2_FLAG_MODE2 0x0002 919 #define CT2_DATA_IN CT_DATA_IN 920 #define CT2_DATA_OUT CT_DATA_OUT 921 #define CT2_NO_DATA CT_NO_DATA 922 #define CT2_DATAMASK CT_DATA_MASK 923 #define CT2_CCINCR 0x0100 924 #define CT2_FASTPOST 0x0200 925 #define CT2_SENDSTATUS 0x8000 926 927 /* 928 * ct_status values are (mostly) the same as that for ct_entry. 929 */ 930 931 /* 932 * ct_scsi_status values- the low 8 bits are the normal SCSI status 933 * we know and love. The upper 8 bits are validity markers for FCP_RSP_IU 934 * fields. 935 */ 936 #define CT2_RSPLEN_VALID 0x0100 937 #define CT2_SNSLEN_VALID 0x0200 938 #define CT2_DATA_OVER 0x0400 939 #define CT2_DATA_UNDER 0x0800 940 941 #endif /* _ISPMBOX_H */ 942
Indexes created Thu Sep 25 16:09:42 GMT 2025