ispmbox.h revision 1.13
1 /* $NetBSD: ispmbox.h,v 1.13 1999/02/09 00:44:06 mjacob Exp $ */ 2 /* release_02_05_99 */ 3 /* 4 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters. 5 * 6 *--------------------------------------- 7 * Copyright (c) 1997, 1998 by Matthew Jacob 8 * NASA/Ames Research Center 9 * All rights reserved. 10 *--------------------------------------- 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice immediately at the beginning of the file, without modification, 17 * this list of conditions, and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 #ifndef _ISPMBOX_H 38 #define _ISPMBOX_H 39 40 /* 41 * Mailbox Command Opcodes 42 */ 43 44 #define MBOX_NO_OP 0x0000 45 #define MBOX_LOAD_RAM 0x0001 46 #define MBOX_EXEC_FIRMWARE 0x0002 47 #define MBOX_DUMP_RAM 0x0003 48 #define MBOX_WRITE_RAM_WORD 0x0004 49 #define MBOX_READ_RAM_WORD 0x0005 50 #define MBOX_MAILBOX_REG_TEST 0x0006 51 #define MBOX_VERIFY_CHECKSUM 0x0007 52 #define MBOX_ABOUT_FIRMWARE 0x0008 53 /* 9 */ 54 /* a */ 55 /* b */ 56 /* c */ 57 /* d */ 58 #define MBOX_CHECK_FIRMWARE 0x000e 59 /* f */ 60 #define MBOX_INIT_REQ_QUEUE 0x0010 61 #define MBOX_INIT_RES_QUEUE 0x0011 62 #define MBOX_EXECUTE_IOCB 0x0012 63 #define MBOX_WAKE_UP 0x0013 64 #define MBOX_STOP_FIRMWARE 0x0014 65 #define MBOX_ABORT 0x0015 66 #define MBOX_ABORT_DEVICE 0x0016 67 #define MBOX_ABORT_TARGET 0x0017 68 #define MBOX_BUS_RESET 0x0018 69 #define MBOX_STOP_QUEUE 0x0019 70 #define MBOX_START_QUEUE 0x001a 71 #define MBOX_SINGLE_STEP_QUEUE 0x001b 72 #define MBOX_ABORT_QUEUE 0x001c 73 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 74 /* 1e */ 75 #define MBOX_GET_FIRMWARE_STATUS 0x001f 76 #define MBOX_GET_INIT_SCSI_ID 0x0020 77 #define MBOX_GET_SELECT_TIMEOUT 0x0021 78 #define MBOX_GET_RETRY_COUNT 0x0022 79 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 80 #define MBOX_GET_CLOCK_RATE 0x0024 81 #define MBOX_GET_ACT_NEG_STATE 0x0025 82 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 83 #define MBOX_GET_SBUS_PARAMS 0x0027 84 #define MBOX_GET_TARGET_PARAMS 0x0028 85 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 86 /* 2a */ 87 /* 2b */ 88 /* 2c */ 89 /* 2d */ 90 /* 2e */ 91 /* 2f */ 92 #define MBOX_SET_INIT_SCSI_ID 0x0030 93 #define MBOX_SET_SELECT_TIMEOUT 0x0031 94 #define MBOX_SET_RETRY_COUNT 0x0032 95 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 96 #define MBOX_SET_CLOCK_RATE 0x0034 97 #define MBOX_SET_ACTIVE_NEG_STATE 0x0035 98 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 99 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 100 #define MBOX_SET_PCI_PARAMETERS 0x0037 101 #define MBOX_SET_TARGET_PARAMS 0x0038 102 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 103 /* 3a */ 104 /* 3b */ 105 /* 3c */ 106 /* 3d */ 107 /* 3e */ 108 /* 3f */ 109 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 110 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 111 #define MBOX_EXEC_BIOS_IOCB 0x0042 112 #define MBOX_SET_FW_FEATURES 0x004a 113 #define MBOX_GET_FW_FEATURES 0x004b 114 #define FW_FEATURE_LVD_NOTIFY 0x2 115 #define FW_FEATURE_FAST_POST 0x1 116 117 /* These are for the ISP2100 FC cards */ 118 #define MBOX_GET_LOOP_ID 0x20 119 #define MBOX_EXEC_COMMAND_IOCB_A64 0x54 120 #define MBOX_INIT_FIRMWARE 0x60 121 #define MBOX_GET_INIT_CONTROL_BLOCK 0x61 122 #define MBOX_INIT_LIP 0x62 123 #define MBOX_GET_FC_AL_POSITION_MAP 0x63 124 #define MBOX_GET_PORT_DB 0x64 125 #define MBOX_CLEAR_ACA 0x65 126 #define MBOX_TARGET_RESET 0x66 127 #define MBOX_CLEAR_TASK_SET 0x67 128 #define MBOX_ABORT_TASK_SET 0x68 129 #define MBOX_GET_FW_STATE 0x69 130 #define MBOX_GET_LINK_STATUS 0x6a 131 #define MBOX_INIT_LIP_RESET 0x6c 132 #define MBOX_INIT_LIP_LOGIN 0x72 133 134 #define ISP2100_SET_PCI_PARAM 0x00ff 135 136 #define MBOX_BUSY 0x04 137 138 typedef struct { 139 u_int16_t param[8]; 140 } mbreg_t; 141 142 /* 143 * Mailbox Command Complete Status Codes 144 */ 145 #define MBOX_COMMAND_COMPLETE 0x4000 146 #define MBOX_INVALID_COMMAND 0x4001 147 #define MBOX_HOST_INTERFACE_ERROR 0x4002 148 #define MBOX_TEST_FAILED 0x4003 149 #define MBOX_COMMAND_ERROR 0x4005 150 #define MBOX_COMMAND_PARAM_ERROR 0x4006 151 152 /* 153 * Asynchronous event status codes 154 */ 155 #define ASYNC_BUS_RESET 0x8001 156 #define ASYNC_SYSTEM_ERROR 0x8002 157 #define ASYNC_RQS_XFER_ERR 0x8003 158 #define ASYNC_RSP_XFER_ERR 0x8004 159 #define ASYNC_QWAKEUP 0x8005 160 #define ASYNC_TIMEOUT_RESET 0x8006 161 #define ASYNC_DEVICE_RESET 0x8007 162 #define ASYNC_EXTMSG_UNDERRUN 0x800A 163 #define ASYNC_SCAM_INT 0x800B 164 #define ASYNC_HUNG_SCSI 0x800C 165 #define ASYNC_KILLED_BUS 0x800D 166 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 167 #define ASYNC_CMD_CMPLT 0x8020 168 #define ASYNC_CTIO_DONE 0x8021 169 170 /* for ISP2100 only */ 171 #define ASYNC_LIP_OCCURRED 0x8010 172 #define ASYNC_LOOP_UP 0x8011 173 #define ASYNC_LOOP_DOWN 0x8012 174 #define ASYNC_LOOP_RESET 0x8013 175 #define ASYNC_PDB_CHANGED 0x8014 176 #define ASYNC_CHANGE_NOTIFY 0x8015 177 178 /* 179 * Command Structure Definitions 180 */ 181 182 typedef struct { 183 u_int32_t ds_base; 184 u_int32_t ds_count; 185 } ispds_t; 186 187 typedef struct { 188 #if BYTE_ORDER == BIG_ENDIAN 189 u_int8_t rqs_entry_count; 190 u_int8_t rqs_entry_type; 191 u_int8_t rqs_flags; 192 u_int8_t rqs_seqno; 193 #else 194 u_int8_t rqs_entry_type; 195 u_int8_t rqs_entry_count; 196 u_int8_t rqs_seqno; 197 u_int8_t rqs_flags; 198 #endif 199 } isphdr_t; 200 201 /* RQS Flag definitions */ 202 #define RQSFLAG_CONTINUATION 0x01 203 #define RQSFLAG_FULL 0x02 204 #define RQSFLAG_BADHEADER 0x04 205 #define RQSFLAG_BADPACKET 0x08 206 207 /* RQS entry_type definitions */ 208 #define RQSTYPE_REQUEST 0x01 209 #define RQSTYPE_DATASEG 0x02 210 #define RQSTYPE_RESPONSE 0x03 211 #define RQSTYPE_MARKER 0x04 212 #define RQSTYPE_CMDONLY 0x05 213 #define RQSTYPE_ATIO 0x06 /* Target Mode */ 214 #define RQSTYPE_CTIO0 0x07 /* Target Mode */ 215 #define RQSTYPE_SCAM 0x08 216 #define RQSTYPE_A64 0x09 217 #define RQSTYPE_A64_CONT 0x0a 218 #define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */ 219 #define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */ 220 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 221 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 222 #define RQSTYPE_CTIO1 0x0f /* Target Mode */ 223 #define RQSTYPE_STATUS_CONT 0x10 224 #define RQSTYPE_T2RQS 0x11 225 226 #define RQSTYPE_T4RQS 0x15 227 #define RQSTYPE_ATIO2 0x16 228 #define RQSTYPE_CTIO2 0x17 229 #define RQSTYPE_CSET0 0x18 230 #define RQSTYPE_T3RQS 0x19 231 232 #define RQSTYPE_CTIO3 0x1f 233 234 235 #define ISP_RQDSEG 4 236 typedef struct { 237 isphdr_t req_header; 238 u_int32_t req_handle; 239 #if BYTE_ORDER == BIG_ENDIAN 240 u_int8_t req_target; 241 u_int8_t req_lun_trn; 242 #else 243 u_int8_t req_lun_trn; 244 u_int8_t req_target; 245 #endif 246 u_int16_t req_cdblen; 247 #define req_modifier req_cdblen /* marker packet */ 248 u_int16_t req_flags; 249 u_int16_t req_reserved; 250 u_int16_t req_time; 251 u_int16_t req_seg_count; 252 u_int8_t req_cdb[12]; 253 ispds_t req_dataseg[ISP_RQDSEG]; 254 } ispreq_t; 255 256 #define ISP_RQDSEG_T2 3 257 typedef struct { 258 isphdr_t req_header; 259 u_int32_t req_handle; 260 #if BYTE_ORDER == BIG_ENDIAN 261 u_int8_t req_target; 262 u_int8_t req_lun_trn; 263 #else 264 u_int8_t req_lun_trn; 265 u_int8_t req_target; 266 #endif 267 u_int16_t req_scclun; 268 u_int16_t req_flags; 269 u_int16_t _res2; 270 u_int16_t req_time; 271 u_int16_t req_seg_count; 272 u_int32_t req_cdb[4]; 273 u_int32_t req_totalcnt; 274 ispds_t req_dataseg[ISP_RQDSEG_T2]; 275 } ispreqt2_t; 276 277 /* req_flag values */ 278 #define REQFLAG_NODISCON 0x0001 279 #define REQFLAG_HTAG 0x0002 280 #define REQFLAG_OTAG 0x0004 281 #define REQFLAG_STAG 0x0008 282 #define REQFLAG_TARGET_RTN 0x0010 283 284 #define REQFLAG_NODATA 0x0000 285 #define REQFLAG_DATA_IN 0x0020 286 #define REQFLAG_DATA_OUT 0x0040 287 #define REQFLAG_DATA_UNKNOWN 0x0060 288 289 #define REQFLAG_DISARQ 0x0100 290 #define REQFLAG_FRC_ASYNC 0x0200 291 #define REQFLAG_FRC_SYNC 0x0400 292 #define REQFLAG_FRC_WIDE 0x0800 293 #define REQFLAG_NOPARITY 0x1000 294 #define REQFLAG_STOPQ 0x2000 295 #define REQFLAG_XTRASNS 0x4000 296 #define REQFLAG_PRIORITY 0x8000 297 298 typedef struct { 299 isphdr_t req_header; 300 u_int32_t req_handle; 301 #if BYTE_ORDER == BIG_ENDIAN 302 u_int8_t req_target; 303 u_int8_t req_lun_trn; 304 #else 305 u_int8_t req_lun_trn; 306 u_int8_t req_target; 307 #endif 308 u_int16_t req_cdblen; 309 u_int16_t req_flags; 310 u_int16_t _res1; 311 u_int16_t req_time; 312 u_int16_t req_seg_count; 313 u_int8_t req_cdb[44]; 314 } ispextreq_t; 315 316 #define ISP_CDSEG 7 317 typedef struct { 318 isphdr_t req_header; 319 u_int32_t _res1; 320 ispds_t req_dataseg[ISP_CDSEG]; 321 } ispcontreq_t; 322 323 typedef struct { 324 isphdr_t req_header; 325 u_int32_t _res1; 326 #if BYTE_ORDER == BIG_ENDIAN 327 u_int8_t req_target; 328 u_int8_t req_lun_trn; 329 u_int8_t _res2; 330 u_int8_t req_modifier; 331 #else 332 u_int8_t req_lun_trn; 333 u_int8_t req_target; 334 u_int8_t req_modifier; 335 u_int8_t _res2; 336 #endif 337 } ispmarkreq_t; 338 339 #define SYNC_DEVICE 0 340 #define SYNC_TARGET 1 341 #define SYNC_ALL 2 342 343 typedef struct { 344 isphdr_t req_header; 345 u_int32_t req_handle; 346 u_int16_t req_scsi_status; 347 u_int16_t req_completion_status; 348 u_int16_t req_state_flags; 349 u_int16_t req_status_flags; 350 u_int16_t req_time; 351 u_int16_t req_sense_len; 352 u_int32_t req_resid; 353 u_int8_t _res1[8]; 354 u_int8_t req_sense_data[32]; 355 } ispstatusreq_t; 356 357 /* 358 * For Qlogic 2100, the high order byte of SCSI status has 359 * additional meaning. 360 */ 361 #define RQCS_RU 0x800 /* Residual Under */ 362 #define RQCS_RO 0x400 /* Residual Over */ 363 #define RQCS_SV 0x200 /* Sense Length Valid */ 364 #define RQCS_RV 0x100 /* Residual Valid */ 365 366 /* 367 * Completion Status Codes. 368 */ 369 #define RQCS_COMPLETE 0x0000 370 #define RQCS_INCOMPLETE 0x0001 371 #define RQCS_DMA_ERROR 0x0002 372 #define RQCS_TRANSPORT_ERROR 0x0003 373 #define RQCS_RESET_OCCURRED 0x0004 374 #define RQCS_ABORTED 0x0005 375 #define RQCS_TIMEOUT 0x0006 376 #define RQCS_DATA_OVERRUN 0x0007 377 #define RQCS_COMMAND_OVERRUN 0x0008 378 #define RQCS_STATUS_OVERRUN 0x0009 379 #define RQCS_BAD_MESSAGE 0x000a 380 #define RQCS_NO_MESSAGE_OUT 0x000b 381 #define RQCS_EXT_ID_FAILED 0x000c 382 #define RQCS_IDE_MSG_FAILED 0x000d 383 #define RQCS_ABORT_MSG_FAILED 0x000e 384 #define RQCS_REJECT_MSG_FAILED 0x000f 385 #define RQCS_NOP_MSG_FAILED 0x0010 386 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 387 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 388 #define RQCS_ID_MSG_FAILED 0x0013 389 #define RQCS_UNEXP_BUS_FREE 0x0014 390 #define RQCS_DATA_UNDERRUN 0x0015 391 #define RQCS_XACT_ERR1 0x0018 392 #define RQCS_XACT_ERR2 0x0019 393 #define RQCS_XACT_ERR3 0x001A 394 #define RQCS_BAD_ENTRY 0x001B 395 #define RQCS_QUEUE_FULL 0x001C 396 #define RQCS_PHASE_SKIPPED 0x001D 397 #define RQCS_ARQS_FAILED 0x001E 398 #define RQCS_WIDE_FAILED 0x001F 399 #define RQCS_SYNCXFER_FAILED 0x0020 400 #define RQCS_LVD_BUSERR 0x0021 401 402 /* 2100 Only Completion Codes */ 403 #define RQCS_PORT_UNAVAILABLE 0x0028 404 #define RQCS_PORT_LOGGED_OUT 0x0029 405 #define RQCS_PORT_CHANGED 0x002A 406 #define RQCS_PORT_BUSY 0x002B 407 408 /* 409 * State Flags (not applicable to 2100) 410 */ 411 #define RQSF_GOT_BUS 0x0100 412 #define RQSF_GOT_TARGET 0x0200 413 #define RQSF_SENT_CDB 0x0400 414 #define RQSF_XFRD_DATA 0x0800 415 #define RQSF_GOT_STATUS 0x1000 416 #define RQSF_GOT_SENSE 0x2000 417 #define RQSF_XFER_COMPLETE 0x4000 418 419 /* 420 * Status Flags (not applicable to 2100) 421 */ 422 #define RQSTF_DISCONNECT 0x0001 423 #define RQSTF_SYNCHRONOUS 0x0002 424 #define RQSTF_PARITY_ERROR 0x0004 425 #define RQSTF_BUS_RESET 0x0008 426 #define RQSTF_DEVICE_RESET 0x0010 427 #define RQSTF_ABORTED 0x0020 428 #define RQSTF_TIMEOUT 0x0040 429 #define RQSTF_NEGOTIATION 0x0080 430 431 /* 432 * FC (ISP2100) specific initialization data structures 433 */ 434 435 /* 436 * Initialization Control Block 437 * 438 * Version One format. 439 */ 440 typedef struct { 441 #if BYTE_ORDER == BIG_ENDIAN 442 u_int8_t _reserved0; 443 u_int8_t icb_version; 444 #else 445 u_int8_t icb_version; 446 u_int8_t _reserved0; 447 #endif 448 u_int16_t icb_fwoptions; 449 u_int16_t icb_maxfrmlen; 450 u_int16_t icb_maxalloc; 451 u_int16_t icb_execthrottle; 452 #if BYTE_ORDER == BIG_ENDIAN 453 u_int8_t icb_retry_delay; 454 u_int8_t icb_retry_count; 455 #else 456 u_int8_t icb_retry_count; 457 u_int8_t icb_retry_delay; 458 #endif 459 u_int8_t icb_nodename[8]; 460 u_int16_t icb_hardaddr; 461 #if BYTE_ORDER == BIG_ENDIAN 462 u_int8_t _reserved1; 463 u_int8_t icb_iqdevtype; 464 #else 465 u_int8_t icb_iqdevtype; 466 u_int8_t _reserved1; 467 #endif 468 u_int8_t icb_portname[8]; 469 u_int16_t icb_rqstout; 470 u_int16_t icb_rspnsin; 471 u_int16_t icb_rqstqlen; 472 u_int16_t icb_rsltqlen; 473 u_int16_t icb_rqstaddr[4]; 474 u_int16_t icb_respaddr[4]; 475 } isp_icb_t; 476 #define ICB_VERSION1 1 477 478 #define ICBOPT_HARD_ADDRESS (1<<0) 479 #define ICBOPT_FAIRNESS (1<<1) 480 #define ICBOPT_FULL_DUPLEX (1<<2) 481 #define ICBOPT_FAST_POST (1<<3) 482 #define ICBOPT_TGT_ENABLE (1<<4) 483 #define ICBOPT_INI_DISABLE (1<<5) 484 #define ICBOPT_INI_ADISC (1<<6) 485 #define ICBOPT_INI_TGTTYPE (1<<7) 486 #define ICBOPT_PDBCHANGE_AE (1<<8) 487 #define ICBOPT_NOLIP (1<<9) 488 #define ICBOPT_SRCHDOWN (1<<10) 489 #define ICBOPT_PREVLOOP (1<<11) 490 #define ICBOPT_STOP_ON_QFULL (1<<12) 491 #define ICBOPT_FULL_LOGIN (1<<13) 492 #define ICBOPT_USE_PORTNAME (1<<14) 493 494 495 #define ICB_MIN_FRMLEN 256 496 #define ICB_MAX_FRMLEN 2112 497 #define ICB_DFLT_FRMLEN 1024 498 499 #define RQRSP_ADDR0015 0 500 #define RQRSP_ADDR1631 1 501 #define RQRSP_ADDR3247 2 502 #define RQRSP_ADDR4863 3 503 504 505 #define ICB_NNM0 7 506 #define ICB_NNM1 6 507 #define ICB_NNM2 5 508 #define ICB_NNM3 4 509 #define ICB_NNM4 3 510 #define ICB_NNM5 2 511 #define ICB_NNM6 1 512 #define ICB_NNM7 0 513 514 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 515 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \ 516 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \ 517 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \ 518 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \ 519 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \ 520 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \ 521 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \ 522 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff) 523 524 /* 525 * Target Mode Structures 526 */ 527 #define TGTSVALID 0x80 /* scsi status & sense data valid */ 528 #define SUGGSENSELEN 18 529 530 /* 531 * Structure for Enable Lun and Modify Lun queue entries 532 */ 533 typedef struct { 534 isphdr_t le_header; 535 u_int32_t le_reserved2; 536 #if BYTE_ORDER == BIG_ENDIAN 537 #else 538 u_int8_t le_lun; 539 u_int8_t le_rsvd; 540 u_int8_t le_ops; /* Modify LUN only */ 541 u_int8_t le_tgt; /* Not for FC */ 542 #endif 543 u_int32_t le_flags; /* Not for FC */ 544 #if BYTE_ORDER == BIG_ENDIAN 545 #else 546 u_int8_t le_status; 547 u_int8_t le_rsvd2; 548 u_int8_t le_cmd_count; 549 u_int8_t le_in_count; 550 u_int8_t le_cdb6len; /* Not for FC */ 551 u_int8_t le_cdb7len; /* Not for FC */ 552 #endif 553 u_int16_t le_timeout; 554 u_int16_t le_reserved[20]; 555 } lun_entry_t; 556 557 /* 558 * le_flags values 559 */ 560 #define LUN_TQAE 0x00000001 /* Tagged Queue Action Enable */ 561 #define LUN_DSSM 0x01000000 /* Disable Sending SDP Message */ 562 #define LUN_DM 0x40000000 /* Disconnects Mandatory */ 563 564 /* 565 * le_ops values 566 */ 567 #define LUN_CCINCR 0x01 /* increment command count */ 568 #define LUN_CCDECR 0x02 /* decrement command count */ 569 #define LUN_ININCR 0x40 /* increment immed. notify count */ 570 #define LUN_INDECR 0x80 /* decrement immed. notify count */ 571 572 /* 573 * le_status values 574 */ 575 #define LUN_ERR 0x04 /* request completed with error */ 576 #define LUN_INVAL 0x06 /* invalid request */ 577 #define LUN_NOCAP 0x16 /* can't provide requested capability */ 578 #define LUN_ENABLED 0x3E /* LUN already enabled */ 579 580 /* 581 * Immediate Notify Entry structure 582 */ 583 #define IN_MSGLEN 8 /* 8 bytes */ 584 #define IN_RSVDLEN 8 /* 8 words */ 585 typedef struct { 586 isphdr_t in_header; 587 u_int32_t in_reserved2; 588 #if BYTE_ORDER == BIG_ENDIAN 589 #else 590 u_int8_t in_lun; /* lun */ 591 u_int8_t in_iid; /* initiator */ 592 u_int8_t in_rsvd; 593 u_int8_t in_tgt; /* target */ 594 #endif 595 u_int32_t in_flags; 596 #if BYTE_ORDER == BIG_ENDIAN 597 #else 598 u_int8_t in_status; 599 u_int8_t in_rsvd2; 600 u_int8_t in_tag_val; /* tag value */ 601 u_int8_t in_tag_type; /* tag type */ 602 #endif 603 u_int16_t in_seqid; /* sequence id */ 604 u_int8_t in_msg[IN_MSGLEN]; /* SCSI message bytes */ 605 u_int16_t in_reserved[IN_RSVDLEN]; 606 u_int8_t in_sense[SUGGSENSELEN]; /* suggested sense data */ 607 } in_entry_t; 608 609 typedef struct { 610 isphdr_t in_header; 611 u_int32_t in_reserved2; 612 #if BYTE_ORDER == BIG_ENDIAN 613 #else 614 u_int8_t in_lun; /* lun */ 615 u_int8_t in_iid; /* initiator */ 616 #endif 617 u_int16_t in_rsvd; 618 u_int32_t in_rsvd2; 619 u_int16_t in_status; 620 u_int16_t in_task_flags; 621 u_int16_t in_seqid; /* sequence id */ 622 } in_fcentry_t; 623 624 /* 625 * Values for the in_status field 626 */ 627 #define IN_NO_RCAP 0x16 /* requested capability not available */ 628 #define IN_IDE_RECEIVED 0x33 /* Initiator Detected Error msg received */ 629 #define IN_RSRC_UNAVAIL 0x34 /* resource unavailable */ 630 #define IN_MSG_RECEIVED 0x36 /* SCSI message received */ 631 #define IN_PORT_LOGOUT 0x29 /* port has logged out (FC) */ 632 #define IN_ABORT_TASK 0x20 /* task named in RX_ID is being aborted (FC) */ 633 634 /* 635 * Notify Acknowledge Entry structure 636 */ 637 #define NA_RSVDLEN 22 638 typedef struct { 639 isphdr_t na_header; 640 u_int32_t na_reserved2; 641 #if BYTE_ORDER == BIG_ENDIAN 642 #else 643 u_int8_t na_lun; /* lun */ 644 u_int8_t na_iid; /* initiator */ 645 u_int8_t na_rsvd; 646 u_int8_t na_tgt; /* target */ 647 #endif 648 u_int32_t na_flags; 649 #if BYTE_ORDER == BIG_ENDIAN 650 #else 651 u_int8_t na_status; 652 u_int8_t na_event; 653 #endif 654 u_int16_t na_seqid; /* sequence id */ 655 u_int16_t na_reserved[NA_RSVDLEN]; 656 } na_entry_t; 657 658 /* 659 * Value for the na_event field 660 */ 661 #define NA_RST_CLRD 0x80 /* Clear an async event notification */ 662 663 #define NA2_RSVDLEN 21 664 typedef struct { 665 isphdr_t na_header; 666 u_int32_t na_reserved2; 667 #if BYTE_ORDER == BIG_ENDIAN 668 #else 669 u_int8_t na_lun; /* lun */ 670 u_int8_t na_iid; /* initiator */ 671 #endif 672 u_int16_t na_rsvd; 673 u_int16_t na_flags; 674 u_int16_t na_rsvd2; 675 u_int16_t na_status; 676 u_int16_t na_task_flags; 677 u_int16_t na_seqid; /* sequence id */ 678 u_int16_t na_reserved[NA2_RSVDLEN]; 679 } na_fcentry_t; 680 #define NAFC_RST_CLRD 0x40 681 682 /* 683 * Value for the na_event field 684 */ 685 #define NA_RST_CLRD 0x80 /* Clear an async event notification */ 686 /* 687 * Accept Target I/O Entry structure 688 */ 689 #define ATIO_CDBLEN 26 690 691 typedef struct { 692 isphdr_t at_header; 693 u_int32_t at_reserved2; 694 #if BYTE_ORDER == BIG_ENDIAN 695 #else 696 u_int8_t at_lun; /* lun */ 697 u_int8_t at_iid; /* initiator */ 698 u_int8_t at_cdblen; /* cdb length */ 699 u_int8_t at_tgt; /* target */ 700 #endif 701 u_int32_t at_flags; 702 #if BYTE_ORDER == BIG_ENDIAN 703 #else 704 u_int8_t at_status; /* firmware status */ 705 u_int8_t at_scsi_status; /* scsi status */ 706 u_int8_t at_tag_val; /* tag value */ 707 u_int8_t at_tag_type; /* tag type */ 708 #endif 709 u_int8_t at_cdb[ATIO_CDBLEN]; /* received CDB */ 710 u_int8_t at_sense[SUGGSENSELEN]; /* suggested sense data */ 711 } at_entry_t; 712 713 /* 714 * at_flags values 715 */ 716 #define AT_NODISC 0x00008000 /* disconnect disabled */ 717 #define AT_TQAE 0x00000001 /* Tagged Queue Action enabled */ 718 719 /* 720 * at_status values 721 */ 722 #define AT_PATH_INVALID 0x07 /* ATIO sent to firmware for disabled lun */ 723 #define AT_PHASE_ERROR 0x14 /* Bus phase sequence error */ 724 #define AT_NOCAP 0x16 /* Requested capability not available */ 725 #define AT_BDR_MSG 0x17 /* Bus Device Reset msg received */ 726 #define AT_CDB 0x3D /* CDB received */ 727 728 /* 729 * Accept Target I/O Entry structure, Type 2 730 */ 731 #define ATIO2_CDBLEN 16 732 733 typedef struct { 734 isphdr_t at_header; 735 u_int32_t at_reserved2; 736 #if BYTE_ORDER == BIG_ENDIAN 737 #else 738 u_int8_t at_lun; /* lun */ 739 u_int8_t at_iid; /* initiator */ 740 #endif 741 u_int16_t at_rxid; /* response ID */ 742 u_int16_t at_flags; 743 u_int16_t at_status; /* firmware status */ 744 #if BYTE_ORDER == BIG_ENDIAN 745 #else 746 u_int8_t at_reserved1; 747 u_int8_t at_taskcodes; 748 u_int8_t at_taskflags; 749 u_int8_t at_execodes; 750 #endif 751 u_int8_t at_cdb[ATIO2_CDBLEN]; /* received CDB */ 752 u_int32_t at_datalen; /* allocated data len */ 753 u_int16_t at_scclun; 754 u_int16_t at_reserved3; 755 u_int16_t at_scsi_status; 756 u_int8_t at_sense[SUGGSENSELEN]; /* suggested sense data */ 757 } at2_entry_t; 758 759 #define ATIO2_TC_ATTR_MASK 0x7 760 #define ATIO2_TC_ATTR_SIMPLEQ 0 761 #define ATIO2_TC_ATTR_HEADOFQ 1 762 #define ATIO2_TC_ATTR_ORDERED 2 763 #define ATIO2_TC_ATTR_ACAQ 4 764 #define ATIO2_TC_ATTR_UNTAGGED 5 765 #define TC2TT(code) \ 766 (((code) == ATIO2_TC_ATTR_SIMPLEQ)? 0x20 : \ 767 (((code) == ATIO2_TC_ATTR_HEADOFQ)? 0x21 : \ 768 (((code) == ATIO2_TC_ATTR_ORDERED)? 0x22 : \ 769 (((code) == ATIO2_TC_ATTR_ACAQ)? 0x24 : 0)))) 770 771 772 /* 773 * Continue Target I/O Entry structure 774 * Request from driver. The response from the 775 * ISP firmware is the same except that the last 18 776 * bytes are overwritten by suggested sense data if 777 * the 'autosense valid' bit is set in the status byte. 778 */ 779 typedef struct { 780 isphdr_t ct_header; 781 u_int32_t ct_reserved; 782 #if BYTE_ORDER == BIG_ENDIAN 783 #else 784 u_int8_t ct_lun; /* lun */ 785 u_int8_t ct_iid; /* initiator id */ 786 u_int8_t ct_rsvd; 787 u_int8_t ct_tgt; /* our target id */ 788 #endif 789 u_int32_t ct_flags; 790 #if BYTE_ORDER == BIG_ENDIAN 791 #else 792 u_int8_t ct_status; /* isp status */ 793 u_int8_t ct_scsi_status; /* scsi status */ 794 u_int8_t ct_tag_val; /* tag value */ 795 u_int8_t ct_tag_type; /* tag type */ 796 #endif 797 u_int32_t ct_xfrlen; /* transfer length */ 798 u_int32_t ct_resid; /* residual length */ 799 u_int16_t ct_timeout; 800 u_int16_t ct_seg_count; 801 ispds_t ct_dataseg[ISP_RQDSEG]; 802 } ct_entry_t; 803 804 /* 805 * ct_flags values 806 */ 807 #define CT_TQAE 0x00000001 /* Tagged Queue Action enable */ 808 #define CT_DATA_IN 0x00000040 /* Data direction */ 809 #define CT_DATA_OUT 0x00000080 /* Data direction */ 810 #define CT_NO_DATA 0x000000C0 /* Data direction */ 811 #define CT_DATAMASK 0x000000C0 /* Data direction */ 812 #define CT_NODISC 0x00008000 /* Disconnects disabled */ 813 #define CT_DSDP 0x01000000 /* Disable Save Data Pointers */ 814 #define CT_SENDRDP 0x04000000 /* Send Restore Pointers msg */ 815 #define CT_SENDSTATUS 0x80000000 /* Send SCSI status byte */ 816 817 /* 818 * ct_status values 819 * - set by the firmware when it returns the CTIO 820 */ 821 #define CT_OK 0x01 /* completed without error */ 822 #define CT_ABORTED 0x02 /* aborted by host */ 823 #define CT_ERR 0x04 /* see sense data for error */ 824 #define CT_INVAL 0x06 /* request for disabled lun */ 825 #define CT_NOPATH 0x07 /* invalid ITL nexus */ 826 #define CT_INVRXID 0x08 /* (FC only) Invalid RX_ID */ 827 #define CT_RSELTMO 0x0A /* reselection timeout after 2 tries */ 828 #define CT_TIMEOUT 0x0B /* timed out */ 829 #define CT_RESET 0x0E /* SCSI Bus Reset occurred */ 830 #define CT_PHASE_ERROR 0x14 /* Bus phase sequence error */ 831 #define CT_BDR_MSG 0x17 /* Bus Device Reset msg received */ 832 #define CT_TERMINATED 0x19 /* due to Terminate Transfer mbox cmd */ 833 #define CT_LOGOUT 0x29 /* port logout not acknowledged yet */ 834 #define CT_NOACK 0x35 /* Outstanding Immed. Notify. entry */ 835 836 /* 837 * When the firmware returns a CTIO entry, it may overwrite the last 838 * part of the structure with sense data. This starts at offset 0x2E 839 * into the entry, which is in the middle of ct_dataseg[1]. Rather 840 * than define a new struct for this, I'm just using the sense data 841 * offset. 842 */ 843 #define CTIO_SENSE_OFFSET 0x2E 844 845 /* 846 * Entry length in u_longs. All entries are the same size so 847 * any one will do as the numerator. 848 */ 849 #define UINT32_ENTRY_SIZE (sizeof(at_entry_t)/sizeof(u_int32_t)) 850 851 /* 852 * QLA2100 CTIO (type 2) entry 853 */ 854 #define MAXRESPLEN 26 855 typedef struct { 856 isphdr_t ct_header; 857 u_int32_t ct_reserved; 858 #if BYTE_ORDER == BIG_ENDIAN 859 #else 860 u_int8_t ct_lun; /* lun */ 861 u_int8_t ct_iid; /* initiator id */ 862 #endif 863 u_int16_t ct_rxid; /* response ID */ 864 u_int16_t ct_flags; 865 u_int16_t ct_status; /* isp status */ 866 u_int16_t ct_timeout; 867 u_int16_t ct_seg_count; 868 u_int32_t ct_reloff; /* relative offset */ 869 u_int32_t ct_resid; /* residual length */ 870 union { 871 /* 872 * The three different modes that the target driver 873 * can set the CTIO2 up as. 874 * 875 * The first is for sending FCP_DATA_IUs as well as 876 * (optionally) sending a terminal SCSI status FCP_RSP_IU. 877 * 878 * The second is for sending SCSI sense data in an FCP_RSP_IU. 879 * Note that no FCP_DATA_IUs will be sent. 880 * 881 * The third is for sending FCP_RSP_IUs as built specifically 882 * in system memory as located by the isp_dataseg. 883 */ 884 struct { 885 u_int32_t _reserved; 886 u_int16_t _reserved2; 887 u_int16_t ct_scsi_status; 888 u_int32_t ct_xfrlen; 889 ispds_t ct_dataseg[ISP_RQDSEG_T2]; 890 } m0; 891 struct { 892 u_int16_t _reserved; 893 u_int16_t _reserved2; 894 u_int16_t ct_senselen; 895 u_int16_t ct_scsi_status; 896 u_int16_t ct_resplen; 897 u_int8_t ct_resp[MAXRESPLEN]; 898 } m1; 899 struct { 900 u_int32_t _reserved; 901 u_int16_t _reserved2; 902 u_int16_t _reserved3; 903 u_int32_t ct_datalen; 904 ispds_t ct_fcp_rsp_iudata; 905 } m2; 906 /* 907 * CTIO2 returned from F/W... 908 */ 909 struct { 910 u_int32_t _reserved[4]; 911 u_int16_t ct_scsi_status; 912 u_int8_t ct_sense[SUGGSENSELEN]; 913 } fw; 914 } rsp; 915 } ct2_entry_t; 916 /* 917 * ct_flags values for CTIO2 918 */ 919 #define CT2_FLAG_MMASK 0x0003 920 #define CT2_FLAG_MODE0 0x0000 921 #define CT2_FLAG_MODE1 0x0001 922 #define CT2_FLAG_MODE2 0x0002 923 #define CT2_DATA_IN CT_DATA_IN 924 #define CT2_DATA_OUT CT_DATA_OUT 925 #define CT2_NO_DATA CT_NO_DATA 926 #define CT2_DATAMASK CT_DATA_MASK 927 #define CT2_CCINCR 0x0100 928 #define CT2_FASTPOST 0x0200 929 #define CT2_SENDSTATUS 0x8000 930 931 /* 932 * ct_status values are (mostly) the same as that for ct_entry. 933 */ 934 935 /* 936 * ct_scsi_status values- the low 8 bits are the normal SCSI status 937 * we know and love. The upper 8 bits are validity markers for FCP_RSP_IU 938 * fields. 939 */ 940 #define CT2_RSPLEN_VALID 0x0100 941 #define CT2_SNSLEN_VALID 0x0200 942 #define CT2_DATA_OVER 0x0400 943 #define CT2_DATA_UNDER 0x0800 944 945 #endif /* _ISPMBOX_H */ 946
Indexes created Fri Oct 31 11:10:07 GMT 2025