ispmbox.h revision 1.14
1 /* $NetBSD: ispmbox.h,v 1.14 1999/03/17 06:15:48 mjacob Exp $ */ 2 /* release_03_16_99 */ 3 /* 4 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters. 5 * 6 *--------------------------------------- 7 * Copyright (c) 1997, 1998 by Matthew Jacob 8 * NASA/Ames Research Center 9 * All rights reserved. 10 *--------------------------------------- 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice immediately at the beginning of the file, without modification, 17 * this list of conditions, and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 #ifndef _ISPMBOX_H 38 #define _ISPMBOX_H 39 40 /* 41 * Mailbox Command Opcodes 42 */ 43 44 #define MBOX_NO_OP 0x0000 45 #define MBOX_LOAD_RAM 0x0001 46 #define MBOX_EXEC_FIRMWARE 0x0002 47 #define MBOX_DUMP_RAM 0x0003 48 #define MBOX_WRITE_RAM_WORD 0x0004 49 #define MBOX_READ_RAM_WORD 0x0005 50 #define MBOX_MAILBOX_REG_TEST 0x0006 51 #define MBOX_VERIFY_CHECKSUM 0x0007 52 #define MBOX_ABOUT_FIRMWARE 0x0008 53 /* 9 */ 54 /* a */ 55 /* b */ 56 /* c */ 57 /* d */ 58 #define MBOX_CHECK_FIRMWARE 0x000e 59 /* f */ 60 #define MBOX_INIT_REQ_QUEUE 0x0010 61 #define MBOX_INIT_RES_QUEUE 0x0011 62 #define MBOX_EXECUTE_IOCB 0x0012 63 #define MBOX_WAKE_UP 0x0013 64 #define MBOX_STOP_FIRMWARE 0x0014 65 #define MBOX_ABORT 0x0015 66 #define MBOX_ABORT_DEVICE 0x0016 67 #define MBOX_ABORT_TARGET 0x0017 68 #define MBOX_BUS_RESET 0x0018 69 #define MBOX_STOP_QUEUE 0x0019 70 #define MBOX_START_QUEUE 0x001a 71 #define MBOX_SINGLE_STEP_QUEUE 0x001b 72 #define MBOX_ABORT_QUEUE 0x001c 73 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 74 /* 1e */ 75 #define MBOX_GET_FIRMWARE_STATUS 0x001f 76 #define MBOX_GET_INIT_SCSI_ID 0x0020 77 #define MBOX_GET_SELECT_TIMEOUT 0x0021 78 #define MBOX_GET_RETRY_COUNT 0x0022 79 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 80 #define MBOX_GET_CLOCK_RATE 0x0024 81 #define MBOX_GET_ACT_NEG_STATE 0x0025 82 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 83 #define MBOX_GET_SBUS_PARAMS 0x0027 84 #define MBOX_GET_TARGET_PARAMS 0x0028 85 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 86 /* 2a */ 87 /* 2b */ 88 /* 2c */ 89 /* 2d */ 90 /* 2e */ 91 /* 2f */ 92 #define MBOX_SET_INIT_SCSI_ID 0x0030 93 #define MBOX_SET_SELECT_TIMEOUT 0x0031 94 #define MBOX_SET_RETRY_COUNT 0x0032 95 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 96 #define MBOX_SET_CLOCK_RATE 0x0034 97 #define MBOX_SET_ACTIVE_NEG_STATE 0x0035 98 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 99 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 100 #define MBOX_SET_PCI_PARAMETERS 0x0037 101 #define MBOX_SET_TARGET_PARAMS 0x0038 102 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 103 /* 3a */ 104 /* 3b */ 105 /* 3c */ 106 /* 3d */ 107 /* 3e */ 108 /* 3f */ 109 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 110 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 111 #define MBOX_EXEC_BIOS_IOCB 0x0042 112 #define MBOX_SET_FW_FEATURES 0x004a 113 #define MBOX_GET_FW_FEATURES 0x004b 114 #define FW_FEATURE_LVD_NOTIFY 0x2 115 #define FW_FEATURE_FAST_POST 0x1 116 117 /* These are for the ISP2100 FC cards */ 118 #define MBOX_GET_LOOP_ID 0x20 119 #define MBOX_EXEC_COMMAND_IOCB_A64 0x54 120 #define MBOX_INIT_FIRMWARE 0x60 121 #define MBOX_GET_INIT_CONTROL_BLOCK 0x61 122 #define MBOX_INIT_LIP 0x62 123 #define MBOX_GET_FC_AL_POSITION_MAP 0x63 124 #define MBOX_GET_PORT_DB 0x64 125 #define MBOX_CLEAR_ACA 0x65 126 #define MBOX_TARGET_RESET 0x66 127 #define MBOX_CLEAR_TASK_SET 0x67 128 #define MBOX_ABORT_TASK_SET 0x68 129 #define MBOX_GET_FW_STATE 0x69 130 #define MBOX_GET_PORT_NAME 0x6a 131 #define MBOX_GET_LINK_STATUS 0x6b 132 #define MBOX_INIT_LIP_RESET 0x6c 133 #define MBOX_INIT_LIP_LOGIN 0x72 134 135 #define ISP2100_SET_PCI_PARAM 0x00ff 136 137 #define MBOX_BUSY 0x04 138 139 typedef struct { 140 u_int16_t param[8]; 141 } mbreg_t; 142 143 /* 144 * Mailbox Command Complete Status Codes 145 */ 146 #define MBOX_COMMAND_COMPLETE 0x4000 147 #define MBOX_INVALID_COMMAND 0x4001 148 #define MBOX_HOST_INTERFACE_ERROR 0x4002 149 #define MBOX_TEST_FAILED 0x4003 150 #define MBOX_COMMAND_ERROR 0x4005 151 #define MBOX_COMMAND_PARAM_ERROR 0x4006 152 153 /* 154 * Asynchronous event status codes 155 */ 156 #define ASYNC_BUS_RESET 0x8001 157 #define ASYNC_SYSTEM_ERROR 0x8002 158 #define ASYNC_RQS_XFER_ERR 0x8003 159 #define ASYNC_RSP_XFER_ERR 0x8004 160 #define ASYNC_QWAKEUP 0x8005 161 #define ASYNC_TIMEOUT_RESET 0x8006 162 #define ASYNC_DEVICE_RESET 0x8007 163 #define ASYNC_EXTMSG_UNDERRUN 0x800A 164 #define ASYNC_SCAM_INT 0x800B 165 #define ASYNC_HUNG_SCSI 0x800C 166 #define ASYNC_KILLED_BUS 0x800D 167 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 168 #define ASYNC_CMD_CMPLT 0x8020 169 #define ASYNC_CTIO_DONE 0x8021 170 171 /* for ISP2100 only */ 172 #define ASYNC_LIP_OCCURRED 0x8010 173 #define ASYNC_LOOP_UP 0x8011 174 #define ASYNC_LOOP_DOWN 0x8012 175 #define ASYNC_LOOP_RESET 0x8013 176 #define ASYNC_PDB_CHANGED 0x8014 177 #define ASYNC_CHANGE_NOTIFY 0x8015 178 179 /* 180 * Command Structure Definitions 181 */ 182 183 typedef struct { 184 u_int32_t ds_base; 185 u_int32_t ds_count; 186 } ispds_t; 187 188 typedef struct { 189 #if BYTE_ORDER == BIG_ENDIAN 190 u_int8_t rqs_entry_count; 191 u_int8_t rqs_entry_type; 192 u_int8_t rqs_flags; 193 u_int8_t rqs_seqno; 194 #else 195 u_int8_t rqs_entry_type; 196 u_int8_t rqs_entry_count; 197 u_int8_t rqs_seqno; 198 u_int8_t rqs_flags; 199 #endif 200 } isphdr_t; 201 202 /* RQS Flag definitions */ 203 #define RQSFLAG_CONTINUATION 0x01 204 #define RQSFLAG_FULL 0x02 205 #define RQSFLAG_BADHEADER 0x04 206 #define RQSFLAG_BADPACKET 0x08 207 208 /* RQS entry_type definitions */ 209 #define RQSTYPE_REQUEST 0x01 210 #define RQSTYPE_DATASEG 0x02 211 #define RQSTYPE_RESPONSE 0x03 212 #define RQSTYPE_MARKER 0x04 213 #define RQSTYPE_CMDONLY 0x05 214 #define RQSTYPE_ATIO 0x06 /* Target Mode */ 215 #define RQSTYPE_CTIO0 0x07 /* Target Mode */ 216 #define RQSTYPE_SCAM 0x08 217 #define RQSTYPE_A64 0x09 218 #define RQSTYPE_A64_CONT 0x0a 219 #define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */ 220 #define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */ 221 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 222 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 223 #define RQSTYPE_CTIO1 0x0f /* Target Mode */ 224 #define RQSTYPE_STATUS_CONT 0x10 225 #define RQSTYPE_T2RQS 0x11 226 227 #define RQSTYPE_T4RQS 0x15 228 #define RQSTYPE_ATIO2 0x16 229 #define RQSTYPE_CTIO2 0x17 230 #define RQSTYPE_CSET0 0x18 231 #define RQSTYPE_T3RQS 0x19 232 233 #define RQSTYPE_CTIO3 0x1f 234 235 236 #define ISP_RQDSEG 4 237 typedef struct { 238 isphdr_t req_header; 239 u_int32_t req_handle; 240 #if BYTE_ORDER == BIG_ENDIAN 241 u_int8_t req_target; 242 u_int8_t req_lun_trn; 243 #else 244 u_int8_t req_lun_trn; 245 u_int8_t req_target; 246 #endif 247 u_int16_t req_cdblen; 248 #define req_modifier req_cdblen /* marker packet */ 249 u_int16_t req_flags; 250 u_int16_t req_reserved; 251 u_int16_t req_time; 252 u_int16_t req_seg_count; 253 u_int8_t req_cdb[12]; 254 ispds_t req_dataseg[ISP_RQDSEG]; 255 } ispreq_t; 256 257 #define ISP_RQDSEG_T2 3 258 typedef struct { 259 isphdr_t req_header; 260 u_int32_t req_handle; 261 #if BYTE_ORDER == BIG_ENDIAN 262 u_int8_t req_target; 263 u_int8_t req_lun_trn; 264 #else 265 u_int8_t req_lun_trn; 266 u_int8_t req_target; 267 #endif 268 u_int16_t req_scclun; 269 u_int16_t req_flags; 270 u_int16_t _res2; 271 u_int16_t req_time; 272 u_int16_t req_seg_count; 273 u_int32_t req_cdb[4]; 274 u_int32_t req_totalcnt; 275 ispds_t req_dataseg[ISP_RQDSEG_T2]; 276 } ispreqt2_t; 277 278 /* req_flag values */ 279 #define REQFLAG_NODISCON 0x0001 280 #define REQFLAG_HTAG 0x0002 281 #define REQFLAG_OTAG 0x0004 282 #define REQFLAG_STAG 0x0008 283 #define REQFLAG_TARGET_RTN 0x0010 284 285 #define REQFLAG_NODATA 0x0000 286 #define REQFLAG_DATA_IN 0x0020 287 #define REQFLAG_DATA_OUT 0x0040 288 #define REQFLAG_DATA_UNKNOWN 0x0060 289 290 #define REQFLAG_DISARQ 0x0100 291 #define REQFLAG_FRC_ASYNC 0x0200 292 #define REQFLAG_FRC_SYNC 0x0400 293 #define REQFLAG_FRC_WIDE 0x0800 294 #define REQFLAG_NOPARITY 0x1000 295 #define REQFLAG_STOPQ 0x2000 296 #define REQFLAG_XTRASNS 0x4000 297 #define REQFLAG_PRIORITY 0x8000 298 299 typedef struct { 300 isphdr_t req_header; 301 u_int32_t req_handle; 302 #if BYTE_ORDER == BIG_ENDIAN 303 u_int8_t req_target; 304 u_int8_t req_lun_trn; 305 #else 306 u_int8_t req_lun_trn; 307 u_int8_t req_target; 308 #endif 309 u_int16_t req_cdblen; 310 u_int16_t req_flags; 311 u_int16_t _res1; 312 u_int16_t req_time; 313 u_int16_t req_seg_count; 314 u_int8_t req_cdb[44]; 315 } ispextreq_t; 316 317 #define ISP_CDSEG 7 318 typedef struct { 319 isphdr_t req_header; 320 u_int32_t _res1; 321 ispds_t req_dataseg[ISP_CDSEG]; 322 } ispcontreq_t; 323 324 typedef struct { 325 isphdr_t req_header; 326 u_int32_t _res1; 327 #if BYTE_ORDER == BIG_ENDIAN 328 u_int8_t req_target; 329 u_int8_t req_lun_trn; 330 u_int8_t _res2; 331 u_int8_t req_modifier; 332 #else 333 u_int8_t req_lun_trn; 334 u_int8_t req_target; 335 u_int8_t req_modifier; 336 u_int8_t _res2; 337 #endif 338 } ispmarkreq_t; 339 340 #define SYNC_DEVICE 0 341 #define SYNC_TARGET 1 342 #define SYNC_ALL 2 343 344 typedef struct { 345 isphdr_t req_header; 346 u_int32_t req_handle; 347 u_int16_t req_scsi_status; 348 u_int16_t req_completion_status; 349 u_int16_t req_state_flags; 350 u_int16_t req_status_flags; 351 u_int16_t req_time; 352 u_int16_t req_sense_len; 353 u_int32_t req_resid; 354 u_int8_t _res1[8]; 355 u_int8_t req_sense_data[32]; 356 } ispstatusreq_t; 357 358 /* 359 * For Qlogic 2100, the high order byte of SCSI status has 360 * additional meaning. 361 */ 362 #define RQCS_RU 0x800 /* Residual Under */ 363 #define RQCS_RO 0x400 /* Residual Over */ 364 #define RQCS_SV 0x200 /* Sense Length Valid */ 365 #define RQCS_RV 0x100 /* Residual Valid */ 366 367 /* 368 * Completion Status Codes. 369 */ 370 #define RQCS_COMPLETE 0x0000 371 #define RQCS_INCOMPLETE 0x0001 372 #define RQCS_DMA_ERROR 0x0002 373 #define RQCS_TRANSPORT_ERROR 0x0003 374 #define RQCS_RESET_OCCURRED 0x0004 375 #define RQCS_ABORTED 0x0005 376 #define RQCS_TIMEOUT 0x0006 377 #define RQCS_DATA_OVERRUN 0x0007 378 #define RQCS_COMMAND_OVERRUN 0x0008 379 #define RQCS_STATUS_OVERRUN 0x0009 380 #define RQCS_BAD_MESSAGE 0x000a 381 #define RQCS_NO_MESSAGE_OUT 0x000b 382 #define RQCS_EXT_ID_FAILED 0x000c 383 #define RQCS_IDE_MSG_FAILED 0x000d 384 #define RQCS_ABORT_MSG_FAILED 0x000e 385 #define RQCS_REJECT_MSG_FAILED 0x000f 386 #define RQCS_NOP_MSG_FAILED 0x0010 387 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 388 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 389 #define RQCS_ID_MSG_FAILED 0x0013 390 #define RQCS_UNEXP_BUS_FREE 0x0014 391 #define RQCS_DATA_UNDERRUN 0x0015 392 #define RQCS_XACT_ERR1 0x0018 393 #define RQCS_XACT_ERR2 0x0019 394 #define RQCS_XACT_ERR3 0x001A 395 #define RQCS_BAD_ENTRY 0x001B 396 #define RQCS_QUEUE_FULL 0x001C 397 #define RQCS_PHASE_SKIPPED 0x001D 398 #define RQCS_ARQS_FAILED 0x001E 399 #define RQCS_WIDE_FAILED 0x001F 400 #define RQCS_SYNCXFER_FAILED 0x0020 401 #define RQCS_LVD_BUSERR 0x0021 402 403 /* 2100 Only Completion Codes */ 404 #define RQCS_PORT_UNAVAILABLE 0x0028 405 #define RQCS_PORT_LOGGED_OUT 0x0029 406 #define RQCS_PORT_CHANGED 0x002A 407 #define RQCS_PORT_BUSY 0x002B 408 409 /* 410 * State Flags (not applicable to 2100) 411 */ 412 #define RQSF_GOT_BUS 0x0100 413 #define RQSF_GOT_TARGET 0x0200 414 #define RQSF_SENT_CDB 0x0400 415 #define RQSF_XFRD_DATA 0x0800 416 #define RQSF_GOT_STATUS 0x1000 417 #define RQSF_GOT_SENSE 0x2000 418 #define RQSF_XFER_COMPLETE 0x4000 419 420 /* 421 * Status Flags (not applicable to 2100) 422 */ 423 #define RQSTF_DISCONNECT 0x0001 424 #define RQSTF_SYNCHRONOUS 0x0002 425 #define RQSTF_PARITY_ERROR 0x0004 426 #define RQSTF_BUS_RESET 0x0008 427 #define RQSTF_DEVICE_RESET 0x0010 428 #define RQSTF_ABORTED 0x0020 429 #define RQSTF_TIMEOUT 0x0040 430 #define RQSTF_NEGOTIATION 0x0080 431 432 /* 433 * FC (ISP2100) specific data structures 434 */ 435 436 /* 437 * Initialization Control Block 438 * 439 * Version One format. 440 */ 441 typedef struct { 442 #if BYTE_ORDER == BIG_ENDIAN 443 u_int8_t _reserved0; 444 u_int8_t icb_version; 445 #else 446 u_int8_t icb_version; 447 u_int8_t _reserved0; 448 #endif 449 u_int16_t icb_fwoptions; 450 u_int16_t icb_maxfrmlen; 451 u_int16_t icb_maxalloc; 452 u_int16_t icb_execthrottle; 453 #if BYTE_ORDER == BIG_ENDIAN 454 u_int8_t icb_retry_delay; 455 u_int8_t icb_retry_count; 456 #else 457 u_int8_t icb_retry_count; 458 u_int8_t icb_retry_delay; 459 #endif 460 u_int8_t icb_nodename[8]; 461 u_int16_t icb_hardaddr; 462 #if BYTE_ORDER == BIG_ENDIAN 463 u_int8_t _reserved1; 464 u_int8_t icb_iqdevtype; 465 #else 466 u_int8_t icb_iqdevtype; 467 u_int8_t _reserved1; 468 #endif 469 u_int8_t icb_portname[8]; 470 u_int16_t icb_rqstout; 471 u_int16_t icb_rspnsin; 472 u_int16_t icb_rqstqlen; 473 u_int16_t icb_rsltqlen; 474 u_int16_t icb_rqstaddr[4]; 475 u_int16_t icb_respaddr[4]; 476 } isp_icb_t; 477 #define ICB_VERSION1 1 478 479 #define ICBOPT_HARD_ADDRESS (1<<0) 480 #define ICBOPT_FAIRNESS (1<<1) 481 #define ICBOPT_FULL_DUPLEX (1<<2) 482 #define ICBOPT_FAST_POST (1<<3) 483 #define ICBOPT_TGT_ENABLE (1<<4) 484 #define ICBOPT_INI_DISABLE (1<<5) 485 #define ICBOPT_INI_ADISC (1<<6) 486 #define ICBOPT_INI_TGTTYPE (1<<7) 487 #define ICBOPT_PDBCHANGE_AE (1<<8) 488 #define ICBOPT_NOLIP (1<<9) 489 #define ICBOPT_SRCHDOWN (1<<10) 490 #define ICBOPT_PREVLOOP (1<<11) 491 #define ICBOPT_STOP_ON_QFULL (1<<12) 492 #define ICBOPT_FULL_LOGIN (1<<13) 493 #define ICBOPT_USE_PORTNAME (1<<14) 494 495 496 #define ICB_MIN_FRMLEN 256 497 #define ICB_MAX_FRMLEN 2112 498 #define ICB_DFLT_FRMLEN 1024 499 500 #define RQRSP_ADDR0015 0 501 #define RQRSP_ADDR1631 1 502 #define RQRSP_ADDR3247 2 503 #define RQRSP_ADDR4863 3 504 505 506 #define ICB_NNM0 7 507 #define ICB_NNM1 6 508 #define ICB_NNM2 5 509 #define ICB_NNM3 4 510 #define ICB_NNM4 3 511 #define ICB_NNM5 2 512 #define ICB_NNM6 1 513 #define ICB_NNM7 0 514 515 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 516 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \ 517 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \ 518 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \ 519 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \ 520 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \ 521 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \ 522 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \ 523 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff) 524 525 /* 526 * Port Data Base Element 527 */ 528 529 typedef struct { 530 u_int16_t pdb_options; 531 #if BYTE_ORDER == BIG_ENDIAN 532 u_int8_t pdb_sstate; 533 u_int8_t pdb_mstate; 534 #else 535 u_int8_t pdb_mstate; 536 u_int8_t pdb_sstate; 537 #endif 538 #if BYTE_ORDER == BIG_ENDIAN 539 #define BITS2WORD(x) \ 540 (x)[1] << 16 | (x)[2] << 8 | (x)[3] 541 #else 542 #define BITS2WORD(x) \ 543 (x)[0] << 16 | (x)[3] << 8 | (x)[2] 544 #endif 545 u_int8_t pdb_hardaddr_bits[4]; 546 u_int8_t pdb_portid_bits[4]; 547 u_int8_t pdb_nodename[8]; 548 u_int8_t pdb_portname[8]; 549 u_int16_t pdb_execthrottle; 550 u_int16_t pdb_exec_count; 551 #if BYTE_ORDER == BIG_ENDIAN 552 u_int8_t pdb_retry_delay; 553 u_int8_t pdb_retry_count; 554 #else 555 u_int8_t pdb_retry_count; 556 u_int8_t pdb_retry_delay; 557 #endif 558 u_int16_t pdb_resalloc; 559 u_int16_t pdb_curalloc; 560 u_int16_t pdb_qhead; 561 u_int16_t pdb_qtail; 562 u_int16_t pdb_tl_next; 563 u_int16_t pdb_tl_last; 564 u_int16_t pdb_features; /* PLOGI, Common Service */ 565 u_int16_t pdb_pconcurrnt; /* PLOGI, Common Service */ 566 u_int16_t pdb_roi; /* PLOGI, Common Service */ 567 #if BYTE_ORDER == BIG_ENDIAN 568 u_int8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */ 569 u_int8_t pdb_target; 570 #else 571 u_int8_t pdb_target; 572 u_int8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */ 573 #endif 574 u_int16_t pdb_rdsiz; /* PLOGI, Class 3 */ 575 u_int16_t pdb_ncseq; /* PLOGI, Class 3 */ 576 u_int16_t pdb_noseq; /* PLOGI, Class 3 */ 577 u_int16_t pdb_labrtflg; 578 u_int16_t pdb_lstopflg; 579 u_int16_t pdb_sqhead; 580 u_int16_t pdb_sqtail; 581 u_int16_t pdb_ptimer; 582 u_int16_t pdb_nxt_seqid; 583 u_int16_t pdb_fcount; 584 u_int16_t pdb_prli_len; 585 u_int16_t pdb_prli_svc0; 586 u_int16_t pdb_prli_svc3; 587 u_int16_t pdb_loopid; 588 u_int16_t pdb_il_ptr; 589 u_int16_t pdb_sl_ptr; 590 } isp_pdb_t; 591 592 #define INVALID_PDB_OPTIONS 0xDEAD 593 594 #define PDB_OPTIONS_XMITTING (1<<11) 595 #define PDB_OPTIONS_LNKXMIT (1<<10) 596 #define PDB_OPTIONS_ABORTED (1<<9) 597 #define PDB_OPTIONS_ADISC (1<<1) 598 599 #define PDB_STATE_DISCOVERY 0 600 #define PDB_STATE_WDISC_ACK 1 601 #define PDB_STATE_PLOGI 2 602 #define PDB_STATE_PLOGI_ACK 3 603 #define PDB_STATE_PRLI 4 604 #define PDB_STATE_PRLI_ACK 5 605 #define PDB_STATE_LOGGED_IN 6 606 #define PDB_STATE_PORT_UNAVAIL 7 607 #define PDB_STATE_PRLO 8 608 #define PDB_STATE_PRLO_ACK 9 609 #define PDB_STATE_PLOGO 10 610 #define PDB_STATE_PLOG_ACK 11 611 612 #define SVC3_TGT_ROLE 0x10 613 #define SVC3_INI_ROLE 0x20 614 #define SVC3_ROLE_MASK 0x30 615 616 /* 617 * Target Mode Structures 618 */ 619 #define TGTSVALID 0x80 /* scsi status & sense data valid */ 620 #define SUGGSENSELEN 18 621 622 /* 623 * Structure for Enable Lun and Modify Lun queue entries 624 */ 625 typedef struct { 626 isphdr_t le_header; 627 u_int32_t le_reserved2; 628 #if BYTE_ORDER == BIG_ENDIAN 629 #else 630 u_int8_t le_lun; 631 u_int8_t le_rsvd; 632 u_int8_t le_ops; /* Modify LUN only */ 633 u_int8_t le_tgt; /* Not for FC */ 634 #endif 635 u_int32_t le_flags; /* Not for FC */ 636 #if BYTE_ORDER == BIG_ENDIAN 637 #else 638 u_int8_t le_status; 639 u_int8_t le_rsvd2; 640 u_int8_t le_cmd_count; 641 u_int8_t le_in_count; 642 u_int8_t le_cdb6len; /* Not for FC */ 643 u_int8_t le_cdb7len; /* Not for FC */ 644 #endif 645 u_int16_t le_timeout; 646 u_int16_t le_reserved[20]; 647 } lun_entry_t; 648 649 /* 650 * le_flags values 651 */ 652 #define LUN_TQAE 0x00000001 /* Tagged Queue Action Enable */ 653 #define LUN_DSSM 0x01000000 /* Disable Sending SDP Message */ 654 #define LUN_DM 0x40000000 /* Disconnects Mandatory */ 655 656 /* 657 * le_ops values 658 */ 659 #define LUN_CCINCR 0x01 /* increment command count */ 660 #define LUN_CCDECR 0x02 /* decrement command count */ 661 #define LUN_ININCR 0x40 /* increment immed. notify count */ 662 #define LUN_INDECR 0x80 /* decrement immed. notify count */ 663 664 /* 665 * le_status values 666 */ 667 #define LUN_ERR 0x04 /* request completed with error */ 668 #define LUN_INVAL 0x06 /* invalid request */ 669 #define LUN_NOCAP 0x16 /* can't provide requested capability */ 670 #define LUN_ENABLED 0x3E /* LUN already enabled */ 671 672 /* 673 * Immediate Notify Entry structure 674 */ 675 #define IN_MSGLEN 8 /* 8 bytes */ 676 #define IN_RSVDLEN 8 /* 8 words */ 677 typedef struct { 678 isphdr_t in_header; 679 u_int32_t in_reserved2; 680 #if BYTE_ORDER == BIG_ENDIAN 681 #else 682 u_int8_t in_lun; /* lun */ 683 u_int8_t in_iid; /* initiator */ 684 u_int8_t in_rsvd; 685 u_int8_t in_tgt; /* target */ 686 #endif 687 u_int32_t in_flags; 688 #if BYTE_ORDER == BIG_ENDIAN 689 #else 690 u_int8_t in_status; 691 u_int8_t in_rsvd2; 692 u_int8_t in_tag_val; /* tag value */ 693 u_int8_t in_tag_type; /* tag type */ 694 #endif 695 u_int16_t in_seqid; /* sequence id */ 696 u_int8_t in_msg[IN_MSGLEN]; /* SCSI message bytes */ 697 u_int16_t in_reserved[IN_RSVDLEN]; 698 u_int8_t in_sense[SUGGSENSELEN]; /* suggested sense data */ 699 } in_entry_t; 700 701 typedef struct { 702 isphdr_t in_header; 703 u_int32_t in_reserved2; 704 #if BYTE_ORDER == BIG_ENDIAN 705 #else 706 u_int8_t in_lun; /* lun */ 707 u_int8_t in_iid; /* initiator */ 708 #endif 709 u_int16_t in_rsvd; 710 u_int32_t in_rsvd2; 711 u_int16_t in_status; 712 u_int16_t in_task_flags; 713 u_int16_t in_seqid; /* sequence id */ 714 } in_fcentry_t; 715 716 /* 717 * Values for the in_status field 718 */ 719 #define IN_NO_RCAP 0x16 /* requested capability not available */ 720 #define IN_IDE_RECEIVED 0x33 /* Initiator Detected Error msg received */ 721 #define IN_RSRC_UNAVAIL 0x34 /* resource unavailable */ 722 #define IN_MSG_RECEIVED 0x36 /* SCSI message received */ 723 #define IN_PORT_LOGOUT 0x29 /* port has logged out (FC) */ 724 #define IN_ABORT_TASK 0x20 /* task named in RX_ID is being aborted (FC) */ 725 726 /* 727 * Notify Acknowledge Entry structure 728 */ 729 #define NA_RSVDLEN 22 730 typedef struct { 731 isphdr_t na_header; 732 u_int32_t na_reserved2; 733 #if BYTE_ORDER == BIG_ENDIAN 734 #else 735 u_int8_t na_lun; /* lun */ 736 u_int8_t na_iid; /* initiator */ 737 u_int8_t na_rsvd; 738 u_int8_t na_tgt; /* target */ 739 #endif 740 u_int32_t na_flags; 741 #if BYTE_ORDER == BIG_ENDIAN 742 #else 743 u_int8_t na_status; 744 u_int8_t na_event; 745 #endif 746 u_int16_t na_seqid; /* sequence id */ 747 u_int16_t na_reserved[NA_RSVDLEN]; 748 } na_entry_t; 749 750 /* 751 * Value for the na_event field 752 */ 753 #define NA_RST_CLRD 0x80 /* Clear an async event notification */ 754 755 #define NA2_RSVDLEN 21 756 typedef struct { 757 isphdr_t na_header; 758 u_int32_t na_reserved2; 759 #if BYTE_ORDER == BIG_ENDIAN 760 #else 761 u_int8_t na_lun; /* lun */ 762 u_int8_t na_iid; /* initiator */ 763 #endif 764 u_int16_t na_rsvd; 765 u_int16_t na_flags; 766 u_int16_t na_rsvd2; 767 u_int16_t na_status; 768 u_int16_t na_task_flags; 769 u_int16_t na_seqid; /* sequence id */ 770 u_int16_t na_reserved[NA2_RSVDLEN]; 771 } na_fcentry_t; 772 #define NAFC_RST_CLRD 0x40 773 774 /* 775 * Value for the na_event field 776 */ 777 #define NA_RST_CLRD 0x80 /* Clear an async event notification */ 778 /* 779 * Accept Target I/O Entry structure 780 */ 781 #define ATIO_CDBLEN 26 782 783 typedef struct { 784 isphdr_t at_header; 785 u_int32_t at_reserved2; 786 #if BYTE_ORDER == BIG_ENDIAN 787 #else 788 u_int8_t at_lun; /* lun */ 789 u_int8_t at_iid; /* initiator */ 790 u_int8_t at_cdblen; /* cdb length */ 791 u_int8_t at_tgt; /* target */ 792 #endif 793 u_int32_t at_flags; 794 #if BYTE_ORDER == BIG_ENDIAN 795 #else 796 u_int8_t at_status; /* firmware status */ 797 u_int8_t at_scsi_status; /* scsi status */ 798 u_int8_t at_tag_val; /* tag value */ 799 u_int8_t at_tag_type; /* tag type */ 800 #endif 801 u_int8_t at_cdb[ATIO_CDBLEN]; /* received CDB */ 802 u_int8_t at_sense[SUGGSENSELEN]; /* suggested sense data */ 803 } at_entry_t; 804 805 /* 806 * at_flags values 807 */ 808 #define AT_NODISC 0x00008000 /* disconnect disabled */ 809 #define AT_TQAE 0x00000001 /* Tagged Queue Action enabled */ 810 811 /* 812 * at_status values 813 */ 814 #define AT_PATH_INVALID 0x07 /* ATIO sent to firmware for disabled lun */ 815 #define AT_PHASE_ERROR 0x14 /* Bus phase sequence error */ 816 #define AT_NOCAP 0x16 /* Requested capability not available */ 817 #define AT_BDR_MSG 0x17 /* Bus Device Reset msg received */ 818 #define AT_CDB 0x3D /* CDB received */ 819 820 /* 821 * Accept Target I/O Entry structure, Type 2 822 */ 823 #define ATIO2_CDBLEN 16 824 825 typedef struct { 826 isphdr_t at_header; 827 u_int32_t at_reserved2; 828 #if BYTE_ORDER == BIG_ENDIAN 829 #else 830 u_int8_t at_lun; /* lun */ 831 u_int8_t at_iid; /* initiator */ 832 #endif 833 u_int16_t at_rxid; /* response ID */ 834 u_int16_t at_flags; 835 u_int16_t at_status; /* firmware status */ 836 #if BYTE_ORDER == BIG_ENDIAN 837 #else 838 u_int8_t at_reserved1; 839 u_int8_t at_taskcodes; 840 u_int8_t at_taskflags; 841 u_int8_t at_execodes; 842 #endif 843 u_int8_t at_cdb[ATIO2_CDBLEN]; /* received CDB */ 844 u_int32_t at_datalen; /* allocated data len */ 845 u_int16_t at_scclun; 846 u_int16_t at_reserved3; 847 u_int16_t at_scsi_status; 848 u_int8_t at_sense[SUGGSENSELEN]; /* suggested sense data */ 849 } at2_entry_t; 850 851 #define ATIO2_TC_ATTR_MASK 0x7 852 #define ATIO2_TC_ATTR_SIMPLEQ 0 853 #define ATIO2_TC_ATTR_HEADOFQ 1 854 #define ATIO2_TC_ATTR_ORDERED 2 855 #define ATIO2_TC_ATTR_ACAQ 4 856 #define ATIO2_TC_ATTR_UNTAGGED 5 857 #define TC2TT(code) \ 858 (((code) == ATIO2_TC_ATTR_SIMPLEQ)? 0x20 : \ 859 (((code) == ATIO2_TC_ATTR_HEADOFQ)? 0x21 : \ 860 (((code) == ATIO2_TC_ATTR_ORDERED)? 0x22 : \ 861 (((code) == ATIO2_TC_ATTR_ACAQ)? 0x24 : 0)))) 862 863 864 /* 865 * Continue Target I/O Entry structure 866 * Request from driver. The response from the 867 * ISP firmware is the same except that the last 18 868 * bytes are overwritten by suggested sense data if 869 * the 'autosense valid' bit is set in the status byte. 870 */ 871 typedef struct { 872 isphdr_t ct_header; 873 u_int32_t ct_reserved; 874 #if BYTE_ORDER == BIG_ENDIAN 875 #else 876 u_int8_t ct_lun; /* lun */ 877 u_int8_t ct_iid; /* initiator id */ 878 u_int8_t ct_rsvd; 879 u_int8_t ct_tgt; /* our target id */ 880 #endif 881 u_int32_t ct_flags; 882 #if BYTE_ORDER == BIG_ENDIAN 883 #else 884 u_int8_t ct_status; /* isp status */ 885 u_int8_t ct_scsi_status; /* scsi status */ 886 u_int8_t ct_tag_val; /* tag value */ 887 u_int8_t ct_tag_type; /* tag type */ 888 #endif 889 u_int32_t ct_xfrlen; /* transfer length */ 890 u_int32_t ct_resid; /* residual length */ 891 u_int16_t ct_timeout; 892 u_int16_t ct_seg_count; 893 ispds_t ct_dataseg[ISP_RQDSEG]; 894 } ct_entry_t; 895 896 /* 897 * ct_flags values 898 */ 899 #define CT_TQAE 0x00000001 /* Tagged Queue Action enable */ 900 #define CT_DATA_IN 0x00000040 /* Data direction */ 901 #define CT_DATA_OUT 0x00000080 /* Data direction */ 902 #define CT_NO_DATA 0x000000C0 /* Data direction */ 903 #define CT_DATAMASK 0x000000C0 /* Data direction */ 904 #define CT_NODISC 0x00008000 /* Disconnects disabled */ 905 #define CT_DSDP 0x01000000 /* Disable Save Data Pointers */ 906 #define CT_SENDRDP 0x04000000 /* Send Restore Pointers msg */ 907 #define CT_SENDSTATUS 0x80000000 /* Send SCSI status byte */ 908 909 /* 910 * ct_status values 911 * - set by the firmware when it returns the CTIO 912 */ 913 #define CT_OK 0x01 /* completed without error */ 914 #define CT_ABORTED 0x02 /* aborted by host */ 915 #define CT_ERR 0x04 /* see sense data for error */ 916 #define CT_INVAL 0x06 /* request for disabled lun */ 917 #define CT_NOPATH 0x07 /* invalid ITL nexus */ 918 #define CT_INVRXID 0x08 /* (FC only) Invalid RX_ID */ 919 #define CT_RSELTMO 0x0A /* reselection timeout after 2 tries */ 920 #define CT_TIMEOUT 0x0B /* timed out */ 921 #define CT_RESET 0x0E /* SCSI Bus Reset occurred */ 922 #define CT_PHASE_ERROR 0x14 /* Bus phase sequence error */ 923 #define CT_BDR_MSG 0x17 /* Bus Device Reset msg received */ 924 #define CT_TERMINATED 0x19 /* due to Terminate Transfer mbox cmd */ 925 #define CT_LOGOUT 0x29 /* port logout not acknowledged yet */ 926 #define CT_NOACK 0x35 /* Outstanding Immed. Notify. entry */ 927 928 /* 929 * When the firmware returns a CTIO entry, it may overwrite the last 930 * part of the structure with sense data. This starts at offset 0x2E 931 * into the entry, which is in the middle of ct_dataseg[1]. Rather 932 * than define a new struct for this, I'm just using the sense data 933 * offset. 934 */ 935 #define CTIO_SENSE_OFFSET 0x2E 936 937 /* 938 * Entry length in u_longs. All entries are the same size so 939 * any one will do as the numerator. 940 */ 941 #define UINT32_ENTRY_SIZE (sizeof(at_entry_t)/sizeof(u_int32_t)) 942 943 /* 944 * QLA2100 CTIO (type 2) entry 945 */ 946 #define MAXRESPLEN 26 947 typedef struct { 948 isphdr_t ct_header; 949 u_int32_t ct_reserved; 950 #if BYTE_ORDER == BIG_ENDIAN 951 #else 952 u_int8_t ct_lun; /* lun */ 953 u_int8_t ct_iid; /* initiator id */ 954 #endif 955 u_int16_t ct_rxid; /* response ID */ 956 u_int16_t ct_flags; 957 u_int16_t ct_status; /* isp status */ 958 u_int16_t ct_timeout; 959 u_int16_t ct_seg_count; 960 u_int32_t ct_reloff; /* relative offset */ 961 u_int32_t ct_resid; /* residual length */ 962 union { 963 /* 964 * The three different modes that the target driver 965 * can set the CTIO2 up as. 966 * 967 * The first is for sending FCP_DATA_IUs as well as 968 * (optionally) sending a terminal SCSI status FCP_RSP_IU. 969 * 970 * The second is for sending SCSI sense data in an FCP_RSP_IU. 971 * Note that no FCP_DATA_IUs will be sent. 972 * 973 * The third is for sending FCP_RSP_IUs as built specifically 974 * in system memory as located by the isp_dataseg. 975 */ 976 struct { 977 u_int32_t _reserved; 978 u_int16_t _reserved2; 979 u_int16_t ct_scsi_status; 980 u_int32_t ct_xfrlen; 981 ispds_t ct_dataseg[ISP_RQDSEG_T2]; 982 } m0; 983 struct { 984 u_int16_t _reserved; 985 u_int16_t _reserved2; 986 u_int16_t ct_senselen; 987 u_int16_t ct_scsi_status; 988 u_int16_t ct_resplen; 989 u_int8_t ct_resp[MAXRESPLEN]; 990 } m1; 991 struct { 992 u_int32_t _reserved; 993 u_int16_t _reserved2; 994 u_int16_t _reserved3; 995 u_int32_t ct_datalen; 996 ispds_t ct_fcp_rsp_iudata; 997 } m2; 998 /* 999 * CTIO2 returned from F/W... 1000 */ 1001 struct { 1002 u_int32_t _reserved[4]; 1003 u_int16_t ct_scsi_status; 1004 u_int8_t ct_sense[SUGGSENSELEN]; 1005 } fw; 1006 } rsp; 1007 } ct2_entry_t; 1008 /* 1009 * ct_flags values for CTIO2 1010 */ 1011 #define CT2_FLAG_MMASK 0x0003 1012 #define CT2_FLAG_MODE0 0x0000 1013 #define CT2_FLAG_MODE1 0x0001 1014 #define CT2_FLAG_MODE2 0x0002 1015 #define CT2_DATA_IN CT_DATA_IN 1016 #define CT2_DATA_OUT CT_DATA_OUT 1017 #define CT2_NO_DATA CT_NO_DATA 1018 #define CT2_DATAMASK CT_DATA_MASK 1019 #define CT2_CCINCR 0x0100 1020 #define CT2_FASTPOST 0x0200 1021 #define CT2_SENDSTATUS 0x8000 1022 1023 /* 1024 * ct_status values are (mostly) the same as that for ct_entry. 1025 */ 1026 1027 /* 1028 * ct_scsi_status values- the low 8 bits are the normal SCSI status 1029 * we know and love. The upper 8 bits are validity markers for FCP_RSP_IU 1030 * fields. 1031 */ 1032 #define CT2_RSPLEN_VALID 0x0100 1033 #define CT2_SNSLEN_VALID 0x0200 1034 #define CT2_DATA_OVER 0x0400 1035 #define CT2_DATA_UNDER 0x0800 1036 1037 #endif /* _ISPMBOX_H */ 1038
Indexes created Wed Sep 24 05:09:52 GMT 2025