ispmbox.h revision 1.40
1 /* $NetBSD: ispmbox.h,v 1.40 2002/04/11 02:32:05 mjacob Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob (at) netbsd.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* 31 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. The name of the author may not be used to endorse or promote products 43 * derived from this software without specific prior written permission 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters. 59 * <mjacob (at) nas.nasa.gov> 60 */ 61 #ifndef _ISPMBOX_H 62 #define _ISPMBOX_H 63 64 /* 65 * Mailbox Command Opcodes 66 */ 67 #define MBOX_NO_OP 0x0000 68 #define MBOX_LOAD_RAM 0x0001 69 #define MBOX_EXEC_FIRMWARE 0x0002 70 #define MBOX_DUMP_RAM 0x0003 71 #define MBOX_WRITE_RAM_WORD 0x0004 72 #define MBOX_READ_RAM_WORD 0x0005 73 #define MBOX_MAILBOX_REG_TEST 0x0006 74 #define MBOX_VERIFY_CHECKSUM 0x0007 75 #define MBOX_ABOUT_FIRMWARE 0x0008 76 /* 9 */ 77 /* a */ 78 /* b */ 79 /* c */ 80 /* d */ 81 #define MBOX_CHECK_FIRMWARE 0x000e 82 #define MBOX_READ_RAM_WORD_EXTENDED 0x000f 83 #define MBOX_INIT_REQ_QUEUE 0x0010 84 #define MBOX_INIT_RES_QUEUE 0x0011 85 #define MBOX_EXECUTE_IOCB 0x0012 86 #define MBOX_WAKE_UP 0x0013 87 #define MBOX_STOP_FIRMWARE 0x0014 88 #define MBOX_ABORT 0x0015 89 #define MBOX_ABORT_DEVICE 0x0016 90 #define MBOX_ABORT_TARGET 0x0017 91 #define MBOX_BUS_RESET 0x0018 92 #define MBOX_STOP_QUEUE 0x0019 93 #define MBOX_START_QUEUE 0x001a 94 #define MBOX_SINGLE_STEP_QUEUE 0x001b 95 #define MBOX_ABORT_QUEUE 0x001c 96 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 97 /* 1e */ 98 #define MBOX_GET_FIRMWARE_STATUS 0x001f 99 #define MBOX_GET_INIT_SCSI_ID 0x0020 100 #define MBOX_GET_SELECT_TIMEOUT 0x0021 101 #define MBOX_GET_RETRY_COUNT 0x0022 102 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 103 #define MBOX_GET_CLOCK_RATE 0x0024 104 #define MBOX_GET_ACT_NEG_STATE 0x0025 105 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 106 #define MBOX_GET_SBUS_PARAMS 0x0027 107 #define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS 108 #define MBOX_GET_TARGET_PARAMS 0x0028 109 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 110 #define MBOX_GET_RESET_DELAY_PARAMS 0x002a 111 /* 2b */ 112 /* 2c */ 113 /* 2d */ 114 /* 2e */ 115 /* 2f */ 116 #define MBOX_SET_INIT_SCSI_ID 0x0030 117 #define MBOX_SET_SELECT_TIMEOUT 0x0031 118 #define MBOX_SET_RETRY_COUNT 0x0032 119 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 120 #define MBOX_SET_CLOCK_RATE 0x0034 121 #define MBOX_SET_ACT_NEG_STATE 0x0035 122 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 123 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 124 #define MBOX_SET_PCI_PARAMETERS 0x0037 125 #define MBOX_SET_TARGET_PARAMS 0x0038 126 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 127 #define MBOX_SET_RESET_DELAY_PARAMS 0x003a 128 /* 3b */ 129 /* 3c */ 130 /* 3d */ 131 /* 3e */ 132 /* 3f */ 133 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 134 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 135 #define MBOX_EXEC_BIOS_IOCB 0x0042 136 #define MBOX_SET_FW_FEATURES 0x004a 137 #define MBOX_GET_FW_FEATURES 0x004b 138 #define FW_FEATURE_FAST_POST 0x1 139 #define FW_FEATURE_LVD_NOTIFY 0x2 140 #define FW_FEATURE_RIO_32BIT 0x4 141 #define FW_FEATURE_RIO_16BIT 0x8 142 143 #define MBOX_ENABLE_TARGET_MODE 0x0055 144 #define ENABLE_TARGET_FLAG 0x8000 145 #define ENABLE_TQING_FLAG 0x0004 146 #define ENABLE_MANDATORY_DISC 0x0002 147 #define MBOX_GET_TARGET_STATUS 0x0056 148 149 /* These are for the ISP2X00 FC cards */ 150 #define MBOX_GET_LOOP_ID 0x0020 151 #define MBOX_GET_FIRMWARE_OPTIONS 0x0028 152 #define MBOX_SET_FIRMWARE_OPTIONS 0x0038 153 #define MBOX_GET_RESOURCE_COUNT 0x0042 154 #define MBOX_ENHANCED_GET_PDB 0x0047 155 #define MBOX_EXEC_COMMAND_IOCB_A64 0x0054 156 #define MBOX_INIT_FIRMWARE 0x0060 157 #define MBOX_GET_INIT_CONTROL_BLOCK 0x0061 158 #define MBOX_INIT_LIP 0x0062 159 #define MBOX_GET_FC_AL_POSITION_MAP 0x0063 160 #define MBOX_GET_PORT_DB 0x0064 161 #define MBOX_CLEAR_ACA 0x0065 162 #define MBOX_TARGET_RESET 0x0066 163 #define MBOX_CLEAR_TASK_SET 0x0067 164 #define MBOX_ABORT_TASK_SET 0x0068 165 #define MBOX_GET_FW_STATE 0x0069 166 #define MBOX_GET_PORT_NAME 0x006A 167 #define MBOX_GET_LINK_STATUS 0x006B 168 #define MBOX_INIT_LIP_RESET 0x006C 169 #define MBOX_SEND_SNS 0x006E 170 #define MBOX_FABRIC_LOGIN 0x006F 171 #define MBOX_SEND_CHANGE_REQUEST 0x0070 172 #define MBOX_FABRIC_LOGOUT 0x0071 173 #define MBOX_INIT_LIP_LOGIN 0x0072 174 175 #define MBOX_GET_SET_DATA_RATE 0x005D /* 23XX only */ 176 #define MBGSD_GET_RATE 0 177 #define MBGSD_SET_RATE 1 178 #define MBGSD_ONEGB 0 179 #define MBGSD_TWOGB 1 180 #define MBGSD_AUTO 2 181 182 183 #define ISP2100_SET_PCI_PARAM 0x00ff 184 185 #define MBOX_BUSY 0x04 186 187 typedef struct { 188 u_int16_t param[8]; 189 } mbreg_t; 190 191 /* 192 * Mailbox Command Complete Status Codes 193 */ 194 #define MBOX_COMMAND_COMPLETE 0x4000 195 #define MBOX_INVALID_COMMAND 0x4001 196 #define MBOX_HOST_INTERFACE_ERROR 0x4002 197 #define MBOX_TEST_FAILED 0x4003 198 #define MBOX_COMMAND_ERROR 0x4005 199 #define MBOX_COMMAND_PARAM_ERROR 0x4006 200 #define MBOX_PORT_ID_USED 0x4007 201 #define MBOX_LOOP_ID_USED 0x4008 202 #define MBOX_ALL_IDS_USED 0x4009 203 #define MBOX_NOT_LOGGED_IN 0x400A 204 #define MBLOGALL 0x000f 205 #define MBLOGNONE 0x0000 206 #define MBLOGMASK(x) ((x) & 0xf) 207 208 /* 209 * Asynchronous event status codes 210 */ 211 #define ASYNC_BUS_RESET 0x8001 212 #define ASYNC_SYSTEM_ERROR 0x8002 213 #define ASYNC_RQS_XFER_ERR 0x8003 214 #define ASYNC_RSP_XFER_ERR 0x8004 215 #define ASYNC_QWAKEUP 0x8005 216 #define ASYNC_TIMEOUT_RESET 0x8006 217 #define ASYNC_DEVICE_RESET 0x8007 218 #define ASYNC_EXTMSG_UNDERRUN 0x800A 219 #define ASYNC_SCAM_INT 0x800B 220 #define ASYNC_HUNG_SCSI 0x800C 221 #define ASYNC_KILLED_BUS 0x800D 222 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 223 #define ASYNC_LIP_OCCURRED 0x8010 224 #define ASYNC_LOOP_UP 0x8011 225 #define ASYNC_LOOP_DOWN 0x8012 226 #define ASYNC_LOOP_RESET 0x8013 227 #define ASYNC_PDB_CHANGED 0x8014 228 #define ASYNC_CHANGE_NOTIFY 0x8015 229 #define ASYNC_LIP_F8 0x8016 230 #define ASYNC_CMD_CMPLT 0x8020 231 #define ASYNC_CTIO_DONE 0x8021 232 #define ASYNC_IP_XMIT_DONE 0x8022 233 #define ASYNC_IP_RECV_DONE 0x8023 234 #define ASYNC_IP_BROADCAST 0x8024 235 #define ASYNC_IP_RCVQ_LOW 0x8025 236 #define ASYNC_IP_RCVQ_EMPTY 0x8026 237 #define ASYNC_IP_RECV_DONE_ALIGNED 0x8027 238 #define ASYNC_PTPMODE 0x8030 239 #define ASYNC_RIO1 0x8031 240 #define ASYNC_RIO2 0x8032 241 #define ASYNC_RIO3 0x8033 242 #define ASYNC_RIO4 0x8034 243 #define ASYNC_RIO5 0x8035 244 #define ASYNC_CONNMODE 0x8036 245 #define ISP_CONN_LOOP 1 246 #define ISP_CONN_PTP 2 247 #define ISP_CONN_BADLIP 3 248 #define ISP_CONN_FATAL 4 249 #define ISP_CONN_LOOPBACK 5 250 #define ASYNC_RIO_RESP 0x8040 251 #define ASYNC_RIO_COMP 0x8042 252 /* 253 * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options 254 * mailbox command to enable this. 255 */ 256 #define ASYNC_QFULL_SENT 0x8049 257 258 /* 259 * Mailbox Usages 260 */ 261 262 #define WRITE_REQUEST_QUEUE_IN_POINTER(isp, value) \ 263 ISP_WRITE(isp, isp->isp_rqstinrp, value) 264 265 #define READ_REQUEST_QUEUE_OUT_POINTER(isp) \ 266 ISP_READ(isp, isp->isp_rqstoutrp) 267 268 #define READ_RESPONSE_QUEUE_IN_POINTER(isp) \ 269 ISP_READ(isp, isp->isp_respinrp) 270 271 #define WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, value) \ 272 ISP_WRITE(isp, isp->isp_respoutrp, value) 273 274 /* 275 * Command Structure Definitions 276 */ 277 278 typedef struct { 279 u_int32_t ds_base; 280 u_int32_t ds_count; 281 } ispds_t; 282 283 typedef struct { 284 u_int32_t ds_base; 285 u_int32_t ds_basehi; 286 u_int32_t ds_count; 287 } ispds64_t; 288 289 #define DSTYPE_32BIT 0 290 #define DSTYPE_64BIT 1 291 typedef struct { 292 u_int16_t ds_type; /* 0-> ispds_t, 1-> ispds64_t */ 293 u_int32_t ds_segment; /* unused */ 294 u_int32_t ds_base; /* 32 bit address of DSD list */ 295 } ispdslist_t; 296 297 298 /* 299 * These elements get swizzled around for SBus instances. 300 */ 301 #define ISP_SWAP8(a, b) { \ 302 u_int8_t tmp; \ 303 tmp = a; \ 304 a = b; \ 305 b = tmp; \ 306 } 307 typedef struct { 308 u_int8_t rqs_entry_type; 309 u_int8_t rqs_entry_count; 310 u_int8_t rqs_seqno; 311 u_int8_t rqs_flags; 312 } isphdr_t; 313 314 /* RQS Flag definitions */ 315 #define RQSFLAG_CONTINUATION 0x01 316 #define RQSFLAG_FULL 0x02 317 #define RQSFLAG_BADHEADER 0x04 318 #define RQSFLAG_BADPACKET 0x08 319 320 /* RQS entry_type definitions */ 321 #define RQSTYPE_REQUEST 0x01 322 #define RQSTYPE_DATASEG 0x02 323 #define RQSTYPE_RESPONSE 0x03 324 #define RQSTYPE_MARKER 0x04 325 #define RQSTYPE_CMDONLY 0x05 326 #define RQSTYPE_ATIO 0x06 /* Target Mode */ 327 #define RQSTYPE_CTIO 0x07 /* Target Mode */ 328 #define RQSTYPE_SCAM 0x08 329 #define RQSTYPE_A64 0x09 330 #define RQSTYPE_A64_CONT 0x0a 331 #define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */ 332 #define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */ 333 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 334 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 335 #define RQSTYPE_CTIO1 0x0f /* Target Mode */ 336 #define RQSTYPE_STATUS_CONT 0x10 337 #define RQSTYPE_T2RQS 0x11 338 #define RQSTYPE_IP_XMIT 0x13 339 #define RQSTYPE_T4RQS 0x15 340 #define RQSTYPE_ATIO2 0x16 /* Target Mode */ 341 #define RQSTYPE_CTIO2 0x17 /* Target Mode */ 342 #define RQSTYPE_CSET0 0x18 343 #define RQSTYPE_T3RQS 0x19 344 #define RQSTYPE_IP_XMIT_64 0x1b 345 #define RQSTYPE_CTIO4 0x1e /* Target Mode */ 346 #define RQSTYPE_CTIO3 0x1f /* Target Mode */ 347 #define RQSTYPE_RIO1 0x21 348 #define RQSTYPE_RIO2 0x22 349 #define RQSTYPE_IP_RECV 0x23 350 #define RQSTYPE_IP_RECV_CONT 0x24 351 352 353 #define ISP_RQDSEG 4 354 typedef struct { 355 isphdr_t req_header; 356 u_int32_t req_handle; 357 u_int8_t req_lun_trn; 358 u_int8_t req_target; 359 u_int16_t req_cdblen; 360 #define req_modifier req_cdblen /* marker packet */ 361 u_int16_t req_flags; 362 u_int16_t req_reserved; 363 u_int16_t req_time; 364 u_int16_t req_seg_count; 365 u_int8_t req_cdb[12]; 366 ispds_t req_dataseg[ISP_RQDSEG]; 367 } ispreq_t; 368 369 /* 370 * A request packet can also be a marker packet. 371 */ 372 #define SYNC_DEVICE 0 373 #define SYNC_TARGET 1 374 #define SYNC_ALL 2 375 376 #define ISP_RQDSEG_T2 3 377 typedef struct { 378 isphdr_t req_header; 379 u_int32_t req_handle; 380 u_int8_t req_lun_trn; 381 u_int8_t req_target; 382 u_int16_t req_scclun; 383 u_int16_t req_flags; 384 u_int16_t _res2; 385 u_int16_t req_time; 386 u_int16_t req_seg_count; 387 u_int8_t req_cdb[16]; 388 u_int32_t req_totalcnt; 389 ispds_t req_dataseg[ISP_RQDSEG_T2]; 390 } ispreqt2_t; 391 392 #define ISP_RQDSEG_T3 2 393 typedef struct { 394 isphdr_t req_header; 395 u_int32_t req_handle; 396 u_int8_t req_lun_trn; 397 u_int8_t req_target; 398 u_int16_t req_scclun; 399 u_int16_t req_flags; 400 u_int16_t _res2; 401 u_int16_t req_time; 402 u_int16_t req_seg_count; 403 u_int8_t req_cdb[16]; 404 u_int32_t req_totalcnt; 405 ispds64_t req_dataseg[ISP_RQDSEG_T3]; 406 } ispreqt3_t; 407 408 /* req_flag values */ 409 #define REQFLAG_NODISCON 0x0001 410 #define REQFLAG_HTAG 0x0002 411 #define REQFLAG_OTAG 0x0004 412 #define REQFLAG_STAG 0x0008 413 #define REQFLAG_TARGET_RTN 0x0010 414 415 #define REQFLAG_NODATA 0x0000 416 #define REQFLAG_DATA_IN 0x0020 417 #define REQFLAG_DATA_OUT 0x0040 418 #define REQFLAG_DATA_UNKNOWN 0x0060 419 420 #define REQFLAG_DISARQ 0x0100 421 #define REQFLAG_FRC_ASYNC 0x0200 422 #define REQFLAG_FRC_SYNC 0x0400 423 #define REQFLAG_FRC_WIDE 0x0800 424 #define REQFLAG_NOPARITY 0x1000 425 #define REQFLAG_STOPQ 0x2000 426 #define REQFLAG_XTRASNS 0x4000 427 #define REQFLAG_PRIORITY 0x8000 428 429 typedef struct { 430 isphdr_t req_header; 431 u_int32_t req_handle; 432 u_int8_t req_lun_trn; 433 u_int8_t req_target; 434 u_int16_t req_cdblen; 435 u_int16_t req_flags; 436 u_int16_t _res1; 437 u_int16_t req_time; 438 u_int16_t req_seg_count; 439 u_int8_t req_cdb[44]; 440 } ispextreq_t; 441 442 #define ISP_CDSEG 7 443 typedef struct { 444 isphdr_t req_header; 445 u_int32_t _res1; 446 ispds_t req_dataseg[ISP_CDSEG]; 447 } ispcontreq_t; 448 449 #define ISP_CDSEG64 5 450 typedef struct { 451 isphdr_t req_header; 452 ispds64_t req_dataseg[ISP_CDSEG64]; 453 } ispcontreq64_t; 454 455 typedef struct { 456 isphdr_t req_header; 457 u_int32_t req_handle; 458 u_int16_t req_scsi_status; 459 u_int16_t req_completion_status; 460 u_int16_t req_state_flags; 461 u_int16_t req_status_flags; 462 u_int16_t req_time; 463 #define req_response_len req_time /* FC only */ 464 u_int16_t req_sense_len; 465 u_int32_t req_resid; 466 u_int8_t req_response[8]; /* FC only */ 467 u_int8_t req_sense_data[32]; 468 } ispstatusreq_t; 469 470 typedef struct { 471 isphdr_t req_header; 472 u_int8_t req_sense_data[60]; 473 } ispstatus_cont_t; 474 475 /* 476 * For Qlogic 2X00, the high order byte of SCSI status has 477 * additional meaning. 478 */ 479 #define RQCS_RU 0x800 /* Residual Under */ 480 #define RQCS_RO 0x400 /* Residual Over */ 481 #define RQCS_RESID (RQCS_RU|RQCS_RO) 482 #define RQCS_SV 0x200 /* Sense Length Valid */ 483 #define RQCS_RV 0x100 /* FCP Response Length Valid */ 484 485 /* 486 * Completion Status Codes. 487 */ 488 #define RQCS_COMPLETE 0x0000 489 #define RQCS_DMA_ERROR 0x0002 490 #define RQCS_RESET_OCCURRED 0x0004 491 #define RQCS_ABORTED 0x0005 492 #define RQCS_TIMEOUT 0x0006 493 #define RQCS_DATA_OVERRUN 0x0007 494 #define RQCS_DATA_UNDERRUN 0x0015 495 #define RQCS_QUEUE_FULL 0x001C 496 497 /* 1X00 Only Completion Codes */ 498 #define RQCS_INCOMPLETE 0x0001 499 #define RQCS_TRANSPORT_ERROR 0x0003 500 #define RQCS_COMMAND_OVERRUN 0x0008 501 #define RQCS_STATUS_OVERRUN 0x0009 502 #define RQCS_BAD_MESSAGE 0x000a 503 #define RQCS_NO_MESSAGE_OUT 0x000b 504 #define RQCS_EXT_ID_FAILED 0x000c 505 #define RQCS_IDE_MSG_FAILED 0x000d 506 #define RQCS_ABORT_MSG_FAILED 0x000e 507 #define RQCS_REJECT_MSG_FAILED 0x000f 508 #define RQCS_NOP_MSG_FAILED 0x0010 509 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 510 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 511 #define RQCS_ID_MSG_FAILED 0x0013 512 #define RQCS_UNEXP_BUS_FREE 0x0014 513 #define RQCS_XACT_ERR1 0x0018 514 #define RQCS_XACT_ERR2 0x0019 515 #define RQCS_XACT_ERR3 0x001A 516 #define RQCS_BAD_ENTRY 0x001B 517 #define RQCS_PHASE_SKIPPED 0x001D 518 #define RQCS_ARQS_FAILED 0x001E 519 #define RQCS_WIDE_FAILED 0x001F 520 #define RQCS_SYNCXFER_FAILED 0x0020 521 #define RQCS_LVD_BUSERR 0x0021 522 523 /* 2X00 Only Completion Codes */ 524 #define RQCS_PORT_UNAVAILABLE 0x0028 525 #define RQCS_PORT_LOGGED_OUT 0x0029 526 #define RQCS_PORT_CHANGED 0x002A 527 #define RQCS_PORT_BUSY 0x002B 528 529 /* 530 * 1X00 specific State Flags 531 */ 532 #define RQSF_GOT_BUS 0x0100 533 #define RQSF_GOT_TARGET 0x0200 534 #define RQSF_SENT_CDB 0x0400 535 #define RQSF_XFRD_DATA 0x0800 536 #define RQSF_GOT_STATUS 0x1000 537 #define RQSF_GOT_SENSE 0x2000 538 #define RQSF_XFER_COMPLETE 0x4000 539 540 /* 541 * 2X00 specific State Flags 542 * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available) 543 */ 544 #define RQSF_DATA_IN 0x0020 545 #define RQSF_DATA_OUT 0x0040 546 #define RQSF_STAG 0x0008 547 #define RQSF_OTAG 0x0004 548 #define RQSF_HTAG 0x0002 549 /* 550 * 1X00 Status Flags 551 */ 552 #define RQSTF_DISCONNECT 0x0001 553 #define RQSTF_SYNCHRONOUS 0x0002 554 #define RQSTF_PARITY_ERROR 0x0004 555 #define RQSTF_BUS_RESET 0x0008 556 #define RQSTF_DEVICE_RESET 0x0010 557 #define RQSTF_ABORTED 0x0020 558 #define RQSTF_TIMEOUT 0x0040 559 #define RQSTF_NEGOTIATION 0x0080 560 561 /* 562 * 2X00 specific state flags 563 */ 564 /* RQSF_SENT_CDB */ 565 /* RQSF_XFRD_DATA */ 566 /* RQSF_GOT_STATUS */ 567 /* RQSF_XFER_COMPLETE */ 568 569 /* 570 * 2X00 specific status flags 571 */ 572 /* RQSTF_ABORTED */ 573 /* RQSTF_TIMEOUT */ 574 #define RQSTF_DMA_ERROR 0x0080 575 #define RQSTF_LOGOUT 0x2000 576 577 /* 578 * Miscellaneous 579 */ 580 #ifndef ISP_EXEC_THROTTLE 581 #define ISP_EXEC_THROTTLE 16 582 #endif 583 584 /* 585 * About Firmware returns an 'attribute' word in mailbox 6. 586 */ 587 #define ISP_FW_ATTR_TMODE 0x01 588 #define ISP_FW_ATTR_SCCLUN 0x02 589 #define ISP_FW_ATTR_FABRIC 0x04 590 #define ISP_FW_ATTR_CLASS2 0x08 591 #define ISP_FW_ATTR_FCTAPE 0x10 592 #define ISP_FW_ATTR_IP 0x20 593 594 /* 595 * Reduced Interrupt Operation Response Queue Entreis 596 */ 597 598 typedef struct { 599 isphdr_t req_header; 600 u_int32_t req_handles[15]; 601 } isp_rio1_t; 602 603 typedef struct { 604 isphdr_t req_header; 605 u_int16_t req_handles[30]; 606 } isp_rio2_t; 607 608 /* 609 * FC (ISP2100) specific data structures 610 */ 611 612 /* 613 * Initialization Control Block 614 * 615 * Version One (prime) format. 616 */ 617 typedef struct isp_icb { 618 u_int8_t icb_version; 619 u_int8_t _reserved0; 620 u_int16_t icb_fwoptions; 621 u_int16_t icb_maxfrmlen; 622 u_int16_t icb_maxalloc; 623 u_int16_t icb_execthrottle; 624 u_int8_t icb_retry_count; 625 u_int8_t icb_retry_delay; 626 u_int8_t icb_portname[8]; 627 u_int16_t icb_hardaddr; 628 u_int8_t icb_iqdevtype; 629 u_int8_t icb_logintime; 630 u_int8_t icb_nodename[8]; 631 u_int16_t icb_rqstout; 632 u_int16_t icb_rspnsin; 633 u_int16_t icb_rqstqlen; 634 u_int16_t icb_rsltqlen; 635 u_int16_t icb_rqstaddr[4]; 636 u_int16_t icb_respaddr[4]; 637 u_int16_t icb_lunenables; 638 u_int8_t icb_ccnt; 639 u_int8_t icb_icnt; 640 u_int16_t icb_lunetimeout; 641 u_int16_t _reserved1; 642 u_int16_t icb_xfwoptions; 643 u_int8_t icb_racctimer; 644 u_int8_t icb_idelaytimer; 645 u_int16_t icb_zfwoptions; 646 u_int16_t _reserved2[13]; 647 } isp_icb_t; 648 #define ICB_VERSION1 1 649 650 #define ICBOPT_HARD_ADDRESS 0x0001 651 #define ICBOPT_FAIRNESS 0x0002 652 #define ICBOPT_FULL_DUPLEX 0x0004 653 #define ICBOPT_FAST_POST 0x0008 654 #define ICBOPT_TGT_ENABLE 0x0010 655 #define ICBOPT_INI_DISABLE 0x0020 656 #define ICBOPT_INI_ADISC 0x0040 657 #define ICBOPT_INI_TGTTYPE 0x0080 658 #define ICBOPT_PDBCHANGE_AE 0x0100 659 #define ICBOPT_NOLIP 0x0200 660 #define ICBOPT_SRCHDOWN 0x0400 661 #define ICBOPT_PREVLOOP 0x0800 662 #define ICBOPT_STOP_ON_QFULL 0x1000 663 #define ICBOPT_FULL_LOGIN 0x2000 664 #define ICBOPT_BOTH_WWNS 0x4000 665 #define ICBOPT_EXTENDED 0x8000 666 667 #define ICBXOPT_CLASS2_ACK0 0x0200 668 #define ICBXOPT_CLASS2 0x0100 669 #define ICBXOPT_LOOP_ONLY (0 << 4) 670 #define ICBXOPT_PTP_ONLY (1 << 4) 671 #define ICBXOPT_LOOP_2_PTP (2 << 4) 672 #define ICBXOPT_PTP_2_LOOP (3 << 4) 673 674 #define ICBXOPT_RIO_OFF 0 675 #define ICBXOPT_RIO_16BIT 1 676 #define ICBXOPT_RIO_32BIT 2 677 #define ICBXOPT_RIO_16BIT_IOCB 3 678 #define ICBXOPT_RIO_32BIT_IOCB 4 679 680 #define ICBZOPT_ENA_RDXFR_RDY 0x01 681 #define ICBZOPT_ENA_OOF (1 << 6) /* out of order frame handling */ 682 /* These 3 only apply to the 2300 */ 683 #define ICBZOPT_RATE_ONEGB (MBGSD_ONEGB << 14) 684 #define ICBZOPT_RATE_TWOGB (MBGSD_TWOGB << 14) 685 #define ICBZOPT_RATE_AUTO (MBGSD_AUTO << 14) 686 687 688 #define ICB_MIN_FRMLEN 256 689 #define ICB_MAX_FRMLEN 2112 690 #define ICB_DFLT_FRMLEN 1024 691 #define ICB_DFLT_ALLOC 256 692 #define ICB_DFLT_THROTTLE 16 693 #define ICB_DFLT_RDELAY 5 694 #define ICB_DFLT_RCOUNT 3 695 696 697 #define RQRSP_ADDR0015 0 698 #define RQRSP_ADDR1631 1 699 #define RQRSP_ADDR3247 2 700 #define RQRSP_ADDR4863 3 701 702 703 #define ICB_NNM0 7 704 #define ICB_NNM1 6 705 #define ICB_NNM2 5 706 #define ICB_NNM3 4 707 #define ICB_NNM4 3 708 #define ICB_NNM5 2 709 #define ICB_NNM6 1 710 #define ICB_NNM7 0 711 712 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 713 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \ 714 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \ 715 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \ 716 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \ 717 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \ 718 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \ 719 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \ 720 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff) 721 722 /* 723 * FC-AL Position Map 724 * 725 * This is an at most 128 byte map that returns either 726 * the LILP or Firmware generated list of ports. 727 * 728 * We deviate a bit from the returned qlogic format to 729 * use an extra bit to say whether this was a LILP or 730 * f/w generated map. 731 */ 732 typedef struct { 733 u_int8_t fwmap : 1, 734 count : 7; 735 u_int8_t map[127]; 736 } fcpos_map_t; 737 738 /* 739 * Port Data Base Element 740 */ 741 742 typedef struct { 743 u_int16_t pdb_options; 744 u_int8_t pdb_mstate; 745 u_int8_t pdb_sstate; 746 #define BITS2WORD(x) ((x)[0] << 16 | (x)[3] << 8 | (x)[2]) 747 u_int8_t pdb_hardaddr_bits[4]; 748 u_int8_t pdb_portid_bits[4]; 749 u_int8_t pdb_nodename[8]; 750 u_int8_t pdb_portname[8]; 751 u_int16_t pdb_execthrottle; 752 u_int16_t pdb_exec_count; 753 u_int8_t pdb_retry_count; 754 u_int8_t pdb_retry_delay; 755 u_int16_t pdb_resalloc; 756 u_int16_t pdb_curalloc; 757 u_int16_t pdb_qhead; 758 u_int16_t pdb_qtail; 759 u_int16_t pdb_tl_next; 760 u_int16_t pdb_tl_last; 761 u_int16_t pdb_features; /* PLOGI, Common Service */ 762 u_int16_t pdb_pconcurrnt; /* PLOGI, Common Service */ 763 u_int16_t pdb_roi; /* PLOGI, Common Service */ 764 u_int8_t pdb_target; 765 u_int8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */ 766 u_int16_t pdb_rdsiz; /* PLOGI, Class 3 */ 767 u_int16_t pdb_ncseq; /* PLOGI, Class 3 */ 768 u_int16_t pdb_noseq; /* PLOGI, Class 3 */ 769 u_int16_t pdb_labrtflg; 770 u_int16_t pdb_lstopflg; 771 u_int16_t pdb_sqhead; 772 u_int16_t pdb_sqtail; 773 u_int16_t pdb_ptimer; 774 u_int16_t pdb_nxt_seqid; 775 u_int16_t pdb_fcount; 776 u_int16_t pdb_prli_len; 777 u_int16_t pdb_prli_svc0; 778 u_int16_t pdb_prli_svc3; 779 u_int16_t pdb_loopid; 780 u_int16_t pdb_il_ptr; 781 u_int16_t pdb_sl_ptr; 782 } isp_pdb_t; 783 784 #define PDB_OPTIONS_XMITTING (1<<11) 785 #define PDB_OPTIONS_LNKXMIT (1<<10) 786 #define PDB_OPTIONS_ABORTED (1<<9) 787 #define PDB_OPTIONS_ADISC (1<<1) 788 789 #define PDB_STATE_DISCOVERY 0 790 #define PDB_STATE_WDISC_ACK 1 791 #define PDB_STATE_PLOGI 2 792 #define PDB_STATE_PLOGI_ACK 3 793 #define PDB_STATE_PRLI 4 794 #define PDB_STATE_PRLI_ACK 5 795 #define PDB_STATE_LOGGED_IN 6 796 #define PDB_STATE_PORT_UNAVAIL 7 797 #define PDB_STATE_PRLO 8 798 #define PDB_STATE_PRLO_ACK 9 799 #define PDB_STATE_PLOGO 10 800 #define PDB_STATE_PLOG_ACK 11 801 802 #define SVC3_TGT_ROLE 0x10 803 #define SVC3_INI_ROLE 0x20 804 #define SVC3_ROLE_MASK 0x30 805 #define SVC3_ROLE_SHIFT 4 806 807 /* 808 * CT definition 809 * 810 * This is as the QLogic f/w documentations defines it- which is just opposite, 811 * bit wise, from what the specification defines it as. Additionally, the 812 * ct_response and ct_resid (really from FC-GS-2) need to be byte swapped. 813 */ 814 815 typedef struct { 816 u_int8_t ct_revision; 817 u_int8_t ct_portid[3]; 818 u_int8_t ct_fcs_type; 819 u_int8_t ct_fcs_subtype; 820 u_int8_t ct_options; 821 u_int8_t ct_res0; 822 u_int16_t ct_response; 823 u_int16_t ct_resid; 824 u_int8_t ct_res1; 825 u_int8_t ct_reason; 826 u_int8_t ct_explanation; 827 u_int8_t ct_vunique; 828 } ct_hdr_t; 829 #define FS_ACC 0x8002 830 #define FS_RJT 0x8001 831 832 #define FC4_IP 5 /* ISO/EEC 8802-2 LLC/SNAP "Out of Order Delivery" */ 833 #define FC4_SCSI 8 /* SCSI-3 via Fivre Channel Protocol (FCP) */ 834 835 #define SNS_GA_NXT 0x100 836 #define SNS_GPN_ID 0x112 837 #define SNS_GNN_ID 0x113 838 #define SNS_GFF_ID 0x11F 839 #define SNS_GID_FT 0x171 840 #define SNS_RFT_ID 0x217 841 typedef struct { 842 u_int16_t snscb_rblen; /* response buffer length (words) */ 843 u_int16_t snscb_res0; 844 u_int16_t snscb_addr[4]; /* response buffer address */ 845 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 846 u_int16_t snscb_res1; 847 u_int16_t snscb_data[1]; /* variable data */ 848 } sns_screq_t; /* Subcommand Request Structure */ 849 850 typedef struct { 851 u_int16_t snscb_rblen; /* response buffer length (words) */ 852 u_int16_t snscb_res0; 853 u_int16_t snscb_addr[4]; /* response buffer address */ 854 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 855 u_int16_t snscb_res1; 856 u_int16_t snscb_cmd; 857 u_int16_t snscb_res2; 858 u_int32_t snscb_res3; 859 u_int32_t snscb_port; 860 } sns_ga_nxt_req_t; 861 #define SNS_GA_NXT_REQ_SIZE (sizeof (sns_ga_nxt_req_t)) 862 863 typedef struct { 864 u_int16_t snscb_rblen; /* response buffer length (words) */ 865 u_int16_t snscb_res0; 866 u_int16_t snscb_addr[4]; /* response buffer address */ 867 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 868 u_int16_t snscb_res1; 869 u_int16_t snscb_cmd; 870 u_int16_t snscb_res2; 871 u_int32_t snscb_res3; 872 u_int32_t snscb_portid; 873 } sns_gxn_id_req_t; 874 #define SNS_GXN_ID_REQ_SIZE (sizeof (sns_gxn_id_req_t)) 875 876 typedef struct { 877 u_int16_t snscb_rblen; /* response buffer length (words) */ 878 u_int16_t snscb_res0; 879 u_int16_t snscb_addr[4]; /* response buffer address */ 880 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 881 u_int16_t snscb_res1; 882 u_int16_t snscb_cmd; 883 u_int16_t snscb_mword_div_2; 884 u_int32_t snscb_res3; 885 u_int32_t snscb_fc4_type; 886 } sns_gid_ft_req_t; 887 #define SNS_GID_FT_REQ_SIZE (sizeof (sns_gid_ft_req_t)) 888 889 typedef struct { 890 u_int16_t snscb_rblen; /* response buffer length (words) */ 891 u_int16_t snscb_res0; 892 u_int16_t snscb_addr[4]; /* response buffer address */ 893 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 894 u_int16_t snscb_res1; 895 u_int16_t snscb_cmd; 896 u_int16_t snscb_res2; 897 u_int32_t snscb_res3; 898 u_int32_t snscb_port; 899 u_int32_t snscb_fc4_types[8]; 900 } sns_rft_id_req_t; 901 #define SNS_RFT_ID_REQ_SIZE (sizeof (sns_rft_id_req_t)) 902 903 typedef struct { 904 ct_hdr_t snscb_cthdr; 905 u_int8_t snscb_port_type; 906 u_int8_t snscb_port_id[3]; 907 u_int8_t snscb_portname[8]; 908 u_int16_t snscb_data[1]; /* variable data */ 909 } sns_scrsp_t; /* Subcommand Response Structure */ 910 911 typedef struct { 912 ct_hdr_t snscb_cthdr; 913 u_int8_t snscb_port_type; 914 u_int8_t snscb_port_id[3]; 915 u_int8_t snscb_portname[8]; 916 u_int8_t snscb_pnlen; /* symbolic port name length */ 917 u_int8_t snscb_pname[255]; /* symbolic port name */ 918 u_int8_t snscb_nodename[8]; 919 u_int8_t snscb_nnlen; /* symbolic node name length */ 920 u_int8_t snscb_nname[255]; /* symbolic node name */ 921 u_int8_t snscb_ipassoc[8]; 922 u_int8_t snscb_ipaddr[16]; 923 u_int8_t snscb_svc_class[4]; 924 u_int8_t snscb_fc4_types[32]; 925 u_int8_t snscb_fpname[8]; 926 u_int8_t snscb_reserved; 927 u_int8_t snscb_hardaddr[3]; 928 } sns_ga_nxt_rsp_t; /* Subcommand Response Structure */ 929 #define SNS_GA_NXT_RESP_SIZE (sizeof (sns_ga_nxt_rsp_t)) 930 931 typedef struct { 932 ct_hdr_t snscb_cthdr; 933 u_int8_t snscb_wwn[8]; 934 } sns_gxn_id_rsp_t; 935 #define SNS_GXN_ID_RESP_SIZE (sizeof (sns_gxn_id_rsp_t)) 936 937 typedef struct { 938 ct_hdr_t snscb_cthdr; 939 u_int32_t snscb_fc4_features[32]; 940 } sns_gff_id_rsp_t; 941 #define SNS_GFF_ID_RESP_SIZE (sizeof (sns_gff_id_rsp_t)) 942 943 typedef struct { 944 ct_hdr_t snscb_cthdr; 945 struct { 946 u_int8_t control; 947 u_int8_t portid[3]; 948 } snscb_ports[1]; 949 } sns_gid_ft_rsp_t; 950 #define SNS_GID_FT_RESP_SIZE(x) ((sizeof (sns_gid_ft_rsp_t)) + ((x - 1) << 2)) 951 952 #define SNS_RFT_ID_RESP_SIZE (sizeof (ct_hdr_t)) 953 954 #endif /* _ISPMBOX_H */ 955
Indexes created Thu Sep 25 16:09:42 GMT 2025