ispmbox.h revision 1.41
1 /* $NetBSD: ispmbox.h,v 1.41 2002/05/17 18:49:43 mjacob Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob (at) netbsd.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* 31 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. The name of the author may not be used to endorse or promote products 43 * derived from this software without specific prior written permission 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters. 59 * <mjacob (at) nas.nasa.gov> 60 */ 61 #ifndef _ISPMBOX_H 62 #define _ISPMBOX_H 63 64 /* 65 * Mailbox Command Opcodes 66 */ 67 #define MBOX_NO_OP 0x0000 68 #define MBOX_LOAD_RAM 0x0001 69 #define MBOX_EXEC_FIRMWARE 0x0002 70 #define MBOX_DUMP_RAM 0x0003 71 #define MBOX_WRITE_RAM_WORD 0x0004 72 #define MBOX_READ_RAM_WORD 0x0005 73 #define MBOX_MAILBOX_REG_TEST 0x0006 74 #define MBOX_VERIFY_CHECKSUM 0x0007 75 #define MBOX_ABOUT_FIRMWARE 0x0008 76 /* 9 */ 77 /* a */ 78 /* b */ 79 /* c */ 80 /* d */ 81 #define MBOX_CHECK_FIRMWARE 0x000e 82 #define MBOX_READ_RAM_WORD_EXTENDED 0x000f 83 #define MBOX_INIT_REQ_QUEUE 0x0010 84 #define MBOX_INIT_RES_QUEUE 0x0011 85 #define MBOX_EXECUTE_IOCB 0x0012 86 #define MBOX_WAKE_UP 0x0013 87 #define MBOX_STOP_FIRMWARE 0x0014 88 #define MBOX_ABORT 0x0015 89 #define MBOX_ABORT_DEVICE 0x0016 90 #define MBOX_ABORT_TARGET 0x0017 91 #define MBOX_BUS_RESET 0x0018 92 #define MBOX_STOP_QUEUE 0x0019 93 #define MBOX_START_QUEUE 0x001a 94 #define MBOX_SINGLE_STEP_QUEUE 0x001b 95 #define MBOX_ABORT_QUEUE 0x001c 96 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 97 /* 1e */ 98 #define MBOX_GET_FIRMWARE_STATUS 0x001f 99 #define MBOX_GET_INIT_SCSI_ID 0x0020 100 #define MBOX_GET_SELECT_TIMEOUT 0x0021 101 #define MBOX_GET_RETRY_COUNT 0x0022 102 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 103 #define MBOX_GET_CLOCK_RATE 0x0024 104 #define MBOX_GET_ACT_NEG_STATE 0x0025 105 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 106 #define MBOX_GET_SBUS_PARAMS 0x0027 107 #define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS 108 #define MBOX_GET_TARGET_PARAMS 0x0028 109 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 110 #define MBOX_GET_RESET_DELAY_PARAMS 0x002a 111 /* 2b */ 112 /* 2c */ 113 /* 2d */ 114 /* 2e */ 115 /* 2f */ 116 #define MBOX_SET_INIT_SCSI_ID 0x0030 117 #define MBOX_SET_SELECT_TIMEOUT 0x0031 118 #define MBOX_SET_RETRY_COUNT 0x0032 119 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 120 #define MBOX_SET_CLOCK_RATE 0x0034 121 #define MBOX_SET_ACT_NEG_STATE 0x0035 122 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 123 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 124 #define MBOX_SET_PCI_PARAMETERS 0x0037 125 #define MBOX_SET_TARGET_PARAMS 0x0038 126 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 127 #define MBOX_SET_RESET_DELAY_PARAMS 0x003a 128 /* 3b */ 129 /* 3c */ 130 /* 3d */ 131 /* 3e */ 132 /* 3f */ 133 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 134 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 135 #define MBOX_EXEC_BIOS_IOCB 0x0042 136 #define MBOX_SET_FW_FEATURES 0x004a 137 #define MBOX_GET_FW_FEATURES 0x004b 138 #define FW_FEATURE_FAST_POST 0x1 139 #define FW_FEATURE_LVD_NOTIFY 0x2 140 #define FW_FEATURE_RIO_32BIT 0x4 141 #define FW_FEATURE_RIO_16BIT 0x8 142 143 #define MBOX_ENABLE_TARGET_MODE 0x0055 144 #define ENABLE_TARGET_FLAG 0x8000 145 #define ENABLE_TQING_FLAG 0x0004 146 #define ENABLE_MANDATORY_DISC 0x0002 147 #define MBOX_GET_TARGET_STATUS 0x0056 148 149 /* These are for the ISP2X00 FC cards */ 150 #define MBOX_GET_LOOP_ID 0x0020 151 #define MBOX_GET_FIRMWARE_OPTIONS 0x0028 152 #define MBOX_SET_FIRMWARE_OPTIONS 0x0038 153 #define MBOX_GET_RESOURCE_COUNT 0x0042 154 #define MBOX_ENHANCED_GET_PDB 0x0047 155 #define MBOX_EXEC_COMMAND_IOCB_A64 0x0054 156 #define MBOX_INIT_FIRMWARE 0x0060 157 #define MBOX_GET_INIT_CONTROL_BLOCK 0x0061 158 #define MBOX_INIT_LIP 0x0062 159 #define MBOX_GET_FC_AL_POSITION_MAP 0x0063 160 #define MBOX_GET_PORT_DB 0x0064 161 #define MBOX_CLEAR_ACA 0x0065 162 #define MBOX_TARGET_RESET 0x0066 163 #define MBOX_CLEAR_TASK_SET 0x0067 164 #define MBOX_ABORT_TASK_SET 0x0068 165 #define MBOX_GET_FW_STATE 0x0069 166 #define MBOX_GET_PORT_NAME 0x006A 167 #define MBOX_GET_LINK_STATUS 0x006B 168 #define MBOX_INIT_LIP_RESET 0x006C 169 #define MBOX_SEND_SNS 0x006E 170 #define MBOX_FABRIC_LOGIN 0x006F 171 #define MBOX_SEND_CHANGE_REQUEST 0x0070 172 #define MBOX_FABRIC_LOGOUT 0x0071 173 #define MBOX_INIT_LIP_LOGIN 0x0072 174 175 #define MBOX_DRIVER_HEARTBEAT 0x005B 176 #define MBOX_FW_HEARTBEAT 0x005C 177 178 #define MBOX_GET_SET_DATA_RATE 0x005D /* 23XX only */ 179 #define MBGSD_GET_RATE 0 180 #define MBGSD_SET_RATE 1 181 #define MBGSD_ONEGB 0 182 #define MBGSD_TWOGB 1 183 #define MBGSD_AUTO 2 184 185 186 #define ISP2100_SET_PCI_PARAM 0x00ff 187 188 #define MBOX_BUSY 0x04 189 190 typedef struct { 191 u_int16_t param[8]; 192 } mbreg_t; 193 194 /* 195 * Mailbox Command Complete Status Codes 196 */ 197 #define MBOX_COMMAND_COMPLETE 0x4000 198 #define MBOX_INVALID_COMMAND 0x4001 199 #define MBOX_HOST_INTERFACE_ERROR 0x4002 200 #define MBOX_TEST_FAILED 0x4003 201 #define MBOX_COMMAND_ERROR 0x4005 202 #define MBOX_COMMAND_PARAM_ERROR 0x4006 203 #define MBOX_PORT_ID_USED 0x4007 204 #define MBOX_LOOP_ID_USED 0x4008 205 #define MBOX_ALL_IDS_USED 0x4009 206 #define MBOX_NOT_LOGGED_IN 0x400A 207 #define MBLOGALL 0x000f 208 #define MBLOGNONE 0x0000 209 #define MBLOGMASK(x) ((x) & 0xf) 210 211 /* 212 * Asynchronous event status codes 213 */ 214 #define ASYNC_BUS_RESET 0x8001 215 #define ASYNC_SYSTEM_ERROR 0x8002 216 #define ASYNC_RQS_XFER_ERR 0x8003 217 #define ASYNC_RSP_XFER_ERR 0x8004 218 #define ASYNC_QWAKEUP 0x8005 219 #define ASYNC_TIMEOUT_RESET 0x8006 220 #define ASYNC_DEVICE_RESET 0x8007 221 #define ASYNC_EXTMSG_UNDERRUN 0x800A 222 #define ASYNC_SCAM_INT 0x800B 223 #define ASYNC_HUNG_SCSI 0x800C 224 #define ASYNC_KILLED_BUS 0x800D 225 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 226 #define ASYNC_LIP_OCCURRED 0x8010 227 #define ASYNC_LOOP_UP 0x8011 228 #define ASYNC_LOOP_DOWN 0x8012 229 #define ASYNC_LOOP_RESET 0x8013 230 #define ASYNC_PDB_CHANGED 0x8014 231 #define ASYNC_CHANGE_NOTIFY 0x8015 232 #define ASYNC_LIP_F8 0x8016 233 #define ASYNC_CMD_CMPLT 0x8020 234 #define ASYNC_CTIO_DONE 0x8021 235 #define ASYNC_IP_XMIT_DONE 0x8022 236 #define ASYNC_IP_RECV_DONE 0x8023 237 #define ASYNC_IP_BROADCAST 0x8024 238 #define ASYNC_IP_RCVQ_LOW 0x8025 239 #define ASYNC_IP_RCVQ_EMPTY 0x8026 240 #define ASYNC_IP_RECV_DONE_ALIGNED 0x8027 241 #define ASYNC_PTPMODE 0x8030 242 #define ASYNC_RIO1 0x8031 243 #define ASYNC_RIO2 0x8032 244 #define ASYNC_RIO3 0x8033 245 #define ASYNC_RIO4 0x8034 246 #define ASYNC_RIO5 0x8035 247 #define ASYNC_CONNMODE 0x8036 248 #define ISP_CONN_LOOP 1 249 #define ISP_CONN_PTP 2 250 #define ISP_CONN_BADLIP 3 251 #define ISP_CONN_FATAL 4 252 #define ISP_CONN_LOOPBACK 5 253 #define ASYNC_RIO_RESP 0x8040 254 #define ASYNC_RIO_COMP 0x8042 255 /* 256 * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options 257 * mailbox command to enable this. 258 */ 259 #define ASYNC_QFULL_SENT 0x8049 260 261 /* 262 * Mailbox Usages 263 */ 264 265 #define WRITE_REQUEST_QUEUE_IN_POINTER(isp, value) \ 266 ISP_WRITE(isp, isp->isp_rqstinrp, value) 267 268 #define READ_REQUEST_QUEUE_OUT_POINTER(isp) \ 269 ISP_READ(isp, isp->isp_rqstoutrp) 270 271 #define READ_RESPONSE_QUEUE_IN_POINTER(isp) \ 272 ISP_READ(isp, isp->isp_respinrp) 273 274 #define WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, value) \ 275 ISP_WRITE(isp, isp->isp_respoutrp, value) 276 277 /* 278 * Command Structure Definitions 279 */ 280 281 typedef struct { 282 u_int32_t ds_base; 283 u_int32_t ds_count; 284 } ispds_t; 285 286 typedef struct { 287 u_int32_t ds_base; 288 u_int32_t ds_basehi; 289 u_int32_t ds_count; 290 } ispds64_t; 291 292 #define DSTYPE_32BIT 0 293 #define DSTYPE_64BIT 1 294 typedef struct { 295 u_int16_t ds_type; /* 0-> ispds_t, 1-> ispds64_t */ 296 u_int32_t ds_segment; /* unused */ 297 u_int32_t ds_base; /* 32 bit address of DSD list */ 298 } ispdslist_t; 299 300 301 /* 302 * These elements get swizzled around for SBus instances. 303 */ 304 #define ISP_SWAP8(a, b) { \ 305 u_int8_t tmp; \ 306 tmp = a; \ 307 a = b; \ 308 b = tmp; \ 309 } 310 typedef struct { 311 u_int8_t rqs_entry_type; 312 u_int8_t rqs_entry_count; 313 u_int8_t rqs_seqno; 314 u_int8_t rqs_flags; 315 } isphdr_t; 316 317 /* RQS Flag definitions */ 318 #define RQSFLAG_CONTINUATION 0x01 319 #define RQSFLAG_FULL 0x02 320 #define RQSFLAG_BADHEADER 0x04 321 #define RQSFLAG_BADPACKET 0x08 322 323 /* RQS entry_type definitions */ 324 #define RQSTYPE_REQUEST 0x01 325 #define RQSTYPE_DATASEG 0x02 326 #define RQSTYPE_RESPONSE 0x03 327 #define RQSTYPE_MARKER 0x04 328 #define RQSTYPE_CMDONLY 0x05 329 #define RQSTYPE_ATIO 0x06 /* Target Mode */ 330 #define RQSTYPE_CTIO 0x07 /* Target Mode */ 331 #define RQSTYPE_SCAM 0x08 332 #define RQSTYPE_A64 0x09 333 #define RQSTYPE_A64_CONT 0x0a 334 #define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */ 335 #define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */ 336 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 337 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 338 #define RQSTYPE_CTIO1 0x0f /* Target Mode */ 339 #define RQSTYPE_STATUS_CONT 0x10 340 #define RQSTYPE_T2RQS 0x11 341 #define RQSTYPE_IP_XMIT 0x13 342 #define RQSTYPE_T4RQS 0x15 343 #define RQSTYPE_ATIO2 0x16 /* Target Mode */ 344 #define RQSTYPE_CTIO2 0x17 /* Target Mode */ 345 #define RQSTYPE_CSET0 0x18 346 #define RQSTYPE_T3RQS 0x19 347 #define RQSTYPE_IP_XMIT_64 0x1b 348 #define RQSTYPE_CTIO4 0x1e /* Target Mode */ 349 #define RQSTYPE_CTIO3 0x1f /* Target Mode */ 350 #define RQSTYPE_RIO1 0x21 351 #define RQSTYPE_RIO2 0x22 352 #define RQSTYPE_IP_RECV 0x23 353 #define RQSTYPE_IP_RECV_CONT 0x24 354 355 356 #define ISP_RQDSEG 4 357 typedef struct { 358 isphdr_t req_header; 359 u_int32_t req_handle; 360 u_int8_t req_lun_trn; 361 u_int8_t req_target; 362 u_int16_t req_cdblen; 363 #define req_modifier req_cdblen /* marker packet */ 364 u_int16_t req_flags; 365 u_int16_t req_reserved; 366 u_int16_t req_time; 367 u_int16_t req_seg_count; 368 u_int8_t req_cdb[12]; 369 ispds_t req_dataseg[ISP_RQDSEG]; 370 } ispreq_t; 371 372 /* 373 * A request packet can also be a marker packet. 374 */ 375 #define SYNC_DEVICE 0 376 #define SYNC_TARGET 1 377 #define SYNC_ALL 2 378 379 #define ISP_RQDSEG_T2 3 380 typedef struct { 381 isphdr_t req_header; 382 u_int32_t req_handle; 383 u_int8_t req_lun_trn; 384 u_int8_t req_target; 385 u_int16_t req_scclun; 386 u_int16_t req_flags; 387 u_int16_t _res2; 388 u_int16_t req_time; 389 u_int16_t req_seg_count; 390 u_int8_t req_cdb[16]; 391 u_int32_t req_totalcnt; 392 ispds_t req_dataseg[ISP_RQDSEG_T2]; 393 } ispreqt2_t; 394 395 #define ISP_RQDSEG_T3 2 396 typedef struct { 397 isphdr_t req_header; 398 u_int32_t req_handle; 399 u_int8_t req_lun_trn; 400 u_int8_t req_target; 401 u_int16_t req_scclun; 402 u_int16_t req_flags; 403 u_int16_t _res2; 404 u_int16_t req_time; 405 u_int16_t req_seg_count; 406 u_int8_t req_cdb[16]; 407 u_int32_t req_totalcnt; 408 ispds64_t req_dataseg[ISP_RQDSEG_T3]; 409 } ispreqt3_t; 410 411 /* req_flag values */ 412 #define REQFLAG_NODISCON 0x0001 413 #define REQFLAG_HTAG 0x0002 414 #define REQFLAG_OTAG 0x0004 415 #define REQFLAG_STAG 0x0008 416 #define REQFLAG_TARGET_RTN 0x0010 417 418 #define REQFLAG_NODATA 0x0000 419 #define REQFLAG_DATA_IN 0x0020 420 #define REQFLAG_DATA_OUT 0x0040 421 #define REQFLAG_DATA_UNKNOWN 0x0060 422 423 #define REQFLAG_DISARQ 0x0100 424 #define REQFLAG_FRC_ASYNC 0x0200 425 #define REQFLAG_FRC_SYNC 0x0400 426 #define REQFLAG_FRC_WIDE 0x0800 427 #define REQFLAG_NOPARITY 0x1000 428 #define REQFLAG_STOPQ 0x2000 429 #define REQFLAG_XTRASNS 0x4000 430 #define REQFLAG_PRIORITY 0x8000 431 432 typedef struct { 433 isphdr_t req_header; 434 u_int32_t req_handle; 435 u_int8_t req_lun_trn; 436 u_int8_t req_target; 437 u_int16_t req_cdblen; 438 u_int16_t req_flags; 439 u_int16_t _res1; 440 u_int16_t req_time; 441 u_int16_t req_seg_count; 442 u_int8_t req_cdb[44]; 443 } ispextreq_t; 444 445 #define ISP_CDSEG 7 446 typedef struct { 447 isphdr_t req_header; 448 u_int32_t _res1; 449 ispds_t req_dataseg[ISP_CDSEG]; 450 } ispcontreq_t; 451 452 #define ISP_CDSEG64 5 453 typedef struct { 454 isphdr_t req_header; 455 ispds64_t req_dataseg[ISP_CDSEG64]; 456 } ispcontreq64_t; 457 458 typedef struct { 459 isphdr_t req_header; 460 u_int32_t req_handle; 461 u_int16_t req_scsi_status; 462 u_int16_t req_completion_status; 463 u_int16_t req_state_flags; 464 u_int16_t req_status_flags; 465 u_int16_t req_time; 466 #define req_response_len req_time /* FC only */ 467 u_int16_t req_sense_len; 468 u_int32_t req_resid; 469 u_int8_t req_response[8]; /* FC only */ 470 u_int8_t req_sense_data[32]; 471 } ispstatusreq_t; 472 473 typedef struct { 474 isphdr_t req_header; 475 u_int8_t req_sense_data[60]; 476 } ispstatus_cont_t; 477 478 /* 479 * For Qlogic 2X00, the high order byte of SCSI status has 480 * additional meaning. 481 */ 482 #define RQCS_RU 0x800 /* Residual Under */ 483 #define RQCS_RO 0x400 /* Residual Over */ 484 #define RQCS_RESID (RQCS_RU|RQCS_RO) 485 #define RQCS_SV 0x200 /* Sense Length Valid */ 486 #define RQCS_RV 0x100 /* FCP Response Length Valid */ 487 488 /* 489 * Completion Status Codes. 490 */ 491 #define RQCS_COMPLETE 0x0000 492 #define RQCS_DMA_ERROR 0x0002 493 #define RQCS_RESET_OCCURRED 0x0004 494 #define RQCS_ABORTED 0x0005 495 #define RQCS_TIMEOUT 0x0006 496 #define RQCS_DATA_OVERRUN 0x0007 497 #define RQCS_DATA_UNDERRUN 0x0015 498 #define RQCS_QUEUE_FULL 0x001C 499 500 /* 1X00 Only Completion Codes */ 501 #define RQCS_INCOMPLETE 0x0001 502 #define RQCS_TRANSPORT_ERROR 0x0003 503 #define RQCS_COMMAND_OVERRUN 0x0008 504 #define RQCS_STATUS_OVERRUN 0x0009 505 #define RQCS_BAD_MESSAGE 0x000a 506 #define RQCS_NO_MESSAGE_OUT 0x000b 507 #define RQCS_EXT_ID_FAILED 0x000c 508 #define RQCS_IDE_MSG_FAILED 0x000d 509 #define RQCS_ABORT_MSG_FAILED 0x000e 510 #define RQCS_REJECT_MSG_FAILED 0x000f 511 #define RQCS_NOP_MSG_FAILED 0x0010 512 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 513 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 514 #define RQCS_ID_MSG_FAILED 0x0013 515 #define RQCS_UNEXP_BUS_FREE 0x0014 516 #define RQCS_XACT_ERR1 0x0018 517 #define RQCS_XACT_ERR2 0x0019 518 #define RQCS_XACT_ERR3 0x001A 519 #define RQCS_BAD_ENTRY 0x001B 520 #define RQCS_PHASE_SKIPPED 0x001D 521 #define RQCS_ARQS_FAILED 0x001E 522 #define RQCS_WIDE_FAILED 0x001F 523 #define RQCS_SYNCXFER_FAILED 0x0020 524 #define RQCS_LVD_BUSERR 0x0021 525 526 /* 2X00 Only Completion Codes */ 527 #define RQCS_PORT_UNAVAILABLE 0x0028 528 #define RQCS_PORT_LOGGED_OUT 0x0029 529 #define RQCS_PORT_CHANGED 0x002A 530 #define RQCS_PORT_BUSY 0x002B 531 532 /* 533 * 1X00 specific State Flags 534 */ 535 #define RQSF_GOT_BUS 0x0100 536 #define RQSF_GOT_TARGET 0x0200 537 #define RQSF_SENT_CDB 0x0400 538 #define RQSF_XFRD_DATA 0x0800 539 #define RQSF_GOT_STATUS 0x1000 540 #define RQSF_GOT_SENSE 0x2000 541 #define RQSF_XFER_COMPLETE 0x4000 542 543 /* 544 * 2X00 specific State Flags 545 * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available) 546 */ 547 #define RQSF_DATA_IN 0x0020 548 #define RQSF_DATA_OUT 0x0040 549 #define RQSF_STAG 0x0008 550 #define RQSF_OTAG 0x0004 551 #define RQSF_HTAG 0x0002 552 /* 553 * 1X00 Status Flags 554 */ 555 #define RQSTF_DISCONNECT 0x0001 556 #define RQSTF_SYNCHRONOUS 0x0002 557 #define RQSTF_PARITY_ERROR 0x0004 558 #define RQSTF_BUS_RESET 0x0008 559 #define RQSTF_DEVICE_RESET 0x0010 560 #define RQSTF_ABORTED 0x0020 561 #define RQSTF_TIMEOUT 0x0040 562 #define RQSTF_NEGOTIATION 0x0080 563 564 /* 565 * 2X00 specific state flags 566 */ 567 /* RQSF_SENT_CDB */ 568 /* RQSF_XFRD_DATA */ 569 /* RQSF_GOT_STATUS */ 570 /* RQSF_XFER_COMPLETE */ 571 572 /* 573 * 2X00 specific status flags 574 */ 575 /* RQSTF_ABORTED */ 576 /* RQSTF_TIMEOUT */ 577 #define RQSTF_DMA_ERROR 0x0080 578 #define RQSTF_LOGOUT 0x2000 579 580 /* 581 * Miscellaneous 582 */ 583 #ifndef ISP_EXEC_THROTTLE 584 #define ISP_EXEC_THROTTLE 16 585 #endif 586 587 /* 588 * About Firmware returns an 'attribute' word in mailbox 6. 589 */ 590 #define ISP_FW_ATTR_TMODE 0x01 591 #define ISP_FW_ATTR_SCCLUN 0x02 592 #define ISP_FW_ATTR_FABRIC 0x04 593 #define ISP_FW_ATTR_CLASS2 0x08 594 #define ISP_FW_ATTR_FCTAPE 0x10 595 #define ISP_FW_ATTR_IP 0x20 596 597 /* 598 * Reduced Interrupt Operation Response Queue Entreis 599 */ 600 601 typedef struct { 602 isphdr_t req_header; 603 u_int32_t req_handles[15]; 604 } isp_rio1_t; 605 606 typedef struct { 607 isphdr_t req_header; 608 u_int16_t req_handles[30]; 609 } isp_rio2_t; 610 611 /* 612 * FC (ISP2100) specific data structures 613 */ 614 615 /* 616 * Initialization Control Block 617 * 618 * Version One (prime) format. 619 */ 620 typedef struct isp_icb { 621 u_int8_t icb_version; 622 u_int8_t _reserved0; 623 u_int16_t icb_fwoptions; 624 u_int16_t icb_maxfrmlen; 625 u_int16_t icb_maxalloc; 626 u_int16_t icb_execthrottle; 627 u_int8_t icb_retry_count; 628 u_int8_t icb_retry_delay; 629 u_int8_t icb_portname[8]; 630 u_int16_t icb_hardaddr; 631 u_int8_t icb_iqdevtype; 632 u_int8_t icb_logintime; 633 u_int8_t icb_nodename[8]; 634 u_int16_t icb_rqstout; 635 u_int16_t icb_rspnsin; 636 u_int16_t icb_rqstqlen; 637 u_int16_t icb_rsltqlen; 638 u_int16_t icb_rqstaddr[4]; 639 u_int16_t icb_respaddr[4]; 640 u_int16_t icb_lunenables; 641 u_int8_t icb_ccnt; 642 u_int8_t icb_icnt; 643 u_int16_t icb_lunetimeout; 644 u_int16_t _reserved1; 645 u_int16_t icb_xfwoptions; 646 u_int8_t icb_racctimer; 647 u_int8_t icb_idelaytimer; 648 u_int16_t icb_zfwoptions; 649 u_int16_t _reserved2[13]; 650 } isp_icb_t; 651 #define ICB_VERSION1 1 652 653 #define ICBOPT_HARD_ADDRESS 0x0001 654 #define ICBOPT_FAIRNESS 0x0002 655 #define ICBOPT_FULL_DUPLEX 0x0004 656 #define ICBOPT_FAST_POST 0x0008 657 #define ICBOPT_TGT_ENABLE 0x0010 658 #define ICBOPT_INI_DISABLE 0x0020 659 #define ICBOPT_INI_ADISC 0x0040 660 #define ICBOPT_INI_TGTTYPE 0x0080 661 #define ICBOPT_PDBCHANGE_AE 0x0100 662 #define ICBOPT_NOLIP 0x0200 663 #define ICBOPT_SRCHDOWN 0x0400 664 #define ICBOPT_PREVLOOP 0x0800 665 #define ICBOPT_STOP_ON_QFULL 0x1000 666 #define ICBOPT_FULL_LOGIN 0x2000 667 #define ICBOPT_BOTH_WWNS 0x4000 668 #define ICBOPT_EXTENDED 0x8000 669 670 #define ICBXOPT_CLASS2_ACK0 0x0200 671 #define ICBXOPT_CLASS2 0x0100 672 #define ICBXOPT_LOOP_ONLY (0 << 4) 673 #define ICBXOPT_PTP_ONLY (1 << 4) 674 #define ICBXOPT_LOOP_2_PTP (2 << 4) 675 #define ICBXOPT_PTP_2_LOOP (3 << 4) 676 677 #define ICBXOPT_RIO_OFF 0 678 #define ICBXOPT_RIO_16BIT 1 679 #define ICBXOPT_RIO_32BIT 2 680 #define ICBXOPT_RIO_16BIT_IOCB 3 681 #define ICBXOPT_RIO_32BIT_IOCB 4 682 683 #define ICBZOPT_ENA_RDXFR_RDY 0x01 684 #define ICBZOPT_ENA_OOF (1 << 6) /* out of order frame handling */ 685 /* These 3 only apply to the 2300 */ 686 #define ICBZOPT_RATE_ONEGB (MBGSD_ONEGB << 14) 687 #define ICBZOPT_RATE_TWOGB (MBGSD_TWOGB << 14) 688 #define ICBZOPT_RATE_AUTO (MBGSD_AUTO << 14) 689 690 691 #define ICB_MIN_FRMLEN 256 692 #define ICB_MAX_FRMLEN 2112 693 #define ICB_DFLT_FRMLEN 1024 694 #define ICB_DFLT_ALLOC 256 695 #define ICB_DFLT_THROTTLE 16 696 #define ICB_DFLT_RDELAY 5 697 #define ICB_DFLT_RCOUNT 3 698 699 700 #define RQRSP_ADDR0015 0 701 #define RQRSP_ADDR1631 1 702 #define RQRSP_ADDR3247 2 703 #define RQRSP_ADDR4863 3 704 705 706 #define ICB_NNM0 7 707 #define ICB_NNM1 6 708 #define ICB_NNM2 5 709 #define ICB_NNM3 4 710 #define ICB_NNM4 3 711 #define ICB_NNM5 2 712 #define ICB_NNM6 1 713 #define ICB_NNM7 0 714 715 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 716 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \ 717 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \ 718 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \ 719 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \ 720 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \ 721 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \ 722 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \ 723 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff) 724 725 /* 726 * FC-AL Position Map 727 * 728 * This is an at most 128 byte map that returns either 729 * the LILP or Firmware generated list of ports. 730 * 731 * We deviate a bit from the returned qlogic format to 732 * use an extra bit to say whether this was a LILP or 733 * f/w generated map. 734 */ 735 typedef struct { 736 u_int8_t fwmap : 1, 737 count : 7; 738 u_int8_t map[127]; 739 } fcpos_map_t; 740 741 /* 742 * Port Data Base Element 743 */ 744 745 typedef struct { 746 u_int16_t pdb_options; 747 u_int8_t pdb_mstate; 748 u_int8_t pdb_sstate; 749 #define BITS2WORD(x) ((x)[0] << 16 | (x)[3] << 8 | (x)[2]) 750 u_int8_t pdb_hardaddr_bits[4]; 751 u_int8_t pdb_portid_bits[4]; 752 u_int8_t pdb_nodename[8]; 753 u_int8_t pdb_portname[8]; 754 u_int16_t pdb_execthrottle; 755 u_int16_t pdb_exec_count; 756 u_int8_t pdb_retry_count; 757 u_int8_t pdb_retry_delay; 758 u_int16_t pdb_resalloc; 759 u_int16_t pdb_curalloc; 760 u_int16_t pdb_qhead; 761 u_int16_t pdb_qtail; 762 u_int16_t pdb_tl_next; 763 u_int16_t pdb_tl_last; 764 u_int16_t pdb_features; /* PLOGI, Common Service */ 765 u_int16_t pdb_pconcurrnt; /* PLOGI, Common Service */ 766 u_int16_t pdb_roi; /* PLOGI, Common Service */ 767 u_int8_t pdb_target; 768 u_int8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */ 769 u_int16_t pdb_rdsiz; /* PLOGI, Class 3 */ 770 u_int16_t pdb_ncseq; /* PLOGI, Class 3 */ 771 u_int16_t pdb_noseq; /* PLOGI, Class 3 */ 772 u_int16_t pdb_labrtflg; 773 u_int16_t pdb_lstopflg; 774 u_int16_t pdb_sqhead; 775 u_int16_t pdb_sqtail; 776 u_int16_t pdb_ptimer; 777 u_int16_t pdb_nxt_seqid; 778 u_int16_t pdb_fcount; 779 u_int16_t pdb_prli_len; 780 u_int16_t pdb_prli_svc0; 781 u_int16_t pdb_prli_svc3; 782 u_int16_t pdb_loopid; 783 u_int16_t pdb_il_ptr; 784 u_int16_t pdb_sl_ptr; 785 } isp_pdb_t; 786 787 #define PDB_OPTIONS_XMITTING (1<<11) 788 #define PDB_OPTIONS_LNKXMIT (1<<10) 789 #define PDB_OPTIONS_ABORTED (1<<9) 790 #define PDB_OPTIONS_ADISC (1<<1) 791 792 #define PDB_STATE_DISCOVERY 0 793 #define PDB_STATE_WDISC_ACK 1 794 #define PDB_STATE_PLOGI 2 795 #define PDB_STATE_PLOGI_ACK 3 796 #define PDB_STATE_PRLI 4 797 #define PDB_STATE_PRLI_ACK 5 798 #define PDB_STATE_LOGGED_IN 6 799 #define PDB_STATE_PORT_UNAVAIL 7 800 #define PDB_STATE_PRLO 8 801 #define PDB_STATE_PRLO_ACK 9 802 #define PDB_STATE_PLOGO 10 803 #define PDB_STATE_PLOG_ACK 11 804 805 #define SVC3_TGT_ROLE 0x10 806 #define SVC3_INI_ROLE 0x20 807 #define SVC3_ROLE_MASK 0x30 808 #define SVC3_ROLE_SHIFT 4 809 810 /* 811 * CT definition 812 * 813 * This is as the QLogic f/w documentations defines it- which is just opposite, 814 * bit wise, from what the specification defines it as. Additionally, the 815 * ct_response and ct_resid (really from FC-GS-2) need to be byte swapped. 816 */ 817 818 typedef struct { 819 u_int8_t ct_revision; 820 u_int8_t ct_portid[3]; 821 u_int8_t ct_fcs_type; 822 u_int8_t ct_fcs_subtype; 823 u_int8_t ct_options; 824 u_int8_t ct_res0; 825 u_int16_t ct_response; 826 u_int16_t ct_resid; 827 u_int8_t ct_res1; 828 u_int8_t ct_reason; 829 u_int8_t ct_explanation; 830 u_int8_t ct_vunique; 831 } ct_hdr_t; 832 #define FS_ACC 0x8002 833 #define FS_RJT 0x8001 834 835 #define FC4_IP 5 /* ISO/EEC 8802-2 LLC/SNAP "Out of Order Delivery" */ 836 #define FC4_SCSI 8 /* SCSI-3 via Fivre Channel Protocol (FCP) */ 837 838 #define SNS_GA_NXT 0x100 839 #define SNS_GPN_ID 0x112 840 #define SNS_GNN_ID 0x113 841 #define SNS_GFF_ID 0x11F 842 #define SNS_GID_FT 0x171 843 #define SNS_RFT_ID 0x217 844 typedef struct { 845 u_int16_t snscb_rblen; /* response buffer length (words) */ 846 u_int16_t snscb_res0; 847 u_int16_t snscb_addr[4]; /* response buffer address */ 848 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 849 u_int16_t snscb_res1; 850 u_int16_t snscb_data[1]; /* variable data */ 851 } sns_screq_t; /* Subcommand Request Structure */ 852 853 typedef struct { 854 u_int16_t snscb_rblen; /* response buffer length (words) */ 855 u_int16_t snscb_res0; 856 u_int16_t snscb_addr[4]; /* response buffer address */ 857 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 858 u_int16_t snscb_res1; 859 u_int16_t snscb_cmd; 860 u_int16_t snscb_res2; 861 u_int32_t snscb_res3; 862 u_int32_t snscb_port; 863 } sns_ga_nxt_req_t; 864 #define SNS_GA_NXT_REQ_SIZE (sizeof (sns_ga_nxt_req_t)) 865 866 typedef struct { 867 u_int16_t snscb_rblen; /* response buffer length (words) */ 868 u_int16_t snscb_res0; 869 u_int16_t snscb_addr[4]; /* response buffer address */ 870 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 871 u_int16_t snscb_res1; 872 u_int16_t snscb_cmd; 873 u_int16_t snscb_res2; 874 u_int32_t snscb_res3; 875 u_int32_t snscb_portid; 876 } sns_gxn_id_req_t; 877 #define SNS_GXN_ID_REQ_SIZE (sizeof (sns_gxn_id_req_t)) 878 879 typedef struct { 880 u_int16_t snscb_rblen; /* response buffer length (words) */ 881 u_int16_t snscb_res0; 882 u_int16_t snscb_addr[4]; /* response buffer address */ 883 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 884 u_int16_t snscb_res1; 885 u_int16_t snscb_cmd; 886 u_int16_t snscb_mword_div_2; 887 u_int32_t snscb_res3; 888 u_int32_t snscb_fc4_type; 889 } sns_gid_ft_req_t; 890 #define SNS_GID_FT_REQ_SIZE (sizeof (sns_gid_ft_req_t)) 891 892 typedef struct { 893 u_int16_t snscb_rblen; /* response buffer length (words) */ 894 u_int16_t snscb_res0; 895 u_int16_t snscb_addr[4]; /* response buffer address */ 896 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 897 u_int16_t snscb_res1; 898 u_int16_t snscb_cmd; 899 u_int16_t snscb_res2; 900 u_int32_t snscb_res3; 901 u_int32_t snscb_port; 902 u_int32_t snscb_fc4_types[8]; 903 } sns_rft_id_req_t; 904 #define SNS_RFT_ID_REQ_SIZE (sizeof (sns_rft_id_req_t)) 905 906 typedef struct { 907 ct_hdr_t snscb_cthdr; 908 u_int8_t snscb_port_type; 909 u_int8_t snscb_port_id[3]; 910 u_int8_t snscb_portname[8]; 911 u_int16_t snscb_data[1]; /* variable data */ 912 } sns_scrsp_t; /* Subcommand Response Structure */ 913 914 typedef struct { 915 ct_hdr_t snscb_cthdr; 916 u_int8_t snscb_port_type; 917 u_int8_t snscb_port_id[3]; 918 u_int8_t snscb_portname[8]; 919 u_int8_t snscb_pnlen; /* symbolic port name length */ 920 u_int8_t snscb_pname[255]; /* symbolic port name */ 921 u_int8_t snscb_nodename[8]; 922 u_int8_t snscb_nnlen; /* symbolic node name length */ 923 u_int8_t snscb_nname[255]; /* symbolic node name */ 924 u_int8_t snscb_ipassoc[8]; 925 u_int8_t snscb_ipaddr[16]; 926 u_int8_t snscb_svc_class[4]; 927 u_int8_t snscb_fc4_types[32]; 928 u_int8_t snscb_fpname[8]; 929 u_int8_t snscb_reserved; 930 u_int8_t snscb_hardaddr[3]; 931 } sns_ga_nxt_rsp_t; /* Subcommand Response Structure */ 932 #define SNS_GA_NXT_RESP_SIZE (sizeof (sns_ga_nxt_rsp_t)) 933 934 typedef struct { 935 ct_hdr_t snscb_cthdr; 936 u_int8_t snscb_wwn[8]; 937 } sns_gxn_id_rsp_t; 938 #define SNS_GXN_ID_RESP_SIZE (sizeof (sns_gxn_id_rsp_t)) 939 940 typedef struct { 941 ct_hdr_t snscb_cthdr; 942 u_int32_t snscb_fc4_features[32]; 943 } sns_gff_id_rsp_t; 944 #define SNS_GFF_ID_RESP_SIZE (sizeof (sns_gff_id_rsp_t)) 945 946 typedef struct { 947 ct_hdr_t snscb_cthdr; 948 struct { 949 u_int8_t control; 950 u_int8_t portid[3]; 951 } snscb_ports[1]; 952 } sns_gid_ft_rsp_t; 953 #define SNS_GID_FT_RESP_SIZE(x) ((sizeof (sns_gid_ft_rsp_t)) + ((x - 1) << 2)) 954 955 #define SNS_RFT_ID_RESP_SIZE (sizeof (ct_hdr_t)) 956 957 #endif /* _ISPMBOX_H */ 958
Indexes created Wed Sep 24 05:09:52 GMT 2025