ispmbox.h revision 1.6
1 /* $NetBSD: */ 2 /* $Id: ispmbox.h,v 1.6 1998/07/15 19:50:16 mjacob Exp $ */ 3 /* 4 * Mailbox and Command Definitions for for Qlogic ISP SCSI adapters. 5 * 6 *--------------------------------------- 7 * Copyright (c) 1997, 1998 by Matthew Jacob 8 * NASA/Ames Research Center 9 * All rights reserved. 10 *--------------------------------------- 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice immediately at the beginning of the file, without modification, 17 * this list of conditions, and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 #ifndef _ISPMBOX_H 38 #define _ISPMBOX_H 39 40 /* 41 * Mailbox Command Opcodes 42 */ 43 44 #define MBOX_NO_OP 0x0000 45 #define MBOX_LOAD_RAM 0x0001 46 #define MBOX_EXEC_FIRMWARE 0x0002 47 #define MBOX_DUMP_RAM 0x0003 48 #define MBOX_WRITE_RAM_WORD 0x0004 49 #define MBOX_READ_RAM_WORD 0x0005 50 #define MBOX_MAILBOX_REG_TEST 0x0006 51 #define MBOX_VERIFY_CHECKSUM 0x0007 52 #define MBOX_ABOUT_FIRMWARE 0x0008 53 /* 9 */ 54 /* a */ 55 /* b */ 56 /* c */ 57 /* d */ 58 #define MBOX_CHECK_FIRMWARE 0x000e 59 /* f */ 60 #define MBOX_INIT_REQ_QUEUE 0x0010 61 #define MBOX_INIT_RES_QUEUE 0x0011 62 #define MBOX_EXECUTE_IOCB 0x0012 63 #define MBOX_WAKE_UP 0x0013 64 #define MBOX_STOP_FIRMWARE 0x0014 65 #define MBOX_ABORT 0x0015 66 #define MBOX_ABORT_DEVICE 0x0016 67 #define MBOX_ABORT_TARGET 0x0017 68 #define MBOX_BUS_RESET 0x0018 69 #define MBOX_STOP_QUEUE 0x0019 70 #define MBOX_START_QUEUE 0x001a 71 #define MBOX_SINGLE_STEP_QUEUE 0x001b 72 #define MBOX_ABORT_QUEUE 0x001c 73 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 74 /* 1e */ 75 #define MBOX_GET_FIRMWARE_STATUS 0x001f 76 #define MBOX_GET_INIT_SCSI_ID 0x0020 77 #define MBOX_GET_SELECT_TIMEOUT 0x0021 78 #define MBOX_GET_RETRY_COUNT 0x0022 79 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 80 #define MBOX_GET_CLOCK_RATE 0x0024 81 #define MBOX_GET_ACT_NEG_STATE 0x0025 82 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 83 #define MBOX_GET_SBUS_PARAMS 0x0027 84 #define MBOX_GET_TARGET_PARAMS 0x0028 85 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 86 /* 2a */ 87 /* 2b */ 88 /* 2c */ 89 /* 2d */ 90 /* 2e */ 91 /* 2f */ 92 #define MBOX_SET_INIT_SCSI_ID 0x0030 93 #define MBOX_SET_SELECT_TIMEOUT 0x0031 94 #define MBOX_SET_RETRY_COUNT 0x0032 95 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 96 #define MBOX_SET_CLOCK_RATE 0x0034 97 #define MBOX_SET_ACTIVE_NEG_STATE 0x0035 98 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 99 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 100 #define MBOX_SET_PCI_PARAMETERS 0x0037 101 #define MBOX_SET_TARGET_PARAMS 0x0038 102 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 103 /* 3a */ 104 /* 3b */ 105 /* 3c */ 106 /* 3d */ 107 /* 3e */ 108 /* 3f */ 109 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 110 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 111 #define MBOX_EXEC_BIOS_IOCB 0x0042 112 113 /* These are for the ISP2100 FC cards */ 114 #define MBOX_GET_LOOP_ID 0x20 115 #define MBOX_EXEC_COMMAND_IOCB_A64 0x54 116 #define MBOX_INIT_FIRMWARE 0x60 117 #define MBOX_GET_INIT_CONTROL_BLOCK 0x61 118 #define MBOX_INIT_LIP 0x62 119 #define MBOX_GET_FC_AL_POSITION_MAP 0x63 120 #define MBOX_GET_PORT_DB 0x64 121 #define MBOX_CLEAR_ACA 0x65 122 #define MBOX_TARGET_RESET 0x66 123 #define MBOX_CLEAR_TASK_SET 0x67 124 #define MBOX_ABORT_TASK_SET 0x68 125 #define MBOX_GET_FW_STATE 0x69 126 127 #define ISP2100_SET_PCI_PARAM 0x00ff 128 129 #define MBOX_BUSY 0x04 130 131 typedef struct { 132 u_int16_t param[8]; 133 } mbreg_t; 134 135 /* 136 * Command Structure Definitions 137 */ 138 139 typedef struct { 140 u_int32_t ds_base; 141 u_int32_t ds_count; 142 } ispds_t; 143 144 typedef struct { 145 #if BYTE_ORDER == BIG_ENDIAN 146 u_int8_t rqs_entry_count; 147 u_int8_t rqs_entry_type; 148 u_int8_t rqs_flags; 149 u_int8_t rqs_seqno; 150 #else 151 u_int8_t rqs_entry_type; 152 u_int8_t rqs_entry_count; 153 u_int8_t rqs_seqno; 154 u_int8_t rqs_flags; 155 #endif 156 } isphdr_t; 157 158 /* RQS Flag definitions */ 159 #define RQSFLAG_CONTINUATION 0x01 160 #define RQSFLAG_FULL 0x02 161 #define RQSFLAG_BADHEADER 0x04 162 #define RQSFLAG_BADPACKET 0x08 163 164 /* RQS entry_type definitions */ 165 #define RQSTYPE_REQUEST 1 166 #define RQSTYPE_DATASEG 2 167 #define RQSTYPE_RESPONSE 3 168 #define RQSTYPE_MARKER 4 169 #define RQSTYPE_CMDONLY 5 170 #define RQSTYPE_T2RQS 17 171 #define RQSTYPE_T3RQS 25 172 #define RQSTYPE_T1DSEG 10 173 174 175 #define ISP_RQDSEG 4 176 typedef struct { 177 isphdr_t req_header; 178 u_int32_t req_handle; 179 #if BYTE_ORDER == BIG_ENDIAN 180 u_int8_t req_target; 181 u_int8_t req_lun_trn; 182 #else 183 u_int8_t req_lun_trn; 184 u_int8_t req_target; 185 #endif 186 u_int16_t req_cdblen; 187 #define req_modifier req_cdblen /* marker packet */ 188 u_int16_t req_flags; 189 u_int16_t _res1; 190 u_int16_t req_time; 191 u_int16_t req_seg_count; 192 u_int8_t req_cdb[12]; 193 ispds_t req_dataseg[ISP_RQDSEG]; 194 } ispreq_t; 195 196 #define ISP_RQDSEG_T2 3 197 typedef struct { 198 isphdr_t req_header; 199 u_int32_t req_handle; 200 #if BYTE_ORDER == BIG_ENDIAN 201 u_int8_t req_target; 202 u_int8_t req_lun_trn; 203 #else 204 u_int8_t req_lun_trn; 205 u_int8_t req_target; 206 #endif 207 u_int16_t _res1; 208 u_int16_t req_flags; 209 u_int16_t _res2; 210 u_int16_t req_time; 211 u_int16_t req_seg_count; 212 u_int32_t req_cdb[4]; 213 u_int32_t req_totalcnt; 214 ispds_t req_dataseg[ISP_RQDSEG_T2]; 215 } ispreqt2_t; 216 217 /* req_flag values */ 218 #define REQFLAG_NODISCON 0x0001 219 #define REQFLAG_HTAG 0x0002 220 #define REQFLAG_OTAG 0x0004 221 #define REQFLAG_STAG 0x0008 222 #define REQFLAG_TARGET_RTN 0x0010 223 224 #define REQFLAG_NODATA 0x0000 225 #define REQFLAG_DATA_IN 0x0020 226 #define REQFLAG_DATA_OUT 0x0040 227 #define REQFLAG_DATA_UNKNOWN 0x0060 228 229 #define REQFLAG_DISARQ 0x0100 230 231 typedef struct { 232 isphdr_t req_header; 233 u_int32_t req_handle; 234 #if BYTE_ORDER == BIG_ENDIAN 235 u_int8_t req_target; 236 u_int8_t req_lun_trn; 237 #else 238 u_int8_t req_lun_trn; 239 u_int8_t req_target; 240 #endif 241 u_int16_t req_cdblen; 242 u_int16_t req_flags; 243 u_int16_t _res1; 244 u_int16_t req_time; 245 u_int16_t req_seg_count; 246 u_int8_t req_cdb[44]; 247 } ispextreq_t; 248 249 #define ISP_CDSEG 7 250 typedef struct { 251 isphdr_t req_header; 252 u_int32_t _res1; 253 ispds_t req_dataseg[ISP_CDSEG]; 254 } ispcontreq_t; 255 256 typedef struct { 257 isphdr_t req_header; 258 u_int32_t _res1; 259 #if BYTE_ORDER == BIG_ENDIAN 260 u_int8_t req_target; 261 u_int8_t req_lun_trn; 262 u_int8_t _res2; 263 u_int8_t req_modifier; 264 #else 265 u_int8_t req_lun_trn; 266 u_int8_t req_target; 267 u_int8_t req_modifier; 268 u_int8_t _res2; 269 #endif 270 } ispmarkreq_t; 271 272 #define SYNC_DEVICE 0 273 #define SYNC_TARGET 1 274 #define SYNC_ALL 2 275 276 typedef struct { 277 isphdr_t req_header; 278 u_int32_t req_handle; 279 u_int16_t req_scsi_status; 280 u_int16_t req_completion_status; 281 u_int16_t req_state_flags; 282 u_int16_t req_status_flags; 283 u_int16_t req_time; 284 u_int16_t req_sense_len; 285 u_int32_t req_resid; 286 u_int8_t _res1[8]; 287 u_int8_t req_sense_data[32]; 288 } ispstatusreq_t; 289 290 /* 291 * For Qlogic 2100, the high order byte of SCSI status has 292 * additional meaning. 293 */ 294 #define RQCS_RU 0x800 /* Residual Under */ 295 #define RQCS_RO 0x400 /* Residual Over */ 296 #define RQCS_SV 0x200 /* Sense Length Valid */ 297 #define RQCS_RV 0x100 /* Residual Valid */ 298 299 /* 300 * Completion Status Codes. 301 */ 302 #define RQCS_COMPLETE 0x0000 303 #define RQCS_INCOMPLETE 0x0001 304 #define RQCS_DMA_ERROR 0x0002 305 #define RQCS_TRANSPORT_ERROR 0x0003 306 #define RQCS_RESET_OCCURRED 0x0004 307 #define RQCS_ABORTED 0x0005 308 #define RQCS_TIMEOUT 0x0006 309 #define RQCS_DATA_OVERRUN 0x0007 310 #define RQCS_COMMAND_OVERRUN 0x0008 311 #define RQCS_STATUS_OVERRUN 0x0009 312 #define RQCS_BAD_MESSAGE 0x000a 313 #define RQCS_NO_MESSAGE_OUT 0x000b 314 #define RQCS_EXT_ID_FAILED 0x000c 315 #define RQCS_IDE_MSG_FAILED 0x000d 316 #define RQCS_ABORT_MSG_FAILED 0x000e 317 #define RQCS_REJECT_MSG_FAILED 0x000f 318 #define RQCS_NOP_MSG_FAILED 0x0010 319 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 320 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 321 #define RQCS_ID_MSG_FAILED 0x0013 322 #define RQCS_UNEXP_BUS_FREE 0x0014 323 #define RQCS_DATA_UNDERRUN 0x0015 324 /* 2100 Only Completion Codes */ 325 #define RQCS_PORT_UNAVAILABLE 0x0028 326 #define RQCS_PORT_LOGGED_OUT 0x0029 327 #define RQCS_PORT_CHANGED 0x002A 328 #define RQCS_PORT_BUSY 0x002B 329 330 /* 331 * State Flags (not applicable to 2100) 332 */ 333 #define RQSF_GOT_BUS 0x0100 334 #define RQSF_GOT_TARGET 0x0200 335 #define RQSF_SENT_CDB 0x0400 336 #define RQSF_XFRD_DATA 0x0800 337 #define RQSF_GOT_STATUS 0x1000 338 #define RQSF_GOT_SENSE 0x2000 339 #define RQSF_XFER_COMPLETE 0x4000 340 341 /* 342 * Status Flags (not applicable to 2100) 343 */ 344 #define RQSTF_DISCONNECT 0x0001 345 #define RQSTF_SYNCHRONOUS 0x0002 346 #define RQSTF_PARITY_ERROR 0x0004 347 #define RQSTF_BUS_RESET 0x0008 348 #define RQSTF_DEVICE_RESET 0x0010 349 #define RQSTF_ABORTED 0x0020 350 #define RQSTF_TIMEOUT 0x0040 351 #define RQSTF_NEGOTIATION 0x0080 352 353 /* 354 * FC (ISP2100) specific data structures 355 */ 356 357 /* 358 * Initialization Control Block 359 */ 360 typedef struct { 361 #if BYTE_ORDER == BIG_ENDIAN 362 u_int8_t _reserved0; 363 u_int8_t icb_version; 364 #else 365 u_int8_t icb_version; 366 u_int8_t _reserved0; 367 #endif 368 u_int16_t icb_fwoptions; 369 u_int16_t icb_maxfrmlen; 370 u_int16_t icb_maxalloc; 371 u_int16_t icb_execthrottle; 372 #if BYTE_ORDER == BIG_ENDIAN 373 u_int8_t icb_retry_delay; 374 u_int8_t icb_retry_count; 375 #else 376 u_int8_t icb_retry_count; 377 u_int8_t icb_retry_delay; 378 #endif 379 u_int16_t icb_nodename[4]; 380 u_int16_t icb_hardaddr; 381 u_int16_t _reserved1[5]; 382 u_int16_t icb_rqstout; 383 u_int16_t icb_rspnsin; 384 u_int16_t icb_rqstqlen; 385 u_int16_t icb_rsltqlen; 386 u_int16_t icb_rqstaddr[4]; 387 u_int16_t icb_respaddr[4]; 388 } isp_icb_t; 389 390 #define ICB_DFLT_FRMLEN 1024 391 #define MAKE_NODE_NAME(isp, icbp) \ 392 (icbp)->icb_nodename[0] = 0, (icbp)->icb_nodename[1] = 0x5355,\ 393 (icbp)->icb_nodename[2] = 0x4E57, (icbp)->icb_nodename[3] = 0 394 395 #endif /* _ISPMBOX_H */ 396
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