ispmbox.h revision 1.8
1 /* $Id: ispmbox.h,v 1.8 1998/09/08 07:24:23 mjacob Exp $ */ 2 /* 3 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters. 4 * 5 *--------------------------------------- 6 * Copyright (c) 1997, 1998 by Matthew Jacob 7 * NASA/Ames Research Center 8 * All rights reserved. 9 *--------------------------------------- 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice immediately at the beginning of the file, without modification, 16 * this list of conditions, and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 #ifndef _ISPMBOX_H 37 #define _ISPMBOX_H 38 39 /* 40 * Mailbox Command Opcodes 41 */ 42 43 #define MBOX_NO_OP 0x0000 44 #define MBOX_LOAD_RAM 0x0001 45 #define MBOX_EXEC_FIRMWARE 0x0002 46 #define MBOX_DUMP_RAM 0x0003 47 #define MBOX_WRITE_RAM_WORD 0x0004 48 #define MBOX_READ_RAM_WORD 0x0005 49 #define MBOX_MAILBOX_REG_TEST 0x0006 50 #define MBOX_VERIFY_CHECKSUM 0x0007 51 #define MBOX_ABOUT_FIRMWARE 0x0008 52 /* 9 */ 53 /* a */ 54 /* b */ 55 /* c */ 56 /* d */ 57 #define MBOX_CHECK_FIRMWARE 0x000e 58 /* f */ 59 #define MBOX_INIT_REQ_QUEUE 0x0010 60 #define MBOX_INIT_RES_QUEUE 0x0011 61 #define MBOX_EXECUTE_IOCB 0x0012 62 #define MBOX_WAKE_UP 0x0013 63 #define MBOX_STOP_FIRMWARE 0x0014 64 #define MBOX_ABORT 0x0015 65 #define MBOX_ABORT_DEVICE 0x0016 66 #define MBOX_ABORT_TARGET 0x0017 67 #define MBOX_BUS_RESET 0x0018 68 #define MBOX_STOP_QUEUE 0x0019 69 #define MBOX_START_QUEUE 0x001a 70 #define MBOX_SINGLE_STEP_QUEUE 0x001b 71 #define MBOX_ABORT_QUEUE 0x001c 72 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 73 /* 1e */ 74 #define MBOX_GET_FIRMWARE_STATUS 0x001f 75 #define MBOX_GET_INIT_SCSI_ID 0x0020 76 #define MBOX_GET_SELECT_TIMEOUT 0x0021 77 #define MBOX_GET_RETRY_COUNT 0x0022 78 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 79 #define MBOX_GET_CLOCK_RATE 0x0024 80 #define MBOX_GET_ACT_NEG_STATE 0x0025 81 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 82 #define MBOX_GET_SBUS_PARAMS 0x0027 83 #define MBOX_GET_TARGET_PARAMS 0x0028 84 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 85 /* 2a */ 86 /* 2b */ 87 /* 2c */ 88 /* 2d */ 89 /* 2e */ 90 /* 2f */ 91 #define MBOX_SET_INIT_SCSI_ID 0x0030 92 #define MBOX_SET_SELECT_TIMEOUT 0x0031 93 #define MBOX_SET_RETRY_COUNT 0x0032 94 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 95 #define MBOX_SET_CLOCK_RATE 0x0034 96 #define MBOX_SET_ACTIVE_NEG_STATE 0x0035 97 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 98 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 99 #define MBOX_SET_PCI_PARAMETERS 0x0037 100 #define MBOX_SET_TARGET_PARAMS 0x0038 101 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 102 /* 3a */ 103 /* 3b */ 104 /* 3c */ 105 /* 3d */ 106 /* 3e */ 107 /* 3f */ 108 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 109 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 110 #define MBOX_EXEC_BIOS_IOCB 0x0042 111 112 /* These are for the ISP2100 FC cards */ 113 #define MBOX_GET_LOOP_ID 0x20 114 #define MBOX_EXEC_COMMAND_IOCB_A64 0x54 115 #define MBOX_INIT_FIRMWARE 0x60 116 #define MBOX_GET_INIT_CONTROL_BLOCK 0x61 117 #define MBOX_INIT_LIP 0x62 118 #define MBOX_GET_FC_AL_POSITION_MAP 0x63 119 #define MBOX_GET_PORT_DB 0x64 120 #define MBOX_CLEAR_ACA 0x65 121 #define MBOX_TARGET_RESET 0x66 122 #define MBOX_CLEAR_TASK_SET 0x67 123 #define MBOX_ABORT_TASK_SET 0x68 124 #define MBOX_GET_FW_STATE 0x69 125 #define MBOX_GET_LINK_STATUS 0x6a 126 #define MBOX_INIT_LIP_RESET 0x6c 127 #define MBOX_INIT_LIP_LOGIN 0x72 128 129 #define ISP2100_SET_PCI_PARAM 0x00ff 130 131 #define MBOX_BUSY 0x04 132 133 typedef struct { 134 u_int16_t param[8]; 135 } mbreg_t; 136 137 /* 138 * Mailbox Command Complete Status Codes 139 */ 140 #define MBOX_COMMAND_COMPLETE 0x4000 141 #define MBOX_INVALID_COMMAND 0x4001 142 #define MBOX_HOST_INTERFACE_ERROR 0x4002 143 #define MBOX_TEST_FAILED 0x4003 144 #define MBOX_COMMAND_ERROR 0x4005 145 #define MBOX_COMMAND_PARAM_ERROR 0x4006 146 147 /* 148 * Asynchronous event status codes 149 */ 150 #define ASYNC_BUS_RESET 0x8001 151 #define ASYNC_SYSTEM_ERROR 0x8002 152 #define ASYNC_RQS_XFER_ERR 0x8003 153 #define ASYNC_RSP_XFER_ERR 0x8004 154 #define ASYNC_QWAKEUP 0x8005 155 #define ASYNC_TIMEOUT_RESET 0x8006 156 #define ASYNC_UNSPEC_TMODE 0x8007 157 #define ASYNC_EXTMSG_UNDERRUN 0x800A 158 #define ASYNC_SCAM_INT 0x800B 159 #define ASYNC_HUNG_SCSI 0x800C 160 #define ASYNC_KILLED_BUS 0x800D 161 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 162 #define ASYNC_CMD_CMPLT 0x8020 163 #define ASYNC_CTIO_DONE 0x8021 164 165 /* for ISP2100 only */ 166 #define ASYNC_LIP_OCCURRED 0x8010 167 #define ASYNC_LOOP_UP 0x8011 168 #define ASYNC_LOOP_DOWN 0x8012 169 #define ASYNC_LOOP_RESET 0x8013 170 #define ASYNC_PDB_CHANGED 0x8014 /* Port Database Changed */ 171 #define ASYNC_CHANGE_NOTIFY 0x8015 172 173 /* 174 * Command Structure Definitions 175 */ 176 177 typedef struct { 178 u_int32_t ds_base; 179 u_int32_t ds_count; 180 } ispds_t; 181 182 typedef struct { 183 #if BYTE_ORDER == BIG_ENDIAN 184 u_int8_t rqs_entry_count; 185 u_int8_t rqs_entry_type; 186 u_int8_t rqs_flags; 187 u_int8_t rqs_seqno; 188 #else 189 u_int8_t rqs_entry_type; 190 u_int8_t rqs_entry_count; 191 u_int8_t rqs_seqno; 192 u_int8_t rqs_flags; 193 #endif 194 } isphdr_t; 195 196 /* RQS Flag definitions */ 197 #define RQSFLAG_CONTINUATION 0x01 198 #define RQSFLAG_FULL 0x02 199 #define RQSFLAG_BADHEADER 0x04 200 #define RQSFLAG_BADPACKET 0x08 201 202 /* RQS entry_type definitions */ 203 #define RQSTYPE_REQUEST 0x01 204 #define RQSTYPE_DATASEG 0x02 205 #define RQSTYPE_RESPONSE 0x03 206 #define RQSTYPE_MARKER 0x04 207 #define RQSTYPE_CMDONLY 0x05 208 #define RQSTYPE_ATIO 0x06 /* Target Mode */ 209 #define RQSTYPE_CTIO0 0x07 /* Target Mode */ 210 #define RQSTYPE_SCAM 0x08 211 #define RQSTYPE_A64 0x09 212 #define RQSTYPE_A64_CONT 0x0a 213 #define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */ 214 #define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */ 215 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 216 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 217 #define RQSTYPE_CTIO1 0x0f /* Target Mode */ 218 #define RQSTYPE_STATUS_CONT 0x10 219 #define RQSTYPE_T2RQS 0x11 220 221 #define RQSTYPE_T4RQS 0x15 222 #define RQSTYPE_ATIO2 0x16 223 #define RQSTYPE_CTIO2 0x17 224 #define RQSTYPE_CSET0 0x18 225 #define RQSTYPE_T3RQS 0x19 226 227 #define RQSTYPE_CTIO3 0x1f 228 229 230 #define ISP_RQDSEG 4 231 typedef struct { 232 isphdr_t req_header; 233 u_int32_t req_handle; 234 #if BYTE_ORDER == BIG_ENDIAN 235 u_int8_t req_target; 236 u_int8_t req_lun_trn; 237 #else 238 u_int8_t req_lun_trn; 239 u_int8_t req_target; 240 #endif 241 u_int16_t req_cdblen; 242 #define req_modifier req_cdblen /* marker packet */ 243 u_int16_t req_flags; 244 u_int16_t _res1; 245 u_int16_t req_time; 246 u_int16_t req_seg_count; 247 u_int8_t req_cdb[12]; 248 ispds_t req_dataseg[ISP_RQDSEG]; 249 } ispreq_t; 250 251 #define ISP_RQDSEG_T2 3 252 typedef struct { 253 isphdr_t req_header; 254 u_int32_t req_handle; 255 #if BYTE_ORDER == BIG_ENDIAN 256 u_int8_t req_target; 257 u_int8_t req_lun_trn; 258 #else 259 u_int8_t req_lun_trn; 260 u_int8_t req_target; 261 #endif 262 u_int16_t _res1; 263 u_int16_t req_flags; 264 u_int16_t _res2; 265 u_int16_t req_time; 266 u_int16_t req_seg_count; 267 u_int32_t req_cdb[4]; 268 u_int32_t req_totalcnt; 269 ispds_t req_dataseg[ISP_RQDSEG_T2]; 270 } ispreqt2_t; 271 272 /* req_flag values */ 273 #define REQFLAG_NODISCON 0x0001 274 #define REQFLAG_HTAG 0x0002 275 #define REQFLAG_OTAG 0x0004 276 #define REQFLAG_STAG 0x0008 277 #define REQFLAG_TARGET_RTN 0x0010 278 279 #define REQFLAG_NODATA 0x0000 280 #define REQFLAG_DATA_IN 0x0020 281 #define REQFLAG_DATA_OUT 0x0040 282 #define REQFLAG_DATA_UNKNOWN 0x0060 283 284 #define REQFLAG_DISARQ 0x0100 285 #define REQFLAG_FRC_ASYNC 0x0200 286 #define REQFLAG_FRC_SYNC 0x0400 287 #define REQFLAG_FRC_WIDE 0x0800 288 #define REQFLAG_NOPARITY 0x1000 289 #define REQFLAG_STOPQ 0x2000 290 #define REQFLAG_XTRASNS 0x4000 291 #define REQFLAG_PRIORITY 0x8000 292 293 typedef struct { 294 isphdr_t req_header; 295 u_int32_t req_handle; 296 #if BYTE_ORDER == BIG_ENDIAN 297 u_int8_t req_target; 298 u_int8_t req_lun_trn; 299 #else 300 u_int8_t req_lun_trn; 301 u_int8_t req_target; 302 #endif 303 u_int16_t req_cdblen; 304 u_int16_t req_flags; 305 u_int16_t _res1; 306 u_int16_t req_time; 307 u_int16_t req_seg_count; 308 u_int8_t req_cdb[44]; 309 } ispextreq_t; 310 311 #define ISP_CDSEG 7 312 typedef struct { 313 isphdr_t req_header; 314 u_int32_t _res1; 315 ispds_t req_dataseg[ISP_CDSEG]; 316 } ispcontreq_t; 317 318 typedef struct { 319 isphdr_t req_header; 320 u_int32_t _res1; 321 #if BYTE_ORDER == BIG_ENDIAN 322 u_int8_t req_target; 323 u_int8_t req_lun_trn; 324 u_int8_t _res2; 325 u_int8_t req_modifier; 326 #else 327 u_int8_t req_lun_trn; 328 u_int8_t req_target; 329 u_int8_t req_modifier; 330 u_int8_t _res2; 331 #endif 332 } ispmarkreq_t; 333 334 #define SYNC_DEVICE 0 335 #define SYNC_TARGET 1 336 #define SYNC_ALL 2 337 338 typedef struct { 339 isphdr_t req_header; 340 u_int32_t req_handle; 341 u_int16_t req_scsi_status; 342 u_int16_t req_completion_status; 343 u_int16_t req_state_flags; 344 u_int16_t req_status_flags; 345 u_int16_t req_time; 346 u_int16_t req_sense_len; 347 u_int32_t req_resid; 348 u_int8_t _res1[8]; 349 u_int8_t req_sense_data[32]; 350 } ispstatusreq_t; 351 352 /* 353 * For Qlogic 2100, the high order byte of SCSI status has 354 * additional meaning. 355 */ 356 #define RQCS_RU 0x800 /* Residual Under */ 357 #define RQCS_RO 0x400 /* Residual Over */ 358 #define RQCS_SV 0x200 /* Sense Length Valid */ 359 #define RQCS_RV 0x100 /* Residual Valid */ 360 361 /* 362 * Completion Status Codes. 363 */ 364 #define RQCS_COMPLETE 0x0000 365 #define RQCS_INCOMPLETE 0x0001 366 #define RQCS_DMA_ERROR 0x0002 367 #define RQCS_TRANSPORT_ERROR 0x0003 368 #define RQCS_RESET_OCCURRED 0x0004 369 #define RQCS_ABORTED 0x0005 370 #define RQCS_TIMEOUT 0x0006 371 #define RQCS_DATA_OVERRUN 0x0007 372 #define RQCS_COMMAND_OVERRUN 0x0008 373 #define RQCS_STATUS_OVERRUN 0x0009 374 #define RQCS_BAD_MESSAGE 0x000a 375 #define RQCS_NO_MESSAGE_OUT 0x000b 376 #define RQCS_EXT_ID_FAILED 0x000c 377 #define RQCS_IDE_MSG_FAILED 0x000d 378 #define RQCS_ABORT_MSG_FAILED 0x000e 379 #define RQCS_REJECT_MSG_FAILED 0x000f 380 #define RQCS_NOP_MSG_FAILED 0x0010 381 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 382 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 383 #define RQCS_ID_MSG_FAILED 0x0013 384 #define RQCS_UNEXP_BUS_FREE 0x0014 385 #define RQCS_DATA_UNDERRUN 0x0015 386 #define RQCS_XACT_ERR1 0x0018 387 #define RQCS_XACT_ERR2 0x0019 388 #define RQCS_XACT_ERR3 0x001A 389 #define RQCS_BAD_ENTRY 0x001B 390 #define RQCS_QUEUE_FULL 0x001C 391 #define RQCS_PHASE_SKIPPED 0x001D 392 #define RQCS_ARQS_FAILED 0x001E 393 #define RQCS_WIDE_FAILED 0x001F 394 #define RQCS_SYNCXFER_FAILED 0x0020 395 #define RQCS_LVD_BUSERR 0x0021 396 397 /* 2100 Only Completion Codes */ 398 #define RQCS_PORT_UNAVAILABLE 0x0028 399 #define RQCS_PORT_LOGGED_OUT 0x0029 400 #define RQCS_PORT_CHANGED 0x002A 401 #define RQCS_PORT_BUSY 0x002B 402 403 /* 404 * State Flags (not applicable to 2100) 405 */ 406 #define RQSF_GOT_BUS 0x0100 407 #define RQSF_GOT_TARGET 0x0200 408 #define RQSF_SENT_CDB 0x0400 409 #define RQSF_XFRD_DATA 0x0800 410 #define RQSF_GOT_STATUS 0x1000 411 #define RQSF_GOT_SENSE 0x2000 412 #define RQSF_XFER_COMPLETE 0x4000 413 414 /* 415 * Status Flags (not applicable to 2100) 416 */ 417 #define RQSTF_DISCONNECT 0x0001 418 #define RQSTF_SYNCHRONOUS 0x0002 419 #define RQSTF_PARITY_ERROR 0x0004 420 #define RQSTF_BUS_RESET 0x0008 421 #define RQSTF_DEVICE_RESET 0x0010 422 #define RQSTF_ABORTED 0x0020 423 #define RQSTF_TIMEOUT 0x0040 424 #define RQSTF_NEGOTIATION 0x0080 425 426 /* 427 * Target Mode Structures 428 */ 429 /* 430 * Used for Enable LUN and Modify Lun types. 431 * (for FC, pre-1.14 FW layout revision). 432 */ 433 typedef struct { 434 isphdr_t req_header; 435 u_int32_t req_handle; 436 #if BYTE_ORDER == BIG_ENDIAN 437 u_int8_t _reserved0; 438 u_int8_t req_lun; /* HOST->FW: LUN to enable */ 439 #else 440 u_int8_t req_lun; /* HOST->FW: LUN to enable */ 441 u_int8_t _reserved0; 442 #endif 443 u_int16_t _reserved1[3]; 444 #if BYTE_ORDER == BIG_ENDIAN 445 u_int8_t _reserved2; 446 u_int8_t req_status; /* FW->HOST: Status of Request */ 447 u_int8_t req_imcount; /* HOST->FW: Immediate Notify Count */ 448 u_int8_t req_cmdcount; /* HOST->FW: ATIO Count */ 449 #else 450 u_int8_t req_status; /* FW->HOST: Status of Request */ 451 u_int8_t _reserved2; 452 u_int8_t req_cmdcount; /* HOST->FW: ATIO Count */ 453 u_int8_t req_imcount; /* HOST->FW: Immediate Notify Count */ 454 #endif 455 u_int16_t _reserved3; 456 u_int16_t req_timeout; /* HOST->FW: Lun timeout value */ 457 } isplun_t; 458 459 typedef struct { 460 isphdr_t req_header; 461 u_int32_t req_handle; 462 #if BYTE_ORDER == BIG_ENDIAN 463 u_int8_t req_initiator; 464 u_int8_t req_lun; 465 #else 466 u_int8_t req_lun; 467 u_int8_t req_initiator; 468 #endif 469 u_int16_t _reserved1[3]; 470 u_int16_t req_status; 471 u_int16_t req_task_flags; 472 u_int16_t req_sequence; 473 } ispnotify_t; 474 475 typedef struct { 476 isphdr_t req_header; 477 u_int32_t req_handle; 478 #if BYTE_ORDER == BIG_ENDIAN 479 u_int8_t req_initiator; 480 u_int8_t req_lun; 481 #else 482 u_int8_t req_lun; 483 u_int8_t req_initiator; 484 #endif 485 u_int16_t req_rxid; 486 u_int16_t req_flags; 487 u_int16_t req_status; 488 #if BYTE_ORDER == BIG_ENDIAN 489 u_int8_t req_taskcodes; 490 u_int8_t _reserved0; 491 u_int8_t req_execodes; 492 u_int8_t req_taskflags; 493 #else 494 u_int8_t _reserved0; 495 u_int8_t req_taskcodes; 496 u_int8_t req_taskflags; 497 u_int8_t req_execodes; 498 #endif 499 u_int32_t req_cdb[4]; 500 u_int32_t req_datalen; 501 u_int32_t _reserved1;; 502 u_int16_t req_scsi_status; 503 u_int8_t req_sense[8]; 504 } ispatiot2_t; 505 506 /* 507 * FC (ISP2100) specific data structures 508 */ 509 510 /* 511 * Initialization Control Block 512 * 513 * Version One format. 514 */ 515 typedef struct { 516 #if BYTE_ORDER == BIG_ENDIAN 517 u_int8_t _reserved0; 518 u_int8_t icb_version; 519 #else 520 u_int8_t icb_version; 521 u_int8_t _reserved0; 522 #endif 523 u_int16_t icb_fwoptions; 524 u_int16_t icb_maxfrmlen; 525 u_int16_t icb_maxalloc; 526 u_int16_t icb_execthrottle; 527 #if BYTE_ORDER == BIG_ENDIAN 528 u_int8_t icb_retry_delay; 529 u_int8_t icb_retry_count; 530 #else 531 u_int8_t icb_retry_count; 532 u_int8_t icb_retry_delay; 533 #endif 534 u_int8_t icb_nodename[8]; 535 u_int16_t icb_hardaddr; 536 #if BYTE_ORDER == BIG_ENDIAN 537 u_int8_t _reserved1; 538 u_int8_t icb_iqdevtype; 539 #else 540 u_int8_t icb_iqdevtype; 541 u_int8_t _reserved1; 542 #endif 543 u_int8_t icb_portname[8]; 544 u_int16_t icb_rqstout; 545 u_int16_t icb_rspnsin; 546 u_int16_t icb_rqstqlen; 547 u_int16_t icb_rsltqlen; 548 u_int16_t icb_rqstaddr[4]; 549 u_int16_t icb_respaddr[4]; 550 } isp_icb_t; 551 #define ICB_VERSION1 1 552 553 #define ICBOPT_HARD_ADDRESS (1<<0) 554 #define ICBOPT_FAIRNESS (1<<1) 555 #define ICBOPT_FULL_DUPLEX (1<<2) 556 #define ICBOPT_FAST_POST (1<<3) 557 #define ICBOPT_TGT_ENABLE (1<<4) 558 #define ICBOPT_INI_DISABLE (1<<5) 559 #define ICBOPT_INI_ADISC (1<<6) 560 #define ICBOPT_INI_TGTTYPE (1<<7) 561 #define ICBOPT_PDBCHANGE_AE (1<<8) 562 #define ICBOPT_NOLIP (1<<9) 563 #define ICBOPT_SRCHDOWN (1<<10) 564 #define ICBOPT_PREVLOOP (1<<11) 565 #define ICBOPT_STOP_ON_QFULL (1<<12) 566 #define ICBOPT_FULL_LOGIN (1<<13) 567 #define ICBOPT_USE_PORTNAME (1<<14) 568 569 570 #define ICB_MIN_FRMLEN 256 571 #define ICB_MAX_FRMLEN 2112 572 #define ICB_DFLT_FRMLEN 1024 573 574 #define RQRSP_ADDR0015 0 575 #define RQRSP_ADDR1631 1 576 #define RQRSP_ADDR3247 2 577 #define RQRSP_ADDR4863 3 578 579 580 #if BYTE_ORDER == BIG_ENDIAN 581 #define ICB_NNM0 6 582 #define ICB_NNM1 7 583 #define ICB_NNM2 4 584 #define ICB_NNM3 5 585 #define ICB_NNM4 2 586 #define ICB_NNM5 3 587 #define ICB_NNM6 0 588 #define ICB_NNM7 1 589 #else 590 #define ICB_NNM0 7 591 #define ICB_NNM1 6 592 #define ICB_NNM2 5 593 #define ICB_NNM3 4 594 #define ICB_NNM4 3 595 #define ICB_NNM5 2 596 #define ICB_NNM6 1 597 #define ICB_NNM7 0 598 #endif 599 600 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 601 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \ 602 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \ 603 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \ 604 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \ 605 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \ 606 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \ 607 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \ 608 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff) 609 610 #endif /* _ISPMBOX_H */ 611
Indexes created Thu Sep 25 02:09:54 GMT 2025