ispreg.h revision 1.1
1 /* $NetBSD: ispreg.h,v 1.1 1997/03/12 20:44:51 cgd Exp $ */ 2 3 /* 4 * Machine Independent (well, as best as possible) register 5 * definitions for Qlogic ISP SCSI adapters. 6 * 7 * Copyright (c) 1997 by Matthew Jacob (for NASA/Ames Research Center) 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice immediately at the beginning of the file, without modification, 15 * this list of conditions, and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 #ifndef _ISPREG_H 36 #define _ISPREG_H 37 38 /* 39 * Hardware definitions for the Qlogic ISP registers. 40 */ 41 42 /* 43 * This defines types of access to various registers. 44 * 45 * R: Read Only 46 * W: Write Only 47 * RW: Read/Write 48 * 49 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 50 * if RISC processor in ISP is paused. 51 */ 52 53 /* 54 * Offsets for various register blocks. 55 * 56 * Sad but true, different architectures have different offsets. 57 */ 58 59 #define BIU_REGS_OFF 0x00 60 61 #define PCI_MBOX_REGS_OFF 0x70 62 #define SBUS_MBOX_REGS_OFF 0x80 63 64 #define PCI_SXP_REGS_OFF 0x80 65 #define SBUS_SXP_REGS_OFF 0x200 66 67 #define PCI_RISC_REGS_OFF 0x80 68 #define SBUS_RISC_REGS_OFF 0x400 69 70 /* 71 * NB: The *_BLOCK definitions have no specific hardware meaning. 72 * They serve simply to note to the MD layer which block of 73 * registers offsets are being accessed. 74 */ 75 76 /* 77 * Bus Interface Block Register Offsets 78 */ 79 #define BIU_BLOCK 0x0100 80 #define BIU_ID_LO BIU_BLOCK+0x0 /* R : Bus ID, Low */ 81 #define BIU_ID_HI BIU_BLOCK+0x2 /* R : Bus ID, High */ 82 #define BIU_CONF0 BIU_BLOCK+0x4 /* R : Bus Configuration #0 */ 83 #define BIU_CONF1 BIU_BLOCK+0x6 /* R : Bus Configuration #1 */ 84 #define BIU_ICR BIU_BLOCK+0x8 /* RW : Bus Interface Ctrl */ 85 #define BIU_ISR BIU_BLOCK+0xA /* R : Bus Interface Status */ 86 #define BIU_SEMA BIU_BLOCK+0xC /* RW : Bus Semaphore */ 87 #define BIU_NVRAM BIU_BLOCK+0xE /* RW : Bus NVRAM */ 88 #define CDMA_CONF BIU_BLOCK+0x20 /* RW*: DMA Configuration */ 89 #define CDMA_CONTROL BIU_BLOCK+0x22 /* RW*: DMA Control */ 90 #define CDMA_STATUS BIU_BLOCK+0x24 /* R : DMA Status */ 91 #define CDMA_FIFO_STS BIU_BLOCK+0x26 /* R : DMA FIFO Status */ 92 #define CDMA_COUNT BIU_BLOCK+0x28 /* RW*: DMA Transfer Count */ 93 #define CDMA_ADDR0 BIU_BLOCK+0x2C /* RW*: DMA Address, Word 0 */ 94 #define CDMA_ADDR1 BIU_BLOCK+0x2E /* RW*: DMA Address, Word 1 */ 95 /* these are for the 1040A cards */ 96 #define CDMA_ADDR2 BIU_BLOCK+0x30 /* RW*: DMA Address, Word 2 */ 97 #define CDMA_ADDR3 BIU_BLOCK+0x32 /* RW*: DMA Address, Word 3 */ 98 99 #define DDMA_CONF BIU_BLOCK+0x40 /* RW*: DMA Configuration */ 100 #define DDMA_CONTROL BIU_BLOCK+0x42 /* RW*: DMA Control */ 101 #define DDMA_STATUS BIU_BLOCK+0x44 /* R : DMA Status */ 102 #define DDMA_FIFO_STS BIU_BLOCK+0x46 /* R : DMA FIFO Status */ 103 #define DDMA_COUNT_LO BIU_BLOCK+0x48 /* RW*: DMA Xfer Count, Low */ 104 #define DDMA_COUNT_HI BIU_BLOCK+0x4A /* RW*: DMA Xfer Count, High */ 105 #define DDMA_ADDR0 BIU_BLOCK+0x4C /* RW*: DMA Address, Word 0 */ 106 #define DDMA_ADDR1 BIU_BLOCK+0x4E /* RW*: DMA Address, Word 1 */ 107 /* these are for the 1040A cards */ 108 #define DDMA_ADDR2 BIU_BLOCK+0x50 /* RW*: DMA Address, Word 2 */ 109 #define DDMA_ADDR3 BIU_BLOCK+0x52 /* RW*: DMA Address, Word 3 */ 110 111 #define DFIFO_COMMAND BIU_BLOCK+0x60 /* RW : Command FIFO Port */ 112 #define DFIFO_DATA BIU_BLOCK+0x62 /* RW : Data FIFO Port */ 113 114 /* 115 * Bus Interface Block Register Definitions 116 */ 117 /* BUS CONFIGURATION REGISTER #0 */ 118 #define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 119 /* BUS CONFIGURATION REGISTER #1 */ 120 121 #define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 122 #define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 123 124 #define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 125 #define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 126 #define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 127 #define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 128 #define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 129 #define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 130 #define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 131 #define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 132 #define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 133 #define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 134 #define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 135 136 /* BUS CONTROL REGISTER */ 137 #define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 138 #define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 139 #define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 140 #define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 141 #define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 142 #define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 143 144 145 /* BUS STATUS REGISTER */ 146 #define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 147 #define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 148 #define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 149 #define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 150 #define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 151 152 153 /* BUS SEMAPHORE REGISTER */ 154 #define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 155 #define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 156 157 158 /* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 159 #define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 160 #define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 161 #define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 162 #define DMA_DMA_DIRECTION 0x0001 /* 163 * Set DMA direction: 164 * 0 - DMA FIFO to host 165 * 1 - Host to DMA FIFO 166 */ 167 168 /* COMMAND && DATA DMA CONTROL REGISTER */ 169 #define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 170 #define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 171 * Clear FIFO and DMA Channel, 172 * reset DMA registers 173 */ 174 #define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 175 #define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 176 #define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 177 178 179 /* DMA STATUS REGISTER */ 180 #define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 181 #define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 182 #define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 183 #define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 184 #define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 185 #define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 186 187 #define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 188 #define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 189 #define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 190 #define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 191 #define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 192 #define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 193 #define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 194 #define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 195 #define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 196 #define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 197 #define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 198 199 /* DMA Status Register, pipeline status bits */ 200 #define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 201 #define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 202 #define DMA_SBUS_PIPE_STAGE1 0x0040 /* 203 * Pipeline stage 1 Loaded, 204 * stage 2 empty 205 */ 206 #define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 207 #define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 208 #define DMA_PCI_PIPE_STAGE1 0x0001 /* 209 * Pipeline stage 1 Loaded, 210 * stage 2 empty 211 */ 212 #define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 213 214 /* DMA Status Register, channel status bits */ 215 #define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 216 #define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 217 #define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 218 #define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 219 #define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 220 #define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 221 #define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 222 223 224 /* DMA FIFO STATUS REGISTER */ 225 #define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 226 #define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 227 #define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 228 #define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 229 230 /* 231 * Mailbox Block Register Offsets 232 */ 233 234 #define MBOX_BLOCK 0x0200 235 #define INMAILBOX0 MBOX_BLOCK+0x0 236 #define INMAILBOX1 MBOX_BLOCK+0x2 237 #define INMAILBOX2 MBOX_BLOCK+0x4 238 #define INMAILBOX3 MBOX_BLOCK+0x6 239 #define INMAILBOX4 MBOX_BLOCK+0x8 240 #define INMAILBOX5 MBOX_BLOCK+0xA 241 242 #define OUTMAILBOX0 MBOX_BLOCK+0x0 243 #define OUTMAILBOX1 MBOX_BLOCK+0x2 244 #define OUTMAILBOX2 MBOX_BLOCK+0x4 245 #define OUTMAILBOX3 MBOX_BLOCK+0x6 246 #define OUTMAILBOX4 MBOX_BLOCK+0x8 247 #define OUTMAILBOX5 MBOX_BLOCK+0xA 248 249 /* 250 * Mailbox Command Complete Status Codes 251 */ 252 #define MBOX_COMMAND_COMPLETE 0x4000 253 #define MBOX_INVALID_COMMAND 0x4001 254 #define MBOX_HOST_INTERFACE_ERROR 0x4002 255 #define MBOX_TEST_FAILED 0x4003 256 #define MBOX_COMMAND_ERROR 0x4005 257 #define MBOX_COMMAND_PARAM_ERROR 0x4006 258 259 /* 260 * Asynchronous event status codes 261 */ 262 #define ASYNC_BUS_RESET 0x8001 263 #define ASYNC_SYSTEM_ERROR 0x8002 264 #define ASYNC_RQS_XFER_ERR 0x8003 265 #define ASYNC_RSP_XFER_ERR 0x8004 266 #define ASYNC_QWAKEUP 0x8005 267 #define ASYNC_TIMEOUT_RESET 0x8006 268 269 /* 270 * SXP Block Register Offsets 271 */ 272 #define SXP_BLOCK 0x0400 273 #define SXP_PART_ID SXP_BLOCK+0x0 /* R : Part ID Code */ 274 #define SXP_CONFIG1 SXP_BLOCK+0x2 /* RW*: Configuration Reg #1 */ 275 #define SXP_CONFIG2 SXP_BLOCK+0x4 /* RW*: Configuration Reg #2 */ 276 #define SXP_CONFIG3 SXP_BLOCK+0x6 /* RW*: Configuration Reg #2 */ 277 #define SXP_INSTRUCTION SXP_BLOCK+0xC /* RW*: Instruction Pointer */ 278 #define SXP_RETURN_ADDR SXP_BLOCK+0x10 /* RW*: Return Address */ 279 #define SXP_COMMAND SXP_BLOCK+0x14 /* RW*: Command */ 280 #define SXP_INTERRUPT SXP_BLOCK+0x18 /* R : Interrupt */ 281 #define SXP_SEQUENCE SXP_BLOCK+0x1C /* RW*: Sequence */ 282 #define SXP_GROSS_ERR SXP_BLOCK+0x1E /* R : Gross Error */ 283 #define SXP_EXCEPTION SXP_BLOCK+0x20 /* RW*: Exception Enable */ 284 #define SXP_OVERRIDE SXP_BLOCK+0x24 /* RW*: Override */ 285 #define SXP_LITERAL_BASE SXP_BLOCK+0x28 /* RW*: Literal Base */ 286 #define SXP_USER_FLAGS SXP_BLOCK+0x2C /* RW*: User Flags */ 287 #define SXP_USER_EXCEPT SXP_BLOCK+0x30 /* RW*: User Exception */ 288 #define SXP_BREAKPOINT SXP_BLOCK+0x34 /* RW*: Breakpoint */ 289 #define SXP_SCSI_ID SXP_BLOCK+0x40 /* RW*: SCSI ID */ 290 #define SXP_DEV_CONFIG1 SXP_BLOCK+0x42 /* RW*: Device Config Reg #1 */ 291 #define SXP_DEV_CONFIG2 SXP_BLOCK+0x44 /* RW*: Device Config Reg #2 */ 292 #define SXP_PHASE_POINTER SXP_BLOCK+0x48 /* RW*: SCSI Phase Pointer */ 293 #define SXP_BUF_POINTER SXP_BLOCK+0x4C /* RW*: SCSI Buffer Pointer */ 294 #define SXP_BUF_COUNTER SXP_BLOCK+0x50 /* RW*: SCSI Buffer Counter */ 295 #define SXP_BUFFER SXP_BLOCK+0x52 /* RW*: SCSI Buffer */ 296 #define SXP_BUF_BYTE SXP_BLOCK+0x54 /* RW*: SCSI Buffer Byte */ 297 #define SXP_BUF_WORD SXP_BLOCK+0x56 /* RW*: SCSI Buffer Word */ 298 #define SXP_BUF_WORD_TRAN SXP_BLOCK+0x58 /* RW*: SCSI Buffer Wd xlate */ 299 #define SXP_FIFO SXP_BLOCK+0x5A /* RW*: SCSI FIFO */ 300 #define SXP_FIFO_STATUS SXP_BLOCK+0x5C /* RW*: SCSI FIFO Status */ 301 #define SXP_FIFO_TOP SXP_BLOCK+0x5E /* RW*: SCSI FIFO Top Resid */ 302 #define SXP_FIFO_BOTTOM SXP_BLOCK+0x60 /* RW*: SCSI FIFO Bot Resid */ 303 #define SXP_TRAN_REG SXP_BLOCK+0x64 /* RW*: SCSI Transferr Reg */ 304 #define SXP_TRAN_COUNT_LO SXP_BLOCK+0x68 /* RW*: SCSI Trans Count */ 305 #define SXP_TRAN_COUNT_HI SXP_BLOCK+0x6A /* RW*: SCSI Trans Count */ 306 #define SXP_TRAN_COUNTER_LO SXP_BLOCK+0x6C /* RW*: SCSI Trans Counter */ 307 #define SXP_TRAN_COUNTER_HI SXP_BLOCK+0x6E /* RW*: SCSI Trans Counter */ 308 #define SXP_ARB_DATA SXP_BLOCK+0x70 /* R : SCSI Arb Data */ 309 #define SXP_PINS_CONTROL SXP_BLOCK+0x72 /* RW*: SCSI Control Pins */ 310 #define SXP_PINS_DATA SXP_BLOCK+0x74 /* RW*: SCSI Data Pins */ 311 #define SXP_PINS_DIFF SXP_BLOCK+0x76 /* RW*: SCSI Diff Pins */ 312 313 314 /* SXP CONF1 REGISTER */ 315 #define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 316 #define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 317 #define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 318 #define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 319 #define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 320 321 /* SXP CONF2 REGISTER */ 322 #define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 323 #define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 324 #define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 325 #define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 326 #define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 327 #define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 328 329 /* SXP INTERRUPT REGISTER */ 330 #define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 331 #define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 332 #define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 333 #define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 334 #define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 335 #define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 336 #define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 337 #define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 338 #define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 339 #define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 340 341 342 /* SXP GROSS ERROR REGISTER */ 343 #define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 344 #define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 345 #define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 346 #define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 347 #define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 348 #define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 349 #define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 350 351 /* SXP EXCEPTION REGISTER */ 352 #define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 353 #define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 354 #define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 355 #define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 356 #define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 357 #define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 358 #define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 359 #define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 360 #define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 361 #define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 362 363 /* SXP OVERRIDE REGISTER */ 364 #define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 365 #define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 366 #define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 367 #define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 368 #define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 369 #define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 370 #define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 371 #define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 372 #define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 373 #define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 374 #define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 375 #define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 376 #define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 377 378 /* SXP COMMANDS */ 379 #define SXP_RESET_BUS_CMD 0x300b 380 381 /* SXP SCSI ID REGISTER */ 382 #define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 383 #define SXP_SELECT_ID 0x000F /* Select id */ 384 385 /* SXP DEV CONFIG1 REGISTER */ 386 #define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 387 #define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 388 #define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 389 390 391 /* SXP DEV CONFIG2 REGISTER */ 392 #define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 393 #define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 394 #define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 395 #define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 396 #define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 397 398 399 /* SXP PHASE POINTER REGISTER */ 400 #define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 401 #define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 402 #define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 403 #define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 404 405 406 /* SXP FIFO STATUS REGISTER */ 407 #define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 408 #define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 409 #define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 410 #define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 411 412 413 /* SXP CONTROL PINS REGISTER */ 414 #define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 415 #define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 416 #define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 417 #define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 418 #define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 419 #define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 420 #define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 421 #define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 422 #define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 423 #define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 424 #define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 425 #define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 426 427 /* 428 * Set the hold time for the SCSI Bus Reset to be 250 ms 429 */ 430 #define SXP_SCSI_BUS_RESET_HOLD_TIME 250 431 432 /* SXP DIFF PINS REGISTER */ 433 #define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 434 #define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 435 #define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 436 #define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 437 #define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 438 #define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 439 440 /* 441 * RISC and Host Command and Control Block Register Offsets 442 */ 443 #define RISC_BLOCK 0x0800 444 445 #define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 446 #define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 447 #define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 448 #define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 449 #define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 450 #define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 451 #define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 452 #define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 453 #define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 454 #define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 455 #define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 456 #define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 457 #define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 458 #define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 459 #define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 460 #define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 461 #define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 462 #define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 463 #define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 464 #define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 465 #define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 466 #define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 467 #define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 468 #define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 469 #define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 470 #define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 471 #define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 472 #define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 473 #define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 474 #define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 475 #define TCR RISC_BLOCK+0x46 /* W : Test Control */ 476 #define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 477 478 479 /* PROCESSOR STATUS REGISTER */ 480 #define RISC_PSR_FORCE_TRUE 0x8000 481 #define RISC_PSR_LOOP_COUNT_DONE 0x4000 482 #define RISC_PSR_RISC_INT 0x2000 483 #define RISC_PSR_TIMER_ROLLOVER 0x1000 484 #define RISC_PSR_ALU_OVERFLOW 0x0800 485 #define RISC_PSR_ALU_MSB 0x0400 486 #define RISC_PSR_ALU_CARRY 0x0200 487 #define RISC_PSR_ALU_ZERO 0x0100 488 #define RISC_PSR_DMA_INT 0x0010 489 #define RISC_PSR_SXP_INT 0x0008 490 #define RISC_PSR_HOST_INT 0x0004 491 #define RISC_PSR_INT_PENDING 0x0002 492 #define RISC_PSR_FORCE_FALSE 0x0001 493 494 495 /* Host Command and Control */ 496 #define HCCR_CMD_NOP 0x0000 /* NOP */ 497 #define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 498 #define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 499 #define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 500 #define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 501 #define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 502 #define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 503 #define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 504 #define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 505 #define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 506 #define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 507 #define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 508 #define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 509 510 #define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 511 #define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 512 #define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 513 514 #define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 515 #define HCCR_RESET 0x0040 /* R : reset in progress */ 516 #define HCCR_PAUSE 0x0020 /* R : RISC paused */ 517 518 #define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 519 #endif /* _ISPREG_H */ 520
Indexes created Thu Sep 25 16:09:42 GMT 2025