ispreg.h revision 1.21
1 /* $NetBSD: ispreg.h,v 1.21 2000/07/05 22:26:53 mjacob Exp $ */ 2 /* release_6_5_99 */ 3 /* 4 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /* 30 * Machine Independent (well, as best as possible) register 31 * definitions for Qlogic ISP SCSI adapters. 32 * 33 * Matthew Jacob <mjacob (at) nas.nasa.gov> 34 * 35 */ 36 #ifndef _ISPREG_H 37 #define _ISPREG_H 38 39 /* 40 * Hardware definitions for the Qlogic ISP registers. 41 */ 42 43 /* 44 * This defines types of access to various registers. 45 * 46 * R: Read Only 47 * W: Write Only 48 * RW: Read/Write 49 * 50 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 51 * if RISC processor in ISP is paused. 52 */ 53 54 /* 55 * Offsets for various register blocks. 56 * 57 * Sad but true, different architectures have different offsets. 58 * 59 * Don't be alarmed if none of this makes sense. The original register 60 * layout set some defines in a certain pattern. Everything else has been 61 * grafted on since. For example, the ISP1080 manual will state that DMA 62 * registers start at 0x80 from the base of the register address space. 63 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 64 * to start at offset 0x60 because the DMA registers are all defined to 65 * be DMA_BLOCK+0x20 and so on. Clear? 66 */ 67 68 #define BIU_REGS_OFF 0x00 69 70 #define PCI_MBOX_REGS_OFF 0x70 71 #define PCI_MBOX_REGS2100_OFF 0x10 72 #define SBUS_MBOX_REGS_OFF 0x80 73 74 #define PCI_SXP_REGS_OFF 0x80 75 #define SBUS_SXP_REGS_OFF 0x200 76 77 #define PCI_RISC_REGS_OFF 0x80 78 #define SBUS_RISC_REGS_OFF 0x400 79 80 /* Bless me! Chip designers have putzed it again! */ 81 #define ISP1080_DMA_REGS_OFF 0x60 82 #define DMA_REGS_OFF 0x00 /* same as BIU block */ 83 84 /* 85 * NB: The *_BLOCK definitions have no specific hardware meaning. 86 * They serve simply to note to the MD layer which block of 87 * registers offsets are being accessed. 88 */ 89 #define _NREG_BLKS 5 90 #define _BLK_REG_SHFT 13 91 #define _BLK_REG_MASK (7 << _BLK_REG_SHFT) 92 #define BIU_BLOCK (0 << _BLK_REG_SHFT) 93 #define MBOX_BLOCK (1 << _BLK_REG_SHFT) 94 #define SXP_BLOCK (2 << _BLK_REG_SHFT) 95 #define RISC_BLOCK (3 << _BLK_REG_SHFT) 96 #define DMA_BLOCK (4 << _BLK_REG_SHFT) 97 98 /* 99 * Bus Interface Block Register Offsets 100 */ 101 102 #define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */ 103 #define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0) 104 #define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */ 105 #define BIU2100_FLASH_DATA (BIU_BLOCK+0x2) 106 #define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */ 107 #define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */ 108 #define BIU2100_CSR (BIU_BLOCK+0x6) 109 #define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */ 110 #define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */ 111 #define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */ 112 #define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ 113 #define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ 114 #define RDMA2100_CONTROL DFIFO_COMMAND 115 #define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ 116 117 /* 118 * Putzed DMA register layouts. 119 */ 120 #define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */ 121 #define CDMA2100_CONTROL CDMA_CONF 122 #define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */ 123 #define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */ 124 #define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */ 125 #define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */ 126 #define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */ 127 #define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */ 128 #define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */ 129 #define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */ 130 131 #define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */ 132 #define TDMA2100_CONTROL DDMA_CONF 133 #define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */ 134 #define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */ 135 #define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */ 136 #define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */ 137 #define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */ 138 #define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */ 139 #define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */ 140 /* these are for the 1040A cards */ 141 #define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */ 142 #define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */ 143 144 145 /* 146 * Bus Interface Block Register Definitions 147 */ 148 /* BUS CONFIGURATION REGISTER #0 */ 149 #define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 150 /* BUS CONFIGURATION REGISTER #1 */ 151 152 #define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 153 #define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 154 155 #define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 156 #define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 157 #define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 158 #define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 159 #define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 160 #define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 161 #define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 162 #define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 163 #define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 164 #define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 165 #define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 166 167 #define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */ 168 #define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */ 169 #define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 170 171 /* ISP2100 Bus Control/Status Register */ 172 173 #define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 174 #define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 175 #define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 176 #define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 177 #define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 178 #define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ 179 #define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 180 #define BIU2100_SOFT_RESET 0x01 181 /* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 182 183 184 /* BUS CONTROL REGISTER */ 185 #define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 186 #define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 187 #define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 188 #define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 189 #define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 190 #define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 191 192 #define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 193 #define BIU2100_ICR_ENA_FPM_INT 0x0020 194 #define BIU2100_ICR_ENA_FB_INT 0x0010 195 #define BIU2100_ICR_ENA_RISC_INT 0x0008 196 #define BIU2100_ICR_ENA_CDMA_INT 0x0004 197 #define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 198 #define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 199 #define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 200 201 #define ENABLE_INTS(isp) (IS_SCSI(isp))? \ 202 ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ 203 ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) 204 205 #define INTS_ENABLED(isp) ((IS_SCSI(isp))? \ 206 (ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\ 207 (ISP_READ(isp, BIU_ICR) & \ 208 (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS))) 209 210 #define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) 211 212 /* BUS STATUS REGISTER */ 213 #define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 214 #define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 215 #define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 216 #define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 217 #define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 218 219 #define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 220 #define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 221 #define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 222 #define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 223 #define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 224 #define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 225 #define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 226 227 #define INT_PENDING(isp, isr) (IS_FC(isp)? \ 228 ((isr & BIU2100_ISR_RISC_INT) != 0) : ((isr & BIU_ISR_RISC_INT) != 0)) 229 230 #define INT_PENDING_MASK(isp) \ 231 (IS_FC(isp)? BIU2100_ISR_RISC_INT: BIU_ISR_RISC_INT) 232 233 /* BUS SEMAPHORE REGISTER */ 234 #define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 235 #define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 236 237 /* NVRAM SEMAPHORE REGISTER */ 238 #define BIU_NVRAM_CLOCK 0x0001 239 #define BIU_NVRAM_SELECT 0x0002 240 #define BIU_NVRAM_DATAOUT 0x0004 241 #define BIU_NVRAM_DATAIN 0x0008 242 #define ISP_NVRAM_READ 6 243 244 /* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 245 #define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 246 #define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 247 #define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 248 #define DMA_DMA_DIRECTION 0x0001 /* 249 * Set DMA direction: 250 * 0 - DMA FIFO to host 251 * 1 - Host to DMA FIFO 252 */ 253 254 /* COMMAND && DATA DMA CONTROL REGISTER */ 255 #define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 256 #define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 257 * Clear FIFO and DMA Channel, 258 * reset DMA registers 259 */ 260 #define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 261 #define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 262 #define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 263 264 /* 265 * Variants of same for 2100 266 */ 267 #define DMA_CNTRL2100_CLEAR_CHAN 0x0004 268 #define DMA_CNTRL2100_RESET_INT 0x0002 269 270 271 272 /* DMA STATUS REGISTER */ 273 #define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 274 #define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 275 #define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 276 #define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 277 #define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 278 #define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 279 280 #define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 281 #define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 282 #define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 283 #define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 284 #define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 285 #define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 286 #define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 287 #define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 288 #define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 289 #define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 290 #define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 291 292 /* DMA Status Register, pipeline status bits */ 293 #define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 294 #define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 295 #define DMA_SBUS_PIPE_STAGE1 0x0040 /* 296 * Pipeline stage 1 Loaded, 297 * stage 2 empty 298 */ 299 #define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 300 #define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 301 #define DMA_PCI_PIPE_STAGE1 0x0001 /* 302 * Pipeline stage 1 Loaded, 303 * stage 2 empty 304 */ 305 #define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 306 307 /* DMA Status Register, channel status bits */ 308 #define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 309 #define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 310 #define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 311 #define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 312 #define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 313 #define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 314 #define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 315 316 317 /* DMA FIFO STATUS REGISTER */ 318 #define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 319 #define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 320 #define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 321 #define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 322 323 /* 324 * Mailbox Block Register Offsets 325 */ 326 327 #define INMAILBOX0 (MBOX_BLOCK+0x0) 328 #define INMAILBOX1 (MBOX_BLOCK+0x2) 329 #define INMAILBOX2 (MBOX_BLOCK+0x4) 330 #define INMAILBOX3 (MBOX_BLOCK+0x6) 331 #define INMAILBOX4 (MBOX_BLOCK+0x8) 332 #define INMAILBOX5 (MBOX_BLOCK+0xA) 333 #define INMAILBOX6 (MBOX_BLOCK+0xC) 334 #define INMAILBOX7 (MBOX_BLOCK+0xE) 335 336 #define OUTMAILBOX0 (MBOX_BLOCK+0x0) 337 #define OUTMAILBOX1 (MBOX_BLOCK+0x2) 338 #define OUTMAILBOX2 (MBOX_BLOCK+0x4) 339 #define OUTMAILBOX3 (MBOX_BLOCK+0x6) 340 #define OUTMAILBOX4 (MBOX_BLOCK+0x8) 341 #define OUTMAILBOX5 (MBOX_BLOCK+0xA) 342 #define OUTMAILBOX6 (MBOX_BLOCK+0xC) 343 #define OUTMAILBOX7 (MBOX_BLOCK+0xE) 344 345 #define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) 346 #define NMBOX(isp) \ 347 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 348 ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 349 #define NMBOX_BMASK(isp) \ 350 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 351 ((isp)->isp_type & ISP_HA_FC))? 0xff : 0x3f) 352 353 #define MAX_MAILBOX 8 354 355 /* 356 * SXP Block Register Offsets 357 */ 358 #define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 359 #define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 360 #define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 361 #define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 362 #define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 363 #define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 364 #define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 365 #define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 366 #define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 367 #define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 368 #define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 369 #define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 370 #define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 371 #define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 372 #define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 373 #define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 374 #define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 375 #define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 376 #define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 377 #define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 378 #define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 379 #define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 380 #define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 381 #define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 382 #define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 383 #define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 384 #define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 385 #define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 386 #define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 387 #define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 388 #define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ 389 #define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 390 #define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 391 #define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 392 #define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 393 #define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 394 #define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 395 #define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 396 #define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ 397 398 /* for 1080/1280/1240 only */ 399 #define SXP_BANK1_SELECT 0x100 400 401 402 /* SXP CONF1 REGISTER */ 403 #define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 404 #define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 405 #define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 406 #define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 407 #define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 408 409 /* SXP CONF2 REGISTER */ 410 #define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 411 #define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 412 #define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 413 #define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 414 #define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 415 #define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 416 417 /* SXP INTERRUPT REGISTER */ 418 #define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 419 #define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 420 #define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 421 #define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 422 #define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 423 #define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 424 #define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 425 #define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 426 #define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 427 #define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 428 429 430 /* SXP GROSS ERROR REGISTER */ 431 #define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 432 #define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 433 #define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 434 #define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 435 #define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 436 #define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 437 #define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 438 439 /* SXP EXCEPTION REGISTER */ 440 #define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 441 #define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 442 #define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 443 #define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 444 #define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 445 #define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 446 #define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 447 #define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 448 #define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 449 #define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 450 451 /* SXP OVERRIDE REGISTER */ 452 #define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 453 #define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 454 #define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 455 #define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 456 #define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 457 #define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 458 #define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 459 #define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 460 #define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 461 #define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 462 #define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 463 #define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 464 #define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 465 466 /* SXP COMMANDS */ 467 #define SXP_RESET_BUS_CMD 0x300b 468 469 /* SXP SCSI ID REGISTER */ 470 #define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 471 #define SXP_SELECT_ID 0x000F /* Select id */ 472 473 /* SXP DEV CONFIG1 REGISTER */ 474 #define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 475 #define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 476 #define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 477 478 479 /* SXP DEV CONFIG2 REGISTER */ 480 #define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 481 #define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 482 #define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 483 #define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 484 #define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 485 486 487 /* SXP PHASE POINTER REGISTER */ 488 #define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 489 #define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 490 #define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 491 #define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 492 493 494 /* SXP FIFO STATUS REGISTER */ 495 #define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 496 #define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 497 #define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 498 #define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 499 500 501 /* SXP CONTROL PINS REGISTER */ 502 #define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 503 #define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 504 #define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 505 #define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 506 #define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 507 #define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 508 #define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 509 #define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 510 #define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 511 #define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 512 #define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 513 #define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 514 515 /* 516 * Set the hold time for the SCSI Bus Reset to be 250 ms 517 */ 518 #define SXP_SCSI_BUS_RESET_HOLD_TIME 250 519 520 /* SXP DIFF PINS REGISTER */ 521 #define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 522 #define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 523 #define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 524 #define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 525 #define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 526 #define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 527 528 /* Ultra2 only */ 529 #define SXP_PINS_LVD_MODE 0x1000 530 #define SXP_PINS_HVD_MODE 0x0800 531 #define SXP_PINS_SE_MODE 0x0400 532 533 /* The above have to be put together with the DIFFM pin to make sense */ 534 #define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 535 #define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 536 #define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 537 #define ISP1080_MODE_MASK \ 538 (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE) 539 540 /* 541 * RISC and Host Command and Control Block Register Offsets 542 */ 543 544 #define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 545 #define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 546 #define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 547 #define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 548 #define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 549 #define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 550 #define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 551 #define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 552 #define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 553 #define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 554 #define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 555 #define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 556 #define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 557 #define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 558 #define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 559 #define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 560 #define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 561 #define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 562 #define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 563 #define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 564 #define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 565 #define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 566 #define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 567 #define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 568 #define RISC_MTR2100 RISC_BLOCK+0x30 569 570 #define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 571 #define DUAL_BANK 8 572 #define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 573 #define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 574 #define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 575 #define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 576 #define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 577 #define TCR RISC_BLOCK+0x46 /* W : Test Control */ 578 #define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 579 580 581 /* PROCESSOR STATUS REGISTER */ 582 #define RISC_PSR_FORCE_TRUE 0x8000 583 #define RISC_PSR_LOOP_COUNT_DONE 0x4000 584 #define RISC_PSR_RISC_INT 0x2000 585 #define RISC_PSR_TIMER_ROLLOVER 0x1000 586 #define RISC_PSR_ALU_OVERFLOW 0x0800 587 #define RISC_PSR_ALU_MSB 0x0400 588 #define RISC_PSR_ALU_CARRY 0x0200 589 #define RISC_PSR_ALU_ZERO 0x0100 590 591 #define RISC_PSR_PCI_ULTRA 0x0080 592 #define RISC_PSR_SBUS_ULTRA 0x0020 593 594 #define RISC_PSR_DMA_INT 0x0010 595 #define RISC_PSR_SXP_INT 0x0008 596 #define RISC_PSR_HOST_INT 0x0004 597 #define RISC_PSR_INT_PENDING 0x0002 598 #define RISC_PSR_FORCE_FALSE 0x0001 599 600 601 /* Host Command and Control */ 602 #define HCCR_CMD_NOP 0x0000 /* NOP */ 603 #define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 604 #define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 605 #define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 606 #define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 607 #define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 608 #define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 609 #define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 610 #define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 611 #define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 612 #define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 613 #define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 614 #define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 615 616 #define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 617 #define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 618 #define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 619 #define ISP2100_HCCR_PARITY 0x0001 620 621 #define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 622 #define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 623 #define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 624 625 #define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 626 #define HCCR_RESET 0x0040 /* R : reset in progress */ 627 #define HCCR_PAUSE 0x0020 /* R : RISC paused */ 628 629 #define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 630 631 /* 632 * NVRAM Definitions (PCI cards only) 633 */ 634 635 #define ISPBSMX(c, byte, shift, mask) \ 636 (((c)[(byte)] >> (shift)) & (mask)) 637 /* 638 * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 639 * 640 * Some portion of the front of this is for general host adapter properties 641 * This is followed by an array of per-target parameters, and is tailed off 642 * with a checksum xor byte at offset 127. For non-byte entities data is 643 * stored in Little Endian order. 644 */ 645 646 #define ISP_NVRAM_SIZE 128 647 648 #define ISP_NVRAM_VERSION(c) (c)[4] 649 #define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 650 #define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 651 #define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 652 #define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 653 #define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 654 #define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 655 #define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 656 #define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 657 #define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 658 #define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 659 #define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 660 #define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 661 #define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 662 #define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 663 #define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 664 #define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 665 #define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 666 #define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 667 #define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 668 #define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 669 #define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 670 #define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 671 #define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 672 #define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 673 #define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 674 #define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 675 #define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 676 #define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 677 #define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 678 679 #define ISP_NVRAM_TARGOFF 28 680 #define ISP_NVARM_TARGSIZE 6 681 #define _IxT(tgt, tidx) \ 682 (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) 683 #define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 684 #define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 685 #define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 686 #define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 687 #define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 688 #define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 689 #define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 690 #define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 691 #define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 692 #define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 693 #define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 694 #define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 695 #define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 696 697 /* 698 * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 699 * 700 * Some portion of the front of this is for general host adapter properties 701 * This is followed by an array of per-target parameters, and is tailed off 702 * with a checksum xor byte at offset 256. For non-byte entities data is 703 * stored in Little Endian order. 704 */ 705 706 #define ISP1080_NVRAM_SIZE 256 707 708 #define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 709 710 /* Offset 5 */ 711 /* 712 u_int8_t bios_configuration_mode :2; 713 u_int8_t bios_disable :1; 714 u_int8_t selectable_scsi_boot_enable :1; 715 u_int8_t cd_rom_boot_enable :1; 716 u_int8_t disable_loading_risc_code :1; 717 u_int8_t enable_64bit_addressing :1; 718 u_int8_t unused_7 :1; 719 */ 720 721 /* Offsets 6, 7 */ 722 /* 723 u_int8_t boot_lun_number :5; 724 u_int8_t scsi_bus_number :1; 725 u_int8_t unused_6 :1; 726 u_int8_t unused_7 :1; 727 u_int8_t boot_target_number :4; 728 u_int8_t unused_12 :1; 729 u_int8_t unused_13 :1; 730 u_int8_t unused_14 :1; 731 u_int8_t unused_15 :1; 732 */ 733 734 #define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 735 736 #define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 737 #define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 738 739 #define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 740 #define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 741 #define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 742 743 #define ISP1080_ISP_PARAMETER(c) \ 744 (((c)[18]) | ((c)[19] << 8)) 745 746 #define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) 747 #define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) 748 749 #define ISP1080_BUS1_OFF 112 750 751 #define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 752 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 753 #define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 754 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 755 #define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 756 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 757 #define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 758 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 759 760 #define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 761 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 762 #define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 763 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 764 #define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 765 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 766 #define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 767 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 768 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 769 #define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 770 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 771 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 772 773 #define ISP1080_NVRAM_TARGOFF(b) \ 774 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 775 #define ISP1080_NVRAM_TARGSIZE 6 776 #define _IxT8(tgt, tidx, b) \ 777 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 778 779 #define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 780 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 781 #define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 782 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 783 #define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 784 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 785 #define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 786 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 787 #define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 788 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 789 #define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 790 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 791 #define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 792 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 793 #define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 794 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 795 #define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 796 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 797 #define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 798 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 799 #define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 800 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 801 #define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 802 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 803 #define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 804 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 805 806 #define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE 807 #define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE 808 #define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD 809 #define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT 810 #define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE 811 #define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE 812 #define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER 813 #define ISP12160_FAST_POST ISP1080_FAST_POST 814 #define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION 815 816 #define ISP12160_NVRAM_INITIATOR_ID \ 817 ISP1080_NVRAM_INITIATOR_ID 818 #define ISP12160_NVRAM_BUS_RESET_DELAY \ 819 ISP1080_NVRAM_BUS_RESET_DELAY 820 #define ISP12160_NVRAM_BUS_RETRY_COUNT \ 821 ISP1080_NVRAM_BUS_RETRY_COUNT 822 #define ISP12160_NVRAM_BUS_RETRY_DELAY \ 823 ISP1080_NVRAM_BUS_RETRY_DELAY 824 #define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ 825 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME 826 #define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ 827 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION 828 #define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ 829 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION 830 #define ISP12160_NVRAM_SELECTION_TIMEOUT \ 831 ISP1080_NVRAM_SELECTION_TIMEOUT 832 #define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ 833 ISP1080_NVRAM_MAX_QUEUE_DEPTH 834 835 836 #define ISP12160_BUS0_OFF 24 837 #define ISP12160_BUS1_OFF 136 838 839 #define ISP12160_NVRAM_TARGOFF(b) \ 840 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) 841 842 #define ISP12160_NVRAM_TARGSIZE 6 843 #define _IxT16(tgt, tidx, b) \ 844 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) 845 846 #define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ 847 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) 848 #define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ 849 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) 850 #define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ 851 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) 852 #define ISP12160_NVRAM_TGT_TQING(c, t, b) \ 853 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) 854 #define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ 855 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) 856 #define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ 857 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) 858 #define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ 859 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) 860 #define ISP12160_NVRAM_TGT_DISC(c, t, b) \ 861 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) 862 863 #define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 864 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) 865 #define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 866 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) 867 868 #define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 869 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) 870 #define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 871 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) 872 873 #define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ 874 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) 875 #define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ 876 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) 877 #define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ 878 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) 879 880 /* 881 * Qlogic 2XXX NVRAM is an array of 256 bytes. 882 * 883 * Some portion of the front of this is for general RISC engine parameters, 884 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 885 * 886 * This is followed by some general host adapter parameters, and ends with 887 * a checksum xor byte at offset 255. For non-byte entities data is stored 888 * in Little Endian order. 889 */ 890 #define ISP2100_NVRAM_SIZE 256 891 /* ISP_NVRAM_VERSION is in same overall place */ 892 #define ISP2100_NVRAM_RISCVER(c) (c)[6] 893 #define ISP2100_NVRAM_OPTIONS(c) (c)[8] 894 #define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 895 #define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 896 #define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 897 #define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 898 #define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 899 900 #define ISP2100_NVRAM_PORT_NAME(c) (\ 901 (((u_int64_t)(c)[18]) << 56) | \ 902 (((u_int64_t)(c)[19]) << 48) | \ 903 (((u_int64_t)(c)[20]) << 40) | \ 904 (((u_int64_t)(c)[21]) << 32) | \ 905 (((u_int64_t)(c)[22]) << 24) | \ 906 (((u_int64_t)(c)[23]) << 16) | \ 907 (((u_int64_t)(c)[24]) << 8) | \ 908 (((u_int64_t)(c)[25]) << 0)) 909 910 #define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] 911 912 #define ISP2100_NVRAM_NODE_NAME(c) (\ 913 (((u_int64_t)(c)[30]) << 56) | \ 914 (((u_int64_t)(c)[31]) << 48) | \ 915 (((u_int64_t)(c)[32]) << 40) | \ 916 (((u_int64_t)(c)[33]) << 32) | \ 917 (((u_int64_t)(c)[34]) << 24) | \ 918 (((u_int64_t)(c)[35]) << 16) | \ 919 (((u_int64_t)(c)[36]) << 8) | \ 920 (((u_int64_t)(c)[37]) << 0)) 921 922 #define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70] 923 #define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 924 #define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 925 #define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 926 #define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 927 #define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 928 #define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 929 930 #define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 931 (((u_int64_t)(c)[72]) << 56) | \ 932 (((u_int64_t)(c)[73]) << 48) | \ 933 (((u_int64_t)(c)[74]) << 40) | \ 934 (((u_int64_t)(c)[75]) << 32) | \ 935 (((u_int64_t)(c)[76]) << 24) | \ 936 (((u_int64_t)(c)[77]) << 16) | \ 937 (((u_int64_t)(c)[78]) << 8) | \ 938 (((u_int64_t)(c)[79]) << 0)) 939 940 #define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 941 942 #endif /* _ISPREG_H */ 943
Indexes created Sat Sep 27 21:09:56 GMT 2025