ispreg.h revision 1.24
1 /* $NetBSD: ispreg.h,v 1.24 2000/12/23 01:38:01 wiz Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob (at) netbsd.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* release_6_5_99 */ 31 /* 32 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. The name of the author may not be used to endorse or promote products 44 * derived from this software without specific prior written permission 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57 /* 58 * Machine Independent (well, as best as possible) register 59 * definitions for Qlogic ISP SCSI adapters. 60 * 61 * Matthew Jacob <mjacob (at) nas.nasa.gov> 62 * 63 */ 64 #ifndef _ISPREG_H 65 #define _ISPREG_H 66 67 /* 68 * Hardware definitions for the Qlogic ISP registers. 69 */ 70 71 /* 72 * This defines types of access to various registers. 73 * 74 * R: Read Only 75 * W: Write Only 76 * RW: Read/Write 77 * 78 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 79 * if RISC processor in ISP is paused. 80 */ 81 82 /* 83 * Offsets for various register blocks. 84 * 85 * Sad but true, different architectures have different offsets. 86 * 87 * Don't be alarmed if none of this makes sense. The original register 88 * layout set some defines in a certain pattern. Everything else has been 89 * grafted on since. For example, the ISP1080 manual will state that DMA 90 * registers start at 0x80 from the base of the register address space. 91 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 92 * to start at offset 0x60 because the DMA registers are all defined to 93 * be DMA_BLOCK+0x20 and so on. Clear? 94 */ 95 96 #define BIU_REGS_OFF 0x00 97 98 #define PCI_MBOX_REGS_OFF 0x70 99 #define PCI_MBOX_REGS2100_OFF 0x10 100 #define SBUS_MBOX_REGS_OFF 0x80 101 102 #define PCI_SXP_REGS_OFF 0x80 103 #define SBUS_SXP_REGS_OFF 0x200 104 105 #define PCI_RISC_REGS_OFF 0x80 106 #define SBUS_RISC_REGS_OFF 0x400 107 108 /* Bless me! Chip designers have putzed it again! */ 109 #define ISP1080_DMA_REGS_OFF 0x60 110 #define DMA_REGS_OFF 0x00 /* same as BIU block */ 111 112 #define SBUS_REGSIZE 0x450 113 #define PCI_REGSIZE 0x100 114 115 /* 116 * NB: The *_BLOCK definitions have no specific hardware meaning. 117 * They serve simply to note to the MD layer which block of 118 * registers offsets are being accessed. 119 */ 120 #define _NREG_BLKS 5 121 #define _BLK_REG_SHFT 13 122 #define _BLK_REG_MASK (7 << _BLK_REG_SHFT) 123 #define BIU_BLOCK (0 << _BLK_REG_SHFT) 124 #define MBOX_BLOCK (1 << _BLK_REG_SHFT) 125 #define SXP_BLOCK (2 << _BLK_REG_SHFT) 126 #define RISC_BLOCK (3 << _BLK_REG_SHFT) 127 #define DMA_BLOCK (4 << _BLK_REG_SHFT) 128 129 /* 130 * Bus Interface Block Register Offsets 131 */ 132 133 #define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */ 134 #define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0) 135 #define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */ 136 #define BIU2100_FLASH_DATA (BIU_BLOCK+0x2) 137 #define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */ 138 #define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */ 139 #define BIU2100_CSR (BIU_BLOCK+0x6) 140 #define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */ 141 #define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */ 142 #define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */ 143 #define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ 144 #define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ 145 #define RDMA2100_CONTROL DFIFO_COMMAND 146 #define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ 147 148 /* 149 * Putzed DMA register layouts. 150 */ 151 #define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */ 152 #define CDMA2100_CONTROL CDMA_CONF 153 #define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */ 154 #define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */ 155 #define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */ 156 #define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */ 157 #define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */ 158 #define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */ 159 #define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */ 160 #define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */ 161 162 #define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */ 163 #define TDMA2100_CONTROL DDMA_CONF 164 #define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */ 165 #define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */ 166 #define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */ 167 #define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */ 168 #define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */ 169 #define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */ 170 #define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */ 171 /* these are for the 1040A cards */ 172 #define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */ 173 #define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */ 174 175 176 /* 177 * Bus Interface Block Register Definitions 178 */ 179 /* BUS CONFIGURATION REGISTER #0 */ 180 #define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 181 /* BUS CONFIGURATION REGISTER #1 */ 182 183 #define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 184 #define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 185 186 #define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 187 #define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 188 #define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 189 #define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 190 #define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 191 #define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 192 #define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 193 #define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 194 #define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 195 #define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 196 #define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 197 198 #define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */ 199 #define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */ 200 #define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 201 202 /* ISP2100 Bus Control/Status Register */ 203 204 #define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 205 #define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 206 #define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 207 #define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 208 #define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 209 #define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ 210 #define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 211 #define BIU2100_SOFT_RESET 0x01 212 /* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 213 214 215 /* BUS CONTROL REGISTER */ 216 #define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 217 #define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 218 #define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 219 #define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 220 #define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 221 #define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 222 223 #define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 224 #define BIU2100_ICR_ENA_FPM_INT 0x0020 225 #define BIU2100_ICR_ENA_FB_INT 0x0010 226 #define BIU2100_ICR_ENA_RISC_INT 0x0008 227 #define BIU2100_ICR_ENA_CDMA_INT 0x0004 228 #define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 229 #define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 230 #define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 231 232 #define ENABLE_INTS(isp) (IS_SCSI(isp))? \ 233 ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ 234 ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) 235 236 #define INTS_ENABLED(isp) ((IS_SCSI(isp))? \ 237 (ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\ 238 (ISP_READ(isp, BIU_ICR) & \ 239 (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS))) 240 241 #define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) 242 243 /* BUS STATUS REGISTER */ 244 #define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 245 #define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 246 #define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 247 #define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 248 #define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 249 250 #define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 251 #define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 252 #define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 253 #define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 254 #define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 255 #define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 256 #define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 257 258 #define INT_PENDING(isp, isr) (IS_FC(isp)? \ 259 ((isr & BIU2100_ISR_RISC_INT) != 0) : ((isr & BIU_ISR_RISC_INT) != 0)) 260 261 #define INT_PENDING_MASK(isp) \ 262 (IS_FC(isp)? BIU2100_ISR_RISC_INT: BIU_ISR_RISC_INT) 263 264 /* BUS SEMAPHORE REGISTER */ 265 #define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 266 #define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 267 268 /* NVRAM SEMAPHORE REGISTER */ 269 #define BIU_NVRAM_CLOCK 0x0001 270 #define BIU_NVRAM_SELECT 0x0002 271 #define BIU_NVRAM_DATAOUT 0x0004 272 #define BIU_NVRAM_DATAIN 0x0008 273 #define ISP_NVRAM_READ 6 274 275 /* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 276 #define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 277 #define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 278 #define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 279 #define DMA_DMA_DIRECTION 0x0001 /* 280 * Set DMA direction: 281 * 0 - DMA FIFO to host 282 * 1 - Host to DMA FIFO 283 */ 284 285 /* COMMAND && DATA DMA CONTROL REGISTER */ 286 #define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 287 #define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 288 * Clear FIFO and DMA Channel, 289 * reset DMA registers 290 */ 291 #define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 292 #define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 293 #define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 294 295 /* 296 * Variants of same for 2100 297 */ 298 #define DMA_CNTRL2100_CLEAR_CHAN 0x0004 299 #define DMA_CNTRL2100_RESET_INT 0x0002 300 301 302 303 /* DMA STATUS REGISTER */ 304 #define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 305 #define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 306 #define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 307 #define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 308 #define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 309 #define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 310 311 #define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 312 #define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 313 #define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 314 #define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 315 #define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 316 #define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 317 #define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 318 #define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 319 #define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 320 #define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 321 #define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 322 323 /* DMA Status Register, pipeline status bits */ 324 #define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 325 #define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 326 #define DMA_SBUS_PIPE_STAGE1 0x0040 /* 327 * Pipeline stage 1 Loaded, 328 * stage 2 empty 329 */ 330 #define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 331 #define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 332 #define DMA_PCI_PIPE_STAGE1 0x0001 /* 333 * Pipeline stage 1 Loaded, 334 * stage 2 empty 335 */ 336 #define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 337 338 /* DMA Status Register, channel status bits */ 339 #define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 340 #define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 341 #define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 342 #define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 343 #define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 344 #define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 345 #define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 346 347 348 /* DMA FIFO STATUS REGISTER */ 349 #define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 350 #define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 351 #define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 352 #define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 353 354 /* 355 * Mailbox Block Register Offsets 356 */ 357 358 #define INMAILBOX0 (MBOX_BLOCK+0x0) 359 #define INMAILBOX1 (MBOX_BLOCK+0x2) 360 #define INMAILBOX2 (MBOX_BLOCK+0x4) 361 #define INMAILBOX3 (MBOX_BLOCK+0x6) 362 #define INMAILBOX4 (MBOX_BLOCK+0x8) 363 #define INMAILBOX5 (MBOX_BLOCK+0xA) 364 #define INMAILBOX6 (MBOX_BLOCK+0xC) 365 #define INMAILBOX7 (MBOX_BLOCK+0xE) 366 367 #define OUTMAILBOX0 (MBOX_BLOCK+0x0) 368 #define OUTMAILBOX1 (MBOX_BLOCK+0x2) 369 #define OUTMAILBOX2 (MBOX_BLOCK+0x4) 370 #define OUTMAILBOX3 (MBOX_BLOCK+0x6) 371 #define OUTMAILBOX4 (MBOX_BLOCK+0x8) 372 #define OUTMAILBOX5 (MBOX_BLOCK+0xA) 373 #define OUTMAILBOX6 (MBOX_BLOCK+0xC) 374 #define OUTMAILBOX7 (MBOX_BLOCK+0xE) 375 376 #define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) 377 #define NMBOX(isp) \ 378 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 379 ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 380 #define NMBOX_BMASK(isp) \ 381 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 382 ((isp)->isp_type & ISP_HA_FC))? 0xff : 0x3f) 383 384 #define MAX_MAILBOX 8 385 386 /* 387 * SXP Block Register Offsets 388 */ 389 #define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 390 #define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 391 #define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 392 #define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 393 #define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 394 #define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 395 #define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 396 #define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 397 #define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 398 #define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 399 #define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 400 #define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 401 #define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 402 #define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 403 #define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 404 #define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 405 #define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 406 #define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 407 #define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 408 #define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 409 #define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 410 #define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 411 #define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 412 #define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 413 #define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 414 #define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 415 #define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 416 #define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 417 #define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 418 #define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 419 #define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ 420 #define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 421 #define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 422 #define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 423 #define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 424 #define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 425 #define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 426 #define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 427 #define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ 428 429 /* for 1080/1280/1240 only */ 430 #define SXP_BANK1_SELECT 0x100 431 432 433 /* SXP CONF1 REGISTER */ 434 #define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 435 #define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 436 #define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 437 #define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 438 #define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 439 440 /* SXP CONF2 REGISTER */ 441 #define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 442 #define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 443 #define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 444 #define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 445 #define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 446 #define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 447 448 /* SXP INTERRUPT REGISTER */ 449 #define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 450 #define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 451 #define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 452 #define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 453 #define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 454 #define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 455 #define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 456 #define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 457 #define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 458 #define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 459 460 461 /* SXP GROSS ERROR REGISTER */ 462 #define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 463 #define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 464 #define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 465 #define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 466 #define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 467 #define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 468 #define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 469 470 /* SXP EXCEPTION REGISTER */ 471 #define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 472 #define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 473 #define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 474 #define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 475 #define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 476 #define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 477 #define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 478 #define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 479 #define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 480 #define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 481 482 /* SXP OVERRIDE REGISTER */ 483 #define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 484 #define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 485 #define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 486 #define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 487 #define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 488 #define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 489 #define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 490 #define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 491 #define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 492 #define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 493 #define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 494 #define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 495 #define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 496 497 /* SXP COMMANDS */ 498 #define SXP_RESET_BUS_CMD 0x300b 499 500 /* SXP SCSI ID REGISTER */ 501 #define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 502 #define SXP_SELECT_ID 0x000F /* Select id */ 503 504 /* SXP DEV CONFIG1 REGISTER */ 505 #define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 506 #define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 507 #define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 508 509 510 /* SXP DEV CONFIG2 REGISTER */ 511 #define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 512 #define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 513 #define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 514 #define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 515 #define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 516 517 518 /* SXP PHASE POINTER REGISTER */ 519 #define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 520 #define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 521 #define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 522 #define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 523 524 525 /* SXP FIFO STATUS REGISTER */ 526 #define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 527 #define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 528 #define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 529 #define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 530 531 532 /* SXP CONTROL PINS REGISTER */ 533 #define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 534 #define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 535 #define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 536 #define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 537 #define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 538 #define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 539 #define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 540 #define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 541 #define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 542 #define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 543 #define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 544 #define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 545 546 /* 547 * Set the hold time for the SCSI Bus Reset to be 250 ms 548 */ 549 #define SXP_SCSI_BUS_RESET_HOLD_TIME 250 550 551 /* SXP DIFF PINS REGISTER */ 552 #define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 553 #define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 554 #define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 555 #define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 556 #define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 557 #define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 558 559 /* Ultra2 only */ 560 #define SXP_PINS_LVD_MODE 0x1000 561 #define SXP_PINS_HVD_MODE 0x0800 562 #define SXP_PINS_SE_MODE 0x0400 563 564 /* The above have to be put together with the DIFFM pin to make sense */ 565 #define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 566 #define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 567 #define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 568 #define ISP1080_MODE_MASK \ 569 (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE) 570 571 /* 572 * RISC and Host Command and Control Block Register Offsets 573 */ 574 575 #define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 576 #define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 577 #define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 578 #define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 579 #define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 580 #define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 581 #define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 582 #define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 583 #define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 584 #define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 585 #define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 586 #define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 587 #define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 588 #define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 589 #define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 590 #define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 591 #define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 592 #define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 593 #define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 594 #define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 595 #define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 596 #define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 597 #define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 598 #define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 599 #define RISC_MTR2100 RISC_BLOCK+0x30 600 601 #define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 602 #define DUAL_BANK 8 603 #define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 604 #define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 605 #define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 606 #define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 607 #define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 608 #define TCR RISC_BLOCK+0x46 /* W : Test Control */ 609 #define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 610 611 612 /* PROCESSOR STATUS REGISTER */ 613 #define RISC_PSR_FORCE_TRUE 0x8000 614 #define RISC_PSR_LOOP_COUNT_DONE 0x4000 615 #define RISC_PSR_RISC_INT 0x2000 616 #define RISC_PSR_TIMER_ROLLOVER 0x1000 617 #define RISC_PSR_ALU_OVERFLOW 0x0800 618 #define RISC_PSR_ALU_MSB 0x0400 619 #define RISC_PSR_ALU_CARRY 0x0200 620 #define RISC_PSR_ALU_ZERO 0x0100 621 622 #define RISC_PSR_PCI_ULTRA 0x0080 623 #define RISC_PSR_SBUS_ULTRA 0x0020 624 625 #define RISC_PSR_DMA_INT 0x0010 626 #define RISC_PSR_SXP_INT 0x0008 627 #define RISC_PSR_HOST_INT 0x0004 628 #define RISC_PSR_INT_PENDING 0x0002 629 #define RISC_PSR_FORCE_FALSE 0x0001 630 631 632 /* Host Command and Control */ 633 #define HCCR_CMD_NOP 0x0000 /* NOP */ 634 #define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 635 #define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 636 #define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 637 #define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 638 #define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 639 #define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 640 #define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 641 #define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 642 #define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 643 #define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 644 #define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 645 #define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 646 647 #define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 648 #define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 649 #define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 650 #define ISP2100_HCCR_PARITY 0x0001 651 652 #define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 653 #define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 654 #define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 655 656 #define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 657 #define HCCR_RESET 0x0040 /* R : reset in progress */ 658 #define HCCR_PAUSE 0x0020 /* R : RISC paused */ 659 660 #define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 661 662 /* 663 * NVRAM Definitions (PCI cards only) 664 */ 665 666 #define ISPBSMX(c, byte, shift, mask) \ 667 (((c)[(byte)] >> (shift)) & (mask)) 668 /* 669 * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 670 * 671 * Some portion of the front of this is for general host adapter properties 672 * This is followed by an array of per-target parameters, and is tailed off 673 * with a checksum xor byte at offset 127. For non-byte entities data is 674 * stored in Little Endian order. 675 */ 676 677 #define ISP_NVRAM_SIZE 128 678 679 #define ISP_NVRAM_VERSION(c) (c)[4] 680 #define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 681 #define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 682 #define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 683 #define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 684 #define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 685 #define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 686 #define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 687 #define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 688 #define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 689 #define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 690 #define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 691 #define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 692 #define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 693 #define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 694 #define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 695 #define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 696 #define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 697 #define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 698 #define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 699 #define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 700 #define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 701 #define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 702 #define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 703 #define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 704 #define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 705 #define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 706 #define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 707 #define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 708 #define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 709 710 #define ISP_NVRAM_TARGOFF 28 711 #define ISP_NVARM_TARGSIZE 6 712 #define _IxT(tgt, tidx) \ 713 (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) 714 #define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 715 #define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 716 #define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 717 #define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 718 #define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 719 #define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 720 #define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 721 #define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 722 #define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 723 #define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 724 #define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 725 #define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 726 #define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 727 728 /* 729 * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 730 * 731 * Some portion of the front of this is for general host adapter properties 732 * This is followed by an array of per-target parameters, and is tailed off 733 * with a checksum xor byte at offset 256. For non-byte entities data is 734 * stored in Little Endian order. 735 */ 736 737 #define ISP1080_NVRAM_SIZE 256 738 739 #define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 740 741 /* Offset 5 */ 742 /* 743 u_int8_t bios_configuration_mode :2; 744 u_int8_t bios_disable :1; 745 u_int8_t selectable_scsi_boot_enable :1; 746 u_int8_t cd_rom_boot_enable :1; 747 u_int8_t disable_loading_risc_code :1; 748 u_int8_t enable_64bit_addressing :1; 749 u_int8_t unused_7 :1; 750 */ 751 752 /* Offsets 6, 7 */ 753 /* 754 u_int8_t boot_lun_number :5; 755 u_int8_t scsi_bus_number :1; 756 u_int8_t unused_6 :1; 757 u_int8_t unused_7 :1; 758 u_int8_t boot_target_number :4; 759 u_int8_t unused_12 :1; 760 u_int8_t unused_13 :1; 761 u_int8_t unused_14 :1; 762 u_int8_t unused_15 :1; 763 */ 764 765 #define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 766 767 #define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 768 #define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 769 770 #define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 771 #define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 772 #define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 773 774 #define ISP1080_ISP_PARAMETER(c) \ 775 (((c)[18]) | ((c)[19] << 8)) 776 777 #define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) 778 #define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) 779 780 #define ISP1080_BUS1_OFF 112 781 782 #define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 783 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 784 #define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 785 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 786 #define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 787 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 788 #define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 789 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 790 791 #define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 792 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 793 #define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 794 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 795 #define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 796 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 797 #define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 798 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 799 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 800 #define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 801 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 802 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 803 804 #define ISP1080_NVRAM_TARGOFF(b) \ 805 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 806 #define ISP1080_NVRAM_TARGSIZE 6 807 #define _IxT8(tgt, tidx, b) \ 808 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 809 810 #define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 811 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 812 #define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 813 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 814 #define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 815 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 816 #define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 817 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 818 #define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 819 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 820 #define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 821 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 822 #define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 823 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 824 #define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 825 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 826 #define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 827 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 828 #define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 829 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 830 #define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 831 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 832 #define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 833 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 834 #define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 835 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 836 837 #define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE 838 #define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE 839 #define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD 840 #define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT 841 #define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE 842 #define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE 843 #define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER 844 #define ISP12160_FAST_POST ISP1080_FAST_POST 845 #define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION 846 847 #define ISP12160_NVRAM_INITIATOR_ID \ 848 ISP1080_NVRAM_INITIATOR_ID 849 #define ISP12160_NVRAM_BUS_RESET_DELAY \ 850 ISP1080_NVRAM_BUS_RESET_DELAY 851 #define ISP12160_NVRAM_BUS_RETRY_COUNT \ 852 ISP1080_NVRAM_BUS_RETRY_COUNT 853 #define ISP12160_NVRAM_BUS_RETRY_DELAY \ 854 ISP1080_NVRAM_BUS_RETRY_DELAY 855 #define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ 856 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME 857 #define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ 858 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION 859 #define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ 860 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION 861 #define ISP12160_NVRAM_SELECTION_TIMEOUT \ 862 ISP1080_NVRAM_SELECTION_TIMEOUT 863 #define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ 864 ISP1080_NVRAM_MAX_QUEUE_DEPTH 865 866 867 #define ISP12160_BUS0_OFF 24 868 #define ISP12160_BUS1_OFF 136 869 870 #define ISP12160_NVRAM_TARGOFF(b) \ 871 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) 872 873 #define ISP12160_NVRAM_TARGSIZE 6 874 #define _IxT16(tgt, tidx, b) \ 875 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) 876 877 #define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ 878 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) 879 #define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ 880 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) 881 #define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ 882 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) 883 #define ISP12160_NVRAM_TGT_TQING(c, t, b) \ 884 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) 885 #define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ 886 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) 887 #define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ 888 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) 889 #define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ 890 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) 891 #define ISP12160_NVRAM_TGT_DISC(c, t, b) \ 892 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) 893 894 #define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 895 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) 896 #define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 897 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) 898 899 #define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 900 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) 901 #define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 902 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) 903 904 #define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ 905 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) 906 #define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ 907 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) 908 #define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ 909 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) 910 911 /* 912 * Qlogic 2XXX NVRAM is an array of 256 bytes. 913 * 914 * Some portion of the front of this is for general RISC engine parameters, 915 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 916 * 917 * This is followed by some general host adapter parameters, and ends with 918 * a checksum xor byte at offset 255. For non-byte entities data is stored 919 * in Little Endian order. 920 */ 921 #define ISP2100_NVRAM_SIZE 256 922 /* ISP_NVRAM_VERSION is in same overall place */ 923 #define ISP2100_NVRAM_RISCVER(c) (c)[6] 924 #define ISP2100_NVRAM_OPTIONS(c) (c)[8] 925 #define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 926 #define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 927 #define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 928 #define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 929 #define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 930 931 #define ISP2100_NVRAM_PORT_NAME(c) (\ 932 (((u_int64_t)(c)[18]) << 56) | \ 933 (((u_int64_t)(c)[19]) << 48) | \ 934 (((u_int64_t)(c)[20]) << 40) | \ 935 (((u_int64_t)(c)[21]) << 32) | \ 936 (((u_int64_t)(c)[22]) << 24) | \ 937 (((u_int64_t)(c)[23]) << 16) | \ 938 (((u_int64_t)(c)[24]) << 8) | \ 939 (((u_int64_t)(c)[25]) << 0)) 940 941 #define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] 942 943 #define ISP2100_NVRAM_NODE_NAME(c) (\ 944 (((u_int64_t)(c)[30]) << 56) | \ 945 (((u_int64_t)(c)[31]) << 48) | \ 946 (((u_int64_t)(c)[32]) << 40) | \ 947 (((u_int64_t)(c)[33]) << 32) | \ 948 (((u_int64_t)(c)[34]) << 24) | \ 949 (((u_int64_t)(c)[35]) << 16) | \ 950 (((u_int64_t)(c)[36]) << 8) | \ 951 (((u_int64_t)(c)[37]) << 0)) 952 953 #define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70] 954 #define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 955 #define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 956 #define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 957 #define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 958 #define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 959 #define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 960 961 #define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 962 (((u_int64_t)(c)[72]) << 56) | \ 963 (((u_int64_t)(c)[73]) << 48) | \ 964 (((u_int64_t)(c)[74]) << 40) | \ 965 (((u_int64_t)(c)[75]) << 32) | \ 966 (((u_int64_t)(c)[76]) << 24) | \ 967 (((u_int64_t)(c)[77]) << 16) | \ 968 (((u_int64_t)(c)[78]) << 8) | \ 969 (((u_int64_t)(c)[79]) << 0)) 970 971 #define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 972 973 #endif /* _ISPREG_H */ 974
Indexes created Mon Sep 29 21:09:56 GMT 2025