ispreg.h revision 1.3
1 /* $NetBSD: ispreg.h,v 1.3 1997/08/16 00:20:28 mjacob Exp $ */ 2 3 /* 4 * Machine Independent (well, as best as possible) register 5 * definitions for Qlogic ISP SCSI adapters. 6 * 7 * Copyright (c) 1997 by Matthew Jacob 8 * NASA/Ames Research Center 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice immediately at the beginning of the file, without modification, 16 * this list of conditions, and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #ifndef _ISPREG_H 37 #define _ISPREG_H 38 39 /* 40 * Hardware definitions for the Qlogic ISP registers. 41 */ 42 43 /* 44 * This defines types of access to various registers. 45 * 46 * R: Read Only 47 * W: Write Only 48 * RW: Read/Write 49 * 50 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 51 * if RISC processor in ISP is paused. 52 */ 53 54 /* 55 * Offsets for various register blocks. 56 * 57 * Sad but true, different architectures have different offsets. 58 */ 59 60 #define BIU_REGS_OFF 0x00 61 62 #define PCI_MBOX_REGS_OFF 0x70 63 #define PCI_MBOX_REGS2100_OFF 0x10 64 #define SBUS_MBOX_REGS_OFF 0x80 65 66 #define PCI_SXP_REGS_OFF 0x80 67 #define SBUS_SXP_REGS_OFF 0x200 68 69 #define PCI_RISC_REGS_OFF 0x80 70 #define SBUS_RISC_REGS_OFF 0x400 71 72 /* 73 * NB: The *_BLOCK definitions have no specific hardware meaning. 74 * They serve simply to note to the MD layer which block of 75 * registers offsets are being accessed. 76 */ 77 78 /* 79 * Bus Interface Block Register Offsets 80 */ 81 #define BIU_BLOCK 0x0100 82 #define BIU_ID_LO BIU_BLOCK+0x0 /* R : Bus ID, Low */ 83 #define BIU2100_FLASH_ADDR BIU_BLOCK+0x0 84 #define BIU_ID_HI BIU_BLOCK+0x2 /* R : Bus ID, High */ 85 #define BIU2100_FLASH_DATA BIU_BLOCK+0x2 86 #define BIU_CONF0 BIU_BLOCK+0x4 /* R : Bus Configuration #0 */ 87 #define BIU_CONF1 BIU_BLOCK+0x6 /* R : Bus Configuration #1 */ 88 #define BIU2100_CSR BIU_BLOCK+0x6 89 #define BIU_ICR BIU_BLOCK+0x8 /* RW : Bus Interface Ctrl */ 90 #define BIU_ISR BIU_BLOCK+0xA /* R : Bus Interface Status */ 91 #define BIU_SEMA BIU_BLOCK+0xC /* RW : Bus Semaphore */ 92 #define BIU_NVRAM BIU_BLOCK+0xE /* RW : Bus NVRAM */ 93 #define CDMA_CONF BIU_BLOCK+0x20 /* RW*: DMA Configuration */ 94 #define CDMA2100_CONTROL CDMA_CONF 95 #define CDMA_CONTROL BIU_BLOCK+0x22 /* RW*: DMA Control */ 96 #define CDMA_STATUS BIU_BLOCK+0x24 /* R : DMA Status */ 97 #define CDMA_FIFO_STS BIU_BLOCK+0x26 /* R : DMA FIFO Status */ 98 #define CDMA_COUNT BIU_BLOCK+0x28 /* RW*: DMA Transfer Count */ 99 #define CDMA_ADDR0 BIU_BLOCK+0x2C /* RW*: DMA Address, Word 0 */ 100 #define CDMA_ADDR1 BIU_BLOCK+0x2E /* RW*: DMA Address, Word 1 */ 101 /* these are for the 1040A cards */ 102 #define CDMA_ADDR2 BIU_BLOCK+0x30 /* RW*: DMA Address, Word 2 */ 103 #define CDMA_ADDR3 BIU_BLOCK+0x32 /* RW*: DMA Address, Word 3 */ 104 105 #define DDMA_CONF BIU_BLOCK+0x40 /* RW*: DMA Configuration */ 106 #define TDMA2100_CONTROL DDMA_CONF 107 #define DDMA_CONTROL BIU_BLOCK+0x42 /* RW*: DMA Control */ 108 #define DDMA_STATUS BIU_BLOCK+0x44 /* R : DMA Status */ 109 #define DDMA_FIFO_STS BIU_BLOCK+0x46 /* R : DMA FIFO Status */ 110 #define DDMA_COUNT_LO BIU_BLOCK+0x48 /* RW*: DMA Xfer Count, Low */ 111 #define DDMA_COUNT_HI BIU_BLOCK+0x4A /* RW*: DMA Xfer Count, High */ 112 #define DDMA_ADDR0 BIU_BLOCK+0x4C /* RW*: DMA Address, Word 0 */ 113 #define DDMA_ADDR1 BIU_BLOCK+0x4E /* RW*: DMA Address, Word 1 */ 114 /* these are for the 1040A cards */ 115 #define DDMA_ADDR2 BIU_BLOCK+0x50 /* RW*: DMA Address, Word 2 */ 116 #define DDMA_ADDR3 BIU_BLOCK+0x52 /* RW*: DMA Address, Word 3 */ 117 118 #define DFIFO_COMMAND BIU_BLOCK+0x60 /* RW : Command FIFO Port */ 119 #define RDMA2100_CONTROL DFIFO_COMMAND 120 #define DFIFO_DATA BIU_BLOCK+0x62 /* RW : Data FIFO Port */ 121 122 /* 123 * Bus Interface Block Register Definitions 124 */ 125 /* BUS CONFIGURATION REGISTER #0 */ 126 #define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 127 /* BUS CONFIGURATION REGISTER #1 */ 128 129 #define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 130 #define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 131 132 #define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 133 #define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 134 #define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 135 #define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 136 #define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 137 #define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 138 #define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 139 #define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 140 #define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 141 #define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 142 #define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 143 144 /* ISP2100 Bus Control/Status Register */ 145 146 #define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 147 #define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 148 #define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 149 #define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 150 #define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 151 #define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ 152 #define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 153 #define BIU2100_SOFT_RESET 0x01 154 /* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 155 156 157 /* BUS CONTROL REGISTER */ 158 #define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 159 #define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 160 #define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 161 #define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 162 #define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 163 #define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 164 165 #define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 166 #define BIU2100_ICR_ENA_FPM_INT 0x0020 167 #define BIU2100_ICR_ENA_FB_INT 0x0010 168 #define BIU2100_ICR_ENA_RISC_INT 0x0008 169 #define BIU2100_ICR_ENA_CDMA_INT 0x0004 170 #define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 171 #define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 172 #define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 173 174 #define ENABLE_INTS(isp) (isp->isp_type & ISP_HA_SCSI)? \ 175 ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ 176 ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) 177 178 #define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) 179 180 /* BUS STATUS REGISTER */ 181 #define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 182 #define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 183 #define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 184 #define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 185 #define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 186 187 #define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 188 #define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 189 #define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 190 #define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 191 #define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 192 #define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 193 #define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 194 195 196 /* BUS SEMAPHORE REGISTER */ 197 #define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 198 #define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 199 200 201 /* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 202 #define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 203 #define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 204 #define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 205 #define DMA_DMA_DIRECTION 0x0001 /* 206 * Set DMA direction: 207 * 0 - DMA FIFO to host 208 * 1 - Host to DMA FIFO 209 */ 210 211 /* COMMAND && DATA DMA CONTROL REGISTER */ 212 #define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 213 #define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 214 * Clear FIFO and DMA Channel, 215 * reset DMA registers 216 */ 217 #define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 218 #define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 219 #define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 220 221 /* 222 * Variants of same for 2100 223 */ 224 #define DMA_CNTRL2100_CLEAR_CHAN 0x0004 225 #define DMA_CNTRL2100_RESET_INT 0x0002 226 227 228 229 /* DMA STATUS REGISTER */ 230 #define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 231 #define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 232 #define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 233 #define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 234 #define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 235 #define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 236 237 #define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 238 #define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 239 #define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 240 #define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 241 #define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 242 #define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 243 #define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 244 #define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 245 #define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 246 #define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 247 #define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 248 249 /* DMA Status Register, pipeline status bits */ 250 #define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 251 #define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 252 #define DMA_SBUS_PIPE_STAGE1 0x0040 /* 253 * Pipeline stage 1 Loaded, 254 * stage 2 empty 255 */ 256 #define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 257 #define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 258 #define DMA_PCI_PIPE_STAGE1 0x0001 /* 259 * Pipeline stage 1 Loaded, 260 * stage 2 empty 261 */ 262 #define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 263 264 /* DMA Status Register, channel status bits */ 265 #define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 266 #define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 267 #define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 268 #define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 269 #define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 270 #define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 271 #define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 272 273 274 /* DMA FIFO STATUS REGISTER */ 275 #define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 276 #define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 277 #define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 278 #define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 279 280 /* 281 * Mailbox Block Register Offsets 282 */ 283 284 #define MBOX_BLOCK 0x0200 285 #define INMAILBOX0 MBOX_BLOCK+0x0 286 #define INMAILBOX1 MBOX_BLOCK+0x2 287 #define INMAILBOX2 MBOX_BLOCK+0x4 288 #define INMAILBOX3 MBOX_BLOCK+0x6 289 #define INMAILBOX4 MBOX_BLOCK+0x8 290 #define INMAILBOX5 MBOX_BLOCK+0xA 291 #define INMAILBOX6 MBOX_BLOCK+0xC 292 #define INMAILBOX7 MBOX_BLOCK+0xE 293 294 #define OUTMAILBOX0 MBOX_BLOCK+0x0 295 #define OUTMAILBOX1 MBOX_BLOCK+0x2 296 #define OUTMAILBOX2 MBOX_BLOCK+0x4 297 #define OUTMAILBOX3 MBOX_BLOCK+0x6 298 #define OUTMAILBOX4 MBOX_BLOCK+0x8 299 #define OUTMAILBOX5 MBOX_BLOCK+0xA 300 #define OUTMAILBOX6 MBOX_BLOCK+0xC 301 #define OUTMAILBOX7 MBOX_BLOCK+0xE 302 303 #define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2)) 304 #define NMBOX(isp) \ 305 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 306 ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 307 /* 308 * Mailbox Command Complete Status Codes 309 */ 310 #define MBOX_COMMAND_COMPLETE 0x4000 311 #define MBOX_INVALID_COMMAND 0x4001 312 #define MBOX_HOST_INTERFACE_ERROR 0x4002 313 #define MBOX_TEST_FAILED 0x4003 314 #define MBOX_COMMAND_ERROR 0x4005 315 #define MBOX_COMMAND_PARAM_ERROR 0x4006 316 317 /* 318 * Asynchronous event status codes 319 */ 320 #define ASYNC_BUS_RESET 0x8001 321 #define ASYNC_SYSTEM_ERROR 0x8002 322 #define ASYNC_RQS_XFER_ERR 0x8003 323 #define ASYNC_RSP_XFER_ERR 0x8004 324 #define ASYNC_QWAKEUP 0x8005 325 #define ASYNC_TIMEOUT_RESET 0x8006 326 327 /* for ISP2100 only */ 328 #define ASYNC_LIP_OCCURRED 0x8010 329 #define ASYNC_LOOP_UP 0x8011 330 #define ASYNC_LOOP_DOWN 0x8012 331 332 /* 333 * SXP Block Register Offsets 334 */ 335 #define SXP_BLOCK 0x0400 336 #define SXP_PART_ID SXP_BLOCK+0x0 /* R : Part ID Code */ 337 #define SXP_CONFIG1 SXP_BLOCK+0x2 /* RW*: Configuration Reg #1 */ 338 #define SXP_CONFIG2 SXP_BLOCK+0x4 /* RW*: Configuration Reg #2 */ 339 #define SXP_CONFIG3 SXP_BLOCK+0x6 /* RW*: Configuration Reg #2 */ 340 #define SXP_INSTRUCTION SXP_BLOCK+0xC /* RW*: Instruction Pointer */ 341 #define SXP_RETURN_ADDR SXP_BLOCK+0x10 /* RW*: Return Address */ 342 #define SXP_COMMAND SXP_BLOCK+0x14 /* RW*: Command */ 343 #define SXP_INTERRUPT SXP_BLOCK+0x18 /* R : Interrupt */ 344 #define SXP_SEQUENCE SXP_BLOCK+0x1C /* RW*: Sequence */ 345 #define SXP_GROSS_ERR SXP_BLOCK+0x1E /* R : Gross Error */ 346 #define SXP_EXCEPTION SXP_BLOCK+0x20 /* RW*: Exception Enable */ 347 #define SXP_OVERRIDE SXP_BLOCK+0x24 /* RW*: Override */ 348 #define SXP_LITERAL_BASE SXP_BLOCK+0x28 /* RW*: Literal Base */ 349 #define SXP_USER_FLAGS SXP_BLOCK+0x2C /* RW*: User Flags */ 350 #define SXP_USER_EXCEPT SXP_BLOCK+0x30 /* RW*: User Exception */ 351 #define SXP_BREAKPOINT SXP_BLOCK+0x34 /* RW*: Breakpoint */ 352 #define SXP_SCSI_ID SXP_BLOCK+0x40 /* RW*: SCSI ID */ 353 #define SXP_DEV_CONFIG1 SXP_BLOCK+0x42 /* RW*: Device Config Reg #1 */ 354 #define SXP_DEV_CONFIG2 SXP_BLOCK+0x44 /* RW*: Device Config Reg #2 */ 355 #define SXP_PHASE_POINTER SXP_BLOCK+0x48 /* RW*: SCSI Phase Pointer */ 356 #define SXP_BUF_POINTER SXP_BLOCK+0x4C /* RW*: SCSI Buffer Pointer */ 357 #define SXP_BUF_COUNTER SXP_BLOCK+0x50 /* RW*: SCSI Buffer Counter */ 358 #define SXP_BUFFER SXP_BLOCK+0x52 /* RW*: SCSI Buffer */ 359 #define SXP_BUF_BYTE SXP_BLOCK+0x54 /* RW*: SCSI Buffer Byte */ 360 #define SXP_BUF_WORD SXP_BLOCK+0x56 /* RW*: SCSI Buffer Word */ 361 #define SXP_BUF_WORD_TRAN SXP_BLOCK+0x58 /* RW*: SCSI Buffer Wd xlate */ 362 #define SXP_FIFO SXP_BLOCK+0x5A /* RW*: SCSI FIFO */ 363 #define SXP_FIFO_STATUS SXP_BLOCK+0x5C /* RW*: SCSI FIFO Status */ 364 #define SXP_FIFO_TOP SXP_BLOCK+0x5E /* RW*: SCSI FIFO Top Resid */ 365 #define SXP_FIFO_BOTTOM SXP_BLOCK+0x60 /* RW*: SCSI FIFO Bot Resid */ 366 #define SXP_TRAN_REG SXP_BLOCK+0x64 /* RW*: SCSI Transferr Reg */ 367 #define SXP_TRAN_COUNT_LO SXP_BLOCK+0x68 /* RW*: SCSI Trans Count */ 368 #define SXP_TRAN_COUNT_HI SXP_BLOCK+0x6A /* RW*: SCSI Trans Count */ 369 #define SXP_TRAN_COUNTER_LO SXP_BLOCK+0x6C /* RW*: SCSI Trans Counter */ 370 #define SXP_TRAN_COUNTER_HI SXP_BLOCK+0x6E /* RW*: SCSI Trans Counter */ 371 #define SXP_ARB_DATA SXP_BLOCK+0x70 /* R : SCSI Arb Data */ 372 #define SXP_PINS_CONTROL SXP_BLOCK+0x72 /* RW*: SCSI Control Pins */ 373 #define SXP_PINS_DATA SXP_BLOCK+0x74 /* RW*: SCSI Data Pins */ 374 #define SXP_PINS_DIFF SXP_BLOCK+0x76 /* RW*: SCSI Diff Pins */ 375 376 377 /* SXP CONF1 REGISTER */ 378 #define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 379 #define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 380 #define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 381 #define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 382 #define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 383 384 /* SXP CONF2 REGISTER */ 385 #define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 386 #define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 387 #define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 388 #define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 389 #define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 390 #define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 391 392 /* SXP INTERRUPT REGISTER */ 393 #define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 394 #define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 395 #define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 396 #define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 397 #define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 398 #define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 399 #define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 400 #define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 401 #define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 402 #define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 403 404 405 /* SXP GROSS ERROR REGISTER */ 406 #define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 407 #define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 408 #define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 409 #define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 410 #define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 411 #define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 412 #define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 413 414 /* SXP EXCEPTION REGISTER */ 415 #define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 416 #define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 417 #define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 418 #define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 419 #define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 420 #define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 421 #define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 422 #define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 423 #define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 424 #define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 425 426 /* SXP OVERRIDE REGISTER */ 427 #define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 428 #define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 429 #define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 430 #define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 431 #define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 432 #define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 433 #define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 434 #define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 435 #define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 436 #define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 437 #define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 438 #define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 439 #define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 440 441 /* SXP COMMANDS */ 442 #define SXP_RESET_BUS_CMD 0x300b 443 444 /* SXP SCSI ID REGISTER */ 445 #define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 446 #define SXP_SELECT_ID 0x000F /* Select id */ 447 448 /* SXP DEV CONFIG1 REGISTER */ 449 #define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 450 #define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 451 #define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 452 453 454 /* SXP DEV CONFIG2 REGISTER */ 455 #define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 456 #define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 457 #define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 458 #define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 459 #define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 460 461 462 /* SXP PHASE POINTER REGISTER */ 463 #define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 464 #define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 465 #define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 466 #define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 467 468 469 /* SXP FIFO STATUS REGISTER */ 470 #define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 471 #define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 472 #define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 473 #define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 474 475 476 /* SXP CONTROL PINS REGISTER */ 477 #define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 478 #define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 479 #define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 480 #define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 481 #define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 482 #define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 483 #define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 484 #define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 485 #define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 486 #define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 487 #define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 488 #define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 489 490 /* 491 * Set the hold time for the SCSI Bus Reset to be 250 ms 492 */ 493 #define SXP_SCSI_BUS_RESET_HOLD_TIME 250 494 495 /* SXP DIFF PINS REGISTER */ 496 #define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 497 #define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 498 #define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 499 #define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 500 #define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 501 #define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 502 503 /* 504 * RISC and Host Command and Control Block Register Offsets 505 */ 506 #define RISC_BLOCK 0x0800 507 508 #define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 509 #define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 510 #define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 511 #define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 512 #define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 513 #define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 514 #define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 515 #define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 516 #define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 517 #define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 518 #define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 519 #define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 520 #define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 521 #define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 522 #define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 523 #define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 524 #define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 525 #define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 526 #define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 527 #define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 528 #define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 529 #define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 530 #define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 531 #define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 532 #define RISC_MTR2100 RISC_BLOCK+0x30 533 534 #define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 535 #define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 536 #define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 537 #define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 538 #define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 539 #define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 540 #define TCR RISC_BLOCK+0x46 /* W : Test Control */ 541 #define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 542 543 544 /* PROCESSOR STATUS REGISTER */ 545 #define RISC_PSR_FORCE_TRUE 0x8000 546 #define RISC_PSR_LOOP_COUNT_DONE 0x4000 547 #define RISC_PSR_RISC_INT 0x2000 548 #define RISC_PSR_TIMER_ROLLOVER 0x1000 549 #define RISC_PSR_ALU_OVERFLOW 0x0800 550 #define RISC_PSR_ALU_MSB 0x0400 551 #define RISC_PSR_ALU_CARRY 0x0200 552 #define RISC_PSR_ALU_ZERO 0x0100 553 #define RISC_PSR_DMA_INT 0x0010 554 #define RISC_PSR_SXP_INT 0x0008 555 #define RISC_PSR_HOST_INT 0x0004 556 #define RISC_PSR_INT_PENDING 0x0002 557 #define RISC_PSR_FORCE_FALSE 0x0001 558 559 560 /* Host Command and Control */ 561 #define HCCR_CMD_NOP 0x0000 /* NOP */ 562 #define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 563 #define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 564 #define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 565 #define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 566 #define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 567 #define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 568 #define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 569 #define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 570 #define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 571 #define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 572 #define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 573 #define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 574 575 #define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 576 #define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 577 #define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 578 #define ISP2100_HCCR_PARITY 0x0001 579 580 #define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 581 #define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 582 #define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 583 584 #define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 585 #define HCCR_RESET 0x0040 /* R : reset in progress */ 586 #define HCCR_PAUSE 0x0020 /* R : RISC paused */ 587 588 #define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 589 #endif /* _ISPREG_H */ 590
Indexes created Thu Sep 25 14:09:45 GMT 2025