ispreg.h revision 1.8
1 /* $NetBSD: ispreg.h,v 1.8 1998/09/17 22:52:14 mjacob Exp $ */ 2 /* 3 * Machine Independent (well, as best as possible) register 4 * definitions for Qlogic ISP SCSI adapters. 5 * 6 *--------------------------------------- 7 * Copyright (c) 1997 by Matthew Jacob 8 * NASA/Ames Research Center 9 * All rights reserved. 10 *--------------------------------------- 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice immediately at the beginning of the file, without modification, 16 * this list of conditions, and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 #ifndef _ISPREG_H 36 #define _ISPREG_H 37 38 /* 39 * Hardware definitions for the Qlogic ISP registers. 40 */ 41 42 /* 43 * This defines types of access to various registers. 44 * 45 * R: Read Only 46 * W: Write Only 47 * RW: Read/Write 48 * 49 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 50 * if RISC processor in ISP is paused. 51 */ 52 53 /* 54 * Offsets for various register blocks. 55 * 56 * Sad but true, different architectures have different offsets. 57 */ 58 59 #define BIU_REGS_OFF 0x00 60 61 #define PCI_MBOX_REGS_OFF 0x70 62 #define PCI_MBOX_REGS2100_OFF 0x10 63 #define SBUS_MBOX_REGS_OFF 0x80 64 65 #define PCI_SXP_REGS_OFF 0x80 66 #define SBUS_SXP_REGS_OFF 0x200 67 68 #define PCI_RISC_REGS_OFF 0x80 69 #define SBUS_RISC_REGS_OFF 0x400 70 71 /* 72 * NB: The *_BLOCK definitions have no specific hardware meaning. 73 * They serve simply to note to the MD layer which block of 74 * registers offsets are being accessed. 75 */ 76 77 /* 78 * Bus Interface Block Register Offsets 79 */ 80 #define BIU_BLOCK 0x0100 81 #define BIU_ID_LO BIU_BLOCK+0x0 /* R : Bus ID, Low */ 82 #define BIU2100_FLASH_ADDR BIU_BLOCK+0x0 83 #define BIU_ID_HI BIU_BLOCK+0x2 /* R : Bus ID, High */ 84 #define BIU2100_FLASH_DATA BIU_BLOCK+0x2 85 #define BIU_CONF0 BIU_BLOCK+0x4 /* R : Bus Configuration #0 */ 86 #define BIU_CONF1 BIU_BLOCK+0x6 /* R : Bus Configuration #1 */ 87 #define BIU2100_CSR BIU_BLOCK+0x6 88 #define BIU_ICR BIU_BLOCK+0x8 /* RW : Bus Interface Ctrl */ 89 #define BIU_ISR BIU_BLOCK+0xA /* R : Bus Interface Status */ 90 #define BIU_SEMA BIU_BLOCK+0xC /* RW : Bus Semaphore */ 91 #define BIU_NVRAM BIU_BLOCK+0xE /* RW : Bus NVRAM */ 92 #define CDMA_CONF BIU_BLOCK+0x20 /* RW*: DMA Configuration */ 93 #define CDMA2100_CONTROL CDMA_CONF 94 #define CDMA_CONTROL BIU_BLOCK+0x22 /* RW*: DMA Control */ 95 #define CDMA_STATUS BIU_BLOCK+0x24 /* R : DMA Status */ 96 #define CDMA_FIFO_STS BIU_BLOCK+0x26 /* R : DMA FIFO Status */ 97 #define CDMA_COUNT BIU_BLOCK+0x28 /* RW*: DMA Transfer Count */ 98 #define CDMA_ADDR0 BIU_BLOCK+0x2C /* RW*: DMA Address, Word 0 */ 99 #define CDMA_ADDR1 BIU_BLOCK+0x2E /* RW*: DMA Address, Word 1 */ 100 /* these are for the 1040A cards */ 101 #define CDMA_ADDR2 BIU_BLOCK+0x30 /* RW*: DMA Address, Word 2 */ 102 #define CDMA_ADDR3 BIU_BLOCK+0x32 /* RW*: DMA Address, Word 3 */ 103 104 #define DDMA_CONF BIU_BLOCK+0x40 /* RW*: DMA Configuration */ 105 #define TDMA2100_CONTROL DDMA_CONF 106 #define DDMA_CONTROL BIU_BLOCK+0x42 /* RW*: DMA Control */ 107 #define DDMA_STATUS BIU_BLOCK+0x44 /* R : DMA Status */ 108 #define DDMA_FIFO_STS BIU_BLOCK+0x46 /* R : DMA FIFO Status */ 109 #define DDMA_COUNT_LO BIU_BLOCK+0x48 /* RW*: DMA Xfer Count, Low */ 110 #define DDMA_COUNT_HI BIU_BLOCK+0x4A /* RW*: DMA Xfer Count, High */ 111 #define DDMA_ADDR0 BIU_BLOCK+0x4C /* RW*: DMA Address, Word 0 */ 112 #define DDMA_ADDR1 BIU_BLOCK+0x4E /* RW*: DMA Address, Word 1 */ 113 /* these are for the 1040A cards */ 114 #define DDMA_ADDR2 BIU_BLOCK+0x50 /* RW*: DMA Address, Word 2 */ 115 #define DDMA_ADDR3 BIU_BLOCK+0x52 /* RW*: DMA Address, Word 3 */ 116 117 #define DFIFO_COMMAND BIU_BLOCK+0x60 /* RW : Command FIFO Port */ 118 #define RDMA2100_CONTROL DFIFO_COMMAND 119 #define DFIFO_DATA BIU_BLOCK+0x62 /* RW : Data FIFO Port */ 120 121 /* 122 * Bus Interface Block Register Definitions 123 */ 124 /* BUS CONFIGURATION REGISTER #0 */ 125 #define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 126 /* BUS CONFIGURATION REGISTER #1 */ 127 128 #define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 129 #define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 130 131 #define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 132 #define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 133 #define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 134 #define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 135 #define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 136 #define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 137 #define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 138 #define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 139 #define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 140 #define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 141 #define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 142 143 /* ISP2100 Bus Control/Status Register */ 144 145 #define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 146 #define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 147 #define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 148 #define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 149 #define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 150 #define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ 151 #define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 152 #define BIU2100_SOFT_RESET 0x01 153 /* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 154 155 156 /* BUS CONTROL REGISTER */ 157 #define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 158 #define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 159 #define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 160 #define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 161 #define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 162 #define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 163 164 #define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 165 #define BIU2100_ICR_ENA_FPM_INT 0x0020 166 #define BIU2100_ICR_ENA_FB_INT 0x0010 167 #define BIU2100_ICR_ENA_RISC_INT 0x0008 168 #define BIU2100_ICR_ENA_CDMA_INT 0x0004 169 #define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 170 #define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 171 #define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 172 173 #define ENABLE_INTS(isp) (isp->isp_type & ISP_HA_SCSI)? \ 174 ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ 175 ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) 176 177 #define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) 178 179 /* BUS STATUS REGISTER */ 180 #define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 181 #define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 182 #define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 183 #define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 184 #define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 185 186 #define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 187 #define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 188 #define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 189 #define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 190 #define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 191 #define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 192 #define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 193 194 195 /* BUS SEMAPHORE REGISTER */ 196 #define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 197 #define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 198 199 /* NVRAM SEMAPHORE REGISTER */ 200 #define BIU_NVRAM_CLOCK 0x0001 201 #define BIU_NVRAM_SELECT 0x0002 202 #define BIU_NVRAM_DATAOUT 0x0004 203 #define BIU_NVRAM_DATAIN 0x0008 204 #define ISP_NVRAM_READ 6 205 206 /* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 207 #define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 208 #define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 209 #define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 210 #define DMA_DMA_DIRECTION 0x0001 /* 211 * Set DMA direction: 212 * 0 - DMA FIFO to host 213 * 1 - Host to DMA FIFO 214 */ 215 216 /* COMMAND && DATA DMA CONTROL REGISTER */ 217 #define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 218 #define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 219 * Clear FIFO and DMA Channel, 220 * reset DMA registers 221 */ 222 #define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 223 #define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 224 #define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 225 226 /* 227 * Variants of same for 2100 228 */ 229 #define DMA_CNTRL2100_CLEAR_CHAN 0x0004 230 #define DMA_CNTRL2100_RESET_INT 0x0002 231 232 233 234 /* DMA STATUS REGISTER */ 235 #define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 236 #define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 237 #define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 238 #define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 239 #define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 240 #define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 241 242 #define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 243 #define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 244 #define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 245 #define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 246 #define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 247 #define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 248 #define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 249 #define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 250 #define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 251 #define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 252 #define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 253 254 /* DMA Status Register, pipeline status bits */ 255 #define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 256 #define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 257 #define DMA_SBUS_PIPE_STAGE1 0x0040 /* 258 * Pipeline stage 1 Loaded, 259 * stage 2 empty 260 */ 261 #define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 262 #define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 263 #define DMA_PCI_PIPE_STAGE1 0x0001 /* 264 * Pipeline stage 1 Loaded, 265 * stage 2 empty 266 */ 267 #define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 268 269 /* DMA Status Register, channel status bits */ 270 #define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 271 #define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 272 #define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 273 #define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 274 #define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 275 #define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 276 #define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 277 278 279 /* DMA FIFO STATUS REGISTER */ 280 #define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 281 #define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 282 #define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 283 #define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 284 285 /* 286 * Mailbox Block Register Offsets 287 */ 288 289 #define MBOX_BLOCK 0x0200 290 #define INMAILBOX0 MBOX_BLOCK+0x0 291 #define INMAILBOX1 MBOX_BLOCK+0x2 292 #define INMAILBOX2 MBOX_BLOCK+0x4 293 #define INMAILBOX3 MBOX_BLOCK+0x6 294 #define INMAILBOX4 MBOX_BLOCK+0x8 295 #define INMAILBOX5 MBOX_BLOCK+0xA 296 #define INMAILBOX6 MBOX_BLOCK+0xC 297 #define INMAILBOX7 MBOX_BLOCK+0xE 298 299 #define OUTMAILBOX0 MBOX_BLOCK+0x0 300 #define OUTMAILBOX1 MBOX_BLOCK+0x2 301 #define OUTMAILBOX2 MBOX_BLOCK+0x4 302 #define OUTMAILBOX3 MBOX_BLOCK+0x6 303 #define OUTMAILBOX4 MBOX_BLOCK+0x8 304 #define OUTMAILBOX5 MBOX_BLOCK+0xA 305 #define OUTMAILBOX6 MBOX_BLOCK+0xC 306 #define OUTMAILBOX7 MBOX_BLOCK+0xE 307 308 #define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2)) 309 #define NMBOX(isp) \ 310 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 311 ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 312 313 /* 314 * SXP Block Register Offsets 315 */ 316 #define SXP_BLOCK 0x0400 317 #define SXP_PART_ID SXP_BLOCK+0x0 /* R : Part ID Code */ 318 #define SXP_CONFIG1 SXP_BLOCK+0x2 /* RW*: Configuration Reg #1 */ 319 #define SXP_CONFIG2 SXP_BLOCK+0x4 /* RW*: Configuration Reg #2 */ 320 #define SXP_CONFIG3 SXP_BLOCK+0x6 /* RW*: Configuration Reg #2 */ 321 #define SXP_INSTRUCTION SXP_BLOCK+0xC /* RW*: Instruction Pointer */ 322 #define SXP_RETURN_ADDR SXP_BLOCK+0x10 /* RW*: Return Address */ 323 #define SXP_COMMAND SXP_BLOCK+0x14 /* RW*: Command */ 324 #define SXP_INTERRUPT SXP_BLOCK+0x18 /* R : Interrupt */ 325 #define SXP_SEQUENCE SXP_BLOCK+0x1C /* RW*: Sequence */ 326 #define SXP_GROSS_ERR SXP_BLOCK+0x1E /* R : Gross Error */ 327 #define SXP_EXCEPTION SXP_BLOCK+0x20 /* RW*: Exception Enable */ 328 #define SXP_OVERRIDE SXP_BLOCK+0x24 /* RW*: Override */ 329 #define SXP_LITERAL_BASE SXP_BLOCK+0x28 /* RW*: Literal Base */ 330 #define SXP_USER_FLAGS SXP_BLOCK+0x2C /* RW*: User Flags */ 331 #define SXP_USER_EXCEPT SXP_BLOCK+0x30 /* RW*: User Exception */ 332 #define SXP_BREAKPOINT SXP_BLOCK+0x34 /* RW*: Breakpoint */ 333 #define SXP_SCSI_ID SXP_BLOCK+0x40 /* RW*: SCSI ID */ 334 #define SXP_DEV_CONFIG1 SXP_BLOCK+0x42 /* RW*: Device Config Reg #1 */ 335 #define SXP_DEV_CONFIG2 SXP_BLOCK+0x44 /* RW*: Device Config Reg #2 */ 336 #define SXP_PHASE_POINTER SXP_BLOCK+0x48 /* RW*: SCSI Phase Pointer */ 337 #define SXP_BUF_POINTER SXP_BLOCK+0x4C /* RW*: SCSI Buffer Pointer */ 338 #define SXP_BUF_COUNTER SXP_BLOCK+0x50 /* RW*: SCSI Buffer Counter */ 339 #define SXP_BUFFER SXP_BLOCK+0x52 /* RW*: SCSI Buffer */ 340 #define SXP_BUF_BYTE SXP_BLOCK+0x54 /* RW*: SCSI Buffer Byte */ 341 #define SXP_BUF_WORD SXP_BLOCK+0x56 /* RW*: SCSI Buffer Word */ 342 #define SXP_BUF_WORD_TRAN SXP_BLOCK+0x58 /* RW*: SCSI Buffer Wd xlate */ 343 #define SXP_FIFO SXP_BLOCK+0x5A /* RW*: SCSI FIFO */ 344 #define SXP_FIFO_STATUS SXP_BLOCK+0x5C /* RW*: SCSI FIFO Status */ 345 #define SXP_FIFO_TOP SXP_BLOCK+0x5E /* RW*: SCSI FIFO Top Resid */ 346 #define SXP_FIFO_BOTTOM SXP_BLOCK+0x60 /* RW*: SCSI FIFO Bot Resid */ 347 #define SXP_TRAN_REG SXP_BLOCK+0x64 /* RW*: SCSI Transferr Reg */ 348 #define SXP_TRAN_COUNT_LO SXP_BLOCK+0x68 /* RW*: SCSI Trans Count */ 349 #define SXP_TRAN_COUNT_HI SXP_BLOCK+0x6A /* RW*: SCSI Trans Count */ 350 #define SXP_TRAN_COUNTER_LO SXP_BLOCK+0x6C /* RW*: SCSI Trans Counter */ 351 #define SXP_TRAN_COUNTER_HI SXP_BLOCK+0x6E /* RW*: SCSI Trans Counter */ 352 #define SXP_ARB_DATA SXP_BLOCK+0x70 /* R : SCSI Arb Data */ 353 #define SXP_PINS_CONTROL SXP_BLOCK+0x72 /* RW*: SCSI Control Pins */ 354 #define SXP_PINS_DATA SXP_BLOCK+0x74 /* RW*: SCSI Data Pins */ 355 #define SXP_PINS_DIFF SXP_BLOCK+0x76 /* RW*: SCSI Diff Pins */ 356 357 358 /* SXP CONF1 REGISTER */ 359 #define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 360 #define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 361 #define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 362 #define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 363 #define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 364 365 /* SXP CONF2 REGISTER */ 366 #define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 367 #define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 368 #define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 369 #define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 370 #define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 371 #define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 372 373 /* SXP INTERRUPT REGISTER */ 374 #define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 375 #define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 376 #define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 377 #define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 378 #define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 379 #define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 380 #define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 381 #define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 382 #define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 383 #define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 384 385 386 /* SXP GROSS ERROR REGISTER */ 387 #define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 388 #define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 389 #define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 390 #define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 391 #define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 392 #define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 393 #define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 394 395 /* SXP EXCEPTION REGISTER */ 396 #define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 397 #define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 398 #define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 399 #define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 400 #define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 401 #define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 402 #define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 403 #define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 404 #define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 405 #define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 406 407 /* SXP OVERRIDE REGISTER */ 408 #define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 409 #define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 410 #define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 411 #define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 412 #define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 413 #define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 414 #define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 415 #define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 416 #define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 417 #define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 418 #define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 419 #define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 420 #define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 421 422 /* SXP COMMANDS */ 423 #define SXP_RESET_BUS_CMD 0x300b 424 425 /* SXP SCSI ID REGISTER */ 426 #define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 427 #define SXP_SELECT_ID 0x000F /* Select id */ 428 429 /* SXP DEV CONFIG1 REGISTER */ 430 #define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 431 #define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 432 #define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 433 434 435 /* SXP DEV CONFIG2 REGISTER */ 436 #define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 437 #define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 438 #define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 439 #define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 440 #define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 441 442 443 /* SXP PHASE POINTER REGISTER */ 444 #define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 445 #define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 446 #define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 447 #define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 448 449 450 /* SXP FIFO STATUS REGISTER */ 451 #define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 452 #define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 453 #define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 454 #define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 455 456 457 /* SXP CONTROL PINS REGISTER */ 458 #define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 459 #define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 460 #define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 461 #define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 462 #define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 463 #define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 464 #define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 465 #define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 466 #define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 467 #define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 468 #define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 469 #define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 470 471 /* 472 * Set the hold time for the SCSI Bus Reset to be 250 ms 473 */ 474 #define SXP_SCSI_BUS_RESET_HOLD_TIME 250 475 476 /* SXP DIFF PINS REGISTER */ 477 #define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 478 #define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 479 #define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 480 #define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 481 #define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 482 #define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 483 484 /* 485 * RISC and Host Command and Control Block Register Offsets 486 */ 487 #define RISC_BLOCK 0x0800 488 489 #define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 490 #define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 491 #define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 492 #define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 493 #define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 494 #define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 495 #define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 496 #define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 497 #define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 498 #define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 499 #define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 500 #define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 501 #define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 502 #define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 503 #define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 504 #define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 505 #define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 506 #define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 507 #define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 508 #define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 509 #define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 510 #define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 511 #define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 512 #define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 513 #define RISC_MTR2100 RISC_BLOCK+0x30 514 515 #define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 516 #define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 517 #define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 518 #define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 519 #define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 520 #define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 521 #define TCR RISC_BLOCK+0x46 /* W : Test Control */ 522 #define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 523 524 525 /* PROCESSOR STATUS REGISTER */ 526 #define RISC_PSR_FORCE_TRUE 0x8000 527 #define RISC_PSR_LOOP_COUNT_DONE 0x4000 528 #define RISC_PSR_RISC_INT 0x2000 529 #define RISC_PSR_TIMER_ROLLOVER 0x1000 530 #define RISC_PSR_ALU_OVERFLOW 0x0800 531 #define RISC_PSR_ALU_MSB 0x0400 532 #define RISC_PSR_ALU_CARRY 0x0200 533 #define RISC_PSR_ALU_ZERO 0x0100 534 535 #define RISC_PSR_PCI_ULTRA 0x0080 536 #define RISC_PSR_SBUS_ULTRA 0x0020 537 538 #define RISC_PSR_DMA_INT 0x0010 539 #define RISC_PSR_SXP_INT 0x0008 540 #define RISC_PSR_HOST_INT 0x0004 541 #define RISC_PSR_INT_PENDING 0x0002 542 #define RISC_PSR_FORCE_FALSE 0x0001 543 544 545 /* Host Command and Control */ 546 #define HCCR_CMD_NOP 0x0000 /* NOP */ 547 #define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 548 #define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 549 #define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 550 #define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 551 #define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 552 #define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 553 #define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 554 #define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 555 #define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 556 #define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 557 #define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 558 #define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 559 560 #define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 561 #define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 562 #define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 563 #define ISP2100_HCCR_PARITY 0x0001 564 565 #define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 566 #define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 567 #define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 568 569 #define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 570 #define HCCR_RESET 0x0040 /* R : reset in progress */ 571 #define HCCR_PAUSE 0x0020 /* R : RISC paused */ 572 573 #define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 574 575 /* 576 * Qlogic 1XXX NVRAM is an array of 128 bytes. 577 * 578 * Some portion of the front of this is for general host adapter properties 579 * This is followed by an array of per-target parameters, and is tailed off 580 * with a checksum xor byte at offset 127. For non-byte entities data is 581 * stored in Little Endian order. 582 */ 583 584 #define ISP_NVRAM_SIZE 128 585 586 #define ISPBSMX(c, byte, shift, mask) \ 587 (((c)[(byte)] >> (shift)) & (mask)) 588 589 #define ISP_NVRAM_VERSION(c) (c)[4] 590 #define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 591 #define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 592 #define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 593 #define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 594 #define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 595 #define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 596 #define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 597 #define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 598 #define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 599 #define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 600 #define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 601 #define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 602 #define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 603 #define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 604 #define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 605 #define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 606 #define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 607 #define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 608 #define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 609 #define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 610 #define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 611 #define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 612 #define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 613 #define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 614 #define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 615 #define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 616 #define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 617 #define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 618 #define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 619 620 #define ISP_NVRAM_TARGOFF 28 621 #define ISP_NVARM_TARGSIZE 6 622 #define _IxT(tgt, tidx) \ 623 (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) 624 #define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 625 #define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 626 #define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 627 #define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 628 #define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 629 #define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 630 #define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 631 #define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 632 #define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 633 #define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 634 #define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 635 #define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 636 #define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 637 638 /* 639 * Qlogic 2XXX NVRAM is an array of 256 bytes. 640 * 641 * Some portion of the front of this is for general RISC engine parameters, 642 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 643 * 644 * This is followed by some general host adapter parameters, and ends with 645 * a checksum xor byte at offset 255. For non-byte entities data is stored 646 * in Little Endian order. 647 */ 648 #define ISP2100_NVRAM_SIZE 256 649 /* ISP_NVRAM_VERSION is in same overall place */ 650 #define ISP2100_NVRAM_RISCVER(c) (c)[6] 651 #define ISP2100_NVRAM_ENABLE_HARDLOOPID(c) ISPBSMX(c, 8, 0, 0x01) 652 #define ISP2100_NVRAM_ENABLE_FAIRNESS(c) ISPBSMX(c, 8, 1, 0x01) 653 #define ISP2100_NVRAM_ENABLE_FULLDUPLEX(c) ISPBSMX(c, 8, 2, 0x01) 654 #define ISP2100_NVRAM_ENABLE_FAST_POSTING(c) ISPBSMX(c, 8, 3, 0x01) 655 #define ISP2100_NVRAM_ENABLE_TARGET_MODE(c) ISPBSMX(c, 8, 4, 0x01) 656 #define ISP2100_NVRAM_ENABLE_INITIATOR_MODE(c) ISPBSMX(c, 8, 5, 0x01) 657 #define ISP2100_NVRAM_QFRZ(c) ISPBSMX(c, 8, 6, 0x01) 658 #define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 659 #define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 660 #define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 661 #define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 662 #define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 663 664 #define ISP2100_NVRAM_NODE_NAME(c) ( \ 665 (((u_int64_t)(c)[18]) << 56) | \ 666 (((u_int64_t)(c)[19]) << 48) | \ 667 (((u_int64_t)(c)[20]) << 40) | \ 668 (((u_int64_t)(c)[21]) << 32) | \ 669 (((u_int64_t)(c)[22]) << 24) | \ 670 (((u_int64_t)(c)[23]) << 16) | \ 671 (((u_int64_t)(c)[24]) << 8) | \ 672 (((u_int64_t)(c)[25]) << 0)) 673 #define ISP2100_NVRAM_HARDLOOPID(c) (c)[24] 674 675 #define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 676 #define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 677 #define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 678 #define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 679 #define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 680 #define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 681 682 #define ISP2100_NVRAM_BOOT_NODE_NAME(c) ( \ 683 (((u_int64_t)(c)[72]) << 56) | \ 684 (((u_int64_t)(c)[73]) << 48) | \ 685 (((u_int64_t)(c)[74]) << 40) | \ 686 (((u_int64_t)(c)[75]) << 32) | \ 687 (((u_int64_t)(c)[76]) << 24) | \ 688 (((u_int64_t)(c)[77]) << 16) | \ 689 (((u_int64_t)(c)[78]) << 8) | \ 690 (((u_int64_t)(c)[79]) << 0)) 691 #define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 692 693 #endif /* _ISPREG_H */ 694
Indexes created Fri Sep 26 08:10:20 GMT 2025