lancereg.h revision 1.4
1 /* $NetBSD: lancereg.h,v 1.4 2001/08/18 21:16:34 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This code is derived from software contributed to Berkeley by 44 * Ralph Campbell and Rick Macklem. 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that the following conditions 48 * are met: 49 * 1. Redistributions of source code must retain the above copyright 50 * notice, this list of conditions and the following disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 3. All advertising materials mentioning features or use of this software 55 * must display the following acknowledgement: 56 * This product includes software developed by the University of 57 * California, Berkeley and its contributors. 58 * 4. Neither the name of the University nor the names of its contributors 59 * may be used to endorse or promote products derived from this software 60 * without specific prior written permission. 61 * 62 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 63 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 65 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 68 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 69 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 70 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 71 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 72 * SUCH DAMAGE. 73 * 74 * @(#)if_lereg.h 8.1 (Berkeley) 6/10/93 75 */ 76 77 /* 78 * Register description for the following Advanced Micro Devices 79 * Ethernet chips: 80 * 81 * - Am7990 Local Area Network Controller for Ethernet (LANCE) 82 * (and its descendent Am79c90 C-LANCE). 83 * 84 * - Am79c900 Integrated Local Area Communications Controller (ILACC) 85 * 86 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA 87 * 88 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller 89 * for ISA 90 * 91 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip 92 * Ethernet Controller for ISA 93 * 94 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller 95 * (for VESA and 486 local busses) 96 * 97 * - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 98 * Local Bus 99 * 100 * - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 101 * for PCI Local Bus 102 * 103 * - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 104 * Ethernet Controller for PCI Local Bus 105 * 106 * - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 107 * with OnNow Support 108 * 109 * - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 110 * Ethernet Controller with Integrated PHY 111 * 112 * - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home 113 * Networking Controller. 114 * 115 * Initialization block, transmit descriptor, and receive descriptor 116 * formats are described in two separate files: 117 * 118 * 16-bit software model (LANCE) am7990reg.h 119 * 120 * 32-bit software model (ILACC) am79900reg.h 121 * 122 * Note that the vast majority of the registers described in this file 123 * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are 124 * valid on the LANCE. 125 */ 126 127 #define LEBLEN 1536 /* ETHERMTU + header + CRC */ 128 #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */ 129 130 #define LE_INITADDR(sc) (sc->sc_initaddr) 131 #define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix)) 132 #define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix)) 133 #define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr[bix]) 134 #define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr[bix]) 135 136 /* 137 * Control and Status Register addresses 138 */ 139 #define LE_CSR0 0x0000 /* Control and status register */ 140 #define LE_CSR1 0x0001 /* low address of init block */ 141 #define LE_CSR2 0x0002 /* high address of init block */ 142 #define LE_CSR3 0x0003 /* Bus master and control */ 143 #define LE_CSR4 0x0004 /* Test and features control */ 144 #define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */ 145 #define LE_CSR6 0x0006 /* Rx/Tx Descriptor table length */ 146 #define LE_CSR7 0x0007 /* Extended control and interrupt 2 */ 147 #define LE_CSR8 0x0008 /* Logical Address Filter 0 */ 148 #define LE_CSR9 0x0009 /* Logical Address Filter 1 */ 149 #define LE_CSR10 0x000a /* Logical Address Filter 2 */ 150 #define LE_CSR11 0x000b /* Logical Address Filter 3 */ 151 #define LE_CSR12 0x000c /* Physical Address 0 */ 152 #define LE_CSR13 0x000d /* Physical Address 1 */ 153 #define LE_CSR14 0x000e /* Physical Address 2 */ 154 #define LE_CSR15 0x000f /* Mode */ 155 #define LE_CSR16 0x0010 /* Initialization Block addr lower */ 156 #define LE_CSR17 0x0011 /* Initialization Block addr upper */ 157 #define LE_CSR18 0x0012 /* Current Rx Buffer addr lower */ 158 #define LE_CSR19 0x0013 /* Current Rx Buffer addr upper */ 159 #define LE_CSR20 0x0014 /* Current Tx Buffer addr lower */ 160 #define LE_CSR21 0x0015 /* Current Tx Buffer addr upper */ 161 #define LE_CSR22 0x0016 /* Next Rx Buffer addr lower */ 162 #define LE_CSR23 0x0017 /* Next Rx Buffer addr upper */ 163 #define LE_CSR24 0x0018 /* Base addr of Rx ring lower */ 164 #define LE_CSR25 0x0019 /* Base addr of Rx ring upper */ 165 #define LE_CSR26 0x001a /* Next Rx Desc addr lower */ 166 #define LE_CSR27 0x001b /* Next Rx Desc addr upper */ 167 #define LE_CSR28 0x001c /* Current Rx Desc addr lower */ 168 #define LE_CSR29 0x001d /* Current Rx Desc addr upper */ 169 #define LE_CSR30 0x001e /* Base addr of Tx ring lower */ 170 #define LE_CSR31 0x001f /* Base addr of Tx ring upper */ 171 #define LE_CSR32 0x0020 /* Next Tx Desc addr lower */ 172 #define LE_CSR33 0x0021 /* Next Tx Desc addr upper */ 173 #define LE_CSR34 0x0022 /* Current Tx Desc addr lower */ 174 #define LE_CSR35 0x0023 /* Current Tx Desc addr upper */ 175 #define LE_CSR36 0x0024 /* Next Next Rx Desc addr lower */ 176 #define LE_CSR37 0x0025 /* Next Next Rx Desc addr upper */ 177 #define LE_CSR38 0x0026 /* Next Next Tx Desc addr lower */ 178 #define LE_CSR39 0x0027 /* Next Next Tx Desc adddr upper */ 179 #define LE_CSR40 0x0028 /* Current Rx Byte Count */ 180 #define LE_CSR41 0x0029 /* Current Rx Status */ 181 #define LE_CSR42 0x002a /* Current Tx Byte Count */ 182 #define LE_CSR43 0x002b /* Current Tx Status */ 183 #define LE_CSR44 0x002c /* Next Rx Byte Count */ 184 #define LE_CSR45 0x002d /* Next Rx Status */ 185 #define LE_CSR46 0x002e /* Tx Poll Time Counter */ 186 #define LE_CSR47 0x002f /* Tx Polling Interval */ 187 #define LE_CSR48 0x0030 /* Rx Poll Time Counter */ 188 #define LE_CSR49 0x0031 /* Rx Polling Interval */ 189 #define LE_CSR58 0x003a /* Software Style */ 190 #define LE_CSR60 0x003c /* Previous Tx Desc addr lower */ 191 #define LE_CSR61 0x003d /* Previous Tx Desc addr upper */ 192 #define LE_CSR62 0x003e /* Previous Tx Byte Count */ 193 #define LE_CSR63 0x003f /* Previous Tx Status */ 194 #define LE_CSR64 0x0040 /* Next Tx Buffer addr lower */ 195 #define LE_CSR65 0x0041 /* Next Tx Buffer addr upper */ 196 #define LE_CSR66 0x0042 /* Next Tx Byte Count */ 197 #define LE_CSR67 0x0043 /* Next Tx Status */ 198 #define LE_CSR72 0x0048 /* Receive Ring Counter */ 199 #define LE_CSR74 0x004a /* Transmit Ring Counter */ 200 #define LE_CSR76 0x004c /* Receive Ring Length */ 201 #define LE_CSR78 0x004e /* Transmit Ring Length */ 202 #define LE_CSR80 0x0050 /* DMA Transfer Counter and FIFO 203 Threshold Control */ 204 #define LE_CSR82 0x0052 /* Tx Desc addr Pointer lower */ 205 #define LE_CSR84 0x0054 /* DMA addr register lower */ 206 #define LE_CSR85 0x0055 /* DMA addr register upper */ 207 #define LE_CSR86 0x0056 /* Buffer Byte Counter */ 208 #define LE_CSR88 0x0058 /* Chip ID Register lower */ 209 #define LE_CSR89 0x0059 /* Chip ID Register upper */ 210 #define LE_CSR92 0x005c /* Ring Length Conversion */ 211 #define LE_CSR100 0x0064 /* Bus Timeout */ 212 #define LE_CSR112 0x0070 /* Missed Frame Count */ 213 #define LE_CSR114 0x0072 /* Receive Collision Count */ 214 #define LE_CSR116 0x0074 /* OnNow Power Mode Register */ 215 #define LE_CSR122 0x007a /* Advanced Feature Control */ 216 #define LE_CSR124 0x007c /* Test Register 1 */ 217 #define LE_CSR125 0x007d /* MAC Enhanced Configuration Control */ 218 219 /* 220 * Bus Configuration Register addresses 221 */ 222 #define LE_BCR0 0x0000 /* Master Mode Read Active */ 223 #define LE_BCR1 0x0001 /* Master Mode Write Active */ 224 #define LE_BCR2 0x0002 /* Misc. Configuration */ 225 #define LE_BCR4 0x0004 /* LED0 Status */ 226 #define LE_BCR5 0x0005 /* LED1 Status */ 227 #define LE_BCR6 0x0006 /* LED2 Status */ 228 #define LE_BCR7 0x0007 /* LED3 Status */ 229 #define LE_BCR9 0x0009 /* Full-duplex Control */ 230 #define LE_BCR16 0x0010 /* I/O Base Address lower */ 231 #define LE_BCR17 0x0011 /* I/O Base Address upper */ 232 #define LE_BCR18 0x0012 /* Burst and Bus Control Register */ 233 #define LE_BCR19 0x0013 /* EEPROM Control and Status */ 234 #define LE_BCR20 0x0014 /* Software Style */ 235 #define LE_BCR22 0x0016 /* PCI Latency Register */ 236 #define LE_BCR23 0x0017 /* PCI Subsystem Vendor ID */ 237 #define LE_BCR24 0x0018 /* PCI Subsystem ID */ 238 #define LE_BCR25 0x0019 /* SRAM Size Register */ 239 #define LE_BCR26 0x001a /* SRAM Boundary Register */ 240 #define LE_BCR27 0x001b /* SRAM Interface Control Register */ 241 #define LE_BCR28 0x001c /* Exp. Bus Port Addr lower */ 242 #define LE_BCR29 0x001d /* Exp. Bus Port Addr upper */ 243 #define LE_BCR30 0x001e /* Exp. Bus Data Port */ 244 #define LE_BCR31 0x001f /* Software Timer Register */ 245 #define LE_BCR32 0x0020 /* PHY Control and Status Register */ 246 #define LE_BCR33 0x0021 /* PHY Address Register */ 247 #define LE_BCR34 0x0022 /* PHY Management Data Register */ 248 #define LE_BCR35 0x0023 /* PCI Vendor ID Register */ 249 #define LE_BCR36 0x0024 /* PCI Power Management Cap. Alias */ 250 #define LE_BCR37 0x0025 /* PCI DATA0 Alias */ 251 #define LE_BCR38 0x0026 /* PCI DATA1 Alias */ 252 #define LE_BCR39 0x0027 /* PCI DATA2 Alias */ 253 #define LE_BCR40 0x0028 /* PCI DATA3 Alias */ 254 #define LE_BCR41 0x0029 /* PCI DATA4 Alias */ 255 #define LE_BCR42 0x002a /* PCI DATA5 Alias */ 256 #define LE_BCR43 0x002b /* PCI DATA6 Alias */ 257 #define LE_BCR44 0x002c /* PCI DATA7 Alias */ 258 #define LE_BCR45 0x002d /* OnNow Pattern Matching 1 */ 259 #define LE_BCR46 0x002e /* OnNow Pattern Matching 2 */ 260 #define LE_BCR47 0x002f /* OnNow Pattern Matching 3 */ 261 #define LE_BCR48 0x0030 /* LED4 Status */ 262 #define LE_BCR49 0x0031 /* PHY Select */ 263 264 /* Control and status register 0 (csr0) */ 265 #define LE_C0_ERR 0x8000 /* error summary */ 266 #define LE_C0_BABL 0x4000 /* transmitter timeout error */ 267 #define LE_C0_CERR 0x2000 /* collision */ 268 #define LE_C0_MISS 0x1000 /* missed a packet */ 269 #define LE_C0_MERR 0x0800 /* memory error */ 270 #define LE_C0_RINT 0x0400 /* receiver interrupt */ 271 #define LE_C0_TINT 0x0200 /* transmitter interrupt */ 272 #define LE_C0_IDON 0x0100 /* initalization done */ 273 #define LE_C0_INTR 0x0080 /* interrupt condition */ 274 #define LE_C0_INEA 0x0040 /* interrupt enable */ 275 #define LE_C0_RXON 0x0020 /* receiver on */ 276 #define LE_C0_TXON 0x0010 /* transmitter on */ 277 #define LE_C0_TDMD 0x0008 /* transmit demand */ 278 #define LE_C0_STOP 0x0004 /* disable all external activity */ 279 #define LE_C0_STRT 0x0002 /* enable external activity */ 280 #define LE_C0_INIT 0x0001 /* begin initalization */ 281 282 #define LE_C0_BITS \ 283 "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\ 284 \12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT" 285 286 /* Control and status register 3 (csr3) */ 287 #define LE_C3_MISSM 0x1000 /* missed frame mask */ 288 #define LE_C3_MERRM 0x0800 /* memory error mask */ 289 #define LE_C3_RINTM 0x0400 /* receive interrupt mask */ 290 #define LE_C3_TINTM 0x0200 /* transmit interrupt mask */ 291 #define LE_C3_IDONM 0x0100 /* initialization done mask */ 292 #define LE_C3_DXSUFLO 0x0040 /* disable tx stop on underflow */ 293 #define LE_C3_LAPPEN 0x0020 /* look ahead packet processing enbl */ 294 #define LE_C3_DXMT2PD 0x0010 /* disable tx two part deferral */ 295 #define LE_C3_EMBA 0x0008 /* enable modified backoff algorithm */ 296 #define LE_C3_BSWP 0x0004 /* byte swap */ 297 #define LE_C3_ACON 0x0002 /* ALE control, eh? */ 298 #define LE_C3_BCON 0x0001 /* byte control */ 299 300 /* Control and status register 4 (csr4) */ 301 #define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */ 302 #define LE_C4_TXDPOLL 0x1000 /* disable transmit polling */ 303 #define LE_C4_APAD_XMT 0x0800 /* auto pad transmit */ 304 #define LE_C4_ASTRP_RCV 0x0400 /* auto strip receive */ 305 #define LE_C4_MFCO 0x0200 /* missed frame counter overflow */ 306 #define LE_C4_MFCOM 0x0100 /* missed frame coutner overflow mask */ 307 #define LE_C4_UINTCMD 0x0080 /* user interrupt command */ 308 #define LE_C4_UINT 0x0040 /* user interrupt */ 309 #define LE_C4_RCVCCO 0x0020 /* receive collision counter overflow */ 310 #define LE_C4_RCVCCOM 0x0010 /* receive collision counter overflow 311 mask */ 312 #define LE_C4_TXSTRT 0x0008 /* transmit start status */ 313 #define LE_C4_TXSTRTM 0x0004 /* transmit start mask */ 314 315 /* Control and status register 5 (csr5) */ 316 #define LE_C5_TOKINTD 0x8000 /* transmit ok interrupt disable */ 317 #define LE_C5_LTINTEN 0x4000 /* last transmit interrupt enable */ 318 #define LE_C5_SINT 0x0800 /* system interrupt */ 319 #define LE_C5_SINTE 0x0400 /* system interrupt enable */ 320 #define LE_C5_EXDINT 0x0080 /* excessive deferral interrupt */ 321 #define LE_C5_EXDINTE 0x0040 /* excessive deferral interrupt enbl */ 322 #define LE_C5_MPPLBA 0x0020 /* magic packet physical logical 323 broadcast accept */ 324 #define LE_C5_MPINT 0x0010 /* magic packet interrupt */ 325 #define LE_C5_MPINTE 0x0008 /* magic packet interrupt enable */ 326 #define LE_C5_MPEN 0x0004 /* magic packet enable */ 327 #define LE_C5_MPMODE 0x0002 /* magic packet mode */ 328 #define LE_C5_SPND 0x0001 /* suspend */ 329 330 /* Control and status register 6 (csr6) */ 331 #define LE_C6_TLEN 0xf000 /* TLEN from init block */ 332 #define LE_C6_RLEN 0x0f00 /* RLEN from init block */ 333 334 /* Control and status register 7 (csr7) */ 335 #define LE_C7_FASTSPNDE 0x8000 /* fast suspend enable */ 336 #define LE_C7_RDMD 0x2000 /* receive demand */ 337 #define LE_C7_RDXPOLL 0x1000 /* receive disable polling */ 338 #define LE_C7_STINT 0x0800 /* software timer interrupt */ 339 #define LE_C7_STINTE 0x0400 /* software timer interrupt enable */ 340 #define LE_C7_MREINT 0x0200 /* PHY management read error intr */ 341 #define LE_C7_MREINTE 0x0100 /* PHY management read error intr 342 enable */ 343 #define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */ 344 #define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr 345 enable */ 346 #define LE_C7_MCCINT 0x0020 /* PHY management command complete 347 interrupt */ 348 #define LE_C7_MCCINTE 0x0010 /* PHY management command complete 349 interrupt enable */ 350 #define LE_C7_MCCIINT 0x0008 /* PHY management command complete 351 internal interrupt */ 352 #define LE_C7_MCCIINTE 0x0004 /* PHY management command complete 353 internal interrupt enable */ 354 #define LE_C7_MIIPDTINT 0x0002 /* PHY management detect transition 355 interrupt */ 356 #define LE_C7_MIIPDTINTE 0x0001 /* PHY management detect transition 357 interrupt enable */ 358 359 /* control and status register 80 (csr80) */ 360 #define LE_C80_RCVFW1 0x2000 /* Receive FIFO Watermark 1 */ 361 #define LE_C80_RCVFW0 0x1000 /* Receive FIFO Watermark 0 */ 362 /* 00 16 bytes */ 363 /* 01 64 bytes */ 364 /* 10 112 bytes */ 365 /* 11 reserved */ 366 #define LE_C80_XMTSP1 0x0800 /* Transmit Start Point 1 */ 367 #define LE_C80_XMTSP0 0x0400 /* Transmit Start Point 0 */ 368 /* 00 0 20 bytes */ 369 /* 01 0 64 bytes */ 370 /* 10 0 128 bytes */ 371 /* 11 0 220 max */ 372 /* 00 >0 36 bytes */ 373 /* 01 >0 64 bytes */ 374 /* 10 >0 128 bytes */ 375 /* 11 >0 store-and-fwd */ 376 #define LE_C80_XMTFW1 0x0200 /* Transmit FIFO Watermark 1 */ 377 #define LE_C80_XMTFW0 0x0100 /* Transmit FIFO Watermark 0 */ 378 /* 00 16 bytes */ 379 /* 01 64 bytes */ 380 /* 10 108 bytes */ 381 /* 11 reserved */ 382 #define LE_C80_DMATC 0x00ff /* DMA transfer counter */ 383 384 /* control and status register 116 (csr116) */ 385 #define LE_C116_PME_EN_OVR 0x0400 /* PME_EN overwrite */ 386 #define LE_C116_LCDET 0x0200 /* link change detected */ 387 #define LE_C116_LCMODE 0x0100 /* link change wakeup mode */ 388 #define LE_C116_PMAT 0x0080 /* pattern matched */ 389 #define LE_C116_EMPPLBA 0x0040 /* magic packet physical logical 390 broadcast accept */ 391 #define LE_C116_MPMAT 0x0020 /* magic packet match */ 392 #define LE_C116_MPPEN 0x0010 /* magic packet pin enable */ 393 #define LE_C116_RST_POL 0x0001 /* PHY_RST pin polarity */ 394 395 /* control and status register 122 (csr122) */ 396 #define LE_C122_RCVALGN 0x0001 /* receive packet align */ 397 398 /* control and status register 124 (csr124) */ 399 #define LE_C124_RPA 0x0008 /* runt packet accept */ 400 401 /* control and status register 125 (csr125) */ 402 #define LE_C125_IPG 0xff00 /* inter-packet gap */ 403 #define LE_C125_IFS1 0x00ff /* inter-frame spacing part 1 */ 404 405 /* bus configuration register 0 (bcr0) */ 406 #define LE_B0_MSRDA 0xffff /* reserved locations */ 407 408 /* bus configuration register 1 (bcr1) */ 409 #define LE_B1_MSWRA 0xffff /* reserved locations */ 410 411 /* bus configuration register 2 (bcr2) */ 412 #define LE_B2_PHYSSELEN 0x2000 /* enable writes to BCR18[4:3] */ 413 #define LE_B2_LEDPE 0x1000 /* LED program enable */ 414 #define LE_B2_APROMWE 0x0100 /* Address PROM Write Enable */ 415 #define LE_B2_INTLEVEL 0x0080 /* 1 == edge triggered */ 416 417 /* bus configuration register 4 (bcr4) */ 418 /* bus configuration register 5 (bcr5) */ 419 /* bus configuration register 6 (bcr6) */ 420 /* bus configuration register 7 (bcr7) */ 421 /* bus configuration register 48 (bcr48) */ 422 #define LE_B4_LEDOUT 0x8000 /* LED output active */ 423 #define LE_B4_LEDPOL 0x4000 /* LED polarity */ 424 #define LE_B4_LEDDIS 0x2000 /* LED disable */ 425 #define LE_B4_100E 0x1000 /* 100Mb/s enable */ 426 #define LE_B4_MPSE 0x0200 /* magic packet status enable */ 427 #define LE_B4_FDLSE 0x0100 /* full-duplex link status enable */ 428 #define LE_B4_PSE 0x0080 /* pulse stretcher enable */ 429 #define LE_B4_LNKSE 0x0040 /* link status enable */ 430 #define LE_B4_RCVME 0x0020 /* receive match status enable */ 431 #define LE_B4_XMTE 0x0010 /* transmit status enable */ 432 #define LE_B4_POWER 0x0008 /* power enable */ 433 #define LE_B4_RCVE 0x0004 /* receive status enable */ 434 #define LE_B4_SPEED 0x0002 /* high speed enable */ 435 #define LE_B4_COLE 0x0001 /* collision status enable */ 436 437 /* bus configuration register 9 (bcr9) */ 438 #define LE_B9_FDRPAD 0x0004 /* full-duplex runt packet accept 439 disable */ 440 #define LE_B9_FDEN 0x0001 /* full-duplex enable */ 441 442 /* bus configuration register 18 (bcr18) */ 443 #define LE_B18_ROMTMG 0xf000 /* expansion rom timing */ 444 #define LE_B18_NOUFLO 0x0800 /* no underflow on transmit */ 445 #define LE_B18_MEMCMD 0x0200 /* memory read multiple enable */ 446 #define LE_B18_EXTREQ 0x0100 /* extended request */ 447 #define LE_B18_DWIO 0x0080 /* double-word I/O */ 448 #define LE_B18_BREADE 0x0040 /* burst read enable */ 449 #define LE_B18_BWRITE 0x0020 /* burst write enable */ 450 #define LE_B18_PHYSEL1 0x0010 /* PHYSEL 1 */ 451 #define LE_B18_PHYSEL0 0x0008 /* PHYSEL 0 */ 452 /* 00 ex ROM/Flash */ 453 /* 01 EADI/MII snoop */ 454 /* 10 reserved */ 455 /* 11 reserved */ 456 #define LE_B18_LINBC 0x0007 /* reserved locations */ 457 458 /* bus configuration register 19 (bcr19) */ 459 #define LE_B19_PVALID 0x8000 /* EEPROM status valid */ 460 #define LE_B19_PREAD 0x4000 /* EEPROM read command */ 461 #define LE_B19_EEDET 0x2000 /* EEPROM detect */ 462 #define LE_B19_EEN 0x0010 /* EEPROM port enable */ 463 #define LE_B19_ECS 0x0004 /* EEPROM chip select */ 464 #define LE_B19_ESK 0x0002 /* EEPROM serial clock */ 465 #define LE_B19_EDI 0x0001 /* EEPROM data in */ 466 #define LE_B19_EDO 0x0001 /* EEPROM data out */ 467 468 /* bus configuration register 20 (bcr20) */ 469 #define LE_B20_APERREN 0x0400 /* Advanced parity error handling */ 470 #define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */ 471 #define LE_B20_SSTYLE 0x0007 /* Software Style */ 472 #define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */ 473 #define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */ 474 #define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI (32-bit) */ 475 476 /* bus configuration register 25 (bcr25) */ 477 #define LE_B25_SRAM_SIZE 0x00ff /* SRAM size */ 478 479 /* bus configuration register 26 (bcr26) */ 480 #define LE_B26_SRAM_BND 0x00ff /* SRAM boundary */ 481 482 /* bus configuration register 27 (bcr27) */ 483 #define LE_B27_PTRTST 0x8000 /* reserved for manuf. tests */ 484 #define LE_B27_LOLATRX 0x4000 /* low latency receive */ 485 #define LE_B27_EBCS 0x0038 /* expansion bus clock source */ 486 /* 000 CLK pin */ 487 /* 001 time base clock */ 488 /* 010 EBCLK pin */ 489 /* 011 reserved */ 490 /* 1xx reserved */ 491 #define LE_B27_CLK_FAC 0x0007 /* clock factor */ 492 /* 000 1 */ 493 /* 001 1/2 */ 494 /* 010 reserved */ 495 /* 011 1/4 */ 496 /* 1xx reserved */ 497 498 /* bus configuration register 28 (bcr28) */ 499 #define LE_B28_EADDRL 0xffff /* expansion port address lower */ 500 501 /* bus configuration register 29 (bcr29) */ 502 #define LE_B29_FLASH 0x8000 /* flash access */ 503 #define LE_B29_LAAINC 0x4000 /* lower address auto increment */ 504 #define LE_B29_EPADDRU 0x0007 /* expansion port address upper */ 505 506 /* bus configuration register 30 (bcr30) */ 507 #define LE_B30_EBDATA 0xffff /* expansion bus data port */ 508 509 /* bus configuration register 31 (bcr31) */ 510 #define LE_B31_STVAL 0xffff /* software timer value */ 511 512 /* bus configuration register 32 (bcr32) */ 513 #define LE_B32_ANTST 0x8000 /* reserved for manuf. tests */ 514 #define LE_B32_MIIPD 0x4000 /* MII PHY Detect (manuf. tests) */ 515 #define LE_B32_FMDC 0x3000 /* fast management data clock */ 516 #define LE_B32_APEP 0x0800 /* auto-poll PHY */ 517 #define LE_B32_APDW 0x0700 /* auto-poll dwell time */ 518 #define LE_B32_DANAS 0x0080 /* disable autonegotiation */ 519 #define LE_B32_XPHYRST 0x0040 /* PHY reset */ 520 #define LE_B32_XPHYANE 0x0020 /* PHY autonegotiation enable */ 521 #define LE_B32_XPHYFD 0x0010 /* PHY full-duplex */ 522 #define LE_B32_XPHYSP 0x0008 /* PHY speed */ 523 #define LE_B32_MIIILP 0x0002 /* MII internal loopback */ 524 525 /* bus configuration register 33 (bcr33) */ 526 #define LE_B33_SHADOW 0x8000 /* shadow enable */ 527 #define LE_B33_MII_SEL 0x4000 /* MII selected */ 528 #define LE_B33_ACOMP 0x2000 /* internal PHY autonegotiation comp */ 529 #define LE_B33_LINK 0x1000 /* link status */ 530 #define LE_B33_FDX 0x0800 /* full-duplex */ 531 #define LE_B33_SPEED 0x0400 /* 1 == high speed */ 532 #define LE_B33_PHYAD 0x03e0 /* PHY address */ 533 #define PHYAD_SHIFT 5 534 #define LE_B33_REGAD 0x001f /* register address */ 535 536 /* bus configuration register 34 (bcr34) */ 537 #define LE_B34_MIIMD 0xffff /* MII data */ 538 539 /* bus configuration register 49 (bcr49) */ 540 #define LE_B49_PCNET 0x8000 /* PCnet mode - Must Be One */ 541 #define LE_B49_PHYSEL_D 0x0300 /* PHY_SEL_Default */ 542 #define LE_B49_PHYSEL_L 0x0010 /* PHY_SEL_Lock */ 543 #define LE_B49_PHYSEL 0x0003 /* PHYSEL */ 544 /* 00 10baseT PHY */ 545 /* 01 HomePNA PYY */ 546 /* 10 external PHY */ 547 /* 11 reserved */ 548 549 /* Initialzation block (mode) */ 550 #define LE_MODE_PROM 0x8000 /* promiscuous mode */ 551 /* 0x7f80 reserved, must be zero */ 552 /* 0x4000 - 0x0080 are not available on LANCE 7990 */ 553 #define LE_MODE_DRCVBC 0x4000 /* disable receive brodcast */ 554 #define LE_MODE_DRCVPA 0x2000 /* disable physical address detection */ 555 #define LE_MODE_DLNKTST 0x1000 /* disable link status */ 556 #define LE_MODE_DAPC 0x0800 /* disable automatic polarity correction */ 557 #define LE_MODE_MENDECL 0x0400 /* MENDEC loopback mode */ 558 #define LE_MODE_LRTTSEL 0x0200 /* lower receice threshold / 559 transmit mode selection */ 560 #define LE_MODE_PSEL1 0x0100 /* port selection bit1 */ 561 #define LE_MODE_PSEL0 0x0080 /* port selection bit0 */ 562 #define LE_MODE_INTL 0x0040 /* internal loopback */ 563 #define LE_MODE_DRTY 0x0020 /* disable retry */ 564 #define LE_MODE_COLL 0x0010 /* force a collision */ 565 #define LE_MODE_DTCR 0x0008 /* disable transmit CRC */ 566 #define LE_MODE_LOOP 0x0004 /* loopback mode */ 567 #define LE_MODE_DTX 0x0002 /* disable transmitter */ 568 #define LE_MODE_DRX 0x0001 /* disable receiver */ 569 #define LE_MODE_NORMAL 0 /* none of the above */ 570 571 /* 572 * Chip ID (CSR88 IDL, CSR89 IDU) values for various AMD PCnet parts. 573 */ 574 #define CHIPID_MANFID(x) (((x) >> 1) & 0x3ff) 575 #define CHIPID_PARTID(x) (((x) >> 12) & 0xffff) 576 #define CHIPID_VER(x) (((x) >> 28) & 0x7) 577 578 #define PARTID_Am79c960 0x0003 579 #deifne PARTID_Am79c961 0x2260 580 #define PARTID_Am79c961A 0x2261 581 #define PARTID_Am79c965 0x2430 582 #define PARTID_Am79c970 0x0242 583 #define PARTID_Am79c970A 0x2621 584 #define PARTID_Am79c971 0x2623 585 #define PARTID_Am79c972 0x2624 586 #define PARTID_Am79c973 0x2625 587 #define PARTID_Am79c978 0x2626 588 #define PARTID_Am79c975 0x2627 589 #define PARTID_Am79c976 0x2628 590
Indexes created Fri Sep 26 08:10:20 GMT 2025