lsi64854.c revision 1.11
1 /* $NetBSD: lsi64854.c,v 1.11 2000/07/04 14:58:36 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <machine/bus.h> 48 #include <machine/autoconf.h> 49 #include <machine/cpu.h> 50 51 #include <dev/scsipi/scsi_all.h> 52 #include <dev/scsipi/scsipi_all.h> 53 #include <dev/scsipi/scsiconf.h> 54 55 #include <dev/ic/lsi64854reg.h> 56 #include <dev/ic/lsi64854var.h> 57 58 #include <dev/ic/ncr53c9xreg.h> 59 #include <dev/ic/ncr53c9xvar.h> 60 61 void lsi64854_reset __P((struct lsi64854_softc *)); 62 int lsi64854_setup __P((struct lsi64854_softc *, caddr_t *, size_t *, 63 int, size_t *)); 64 int lsi64854_setup_pp __P((struct lsi64854_softc *, caddr_t *, size_t *, 65 int, size_t *)); 66 67 #ifdef DEBUG 68 int lsi64854debug = 0; 69 #define DPRINTF(x) do { if (lsi64854debug != 0) printf x ; } while (0) 70 #else 71 #define DPRINTF(x) 72 #endif 73 74 #define MAX_DMA_SZ (16*1024*1024) 75 76 /* 77 * Finish attaching this DMA device. 78 * Front-end must fill in these fields: 79 * sc_bustag 80 * sc_dmatag 81 * sc_regs 82 * sc_burst 83 * sc_channel (one of SCSI, ENET, PP) 84 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 85 */ 86 void 87 lsi64854_attach(sc) 88 struct lsi64854_softc *sc; 89 { 90 91 /* Indirect functions */ 92 switch (sc->sc_channel) { 93 case L64854_CHANNEL_SCSI: 94 sc->intr = lsi64854_scsi_intr; 95 sc->setup = lsi64854_setup; 96 break; 97 case L64854_CHANNEL_ENET: 98 sc->intr = lsi64854_enet_intr; 99 break; 100 case L64854_CHANNEL_PP: 101 sc->setup = lsi64854_setup_pp; 102 break; 103 default: 104 printf("%s: unknown channel\n", sc->sc_dev.dv_xname); 105 } 106 sc->reset = lsi64854_reset; 107 108 /* Allocate a dmamap */ 109 if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 110 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) { 111 printf("%s: dma map create failed\n", sc->sc_dev.dv_xname); 112 return; 113 } 114 115 printf(": rev "); 116 sc->sc_rev = L64854_GCSR(sc) & L64854_DEVID; 117 switch (sc->sc_rev) { 118 case DMAREV_0: 119 printf("0"); 120 break; 121 case DMAREV_ESC: 122 printf("esc"); 123 break; 124 case DMAREV_1: 125 printf("1"); 126 break; 127 case DMAREV_PLUS: 128 printf("1+"); 129 break; 130 case DMAREV_2: 131 printf("2"); 132 break; 133 default: 134 printf("unknown (0x%x)", sc->sc_rev); 135 } 136 printf("\n"); 137 138 } 139 140 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 141 int count = 500000; \ 142 while ((COND) && --count > 0) DELAY(1); \ 143 if (count == 0) { \ 144 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 145 (u_long)L64854_GCSR(SC)); \ 146 if (DONTPANIC) \ 147 printf(MSG); \ 148 else \ 149 panic(MSG); \ 150 } \ 151 } while (0) 152 153 #define DMA_DRAIN(sc, dontpanic) do { \ 154 u_int32_t csr; \ 155 /* \ 156 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 157 * and "drain" bits while it is still thinking about a \ 158 * request. \ 159 * other revs: D_ESC_R_PEND bit reads as 0 \ 160 */ \ 161 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 162 /* \ 163 * Select drain bit based on revision \ 164 * also clears errors and D_TC flag \ 165 */ \ 166 csr = L64854_GCSR(sc); \ 167 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 168 csr |= D_ESC_DRAIN; \ 169 else \ 170 csr |= L64854_INVALIDATE; \ 171 \ 172 L64854_SCSR(sc,csr); \ 173 /* \ 174 * Wait for draining to finish \ 175 * rev0 & rev1 call this PACKCNT \ 176 */ \ 177 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 178 } while(0) 179 180 #define DMA_FLUSH(sc, dontpanic) do { \ 181 u_int32_t csr; \ 182 /* \ 183 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 184 * and "drain" bits while it is still thinking about a \ 185 * request. \ 186 * other revs: D_ESC_R_PEND bit reads as 0 \ 187 */ \ 188 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 189 csr = L64854_GCSR(sc); \ 190 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 191 csr |= L64854_INVALIDATE; \ 192 L64854_SCSR(sc,csr); \ 193 } while(0) 194 195 void 196 lsi64854_reset(sc) 197 struct lsi64854_softc *sc; 198 { 199 u_int32_t csr; 200 201 DMA_FLUSH(sc, 1); 202 csr = L64854_GCSR(sc); 203 csr |= L64854_RESET; /* reset DMA */ 204 L64854_SCSR(sc, csr); 205 DELAY(200); /* > 10 Sbus clocks(?) */ 206 207 /*DMAWAIT1(sc); why was this here? */ 208 csr = L64854_GCSR(sc); 209 csr &= ~L64854_RESET; /* de-assert reset line */ 210 L64854_SCSR(sc, csr); 211 DELAY(5); /* allow a few ticks to settle */ 212 213 csr = L64854_GCSR(sc); 214 csr |= L64854_INT_EN; /* enable interrupts */ 215 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) 216 csr |= D_FASTER; 217 218 /* Set burst */ 219 switch (sc->sc_rev) { 220 case DMAREV_2: 221 csr &= ~L64854_BURST_SIZE; 222 if (sc->sc_burst == 32) { 223 csr |= L64854_BURST_32; 224 } else if (sc->sc_burst == 16) { 225 csr |= L64854_BURST_16; 226 } else { 227 csr |= L64854_BURST_0; 228 } 229 break; 230 case DMAREV_ESC: 231 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 232 if (sc->sc_burst == 32) { 233 csr &= ~D_ESC_BURST; 234 } else 235 csr |= D_ESC_BURST; 236 break; 237 default: 238 } 239 L64854_SCSR(sc, csr); 240 241 sc->sc_active = 0; 242 } 243 244 245 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 246 /* 247 * setup a dma transfer 248 */ 249 int 250 lsi64854_setup(sc, addr, len, datain, dmasize) 251 struct lsi64854_softc *sc; 252 caddr_t *addr; 253 size_t *len; 254 int datain; 255 size_t *dmasize; /* IN-OUT */ 256 { 257 u_int32_t csr; 258 259 DMA_FLUSH(sc, 0); 260 261 #if 0 262 DMACSR(sc) &= ~D_INT_EN; 263 #endif 264 sc->sc_dmaaddr = addr; 265 sc->sc_dmalen = len; 266 267 DPRINTF(("%s: start %ld@%p,%d\n", sc->sc_dev.dv_xname, 268 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 269 270 /* 271 * the rules say we cannot transfer more than the limit 272 * of this DMA chip (64k for old and 16Mb for new), 273 * and we cannot cross a 16Mb boundary. 274 */ 275 *dmasize = sc->sc_dmasize = 276 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 277 278 DPRINTF(("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize)); 279 280 /* Program the DMA address */ 281 if (sc->sc_dmasize) { 282 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 283 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 284 *sc->sc_dmaaddr, sc->sc_dmasize, 285 NULL /* kernel address */, 286 BUS_DMA_NOWAIT)) 287 panic("%s: cannot allocate DVMA address", 288 sc->sc_dev.dv_xname); 289 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 290 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 291 datain 292 ? BUS_DMASYNC_PREREAD 293 : BUS_DMASYNC_PREWRITE); 294 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 295 sc->sc_dmamap->dm_segs[0].ds_addr); 296 } 297 298 if (sc->sc_rev == DMAREV_ESC) { 299 /* DMA ESC chip bug work-around */ 300 long bcnt = sc->sc_dmasize; 301 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 302 if ((eaddr & PGOFSET) != 0) 303 bcnt = roundup(bcnt, NBPG); 304 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 305 bcnt); 306 } 307 /* Setup DMA control register */ 308 csr = L64854_GCSR(sc); 309 if (datain) 310 csr |= L64854_WRITE; 311 else 312 csr &= ~L64854_WRITE; 313 csr |= L64854_INT_EN; 314 L64854_SCSR(sc, csr); 315 316 return (0); 317 } 318 319 /* 320 * Pseudo (chained) interrupt from the esp driver to kick the 321 * current running DMA transfer. Called from ncr53c9x_intr() 322 * for now. 323 * 324 * return 1 if it was a DMA continue. 325 */ 326 int 327 lsi64854_scsi_intr(arg) 328 void *arg; 329 { 330 struct lsi64854_softc *sc = arg; 331 struct ncr53c9x_softc *nsc = sc->sc_client; 332 char bits[64]; 333 int trans, resid; 334 u_int32_t csr; 335 336 csr = L64854_GCSR(sc); 337 338 DPRINTF(("%s: intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 339 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 340 bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits)))); 341 342 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 343 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 344 bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits))); 345 csr &= ~D_EN_DMA; /* Stop DMA */ 346 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 347 csr |= D_INVALIDATE|D_SLAVE_ERR; 348 L64854_SCSR(sc, csr); 349 return (-1); 350 } 351 352 /* This is an "assertion" :) */ 353 if (sc->sc_active == 0) 354 panic("dmaintr: DMA wasn't active"); 355 356 DMA_DRAIN(sc, 0); 357 358 /* DMA has stopped */ 359 csr &= ~D_EN_DMA; 360 L64854_SCSR(sc, csr); 361 sc->sc_active = 0; 362 363 if (sc->sc_dmasize == 0) { 364 /* A "Transfer Pad" operation completed */ 365 DPRINTF(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 366 NCR_READ_REG(nsc, NCR_TCL) | 367 (NCR_READ_REG(nsc, NCR_TCM) << 8), 368 NCR_READ_REG(nsc, NCR_TCL), 369 NCR_READ_REG(nsc, NCR_TCM))); 370 return 0; 371 } 372 373 resid = 0; 374 /* 375 * If a transfer onto the SCSI bus gets interrupted by the device 376 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 377 * as residual since the NCR53C9X counter registers get decremented 378 * as bytes are clocked into the FIFO. 379 */ 380 if (!(csr & D_WRITE) && 381 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 382 DPRINTF(("dmaintr: empty esp FIFO of %d ", resid)); 383 } 384 385 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 386 /* 387 * `Terminal count' is off, so read the residue 388 * out of the NCR53C9X counter registers. 389 */ 390 resid += (NCR_READ_REG(nsc, NCR_TCL) | 391 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 392 ((nsc->sc_cfg2 & NCRCFG2_FE) 393 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 394 : 0)); 395 396 if (resid == 0 && sc->sc_dmasize == 65536 && 397 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 398 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 399 resid = 65536; 400 } 401 402 trans = sc->sc_dmasize - resid; 403 if (trans < 0) { /* transferred < 0 ? */ 404 #if 0 405 /* 406 * This situation can happen in perfectly normal operation 407 * if the ESP is reselected while using DMA to select 408 * another target. As such, don't print the warning. 409 */ 410 printf("%s: xfer (%d) > req (%d)\n", 411 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 412 #endif 413 trans = sc->sc_dmasize; 414 } 415 416 DPRINTF(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 417 NCR_READ_REG(nsc, NCR_TCL), 418 NCR_READ_REG(nsc, NCR_TCM), 419 (nsc->sc_cfg2 & NCRCFG2_FE) 420 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 421 trans, resid)); 422 423 if (sc->sc_dmamap->dm_nsegs > 0) { 424 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 425 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 426 (csr & D_WRITE) != 0 427 ? BUS_DMASYNC_POSTREAD 428 : BUS_DMASYNC_POSTWRITE); 429 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 430 } 431 432 *sc->sc_dmalen -= trans; 433 *sc->sc_dmaaddr += trans; 434 435 #if 0 /* this is not normal operation just yet */ 436 if (*sc->sc_dmalen == 0 || 437 nsc->sc_phase != nsc->sc_prevphase) 438 return 0; 439 440 /* and again */ 441 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 442 return 1; 443 #endif 444 return 0; 445 } 446 447 /* 448 * Pseudo (chained) interrupt to le driver to handle DMA errors. 449 */ 450 int 451 lsi64854_enet_intr(arg) 452 void *arg; 453 { 454 struct lsi64854_softc *sc = arg; 455 char bits[64]; 456 u_int32_t csr; 457 static int dodrain = 0; 458 int rv; 459 460 csr = L64854_GCSR(sc); 461 462 /* If the DMA logic shows an interrupt, claim it */ 463 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 464 465 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 466 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 467 bitmask_snprintf(csr, EDMACSR_BITS, bits,sizeof(bits))); 468 csr &= ~L64854_EN_DMA; /* Stop DMA */ 469 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 470 csr |= E_INVALIDATE|E_SLAVE_ERR; 471 L64854_SCSR(sc, csr); 472 DMA_RESET(sc); 473 dodrain = 1; 474 return (1); 475 } 476 477 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 478 int i = 10; 479 csr |= E_DRAIN; 480 L64854_SCSR(sc, csr); 481 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 482 delay(1); 483 } 484 485 return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg)); 486 } 487 488 /* 489 * setup a dma transfer 490 */ 491 int 492 lsi64854_setup_pp(sc, addr, len, datain, dmasize) 493 struct lsi64854_softc *sc; 494 caddr_t *addr; 495 size_t *len; 496 int datain; 497 size_t *dmasize; /* IN-OUT */ 498 { 499 u_int32_t csr; 500 501 DMA_FLUSH(sc, 0); 502 503 sc->sc_dmaaddr = addr; 504 sc->sc_dmalen = len; 505 506 DPRINTF(("%s: start %ld@%p,%d\n", sc->sc_dev.dv_xname, 507 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 508 509 /* 510 * the rules say we cannot transfer more than the limit 511 * of this DMA chip (64k for old and 16Mb for new), 512 * and we cannot cross a 16Mb boundary. 513 */ 514 *dmasize = sc->sc_dmasize = 515 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 516 517 DPRINTF(("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize)); 518 519 /* Program the DMA address */ 520 if (sc->sc_dmasize) { 521 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 522 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 523 *sc->sc_dmaaddr, sc->sc_dmasize, 524 NULL /* kernel address */, 525 BUS_DMA_NOWAIT)) 526 panic("%s: cannot allocate DVMA address", 527 sc->sc_dev.dv_xname); 528 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 529 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 530 datain 531 ? BUS_DMASYNC_PREREAD 532 : BUS_DMASYNC_PREWRITE); 533 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 534 sc->sc_dmamap->dm_segs[0].ds_addr); 535 536 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 537 sc->sc_dmasize); 538 } 539 540 /* Setup DMA control register */ 541 csr = L64854_GCSR(sc); 542 #if 0 543 /* This bit is read-only in PP csr register */ 544 if (datain) 545 csr |= L64854_WRITE; 546 else 547 csr &= ~L64854_WRITE; 548 #endif 549 csr |= L64854_INT_EN; 550 L64854_SCSR(sc, csr); 551 552 return (0); 553 } 554 /* 555 * Parallel port DMA interrupt. 556 */ 557 int 558 lsi64854_pp_intr(arg) 559 void *arg; 560 { 561 struct lsi64854_softc *sc = arg; 562 char bits[64]; 563 int ret, trans, resid = 0; 564 u_int32_t csr; 565 566 csr = L64854_GCSR(sc); 567 568 DPRINTF(("%s: intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 569 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 570 bitmask_snprintf(csr, PDMACSR_BITS, bits, sizeof(bits)))); 571 572 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 573 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 574 bitmask_snprintf(csr, PDMACSR_BITS, bits,sizeof(bits))); 575 csr &= ~P_EN_DMA; /* Stop DMA */ 576 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 577 csr |= P_INVALIDATE|P_SLAVE_ERR; 578 L64854_SCSR(sc, csr); 579 return (1); 580 } 581 582 ret = (csr & P_INT_PEND) != 0; 583 584 if (sc->sc_active != 0) { 585 DMA_DRAIN(sc, 0); 586 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 587 L64854_REG_CNT); 588 } 589 590 /* DMA has stopped */ 591 csr &= ~D_EN_DMA; 592 L64854_SCSR(sc, csr); 593 sc->sc_active = 0; 594 595 trans = sc->sc_dmasize - resid; 596 if (trans < 0) { /* transferred < 0 ? */ 597 trans = sc->sc_dmasize; 598 } 599 *sc->sc_dmalen -= trans; 600 *sc->sc_dmaaddr += trans; 601 602 if (sc->sc_dmamap->dm_nsegs > 0) { 603 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 604 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 605 (csr & D_WRITE) != 0 606 ? BUS_DMASYNC_POSTREAD 607 : BUS_DMASYNC_POSTWRITE); 608 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 609 } 610 611 ret |= (*sc->sc_intrchain)(sc->sc_intrchainarg); 612 return (ret != 0); 613 } 614
Indexes created Tue Sep 23 02:09:52 GMT 2025