lsi64854.c revision 1.12
1 /* $NetBSD: lsi64854.c,v 1.12 2000/10/31 06:32:06 eeh Exp $ */ 2 #define DEBUG 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <machine/bus.h> 48 #include <machine/autoconf.h> 49 #include <machine/cpu.h> 50 51 #include <dev/scsipi/scsi_all.h> 52 #include <dev/scsipi/scsipi_all.h> 53 #include <dev/scsipi/scsiconf.h> 54 55 #include <dev/ic/lsi64854reg.h> 56 #include <dev/ic/lsi64854var.h> 57 58 #include <dev/ic/ncr53c9xreg.h> 59 #include <dev/ic/ncr53c9xvar.h> 60 61 void lsi64854_reset __P((struct lsi64854_softc *)); 62 int lsi64854_setup __P((struct lsi64854_softc *, caddr_t *, size_t *, 63 int, size_t *)); 64 int lsi64854_setup_pp __P((struct lsi64854_softc *, caddr_t *, size_t *, 65 int, size_t *)); 66 67 #ifdef DEBUG 68 #define LDB_SCSI 1 69 #define LDB_ENET 2 70 #define LDB_PP 4 71 #define LDB_ANY 0xff 72 int lsi64854debug = 0; 73 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 74 #else 75 #define DPRINTF(a,x) 76 #endif 77 78 #define MAX_DMA_SZ (16*1024*1024) 79 80 /* 81 * Finish attaching this DMA device. 82 * Front-end must fill in these fields: 83 * sc_bustag 84 * sc_dmatag 85 * sc_regs 86 * sc_burst 87 * sc_channel (one of SCSI, ENET, PP) 88 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 89 */ 90 void 91 lsi64854_attach(sc) 92 struct lsi64854_softc *sc; 93 { 94 95 /* Indirect functions */ 96 switch (sc->sc_channel) { 97 case L64854_CHANNEL_SCSI: 98 sc->intr = lsi64854_scsi_intr; 99 sc->setup = lsi64854_setup; 100 break; 101 case L64854_CHANNEL_ENET: 102 sc->intr = lsi64854_enet_intr; 103 break; 104 case L64854_CHANNEL_PP: 105 sc->setup = lsi64854_setup_pp; 106 break; 107 default: 108 printf("%s: unknown channel\n", sc->sc_dev.dv_xname); 109 } 110 sc->reset = lsi64854_reset; 111 112 /* Allocate a dmamap */ 113 if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 114 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) { 115 printf("%s: dma map create failed\n", sc->sc_dev.dv_xname); 116 return; 117 } 118 119 printf(": rev "); 120 sc->sc_rev = L64854_GCSR(sc) & L64854_DEVID; 121 switch (sc->sc_rev) { 122 case DMAREV_0: 123 printf("0"); 124 break; 125 case DMAREV_ESC: 126 printf("esc"); 127 break; 128 case DMAREV_1: 129 printf("1"); 130 break; 131 case DMAREV_PLUS: 132 printf("1+"); 133 break; 134 case DMAREV_2: 135 printf("2"); 136 break; 137 default: 138 printf("unknown (0x%x)", sc->sc_rev); 139 } 140 printf("\n"); 141 142 } 143 144 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 145 int count = 500000; \ 146 while ((COND) && --count > 0) DELAY(1); \ 147 if (count == 0) { \ 148 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 149 (u_long)L64854_GCSR(SC)); \ 150 if (DONTPANIC) \ 151 printf(MSG); \ 152 else \ 153 panic(MSG); \ 154 } \ 155 } while (0) 156 157 #define DMA_DRAIN(sc, dontpanic) do { \ 158 u_int32_t csr; \ 159 /* \ 160 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 161 * and "drain" bits while it is still thinking about a \ 162 * request. \ 163 * other revs: D_ESC_R_PEND bit reads as 0 \ 164 */ \ 165 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 166 /* \ 167 * Select drain bit based on revision \ 168 * also clears errors and D_TC flag \ 169 */ \ 170 csr = L64854_GCSR(sc); \ 171 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 172 csr |= D_ESC_DRAIN; \ 173 else \ 174 csr |= L64854_INVALIDATE; \ 175 \ 176 L64854_SCSR(sc,csr); \ 177 /* \ 178 * Wait for draining to finish \ 179 * rev0 & rev1 call this PACKCNT \ 180 */ \ 181 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 182 } while(0) 183 184 #define DMA_FLUSH(sc, dontpanic) do { \ 185 u_int32_t csr; \ 186 /* \ 187 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 188 * and "drain" bits while it is still thinking about a \ 189 * request. \ 190 * other revs: D_ESC_R_PEND bit reads as 0 \ 191 */ \ 192 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 193 csr = L64854_GCSR(sc); \ 194 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 195 csr |= L64854_INVALIDATE; \ 196 L64854_SCSR(sc,csr); \ 197 } while(0) 198 199 void 200 lsi64854_reset(sc) 201 struct lsi64854_softc *sc; 202 { 203 u_int32_t csr; 204 205 DMA_FLUSH(sc, 1); 206 csr = L64854_GCSR(sc); 207 csr |= L64854_RESET; /* reset DMA */ 208 L64854_SCSR(sc, csr); 209 DELAY(200); /* > 10 Sbus clocks(?) */ 210 211 /*DMAWAIT1(sc); why was this here? */ 212 csr = L64854_GCSR(sc); 213 csr &= ~L64854_RESET; /* de-assert reset line */ 214 L64854_SCSR(sc, csr); 215 DELAY(5); /* allow a few ticks to settle */ 216 217 csr = L64854_GCSR(sc); 218 csr |= L64854_INT_EN; /* enable interrupts */ 219 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) 220 csr |= D_FASTER; 221 222 /* Set burst */ 223 switch (sc->sc_rev) { 224 case DMAREV_2: 225 csr &= ~L64854_BURST_SIZE; 226 if (sc->sc_burst == 32) { 227 csr |= L64854_BURST_32; 228 } else if (sc->sc_burst == 16) { 229 csr |= L64854_BURST_16; 230 } else { 231 csr |= L64854_BURST_0; 232 } 233 break; 234 case DMAREV_ESC: 235 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 236 if (sc->sc_burst == 32) { 237 csr &= ~D_ESC_BURST; 238 } else 239 csr |= D_ESC_BURST; 240 break; 241 default: 242 } 243 L64854_SCSR(sc, csr); 244 245 sc->sc_active = 0; 246 } 247 248 249 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 250 /* 251 * setup a dma transfer 252 */ 253 int 254 lsi64854_setup(sc, addr, len, datain, dmasize) 255 struct lsi64854_softc *sc; 256 caddr_t *addr; 257 size_t *len; 258 int datain; 259 size_t *dmasize; /* IN-OUT */ 260 { 261 u_int32_t csr; 262 263 DMA_FLUSH(sc, 0); 264 265 #if 0 266 DMACSR(sc) &= ~D_INT_EN; 267 #endif 268 sc->sc_dmaaddr = addr; 269 sc->sc_dmalen = len; 270 271 DPRINTF(LDB_ANY, ("%s: start %ld@%p,%d\n", sc->sc_dev.dv_xname, 272 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 273 274 /* 275 * the rules say we cannot transfer more than the limit 276 * of this DMA chip (64k for old and 16Mb for new), 277 * and we cannot cross a 16Mb boundary. 278 */ 279 *dmasize = sc->sc_dmasize = 280 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 281 282 DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize)); 283 284 /* Program the DMA address */ 285 if (sc->sc_dmasize) { 286 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 287 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 288 *sc->sc_dmaaddr, sc->sc_dmasize, 289 NULL /* kernel address */, 290 BUS_DMA_NOWAIT)) 291 panic("%s: cannot allocate DVMA address", 292 sc->sc_dev.dv_xname); 293 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 294 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 295 datain 296 ? BUS_DMASYNC_PREREAD 297 : BUS_DMASYNC_PREWRITE); 298 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 299 sc->sc_dmamap->dm_segs[0].ds_addr); 300 } 301 302 if (sc->sc_rev == DMAREV_ESC) { 303 /* DMA ESC chip bug work-around */ 304 long bcnt = sc->sc_dmasize; 305 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 306 if ((eaddr & PGOFSET) != 0) 307 bcnt = roundup(bcnt, NBPG); 308 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 309 bcnt); 310 } 311 /* Setup DMA control register */ 312 csr = L64854_GCSR(sc); 313 if (datain) 314 csr |= L64854_WRITE; 315 else 316 csr &= ~L64854_WRITE; 317 csr |= L64854_INT_EN; 318 L64854_SCSR(sc, csr); 319 320 return (0); 321 } 322 323 /* 324 * Pseudo (chained) interrupt from the esp driver to kick the 325 * current running DMA transfer. Called from ncr53c9x_intr() 326 * for now. 327 * 328 * return 1 if it was a DMA continue. 329 */ 330 int 331 lsi64854_scsi_intr(arg) 332 void *arg; 333 { 334 struct lsi64854_softc *sc = arg; 335 struct ncr53c9x_softc *nsc = sc->sc_client; 336 char bits[64]; 337 int trans, resid; 338 u_int32_t csr; 339 340 csr = L64854_GCSR(sc); 341 342 DPRINTF(LDB_SCSI, ("%s: intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 343 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 344 bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits)))); 345 346 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 347 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 348 bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits))); 349 csr &= ~D_EN_DMA; /* Stop DMA */ 350 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 351 csr |= D_INVALIDATE|D_SLAVE_ERR; 352 L64854_SCSR(sc, csr); 353 return (-1); 354 } 355 356 /* This is an "assertion" :) */ 357 if (sc->sc_active == 0) 358 panic("dmaintr: DMA wasn't active"); 359 360 DMA_DRAIN(sc, 0); 361 362 /* DMA has stopped */ 363 csr &= ~D_EN_DMA; 364 L64854_SCSR(sc, csr); 365 sc->sc_active = 0; 366 367 if (sc->sc_dmasize == 0) { 368 /* A "Transfer Pad" operation completed */ 369 DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 370 NCR_READ_REG(nsc, NCR_TCL) | 371 (NCR_READ_REG(nsc, NCR_TCM) << 8), 372 NCR_READ_REG(nsc, NCR_TCL), 373 NCR_READ_REG(nsc, NCR_TCM))); 374 return 0; 375 } 376 377 resid = 0; 378 /* 379 * If a transfer onto the SCSI bus gets interrupted by the device 380 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 381 * as residual since the NCR53C9X counter registers get decremented 382 * as bytes are clocked into the FIFO. 383 */ 384 if (!(csr & D_WRITE) && 385 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 386 DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid)); 387 } 388 389 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 390 /* 391 * `Terminal count' is off, so read the residue 392 * out of the NCR53C9X counter registers. 393 */ 394 resid += (NCR_READ_REG(nsc, NCR_TCL) | 395 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 396 ((nsc->sc_cfg2 & NCRCFG2_FE) 397 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 398 : 0)); 399 400 if (resid == 0 && sc->sc_dmasize == 65536 && 401 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 402 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 403 resid = 65536; 404 } 405 406 trans = sc->sc_dmasize - resid; 407 if (trans < 0) { /* transferred < 0 ? */ 408 #if 0 409 /* 410 * This situation can happen in perfectly normal operation 411 * if the ESP is reselected while using DMA to select 412 * another target. As such, don't print the warning. 413 */ 414 printf("%s: xfer (%d) > req (%d)\n", 415 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 416 #endif 417 trans = sc->sc_dmasize; 418 } 419 420 DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 421 NCR_READ_REG(nsc, NCR_TCL), 422 NCR_READ_REG(nsc, NCR_TCM), 423 (nsc->sc_cfg2 & NCRCFG2_FE) 424 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 425 trans, resid)); 426 427 if (sc->sc_dmamap->dm_nsegs > 0) { 428 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 429 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 430 (csr & D_WRITE) != 0 431 ? BUS_DMASYNC_POSTREAD 432 : BUS_DMASYNC_POSTWRITE); 433 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 434 } 435 436 *sc->sc_dmalen -= trans; 437 *sc->sc_dmaaddr += trans; 438 439 #if 0 /* this is not normal operation just yet */ 440 if (*sc->sc_dmalen == 0 || 441 nsc->sc_phase != nsc->sc_prevphase) 442 return 0; 443 444 /* and again */ 445 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 446 return 1; 447 #endif 448 return 0; 449 } 450 451 /* 452 * Pseudo (chained) interrupt to le driver to handle DMA errors. 453 */ 454 int 455 lsi64854_enet_intr(arg) 456 void *arg; 457 { 458 struct lsi64854_softc *sc = arg; 459 char bits[64]; 460 u_int32_t csr; 461 static int dodrain = 0; 462 int rv; 463 464 csr = L64854_GCSR(sc); 465 466 /* If the DMA logic shows an interrupt, claim it */ 467 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 468 469 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 470 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 471 bitmask_snprintf(csr, EDMACSR_BITS, bits,sizeof(bits))); 472 csr &= ~L64854_EN_DMA; /* Stop DMA */ 473 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 474 csr |= E_INVALIDATE|E_SLAVE_ERR; 475 L64854_SCSR(sc, csr); 476 DMA_RESET(sc); 477 dodrain = 1; 478 return (1); 479 } 480 481 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 482 int i = 10; 483 csr |= E_DRAIN; 484 L64854_SCSR(sc, csr); 485 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 486 delay(1); 487 } 488 489 return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg)); 490 } 491 492 /* 493 * setup a dma transfer 494 */ 495 int 496 lsi64854_setup_pp(sc, addr, len, datain, dmasize) 497 struct lsi64854_softc *sc; 498 caddr_t *addr; 499 size_t *len; 500 int datain; 501 size_t *dmasize; /* IN-OUT */ 502 { 503 u_int32_t csr; 504 505 DMA_FLUSH(sc, 0); 506 507 sc->sc_dmaaddr = addr; 508 sc->sc_dmalen = len; 509 510 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->sc_dev.dv_xname, 511 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 512 513 /* 514 * the rules say we cannot transfer more than the limit 515 * of this DMA chip (64k for old and 16Mb for new), 516 * and we cannot cross a 16Mb boundary. 517 */ 518 *dmasize = sc->sc_dmasize = 519 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 520 521 DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize)); 522 523 /* Program the DMA address */ 524 if (sc->sc_dmasize) { 525 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 526 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 527 *sc->sc_dmaaddr, sc->sc_dmasize, 528 NULL /* kernel address */, 529 BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/)) 530 panic("%s: pp cannot allocate DVMA address", 531 sc->sc_dev.dv_xname); 532 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 533 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 534 datain 535 ? BUS_DMASYNC_PREREAD 536 : BUS_DMASYNC_PREWRITE); 537 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 538 sc->sc_dmamap->dm_segs[0].ds_addr); 539 540 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 541 sc->sc_dmasize); 542 } 543 544 /* Setup DMA control register */ 545 csr = L64854_GCSR(sc); 546 csr &= ~L64854_BURST_SIZE; 547 if (sc->sc_burst == 32) { 548 csr |= L64854_BURST_32; 549 } else if (sc->sc_burst == 16) { 550 csr |= L64854_BURST_16; 551 } else { 552 csr |= L64854_BURST_0; 553 } 554 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 555 #if 0 556 /* This bit is read-only in PP csr register */ 557 if (datain) 558 csr |= P_WRITE; 559 else 560 csr &= ~P_WRITE; 561 #endif 562 L64854_SCSR(sc, csr); 563 564 return (0); 565 } 566 /* 567 * Parallel port DMA interrupt. 568 */ 569 int 570 lsi64854_pp_intr(arg) 571 void *arg; 572 { 573 struct lsi64854_softc *sc = arg; 574 char bits[64]; 575 int ret, trans, resid = 0; 576 u_int32_t csr; 577 578 csr = L64854_GCSR(sc); 579 580 DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 581 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 582 bitmask_snprintf(csr, PDMACSR_BITS, bits, sizeof(bits)))); 583 584 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 585 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 586 L64854_REG_CNT); 587 printf("%s: pp error: resid %d csr=%s\n", sc->sc_dev.dv_xname, 588 resid, 589 bitmask_snprintf(csr, PDMACSR_BITS, bits,sizeof(bits))); 590 csr &= ~P_EN_DMA; /* Stop DMA */ 591 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 592 csr |= P_INVALIDATE|P_SLAVE_ERR; 593 L64854_SCSR(sc, csr); 594 return (1); 595 } 596 597 ret = (csr & P_INT_PEND) != 0; 598 599 if (sc->sc_active != 0) { 600 DMA_DRAIN(sc, 0); 601 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 602 L64854_REG_CNT); 603 } 604 605 /* DMA has stopped */ 606 csr &= ~D_EN_DMA; 607 L64854_SCSR(sc, csr); 608 sc->sc_active = 0; 609 610 trans = sc->sc_dmasize - resid; 611 if (trans < 0) { /* transferred < 0 ? */ 612 trans = sc->sc_dmasize; 613 } 614 *sc->sc_dmalen -= trans; 615 *sc->sc_dmaaddr += trans; 616 617 if (sc->sc_dmamap->dm_nsegs > 0) { 618 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 619 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 620 (csr & D_WRITE) != 0 621 ? BUS_DMASYNC_POSTREAD 622 : BUS_DMASYNC_POSTWRITE); 623 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 624 } 625 626 return (ret != 0); 627 } 628
Indexes created Fri Sep 26 20:09:58 GMT 2025