lsi64854.c revision 1.14
1 /* $NetBSD: lsi64854.c,v 1.14 2000/11/14 18:21:02 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 #include <machine/cpu.h> 52 53 #include <dev/scsipi/scsi_all.h> 54 #include <dev/scsipi/scsipi_all.h> 55 #include <dev/scsipi/scsiconf.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 void lsi64854_reset __P((struct lsi64854_softc *)); 64 int lsi64854_setup __P((struct lsi64854_softc *, caddr_t *, size_t *, 65 int, size_t *)); 66 int lsi64854_setup_pp __P((struct lsi64854_softc *, caddr_t *, size_t *, 67 int, size_t *)); 68 69 #ifdef DEBUG 70 #define LDB_SCSI 1 71 #define LDB_ENET 2 72 #define LDB_PP 4 73 #define LDB_ANY 0xff 74 int lsi64854debug = 0; 75 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 76 #else 77 #define DPRINTF(a,x) 78 #endif 79 80 #define MAX_DMA_SZ (16*1024*1024) 81 82 /* 83 * Finish attaching this DMA device. 84 * Front-end must fill in these fields: 85 * sc_bustag 86 * sc_dmatag 87 * sc_regs 88 * sc_burst 89 * sc_channel (one of SCSI, ENET, PP) 90 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 91 */ 92 void 93 lsi64854_attach(sc) 94 struct lsi64854_softc *sc; 95 { 96 97 /* Indirect functions */ 98 switch (sc->sc_channel) { 99 case L64854_CHANNEL_SCSI: 100 sc->intr = lsi64854_scsi_intr; 101 sc->setup = lsi64854_setup; 102 break; 103 case L64854_CHANNEL_ENET: 104 sc->intr = lsi64854_enet_intr; 105 break; 106 case L64854_CHANNEL_PP: 107 sc->setup = lsi64854_setup_pp; 108 break; 109 default: 110 printf("%s: unknown channel\n", sc->sc_dev.dv_xname); 111 } 112 sc->reset = lsi64854_reset; 113 114 /* Allocate a dmamap */ 115 if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 116 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) { 117 printf("%s: dma map create failed\n", sc->sc_dev.dv_xname); 118 return; 119 } 120 121 printf(": rev "); 122 sc->sc_rev = L64854_GCSR(sc) & L64854_DEVID; 123 switch (sc->sc_rev) { 124 case DMAREV_0: 125 printf("0"); 126 break; 127 case DMAREV_ESC: 128 printf("esc"); 129 break; 130 case DMAREV_1: 131 printf("1"); 132 break; 133 case DMAREV_PLUS: 134 printf("1+"); 135 break; 136 case DMAREV_2: 137 printf("2"); 138 break; 139 default: 140 printf("unknown (0x%x)", sc->sc_rev); 141 } 142 printf("\n"); 143 144 } 145 146 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 147 int count = 500000; \ 148 while ((COND) && --count > 0) DELAY(1); \ 149 if (count == 0) { \ 150 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 151 (u_long)L64854_GCSR(SC)); \ 152 if (DONTPANIC) \ 153 printf(MSG); \ 154 else \ 155 panic(MSG); \ 156 } \ 157 } while (0) 158 159 #define DMA_DRAIN(sc, dontpanic) do { \ 160 u_int32_t csr; \ 161 /* \ 162 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 163 * and "drain" bits while it is still thinking about a \ 164 * request. \ 165 * other revs: D_ESC_R_PEND bit reads as 0 \ 166 */ \ 167 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 168 /* \ 169 * Select drain bit based on revision \ 170 * also clears errors and D_TC flag \ 171 */ \ 172 csr = L64854_GCSR(sc); \ 173 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 174 csr |= D_ESC_DRAIN; \ 175 else \ 176 csr |= L64854_INVALIDATE; \ 177 \ 178 L64854_SCSR(sc,csr); \ 179 /* \ 180 * Wait for draining to finish \ 181 * rev0 & rev1 call this PACKCNT \ 182 */ \ 183 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 184 } while(0) 185 186 #define DMA_FLUSH(sc, dontpanic) do { \ 187 u_int32_t csr; \ 188 /* \ 189 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 190 * and "drain" bits while it is still thinking about a \ 191 * request. \ 192 * other revs: D_ESC_R_PEND bit reads as 0 \ 193 */ \ 194 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 195 csr = L64854_GCSR(sc); \ 196 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 197 csr |= L64854_INVALIDATE; \ 198 L64854_SCSR(sc,csr); \ 199 } while(0) 200 201 void 202 lsi64854_reset(sc) 203 struct lsi64854_softc *sc; 204 { 205 u_int32_t csr; 206 207 DMA_FLUSH(sc, 1); 208 csr = L64854_GCSR(sc); 209 csr |= L64854_RESET; /* reset DMA */ 210 L64854_SCSR(sc, csr); 211 DELAY(200); /* > 10 Sbus clocks(?) */ 212 213 /*DMAWAIT1(sc); why was this here? */ 214 csr = L64854_GCSR(sc); 215 csr &= ~L64854_RESET; /* de-assert reset line */ 216 L64854_SCSR(sc, csr); 217 DELAY(5); /* allow a few ticks to settle */ 218 219 csr = L64854_GCSR(sc); 220 csr |= L64854_INT_EN; /* enable interrupts */ 221 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) 222 csr |= D_FASTER; 223 224 /* Set burst */ 225 switch (sc->sc_rev) { 226 case DMAREV_2: 227 csr &= ~L64854_BURST_SIZE; 228 if (sc->sc_burst == 32) { 229 csr |= L64854_BURST_32; 230 } else if (sc->sc_burst == 16) { 231 csr |= L64854_BURST_16; 232 } else { 233 csr |= L64854_BURST_0; 234 } 235 break; 236 case DMAREV_ESC: 237 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 238 if (sc->sc_burst == 32) { 239 csr &= ~D_ESC_BURST; 240 } else 241 csr |= D_ESC_BURST; 242 break; 243 default: 244 } 245 L64854_SCSR(sc, csr); 246 247 sc->sc_active = 0; 248 } 249 250 251 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 252 /* 253 * setup a dma transfer 254 */ 255 int 256 lsi64854_setup(sc, addr, len, datain, dmasize) 257 struct lsi64854_softc *sc; 258 caddr_t *addr; 259 size_t *len; 260 int datain; 261 size_t *dmasize; /* IN-OUT */ 262 { 263 u_int32_t csr; 264 265 DMA_FLUSH(sc, 0); 266 267 #if 0 268 DMACSR(sc) &= ~D_INT_EN; 269 #endif 270 sc->sc_dmaaddr = addr; 271 sc->sc_dmalen = len; 272 273 DPRINTF(LDB_ANY, ("%s: start %ld@%p,%d\n", sc->sc_dev.dv_xname, 274 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 275 276 /* 277 * the rules say we cannot transfer more than the limit 278 * of this DMA chip (64k for old and 16Mb for new), 279 * and we cannot cross a 16Mb boundary. 280 */ 281 *dmasize = sc->sc_dmasize = 282 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 283 284 DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize)); 285 286 /* Program the DMA address */ 287 if (sc->sc_dmasize) { 288 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 289 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 290 *sc->sc_dmaaddr, sc->sc_dmasize, 291 NULL /* kernel address */, 292 BUS_DMA_NOWAIT)) 293 panic("%s: cannot allocate DVMA address", 294 sc->sc_dev.dv_xname); 295 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 296 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 297 datain 298 ? BUS_DMASYNC_PREREAD 299 : BUS_DMASYNC_PREWRITE); 300 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 301 sc->sc_dmamap->dm_segs[0].ds_addr); 302 } 303 304 if (sc->sc_rev == DMAREV_ESC) { 305 /* DMA ESC chip bug work-around */ 306 long bcnt = sc->sc_dmasize; 307 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 308 if ((eaddr & PGOFSET) != 0) 309 bcnt = roundup(bcnt, PAGE_SIZE); 310 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 311 bcnt); 312 } 313 /* Setup DMA control register */ 314 csr = L64854_GCSR(sc); 315 if (datain) 316 csr |= L64854_WRITE; 317 else 318 csr &= ~L64854_WRITE; 319 csr |= L64854_INT_EN; 320 L64854_SCSR(sc, csr); 321 322 return (0); 323 } 324 325 /* 326 * Pseudo (chained) interrupt from the esp driver to kick the 327 * current running DMA transfer. Called from ncr53c9x_intr() 328 * for now. 329 * 330 * return 1 if it was a DMA continue. 331 */ 332 int 333 lsi64854_scsi_intr(arg) 334 void *arg; 335 { 336 struct lsi64854_softc *sc = arg; 337 struct ncr53c9x_softc *nsc = sc->sc_client; 338 char bits[64]; 339 int trans, resid; 340 u_int32_t csr; 341 342 csr = L64854_GCSR(sc); 343 344 DPRINTF(LDB_SCSI, ("%s: intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 345 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 346 bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits)))); 347 348 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 349 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 350 bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits))); 351 csr &= ~D_EN_DMA; /* Stop DMA */ 352 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 353 csr |= D_INVALIDATE|D_SLAVE_ERR; 354 L64854_SCSR(sc, csr); 355 return (-1); 356 } 357 358 /* This is an "assertion" :) */ 359 if (sc->sc_active == 0) 360 panic("dmaintr: DMA wasn't active"); 361 362 DMA_DRAIN(sc, 0); 363 364 /* DMA has stopped */ 365 csr &= ~D_EN_DMA; 366 L64854_SCSR(sc, csr); 367 sc->sc_active = 0; 368 369 if (sc->sc_dmasize == 0) { 370 /* A "Transfer Pad" operation completed */ 371 DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 372 NCR_READ_REG(nsc, NCR_TCL) | 373 (NCR_READ_REG(nsc, NCR_TCM) << 8), 374 NCR_READ_REG(nsc, NCR_TCL), 375 NCR_READ_REG(nsc, NCR_TCM))); 376 return 0; 377 } 378 379 resid = 0; 380 /* 381 * If a transfer onto the SCSI bus gets interrupted by the device 382 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 383 * as residual since the NCR53C9X counter registers get decremented 384 * as bytes are clocked into the FIFO. 385 */ 386 if (!(csr & D_WRITE) && 387 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 388 DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid)); 389 } 390 391 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 392 /* 393 * `Terminal count' is off, so read the residue 394 * out of the NCR53C9X counter registers. 395 */ 396 resid += (NCR_READ_REG(nsc, NCR_TCL) | 397 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 398 ((nsc->sc_cfg2 & NCRCFG2_FE) 399 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 400 : 0)); 401 402 if (resid == 0 && sc->sc_dmasize == 65536 && 403 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 404 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 405 resid = 65536; 406 } 407 408 trans = sc->sc_dmasize - resid; 409 if (trans < 0) { /* transferred < 0 ? */ 410 #if 0 411 /* 412 * This situation can happen in perfectly normal operation 413 * if the ESP is reselected while using DMA to select 414 * another target. As such, don't print the warning. 415 */ 416 printf("%s: xfer (%d) > req (%d)\n", 417 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 418 #endif 419 trans = sc->sc_dmasize; 420 } 421 422 DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 423 NCR_READ_REG(nsc, NCR_TCL), 424 NCR_READ_REG(nsc, NCR_TCM), 425 (nsc->sc_cfg2 & NCRCFG2_FE) 426 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 427 trans, resid)); 428 429 if (sc->sc_dmamap->dm_nsegs > 0) { 430 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 431 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 432 (csr & D_WRITE) != 0 433 ? BUS_DMASYNC_POSTREAD 434 : BUS_DMASYNC_POSTWRITE); 435 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 436 } 437 438 *sc->sc_dmalen -= trans; 439 *sc->sc_dmaaddr += trans; 440 441 #if 0 /* this is not normal operation just yet */ 442 if (*sc->sc_dmalen == 0 || 443 nsc->sc_phase != nsc->sc_prevphase) 444 return 0; 445 446 /* and again */ 447 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 448 return 1; 449 #endif 450 return 0; 451 } 452 453 /* 454 * Pseudo (chained) interrupt to le driver to handle DMA errors. 455 */ 456 int 457 lsi64854_enet_intr(arg) 458 void *arg; 459 { 460 struct lsi64854_softc *sc = arg; 461 char bits[64]; 462 u_int32_t csr; 463 static int dodrain = 0; 464 int rv; 465 466 csr = L64854_GCSR(sc); 467 468 /* If the DMA logic shows an interrupt, claim it */ 469 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 470 471 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 472 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 473 bitmask_snprintf(csr, EDMACSR_BITS, bits,sizeof(bits))); 474 csr &= ~L64854_EN_DMA; /* Stop DMA */ 475 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 476 csr |= E_INVALIDATE|E_SLAVE_ERR; 477 L64854_SCSR(sc, csr); 478 DMA_RESET(sc); 479 dodrain = 1; 480 return (1); 481 } 482 483 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 484 int i = 10; 485 csr |= E_DRAIN; 486 L64854_SCSR(sc, csr); 487 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 488 delay(1); 489 } 490 491 return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg)); 492 } 493 494 /* 495 * setup a dma transfer 496 */ 497 int 498 lsi64854_setup_pp(sc, addr, len, datain, dmasize) 499 struct lsi64854_softc *sc; 500 caddr_t *addr; 501 size_t *len; 502 int datain; 503 size_t *dmasize; /* IN-OUT */ 504 { 505 u_int32_t csr; 506 507 DMA_FLUSH(sc, 0); 508 509 sc->sc_dmaaddr = addr; 510 sc->sc_dmalen = len; 511 512 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->sc_dev.dv_xname, 513 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 514 515 /* 516 * the rules say we cannot transfer more than the limit 517 * of this DMA chip (64k for old and 16Mb for new), 518 * and we cannot cross a 16Mb boundary. 519 */ 520 *dmasize = sc->sc_dmasize = 521 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 522 523 DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize)); 524 525 /* Program the DMA address */ 526 if (sc->sc_dmasize) { 527 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 528 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 529 *sc->sc_dmaaddr, sc->sc_dmasize, 530 NULL /* kernel address */, 531 BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/)) 532 panic("%s: pp cannot allocate DVMA address", 533 sc->sc_dev.dv_xname); 534 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 535 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 536 datain 537 ? BUS_DMASYNC_PREREAD 538 : BUS_DMASYNC_PREWRITE); 539 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 540 sc->sc_dmamap->dm_segs[0].ds_addr); 541 542 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 543 sc->sc_dmasize); 544 } 545 546 /* Setup DMA control register */ 547 csr = L64854_GCSR(sc); 548 csr &= ~L64854_BURST_SIZE; 549 if (sc->sc_burst == 32) { 550 csr |= L64854_BURST_32; 551 } else if (sc->sc_burst == 16) { 552 csr |= L64854_BURST_16; 553 } else { 554 csr |= L64854_BURST_0; 555 } 556 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 557 #if 0 558 /* This bit is read-only in PP csr register */ 559 if (datain) 560 csr |= P_WRITE; 561 else 562 csr &= ~P_WRITE; 563 #endif 564 L64854_SCSR(sc, csr); 565 566 return (0); 567 } 568 /* 569 * Parallel port DMA interrupt. 570 */ 571 int 572 lsi64854_pp_intr(arg) 573 void *arg; 574 { 575 struct lsi64854_softc *sc = arg; 576 char bits[64]; 577 int ret, trans, resid = 0; 578 u_int32_t csr; 579 580 csr = L64854_GCSR(sc); 581 582 DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 583 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 584 bitmask_snprintf(csr, PDMACSR_BITS, bits, sizeof(bits)))); 585 586 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 587 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 588 L64854_REG_CNT); 589 printf("%s: pp error: resid %d csr=%s\n", sc->sc_dev.dv_xname, 590 resid, 591 bitmask_snprintf(csr, PDMACSR_BITS, bits,sizeof(bits))); 592 csr &= ~P_EN_DMA; /* Stop DMA */ 593 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 594 csr |= P_INVALIDATE|P_SLAVE_ERR; 595 L64854_SCSR(sc, csr); 596 return (1); 597 } 598 599 ret = (csr & P_INT_PEND) != 0; 600 601 if (sc->sc_active != 0) { 602 DMA_DRAIN(sc, 0); 603 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 604 L64854_REG_CNT); 605 } 606 607 /* DMA has stopped */ 608 csr &= ~D_EN_DMA; 609 L64854_SCSR(sc, csr); 610 sc->sc_active = 0; 611 612 trans = sc->sc_dmasize - resid; 613 if (trans < 0) { /* transferred < 0 ? */ 614 trans = sc->sc_dmasize; 615 } 616 *sc->sc_dmalen -= trans; 617 *sc->sc_dmaaddr += trans; 618 619 if (sc->sc_dmamap->dm_nsegs > 0) { 620 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 621 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 622 (csr & D_WRITE) != 0 623 ? BUS_DMASYNC_POSTREAD 624 : BUS_DMASYNC_POSTWRITE); 625 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 626 } 627 628 return (ret != 0); 629 } 630
Indexes created Tue Sep 23 01:09:51 GMT 2025