lsi64854.c revision 1.15
1 /* $NetBSD: lsi64854.c,v 1.15 2001/03/29 02:58:39 petrov Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 #include <machine/cpu.h> 52 53 #include <dev/scsipi/scsi_all.h> 54 #include <dev/scsipi/scsipi_all.h> 55 #include <dev/scsipi/scsiconf.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 void lsi64854_reset __P((struct lsi64854_softc *)); 64 int lsi64854_setup __P((struct lsi64854_softc *, caddr_t *, size_t *, 65 int, size_t *)); 66 int lsi64854_setup_pp __P((struct lsi64854_softc *, caddr_t *, size_t *, 67 int, size_t *)); 68 69 #ifdef DEBUG 70 #define LDB_SCSI 1 71 #define LDB_ENET 2 72 #define LDB_PP 4 73 #define LDB_ANY 0xff 74 int lsi64854debug = 0; 75 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 76 #else 77 #define DPRINTF(a,x) 78 #endif 79 80 #define MAX_DMA_SZ (16*1024*1024) 81 82 /* 83 * Finish attaching this DMA device. 84 * Front-end must fill in these fields: 85 * sc_bustag 86 * sc_dmatag 87 * sc_regs 88 * sc_burst 89 * sc_channel (one of SCSI, ENET, PP) 90 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 91 */ 92 void 93 lsi64854_attach(sc) 94 struct lsi64854_softc *sc; 95 { 96 u_int32_t csr; 97 98 /* Indirect functions */ 99 switch (sc->sc_channel) { 100 case L64854_CHANNEL_SCSI: 101 sc->intr = lsi64854_scsi_intr; 102 sc->setup = lsi64854_setup; 103 break; 104 case L64854_CHANNEL_ENET: 105 sc->intr = lsi64854_enet_intr; 106 break; 107 case L64854_CHANNEL_PP: 108 sc->setup = lsi64854_setup_pp; 109 break; 110 default: 111 printf("%s: unknown channel\n", sc->sc_dev.dv_xname); 112 } 113 sc->reset = lsi64854_reset; 114 115 /* Allocate a dmamap */ 116 if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 117 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) { 118 printf("%s: dma map create failed\n", sc->sc_dev.dv_xname); 119 return; 120 } 121 122 printf(": dma rev "); 123 csr = L64854_GCSR(sc); 124 sc->sc_rev = csr & L64854_DEVID; 125 switch (sc->sc_rev) { 126 case DMAREV_0: 127 printf("0"); 128 break; 129 case DMAREV_ESC: 130 printf("esc"); 131 break; 132 case DMAREV_1: 133 printf("1"); 134 break; 135 case DMAREV_PLUS: 136 printf("1+"); 137 break; 138 case DMAREV_2: 139 printf("2"); 140 break; 141 case DMAREV_HME: 142 printf("fas"); 143 break; 144 default: 145 printf("unknown (0x%x)", sc->sc_rev); 146 } 147 148 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x\n", sc->sc_burst, csr)); 149 } 150 151 /* 152 * DMAWAIT waits while condition is true 153 */ 154 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 155 int count = 500000; \ 156 while ((COND) && --count > 0) DELAY(1); \ 157 if (count == 0) { \ 158 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 159 (u_long)L64854_GCSR(SC)); \ 160 if (DONTPANIC) \ 161 printf(MSG); \ 162 else \ 163 panic(MSG); \ 164 } \ 165 } while (0) 166 167 #define DMA_DRAIN(sc, dontpanic) do { \ 168 u_int32_t csr; \ 169 /* \ 170 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 171 * and "drain" bits while it is still thinking about a \ 172 * request. \ 173 * other revs: D_ESC_R_PEND bit reads as 0 \ 174 */ \ 175 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 176 if (sc->sc_rev != DMAREV_HME) { \ 177 /* \ 178 * Select drain bit based on revision \ 179 * also clears errors and D_TC flag \ 180 */ \ 181 csr = L64854_GCSR(sc); \ 182 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 183 csr |= D_ESC_DRAIN; \ 184 else \ 185 csr |= L64854_INVALIDATE; \ 186 \ 187 L64854_SCSR(sc,csr); \ 188 } \ 189 /* \ 190 * Wait for draining to finish \ 191 * rev0 & rev1 call this PACKCNT \ 192 */ \ 193 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 194 } while(0) 195 196 #define DMA_FLUSH(sc, dontpanic) do { \ 197 u_int32_t csr; \ 198 /* \ 199 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 200 * and "drain" bits while it is still thinking about a \ 201 * request. \ 202 * other revs: D_ESC_R_PEND bit reads as 0 \ 203 */ \ 204 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 205 csr = L64854_GCSR(sc); \ 206 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 207 csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ 208 L64854_SCSR(sc,csr); \ 209 } while(0) 210 211 void 212 lsi64854_reset(sc) 213 struct lsi64854_softc *sc; 214 { 215 u_int32_t csr; 216 217 DMA_FLUSH(sc, 1); 218 csr = L64854_GCSR(sc); 219 220 DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr)); 221 222 /* 223 * XXX is sync needed? 224 */ 225 if (sc->sc_dmamap->dm_nsegs > 0) 226 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 227 228 if (sc->sc_rev == DMAREV_HME) 229 L64854_SCSR(sc, csr | D_HW_RESET_FAS366); 230 231 232 csr |= L64854_RESET; /* reset DMA */ 233 L64854_SCSR(sc, csr); 234 DELAY(200); /* > 10 Sbus clocks(?) */ 235 236 /*DMAWAIT1(sc); why was this here? */ 237 csr = L64854_GCSR(sc); 238 csr &= ~L64854_RESET; /* de-assert reset line */ 239 L64854_SCSR(sc, csr); 240 DELAY(5); /* allow a few ticks to settle */ 241 242 csr = L64854_GCSR(sc); 243 csr |= L64854_INT_EN; /* enable interrupts */ 244 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) { 245 if (sc->sc_rev == DMAREV_HME) 246 csr |= D_TWO_CYCLE; 247 else 248 csr |= D_FASTER; 249 } 250 251 /* Set burst */ 252 switch (sc->sc_rev) { 253 case DMAREV_HME: 254 case DMAREV_2: 255 csr &= ~L64854_BURST_SIZE; 256 if (sc->sc_burst == 32) { 257 csr |= L64854_BURST_32; 258 } else if (sc->sc_burst == 16) { 259 csr |= L64854_BURST_16; 260 } else { 261 csr |= L64854_BURST_0; 262 } 263 break; 264 case DMAREV_ESC: 265 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 266 if (sc->sc_burst == 32) { 267 csr &= ~D_ESC_BURST; 268 } else 269 csr |= D_ESC_BURST; 270 break; 271 default: 272 } 273 L64854_SCSR(sc, csr); 274 275 if (sc->sc_rev == DMAREV_HME) { 276 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 0); 277 sc->sc_dmactl = csr; 278 } 279 sc->sc_active = 0; 280 281 DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr)); 282 } 283 284 285 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 286 /* 287 * setup a dma transfer 288 */ 289 int 290 lsi64854_setup(sc, addr, len, datain, dmasize) 291 struct lsi64854_softc *sc; 292 caddr_t *addr; 293 size_t *len; 294 int datain; 295 size_t *dmasize; /* IN-OUT */ 296 { 297 u_int32_t csr; 298 299 DMA_FLUSH(sc, 0); 300 301 #if 0 302 DMACSR(sc) &= ~D_INT_EN; 303 #endif 304 sc->sc_dmaaddr = addr; 305 sc->sc_dmalen = len; 306 307 /* 308 * the rules say we cannot transfer more than the limit 309 * of this DMA chip (64k for old and 16Mb for new), 310 * and we cannot cross a 16Mb boundary. 311 */ 312 *dmasize = sc->sc_dmasize = 313 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 314 315 DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize)); 316 317 /* 318 * XXX what length? 319 */ 320 if (sc->sc_rev == DMAREV_HME) { 321 322 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET); 323 L64854_SCSR(sc, sc->sc_dmactl); 324 325 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, *dmasize); 326 } 327 328 /* Program the DMA address */ 329 if (sc->sc_dmasize) { 330 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 331 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 332 *sc->sc_dmaaddr, sc->sc_dmasize, 333 NULL /* kernel address */, 334 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) 335 panic("%s: cannot allocate DVMA address", 336 sc->sc_dev.dv_xname); 337 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 338 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 339 datain 340 ? BUS_DMASYNC_PREREAD 341 : BUS_DMASYNC_PREWRITE); 342 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 343 sc->sc_dmamap->dm_segs[0].ds_addr); 344 } 345 346 if (sc->sc_rev == DMAREV_ESC) { 347 /* DMA ESC chip bug work-around */ 348 long bcnt = sc->sc_dmasize; 349 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 350 if ((eaddr & PGOFSET) != 0) 351 bcnt = roundup(bcnt, PAGE_SIZE); 352 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 353 bcnt); 354 } 355 356 /* Setup DMA control register */ 357 csr = L64854_GCSR(sc); 358 359 if (datain) 360 csr |= L64854_WRITE; 361 else 362 csr &= ~L64854_WRITE; 363 csr |= L64854_INT_EN; 364 365 if (sc->sc_rev == DMAREV_HME) { 366 csr |= (D_DSBL_SCSI_DRN | D_EN_DMA); 367 } 368 369 L64854_SCSR(sc, csr); 370 371 return (0); 372 } 373 374 /* 375 * Pseudo (chained) interrupt from the esp driver to kick the 376 * current running DMA transfer. Called from ncr53c9x_intr() 377 * for now. 378 * 379 * return 1 if it was a DMA continue. 380 */ 381 int 382 lsi64854_scsi_intr(arg) 383 void *arg; 384 { 385 struct lsi64854_softc *sc = arg; 386 struct ncr53c9x_softc *nsc = sc->sc_client; 387 char bits[64]; 388 int trans, resid; 389 u_int32_t csr; 390 391 csr = L64854_GCSR(sc); 392 393 DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 394 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 395 bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits)))); 396 397 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 398 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 399 bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits))); 400 csr &= ~D_EN_DMA; /* Stop DMA */ 401 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 402 csr |= D_INVALIDATE|D_SLAVE_ERR; 403 L64854_SCSR(sc, csr); 404 return (-1); 405 } 406 407 /* This is an "assertion" :) */ 408 if (sc->sc_active == 0) 409 panic("dmaintr: DMA wasn't active"); 410 411 DMA_DRAIN(sc, 0); 412 413 /* DMA has stopped */ 414 csr &= ~D_EN_DMA; 415 L64854_SCSR(sc, csr); 416 sc->sc_active = 0; 417 418 if (sc->sc_dmasize == 0) { 419 /* A "Transfer Pad" operation completed */ 420 DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 421 NCR_READ_REG(nsc, NCR_TCL) | 422 (NCR_READ_REG(nsc, NCR_TCM) << 8), 423 NCR_READ_REG(nsc, NCR_TCL), 424 NCR_READ_REG(nsc, NCR_TCM))); 425 return 0; 426 } 427 428 resid = 0; 429 /* 430 * If a transfer onto the SCSI bus gets interrupted by the device 431 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 432 * as residual since the NCR53C9X counter registers get decremented 433 * as bytes are clocked into the FIFO. 434 */ 435 if (!(csr & D_WRITE) && 436 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 437 DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid)); 438 } 439 440 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 441 /* 442 * `Terminal count' is off, so read the residue 443 * out of the NCR53C9X counter registers. 444 */ 445 resid += (NCR_READ_REG(nsc, NCR_TCL) | 446 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 447 ((nsc->sc_cfg2 & NCRCFG2_FE) 448 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 449 : 0)); 450 451 if (resid == 0 && sc->sc_dmasize == 65536 && 452 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 453 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 454 resid = 65536; 455 } 456 457 trans = sc->sc_dmasize - resid; 458 if (trans < 0) { /* transferred < 0 ? */ 459 #if 0 460 /* 461 * This situation can happen in perfectly normal operation 462 * if the ESP is reselected while using DMA to select 463 * another target. As such, don't print the warning. 464 */ 465 printf("%s: xfer (%d) > req (%d)\n", 466 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 467 #endif 468 trans = sc->sc_dmasize; 469 } 470 471 DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 472 NCR_READ_REG(nsc, NCR_TCL), 473 NCR_READ_REG(nsc, NCR_TCM), 474 (nsc->sc_cfg2 & NCRCFG2_FE) 475 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 476 trans, resid)); 477 478 if (sc->sc_dmamap->dm_nsegs > 0) { 479 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 480 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 481 (csr & D_WRITE) != 0 482 ? BUS_DMASYNC_POSTREAD 483 : BUS_DMASYNC_POSTWRITE); 484 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 485 } 486 487 *sc->sc_dmalen -= trans; 488 *sc->sc_dmaaddr += trans; 489 490 #if 0 /* this is not normal operation just yet */ 491 if (*sc->sc_dmalen == 0 || 492 nsc->sc_phase != nsc->sc_prevphase) 493 return 0; 494 495 /* and again */ 496 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 497 return 1; 498 #endif 499 return 0; 500 } 501 502 /* 503 * Pseudo (chained) interrupt to le driver to handle DMA errors. 504 */ 505 int 506 lsi64854_enet_intr(arg) 507 void *arg; 508 { 509 struct lsi64854_softc *sc = arg; 510 char bits[64]; 511 u_int32_t csr; 512 static int dodrain = 0; 513 int rv; 514 515 csr = L64854_GCSR(sc); 516 517 /* If the DMA logic shows an interrupt, claim it */ 518 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 519 520 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 521 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 522 bitmask_snprintf(csr, EDMACSR_BITS, bits,sizeof(bits))); 523 csr &= ~L64854_EN_DMA; /* Stop DMA */ 524 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 525 csr |= E_INVALIDATE|E_SLAVE_ERR; 526 L64854_SCSR(sc, csr); 527 DMA_RESET(sc); 528 dodrain = 1; 529 return (1); 530 } 531 532 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 533 int i = 10; 534 csr |= E_DRAIN; 535 L64854_SCSR(sc, csr); 536 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 537 delay(1); 538 } 539 540 return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg)); 541 } 542 543 /* 544 * setup a dma transfer 545 */ 546 int 547 lsi64854_setup_pp(sc, addr, len, datain, dmasize) 548 struct lsi64854_softc *sc; 549 caddr_t *addr; 550 size_t *len; 551 int datain; 552 size_t *dmasize; /* IN-OUT */ 553 { 554 u_int32_t csr; 555 556 DMA_FLUSH(sc, 0); 557 558 sc->sc_dmaaddr = addr; 559 sc->sc_dmalen = len; 560 561 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->sc_dev.dv_xname, 562 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 563 564 /* 565 * the rules say we cannot transfer more than the limit 566 * of this DMA chip (64k for old and 16Mb for new), 567 * and we cannot cross a 16Mb boundary. 568 */ 569 *dmasize = sc->sc_dmasize = 570 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 571 572 DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize)); 573 574 /* Program the DMA address */ 575 if (sc->sc_dmasize) { 576 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 577 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 578 *sc->sc_dmaaddr, sc->sc_dmasize, 579 NULL /* kernel address */, 580 BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/)) 581 panic("%s: pp cannot allocate DVMA address", 582 sc->sc_dev.dv_xname); 583 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 584 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 585 datain 586 ? BUS_DMASYNC_PREREAD 587 : BUS_DMASYNC_PREWRITE); 588 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 589 sc->sc_dmamap->dm_segs[0].ds_addr); 590 591 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 592 sc->sc_dmasize); 593 } 594 595 /* Setup DMA control register */ 596 csr = L64854_GCSR(sc); 597 csr &= ~L64854_BURST_SIZE; 598 if (sc->sc_burst == 32) { 599 csr |= L64854_BURST_32; 600 } else if (sc->sc_burst == 16) { 601 csr |= L64854_BURST_16; 602 } else { 603 csr |= L64854_BURST_0; 604 } 605 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 606 #if 0 607 /* This bit is read-only in PP csr register */ 608 if (datain) 609 csr |= P_WRITE; 610 else 611 csr &= ~P_WRITE; 612 #endif 613 L64854_SCSR(sc, csr); 614 615 return (0); 616 } 617 /* 618 * Parallel port DMA interrupt. 619 */ 620 int 621 lsi64854_pp_intr(arg) 622 void *arg; 623 { 624 struct lsi64854_softc *sc = arg; 625 char bits[64]; 626 int ret, trans, resid = 0; 627 u_int32_t csr; 628 629 csr = L64854_GCSR(sc); 630 631 DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 632 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 633 bitmask_snprintf(csr, PDMACSR_BITS, bits, sizeof(bits)))); 634 635 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 636 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 637 L64854_REG_CNT); 638 printf("%s: pp error: resid %d csr=%s\n", sc->sc_dev.dv_xname, 639 resid, 640 bitmask_snprintf(csr, PDMACSR_BITS, bits,sizeof(bits))); 641 csr &= ~P_EN_DMA; /* Stop DMA */ 642 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 643 csr |= P_INVALIDATE|P_SLAVE_ERR; 644 L64854_SCSR(sc, csr); 645 return (1); 646 } 647 648 ret = (csr & P_INT_PEND) != 0; 649 650 if (sc->sc_active != 0) { 651 DMA_DRAIN(sc, 0); 652 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 653 L64854_REG_CNT); 654 } 655 656 /* DMA has stopped */ 657 csr &= ~D_EN_DMA; 658 L64854_SCSR(sc, csr); 659 sc->sc_active = 0; 660 661 trans = sc->sc_dmasize - resid; 662 if (trans < 0) { /* transferred < 0 ? */ 663 trans = sc->sc_dmasize; 664 } 665 *sc->sc_dmalen -= trans; 666 *sc->sc_dmaaddr += trans; 667 668 if (sc->sc_dmamap->dm_nsegs > 0) { 669 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 670 (bus_addr_t)(u_long)sc->sc_dvmaaddr, sc->sc_dmasize, 671 (csr & D_WRITE) != 0 672 ? BUS_DMASYNC_POSTREAD 673 : BUS_DMASYNC_POSTWRITE); 674 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 675 } 676 677 return (ret != 0); 678 } 679
Indexes created Thu Sep 25 08:09:54 GMT 2025