lsi64854.c revision 1.17
1 /* $NetBSD: lsi64854.c,v 1.17 2001/04/08 11:45:45 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 #include <machine/cpu.h> 52 53 #include <dev/scsipi/scsi_all.h> 54 #include <dev/scsipi/scsipi_all.h> 55 #include <dev/scsipi/scsiconf.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 void lsi64854_reset __P((struct lsi64854_softc *)); 64 int lsi64854_setup __P((struct lsi64854_softc *, caddr_t *, size_t *, 65 int, size_t *)); 66 int lsi64854_setup_pp __P((struct lsi64854_softc *, caddr_t *, size_t *, 67 int, size_t *)); 68 69 #ifdef DEBUG 70 #define LDB_SCSI 1 71 #define LDB_ENET 2 72 #define LDB_PP 4 73 #define LDB_ANY 0xff 74 int lsi64854debug = 0; 75 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 76 #else 77 #define DPRINTF(a,x) 78 #endif 79 80 #define MAX_DMA_SZ (16*1024*1024) 81 82 /* 83 * Finish attaching this DMA device. 84 * Front-end must fill in these fields: 85 * sc_bustag 86 * sc_dmatag 87 * sc_regs 88 * sc_burst 89 * sc_channel (one of SCSI, ENET, PP) 90 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 91 */ 92 void 93 lsi64854_attach(sc) 94 struct lsi64854_softc *sc; 95 { 96 u_int32_t csr; 97 98 /* Indirect functions */ 99 switch (sc->sc_channel) { 100 case L64854_CHANNEL_SCSI: 101 sc->intr = lsi64854_scsi_intr; 102 sc->setup = lsi64854_setup; 103 break; 104 case L64854_CHANNEL_ENET: 105 sc->intr = lsi64854_enet_intr; 106 break; 107 case L64854_CHANNEL_PP: 108 sc->setup = lsi64854_setup_pp; 109 break; 110 default: 111 printf("%s: unknown channel\n", sc->sc_dev.dv_xname); 112 } 113 sc->reset = lsi64854_reset; 114 115 /* Allocate a dmamap */ 116 if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 117 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) { 118 printf("%s: dma map create failed\n", sc->sc_dev.dv_xname); 119 return; 120 } 121 122 printf(": dma rev "); 123 csr = L64854_GCSR(sc); 124 sc->sc_rev = csr & L64854_DEVID; 125 switch (sc->sc_rev) { 126 case DMAREV_0: 127 printf("0"); 128 break; 129 case DMAREV_ESC: 130 printf("esc"); 131 break; 132 case DMAREV_1: 133 printf("1"); 134 break; 135 case DMAREV_PLUS: 136 printf("1+"); 137 break; 138 case DMAREV_2: 139 printf("2"); 140 break; 141 case DMAREV_HME: 142 printf("fas"); 143 break; 144 default: 145 printf("unknown (0x%x)", sc->sc_rev); 146 } 147 148 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr)); 149 printf("\n"); 150 } 151 152 /* 153 * DMAWAIT waits while condition is true 154 */ 155 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 156 int count = 500000; \ 157 while ((COND) && --count > 0) DELAY(1); \ 158 if (count == 0) { \ 159 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 160 (u_long)L64854_GCSR(SC)); \ 161 if (DONTPANIC) \ 162 printf(MSG); \ 163 else \ 164 panic(MSG); \ 165 } \ 166 } while (0) 167 168 #define DMA_DRAIN(sc, dontpanic) do { \ 169 u_int32_t csr; \ 170 /* \ 171 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 172 * and "drain" bits while it is still thinking about a \ 173 * request. \ 174 * other revs: D_ESC_R_PEND bit reads as 0 \ 175 */ \ 176 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 177 if (sc->sc_rev != DMAREV_HME) { \ 178 /* \ 179 * Select drain bit based on revision \ 180 * also clears errors and D_TC flag \ 181 */ \ 182 csr = L64854_GCSR(sc); \ 183 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 184 csr |= D_ESC_DRAIN; \ 185 else \ 186 csr |= L64854_INVALIDATE; \ 187 \ 188 L64854_SCSR(sc,csr); \ 189 } \ 190 /* \ 191 * Wait for draining to finish \ 192 * rev0 & rev1 call this PACKCNT \ 193 */ \ 194 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 195 } while(0) 196 197 #define DMA_FLUSH(sc, dontpanic) do { \ 198 u_int32_t csr; \ 199 /* \ 200 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 201 * and "drain" bits while it is still thinking about a \ 202 * request. \ 203 * other revs: D_ESC_R_PEND bit reads as 0 \ 204 */ \ 205 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 206 csr = L64854_GCSR(sc); \ 207 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 208 csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ 209 L64854_SCSR(sc,csr); \ 210 } while(0) 211 212 void 213 lsi64854_reset(sc) 214 struct lsi64854_softc *sc; 215 { 216 u_int32_t csr; 217 218 DMA_FLUSH(sc, 1); 219 csr = L64854_GCSR(sc); 220 221 DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr)); 222 223 /* 224 * XXX is sync needed? 225 */ 226 if (sc->sc_dmamap->dm_nsegs > 0) 227 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 228 229 if (sc->sc_rev == DMAREV_HME) 230 L64854_SCSR(sc, csr | D_HW_RESET_FAS366); 231 232 233 csr |= L64854_RESET; /* reset DMA */ 234 L64854_SCSR(sc, csr); 235 DELAY(200); /* > 10 Sbus clocks(?) */ 236 237 /*DMAWAIT1(sc); why was this here? */ 238 csr = L64854_GCSR(sc); 239 csr &= ~L64854_RESET; /* de-assert reset line */ 240 L64854_SCSR(sc, csr); 241 DELAY(5); /* allow a few ticks to settle */ 242 243 csr = L64854_GCSR(sc); 244 csr |= L64854_INT_EN; /* enable interrupts */ 245 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) { 246 if (sc->sc_rev == DMAREV_HME) 247 csr |= D_TWO_CYCLE; 248 else 249 csr |= D_FASTER; 250 } 251 252 /* Set burst */ 253 switch (sc->sc_rev) { 254 case DMAREV_HME: 255 case DMAREV_2: 256 csr &= ~L64854_BURST_SIZE; 257 if (sc->sc_burst == 32) { 258 csr |= L64854_BURST_32; 259 } else if (sc->sc_burst == 16) { 260 csr |= L64854_BURST_16; 261 } else { 262 csr |= L64854_BURST_0; 263 } 264 break; 265 case DMAREV_ESC: 266 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 267 if (sc->sc_burst == 32) { 268 csr &= ~D_ESC_BURST; 269 } else 270 csr |= D_ESC_BURST; 271 break; 272 default: 273 } 274 L64854_SCSR(sc, csr); 275 276 if (sc->sc_rev == DMAREV_HME) { 277 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 0); 278 sc->sc_dmactl = csr; 279 } 280 sc->sc_active = 0; 281 282 DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr)); 283 } 284 285 286 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 287 /* 288 * setup a dma transfer 289 */ 290 int 291 lsi64854_setup(sc, addr, len, datain, dmasize) 292 struct lsi64854_softc *sc; 293 caddr_t *addr; 294 size_t *len; 295 int datain; 296 size_t *dmasize; /* IN-OUT */ 297 { 298 u_int32_t csr; 299 300 DMA_FLUSH(sc, 0); 301 302 #if 0 303 DMACSR(sc) &= ~D_INT_EN; 304 #endif 305 sc->sc_dmaaddr = addr; 306 sc->sc_dmalen = len; 307 308 /* 309 * the rules say we cannot transfer more than the limit 310 * of this DMA chip (64k for old and 16Mb for new), 311 * and we cannot cross a 16Mb boundary. 312 */ 313 *dmasize = sc->sc_dmasize = 314 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 315 316 DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize)); 317 318 /* 319 * XXX what length? 320 */ 321 if (sc->sc_rev == DMAREV_HME) { 322 323 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET); 324 L64854_SCSR(sc, sc->sc_dmactl); 325 326 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, *dmasize); 327 } 328 329 /* Program the DMA address */ 330 if (sc->sc_dmasize) { 331 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 332 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 333 *sc->sc_dmaaddr, sc->sc_dmasize, 334 NULL /* kernel address */, 335 BUS_DMA_NOWAIT | BUS_DMA_STREAMING)) 336 panic("%s: cannot allocate DVMA address", 337 sc->sc_dev.dv_xname); 338 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 339 datain 340 ? BUS_DMASYNC_PREREAD 341 : BUS_DMASYNC_PREWRITE); 342 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 343 sc->sc_dmamap->dm_segs[0].ds_addr); 344 } 345 346 if (sc->sc_rev == DMAREV_ESC) { 347 /* DMA ESC chip bug work-around */ 348 long bcnt = sc->sc_dmasize; 349 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 350 if ((eaddr & PGOFSET) != 0) 351 bcnt = roundup(bcnt, PAGE_SIZE); 352 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 353 bcnt); 354 } 355 356 /* Setup DMA control register */ 357 csr = L64854_GCSR(sc); 358 359 if (datain) 360 csr |= L64854_WRITE; 361 else 362 csr &= ~L64854_WRITE; 363 csr |= L64854_INT_EN; 364 365 if (sc->sc_rev == DMAREV_HME) { 366 csr |= (D_DSBL_SCSI_DRN | D_EN_DMA); 367 } 368 369 L64854_SCSR(sc, csr); 370 371 return (0); 372 } 373 374 /* 375 * Pseudo (chained) interrupt from the esp driver to kick the 376 * current running DMA transfer. Called from ncr53c9x_intr() 377 * for now. 378 * 379 * return 1 if it was a DMA continue. 380 */ 381 int 382 lsi64854_scsi_intr(arg) 383 void *arg; 384 { 385 struct lsi64854_softc *sc = arg; 386 struct ncr53c9x_softc *nsc = sc->sc_client; 387 char bits[64]; 388 int trans, resid; 389 u_int32_t csr; 390 391 csr = L64854_GCSR(sc); 392 393 DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 394 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 395 bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits)))); 396 397 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 398 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 399 bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits))); 400 csr &= ~D_EN_DMA; /* Stop DMA */ 401 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 402 csr |= D_INVALIDATE|D_SLAVE_ERR; 403 L64854_SCSR(sc, csr); 404 return (-1); 405 } 406 407 /* This is an "assertion" :) */ 408 if (sc->sc_active == 0) 409 panic("dmaintr: DMA wasn't active"); 410 411 DMA_DRAIN(sc, 0); 412 413 /* DMA has stopped */ 414 csr &= ~D_EN_DMA; 415 L64854_SCSR(sc, csr); 416 sc->sc_active = 0; 417 418 if (sc->sc_dmasize == 0) { 419 /* A "Transfer Pad" operation completed */ 420 DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 421 NCR_READ_REG(nsc, NCR_TCL) | 422 (NCR_READ_REG(nsc, NCR_TCM) << 8), 423 NCR_READ_REG(nsc, NCR_TCL), 424 NCR_READ_REG(nsc, NCR_TCM))); 425 return 0; 426 } 427 428 resid = 0; 429 /* 430 * If a transfer onto the SCSI bus gets interrupted by the device 431 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 432 * as residual since the NCR53C9X counter registers get decremented 433 * as bytes are clocked into the FIFO. 434 */ 435 if (!(csr & D_WRITE) && 436 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 437 DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid)); 438 } 439 440 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 441 /* 442 * `Terminal count' is off, so read the residue 443 * out of the NCR53C9X counter registers. 444 */ 445 resid += (NCR_READ_REG(nsc, NCR_TCL) | 446 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 447 ((nsc->sc_cfg2 & NCRCFG2_FE) 448 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 449 : 0)); 450 451 if (resid == 0 && sc->sc_dmasize == 65536 && 452 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 453 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 454 resid = 65536; 455 } 456 457 trans = sc->sc_dmasize - resid; 458 if (trans < 0) { /* transferred < 0 ? */ 459 #if 0 460 /* 461 * This situation can happen in perfectly normal operation 462 * if the ESP is reselected while using DMA to select 463 * another target. As such, don't print the warning. 464 */ 465 printf("%s: xfer (%d) > req (%d)\n", 466 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 467 #endif 468 trans = sc->sc_dmasize; 469 } 470 471 DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 472 NCR_READ_REG(nsc, NCR_TCL), 473 NCR_READ_REG(nsc, NCR_TCM), 474 (nsc->sc_cfg2 & NCRCFG2_FE) 475 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 476 trans, resid)); 477 478 if (sc->sc_dmamap->dm_nsegs > 0) { 479 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 480 (csr & D_WRITE) != 0 481 ? BUS_DMASYNC_POSTREAD 482 : BUS_DMASYNC_POSTWRITE); 483 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 484 } 485 486 *sc->sc_dmalen -= trans; 487 *sc->sc_dmaaddr += trans; 488 489 #if 0 /* this is not normal operation just yet */ 490 if (*sc->sc_dmalen == 0 || 491 nsc->sc_phase != nsc->sc_prevphase) 492 return 0; 493 494 /* and again */ 495 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 496 return 1; 497 #endif 498 return 0; 499 } 500 501 /* 502 * Pseudo (chained) interrupt to le driver to handle DMA errors. 503 */ 504 int 505 lsi64854_enet_intr(arg) 506 void *arg; 507 { 508 struct lsi64854_softc *sc = arg; 509 char bits[64]; 510 u_int32_t csr; 511 static int dodrain = 0; 512 int rv; 513 514 csr = L64854_GCSR(sc); 515 516 /* If the DMA logic shows an interrupt, claim it */ 517 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 518 519 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 520 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 521 bitmask_snprintf(csr, EDMACSR_BITS, bits,sizeof(bits))); 522 csr &= ~L64854_EN_DMA; /* Stop DMA */ 523 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 524 csr |= E_INVALIDATE|E_SLAVE_ERR; 525 L64854_SCSR(sc, csr); 526 DMA_RESET(sc); 527 dodrain = 1; 528 return (1); 529 } 530 531 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 532 int i = 10; 533 csr |= E_DRAIN; 534 L64854_SCSR(sc, csr); 535 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 536 delay(1); 537 } 538 539 return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg)); 540 } 541 542 /* 543 * setup a dma transfer 544 */ 545 int 546 lsi64854_setup_pp(sc, addr, len, datain, dmasize) 547 struct lsi64854_softc *sc; 548 caddr_t *addr; 549 size_t *len; 550 int datain; 551 size_t *dmasize; /* IN-OUT */ 552 { 553 u_int32_t csr; 554 555 DMA_FLUSH(sc, 0); 556 557 sc->sc_dmaaddr = addr; 558 sc->sc_dmalen = len; 559 560 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->sc_dev.dv_xname, 561 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 562 563 /* 564 * the rules say we cannot transfer more than the limit 565 * of this DMA chip (64k for old and 16Mb for new), 566 * and we cannot cross a 16Mb boundary. 567 */ 568 *dmasize = sc->sc_dmasize = 569 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 570 571 DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize)); 572 573 /* Program the DMA address */ 574 if (sc->sc_dmasize) { 575 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 576 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 577 *sc->sc_dmaaddr, sc->sc_dmasize, 578 NULL /* kernel address */, 579 BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/)) 580 panic("%s: pp cannot allocate DVMA address", 581 sc->sc_dev.dv_xname); 582 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 583 datain 584 ? BUS_DMASYNC_PREREAD 585 : BUS_DMASYNC_PREWRITE); 586 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 587 sc->sc_dmamap->dm_segs[0].ds_addr); 588 589 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 590 sc->sc_dmasize); 591 } 592 593 /* Setup DMA control register */ 594 csr = L64854_GCSR(sc); 595 csr &= ~L64854_BURST_SIZE; 596 if (sc->sc_burst == 32) { 597 csr |= L64854_BURST_32; 598 } else if (sc->sc_burst == 16) { 599 csr |= L64854_BURST_16; 600 } else { 601 csr |= L64854_BURST_0; 602 } 603 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 604 #if 0 605 /* This bit is read-only in PP csr register */ 606 if (datain) 607 csr |= P_WRITE; 608 else 609 csr &= ~P_WRITE; 610 #endif 611 L64854_SCSR(sc, csr); 612 613 return (0); 614 } 615 /* 616 * Parallel port DMA interrupt. 617 */ 618 int 619 lsi64854_pp_intr(arg) 620 void *arg; 621 { 622 struct lsi64854_softc *sc = arg; 623 char bits[64]; 624 int ret, trans, resid = 0; 625 u_int32_t csr; 626 627 csr = L64854_GCSR(sc); 628 629 DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 630 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 631 bitmask_snprintf(csr, PDMACSR_BITS, bits, sizeof(bits)))); 632 633 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 634 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 635 L64854_REG_CNT); 636 printf("%s: pp error: resid %d csr=%s\n", sc->sc_dev.dv_xname, 637 resid, 638 bitmask_snprintf(csr, PDMACSR_BITS, bits,sizeof(bits))); 639 csr &= ~P_EN_DMA; /* Stop DMA */ 640 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 641 csr |= P_INVALIDATE|P_SLAVE_ERR; 642 L64854_SCSR(sc, csr); 643 return (1); 644 } 645 646 ret = (csr & P_INT_PEND) != 0; 647 648 if (sc->sc_active != 0) { 649 DMA_DRAIN(sc, 0); 650 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 651 L64854_REG_CNT); 652 } 653 654 /* DMA has stopped */ 655 csr &= ~D_EN_DMA; 656 L64854_SCSR(sc, csr); 657 sc->sc_active = 0; 658 659 trans = sc->sc_dmasize - resid; 660 if (trans < 0) { /* transferred < 0 ? */ 661 trans = sc->sc_dmasize; 662 } 663 *sc->sc_dmalen -= trans; 664 *sc->sc_dmaaddr += trans; 665 666 if (sc->sc_dmamap->dm_nsegs > 0) { 667 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 668 (csr & D_WRITE) != 0 669 ? BUS_DMASYNC_POSTREAD 670 : BUS_DMASYNC_POSTWRITE); 671 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 672 } 673 674 return (ret != 0); 675 } 676
Indexes created Thu Sep 25 02:09:54 GMT 2025