lsi64854.c revision 1.19
1 /* $NetBSD: lsi64854.c,v 1.19 2001/11/13 13:14:41 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: lsi64854.c,v 1.19 2001/11/13 13:14:41 lukem Exp $"); 41 42 #include <sys/types.h> 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/errno.h> 47 #include <sys/device.h> 48 #include <sys/malloc.h> 49 50 #include <uvm/uvm_extern.h> 51 52 #include <machine/bus.h> 53 #include <machine/autoconf.h> 54 #include <machine/cpu.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsiconf.h> 59 60 #include <dev/ic/lsi64854reg.h> 61 #include <dev/ic/lsi64854var.h> 62 63 #include <dev/ic/ncr53c9xreg.h> 64 #include <dev/ic/ncr53c9xvar.h> 65 66 void lsi64854_reset __P((struct lsi64854_softc *)); 67 int lsi64854_setup __P((struct lsi64854_softc *, caddr_t *, size_t *, 68 int, size_t *)); 69 int lsi64854_setup_pp __P((struct lsi64854_softc *, caddr_t *, size_t *, 70 int, size_t *)); 71 72 #ifdef DEBUG 73 #define LDB_SCSI 1 74 #define LDB_ENET 2 75 #define LDB_PP 4 76 #define LDB_ANY 0xff 77 int lsi64854debug = 0; 78 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 79 #else 80 #define DPRINTF(a,x) 81 #endif 82 83 #define MAX_DMA_SZ (16*1024*1024) 84 85 /* 86 * Finish attaching this DMA device. 87 * Front-end must fill in these fields: 88 * sc_bustag 89 * sc_dmatag 90 * sc_regs 91 * sc_burst 92 * sc_channel (one of SCSI, ENET, PP) 93 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 94 */ 95 void 96 lsi64854_attach(sc) 97 struct lsi64854_softc *sc; 98 { 99 u_int32_t csr; 100 101 /* Indirect functions */ 102 switch (sc->sc_channel) { 103 case L64854_CHANNEL_SCSI: 104 sc->intr = lsi64854_scsi_intr; 105 sc->setup = lsi64854_setup; 106 break; 107 case L64854_CHANNEL_ENET: 108 sc->intr = lsi64854_enet_intr; 109 break; 110 case L64854_CHANNEL_PP: 111 sc->setup = lsi64854_setup_pp; 112 break; 113 default: 114 printf("%s: unknown channel\n", sc->sc_dev.dv_xname); 115 } 116 sc->reset = lsi64854_reset; 117 118 /* Allocate a dmamap */ 119 if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 120 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) { 121 printf("%s: dma map create failed\n", sc->sc_dev.dv_xname); 122 return; 123 } 124 125 printf(": dma rev "); 126 csr = L64854_GCSR(sc); 127 sc->sc_rev = csr & L64854_DEVID; 128 switch (sc->sc_rev) { 129 case DMAREV_0: 130 printf("0"); 131 break; 132 case DMAREV_ESC: 133 printf("esc"); 134 break; 135 case DMAREV_1: 136 printf("1"); 137 break; 138 case DMAREV_PLUS: 139 printf("1+"); 140 break; 141 case DMAREV_2: 142 printf("2"); 143 break; 144 case DMAREV_HME: 145 printf("fas"); 146 break; 147 default: 148 printf("unknown (0x%x)", sc->sc_rev); 149 } 150 151 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr)); 152 printf("\n"); 153 } 154 155 /* 156 * DMAWAIT waits while condition is true 157 */ 158 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 159 int count = 500000; \ 160 while ((COND) && --count > 0) DELAY(1); \ 161 if (count == 0) { \ 162 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 163 (u_long)L64854_GCSR(SC)); \ 164 if (DONTPANIC) \ 165 printf(MSG); \ 166 else \ 167 panic(MSG); \ 168 } \ 169 } while (0) 170 171 #define DMA_DRAIN(sc, dontpanic) do { \ 172 u_int32_t csr; \ 173 /* \ 174 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 175 * and "drain" bits while it is still thinking about a \ 176 * request. \ 177 * other revs: D_ESC_R_PEND bit reads as 0 \ 178 */ \ 179 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 180 if (sc->sc_rev != DMAREV_HME) { \ 181 /* \ 182 * Select drain bit based on revision \ 183 * also clears errors and D_TC flag \ 184 */ \ 185 csr = L64854_GCSR(sc); \ 186 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 187 csr |= D_ESC_DRAIN; \ 188 else \ 189 csr |= L64854_INVALIDATE; \ 190 \ 191 L64854_SCSR(sc,csr); \ 192 } \ 193 /* \ 194 * Wait for draining to finish \ 195 * rev0 & rev1 call this PACKCNT \ 196 */ \ 197 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 198 } while(0) 199 200 #define DMA_FLUSH(sc, dontpanic) do { \ 201 u_int32_t csr; \ 202 /* \ 203 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 204 * and "drain" bits while it is still thinking about a \ 205 * request. \ 206 * other revs: D_ESC_R_PEND bit reads as 0 \ 207 */ \ 208 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 209 csr = L64854_GCSR(sc); \ 210 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 211 csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ 212 L64854_SCSR(sc,csr); \ 213 } while(0) 214 215 void 216 lsi64854_reset(sc) 217 struct lsi64854_softc *sc; 218 { 219 u_int32_t csr; 220 221 DMA_FLUSH(sc, 1); 222 csr = L64854_GCSR(sc); 223 224 DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr)); 225 226 /* 227 * XXX is sync needed? 228 */ 229 if (sc->sc_dmamap->dm_nsegs > 0) 230 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 231 232 if (sc->sc_rev == DMAREV_HME) 233 L64854_SCSR(sc, csr | D_HW_RESET_FAS366); 234 235 236 csr |= L64854_RESET; /* reset DMA */ 237 L64854_SCSR(sc, csr); 238 DELAY(200); /* > 10 Sbus clocks(?) */ 239 240 /*DMAWAIT1(sc); why was this here? */ 241 csr = L64854_GCSR(sc); 242 csr &= ~L64854_RESET; /* de-assert reset line */ 243 L64854_SCSR(sc, csr); 244 DELAY(5); /* allow a few ticks to settle */ 245 246 csr = L64854_GCSR(sc); 247 csr |= L64854_INT_EN; /* enable interrupts */ 248 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) { 249 if (sc->sc_rev == DMAREV_HME) 250 csr |= D_TWO_CYCLE; 251 else 252 csr |= D_FASTER; 253 } 254 255 /* Set burst */ 256 switch (sc->sc_rev) { 257 case DMAREV_HME: 258 case DMAREV_2: 259 csr &= ~L64854_BURST_SIZE; 260 if (sc->sc_burst == 32) { 261 csr |= L64854_BURST_32; 262 } else if (sc->sc_burst == 16) { 263 csr |= L64854_BURST_16; 264 } else { 265 csr |= L64854_BURST_0; 266 } 267 break; 268 case DMAREV_ESC: 269 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 270 if (sc->sc_burst == 32) { 271 csr &= ~D_ESC_BURST; 272 } else 273 csr |= D_ESC_BURST; 274 break; 275 default: 276 break; 277 } 278 L64854_SCSR(sc, csr); 279 280 if (sc->sc_rev == DMAREV_HME) { 281 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 0); 282 sc->sc_dmactl = csr; 283 } 284 sc->sc_active = 0; 285 286 DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr)); 287 } 288 289 290 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 291 /* 292 * setup a dma transfer 293 */ 294 int 295 lsi64854_setup(sc, addr, len, datain, dmasize) 296 struct lsi64854_softc *sc; 297 caddr_t *addr; 298 size_t *len; 299 int datain; 300 size_t *dmasize; /* IN-OUT */ 301 { 302 u_int32_t csr; 303 304 DMA_FLUSH(sc, 0); 305 306 #if 0 307 DMACSR(sc) &= ~D_INT_EN; 308 #endif 309 sc->sc_dmaaddr = addr; 310 sc->sc_dmalen = len; 311 312 /* 313 * the rules say we cannot transfer more than the limit 314 * of this DMA chip (64k for old and 16Mb for new), 315 * and we cannot cross a 16Mb boundary. 316 */ 317 *dmasize = sc->sc_dmasize = 318 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 319 320 DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize)); 321 322 /* 323 * XXX what length? 324 */ 325 if (sc->sc_rev == DMAREV_HME) { 326 327 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET); 328 L64854_SCSR(sc, sc->sc_dmactl); 329 330 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, *dmasize); 331 } 332 333 /* Program the DMA address */ 334 if (sc->sc_dmasize) { 335 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 336 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 337 *sc->sc_dmaaddr, sc->sc_dmasize, 338 NULL /* kernel address */, 339 BUS_DMA_NOWAIT | BUS_DMA_STREAMING)) 340 panic("%s: cannot allocate DVMA address", 341 sc->sc_dev.dv_xname); 342 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 343 datain 344 ? BUS_DMASYNC_PREREAD 345 : BUS_DMASYNC_PREWRITE); 346 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 347 sc->sc_dmamap->dm_segs[0].ds_addr); 348 } 349 350 if (sc->sc_rev == DMAREV_ESC) { 351 /* DMA ESC chip bug work-around */ 352 long bcnt = sc->sc_dmasize; 353 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 354 if ((eaddr & PGOFSET) != 0) 355 bcnt = roundup(bcnt, PAGE_SIZE); 356 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 357 bcnt); 358 } 359 360 /* Setup DMA control register */ 361 csr = L64854_GCSR(sc); 362 363 if (datain) 364 csr |= L64854_WRITE; 365 else 366 csr &= ~L64854_WRITE; 367 csr |= L64854_INT_EN; 368 369 if (sc->sc_rev == DMAREV_HME) { 370 csr |= (D_DSBL_SCSI_DRN | D_EN_DMA); 371 } 372 373 L64854_SCSR(sc, csr); 374 375 return (0); 376 } 377 378 /* 379 * Pseudo (chained) interrupt from the esp driver to kick the 380 * current running DMA transfer. Called from ncr53c9x_intr() 381 * for now. 382 * 383 * return 1 if it was a DMA continue. 384 */ 385 int 386 lsi64854_scsi_intr(arg) 387 void *arg; 388 { 389 struct lsi64854_softc *sc = arg; 390 struct ncr53c9x_softc *nsc = sc->sc_client; 391 char bits[64]; 392 int trans, resid; 393 u_int32_t csr; 394 395 csr = L64854_GCSR(sc); 396 397 DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 398 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 399 bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits)))); 400 401 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 402 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 403 bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits))); 404 csr &= ~D_EN_DMA; /* Stop DMA */ 405 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 406 csr |= D_INVALIDATE|D_SLAVE_ERR; 407 L64854_SCSR(sc, csr); 408 return (-1); 409 } 410 411 /* This is an "assertion" :) */ 412 if (sc->sc_active == 0) 413 panic("dmaintr: DMA wasn't active"); 414 415 DMA_DRAIN(sc, 0); 416 417 /* DMA has stopped */ 418 csr &= ~D_EN_DMA; 419 L64854_SCSR(sc, csr); 420 sc->sc_active = 0; 421 422 if (sc->sc_dmasize == 0) { 423 /* A "Transfer Pad" operation completed */ 424 DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 425 NCR_READ_REG(nsc, NCR_TCL) | 426 (NCR_READ_REG(nsc, NCR_TCM) << 8), 427 NCR_READ_REG(nsc, NCR_TCL), 428 NCR_READ_REG(nsc, NCR_TCM))); 429 return 0; 430 } 431 432 resid = 0; 433 /* 434 * If a transfer onto the SCSI bus gets interrupted by the device 435 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 436 * as residual since the NCR53C9X counter registers get decremented 437 * as bytes are clocked into the FIFO. 438 */ 439 if (!(csr & D_WRITE) && 440 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 441 DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid)); 442 } 443 444 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 445 /* 446 * `Terminal count' is off, so read the residue 447 * out of the NCR53C9X counter registers. 448 */ 449 resid += (NCR_READ_REG(nsc, NCR_TCL) | 450 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 451 ((nsc->sc_cfg2 & NCRCFG2_FE) 452 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 453 : 0)); 454 455 if (resid == 0 && sc->sc_dmasize == 65536 && 456 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 457 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 458 resid = 65536; 459 } 460 461 trans = sc->sc_dmasize - resid; 462 if (trans < 0) { /* transferred < 0 ? */ 463 #if 0 464 /* 465 * This situation can happen in perfectly normal operation 466 * if the ESP is reselected while using DMA to select 467 * another target. As such, don't print the warning. 468 */ 469 printf("%s: xfer (%d) > req (%d)\n", 470 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 471 #endif 472 trans = sc->sc_dmasize; 473 } 474 475 DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 476 NCR_READ_REG(nsc, NCR_TCL), 477 NCR_READ_REG(nsc, NCR_TCM), 478 (nsc->sc_cfg2 & NCRCFG2_FE) 479 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 480 trans, resid)); 481 482 if (sc->sc_dmamap->dm_nsegs > 0) { 483 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 484 (csr & D_WRITE) != 0 485 ? BUS_DMASYNC_POSTREAD 486 : BUS_DMASYNC_POSTWRITE); 487 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 488 } 489 490 *sc->sc_dmalen -= trans; 491 *sc->sc_dmaaddr += trans; 492 493 #if 0 /* this is not normal operation just yet */ 494 if (*sc->sc_dmalen == 0 || 495 nsc->sc_phase != nsc->sc_prevphase) 496 return 0; 497 498 /* and again */ 499 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 500 return 1; 501 #endif 502 return 0; 503 } 504 505 /* 506 * Pseudo (chained) interrupt to le driver to handle DMA errors. 507 */ 508 int 509 lsi64854_enet_intr(arg) 510 void *arg; 511 { 512 struct lsi64854_softc *sc = arg; 513 char bits[64]; 514 u_int32_t csr; 515 static int dodrain = 0; 516 int rv; 517 518 csr = L64854_GCSR(sc); 519 520 /* If the DMA logic shows an interrupt, claim it */ 521 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 522 523 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 524 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 525 bitmask_snprintf(csr, EDMACSR_BITS, bits,sizeof(bits))); 526 csr &= ~L64854_EN_DMA; /* Stop DMA */ 527 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 528 csr |= E_INVALIDATE|E_SLAVE_ERR; 529 L64854_SCSR(sc, csr); 530 DMA_RESET(sc); 531 dodrain = 1; 532 return (1); 533 } 534 535 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 536 int i = 10; 537 csr |= E_DRAIN; 538 L64854_SCSR(sc, csr); 539 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 540 delay(1); 541 } 542 543 return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg)); 544 } 545 546 /* 547 * setup a dma transfer 548 */ 549 int 550 lsi64854_setup_pp(sc, addr, len, datain, dmasize) 551 struct lsi64854_softc *sc; 552 caddr_t *addr; 553 size_t *len; 554 int datain; 555 size_t *dmasize; /* IN-OUT */ 556 { 557 u_int32_t csr; 558 559 DMA_FLUSH(sc, 0); 560 561 sc->sc_dmaaddr = addr; 562 sc->sc_dmalen = len; 563 564 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->sc_dev.dv_xname, 565 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 566 567 /* 568 * the rules say we cannot transfer more than the limit 569 * of this DMA chip (64k for old and 16Mb for new), 570 * and we cannot cross a 16Mb boundary. 571 */ 572 *dmasize = sc->sc_dmasize = 573 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 574 575 DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize)); 576 577 /* Program the DMA address */ 578 if (sc->sc_dmasize) { 579 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 580 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 581 *sc->sc_dmaaddr, sc->sc_dmasize, 582 NULL /* kernel address */, 583 BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/)) 584 panic("%s: pp cannot allocate DVMA address", 585 sc->sc_dev.dv_xname); 586 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 587 datain 588 ? BUS_DMASYNC_PREREAD 589 : BUS_DMASYNC_PREWRITE); 590 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 591 sc->sc_dmamap->dm_segs[0].ds_addr); 592 593 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 594 sc->sc_dmasize); 595 } 596 597 /* Setup DMA control register */ 598 csr = L64854_GCSR(sc); 599 csr &= ~L64854_BURST_SIZE; 600 if (sc->sc_burst == 32) { 601 csr |= L64854_BURST_32; 602 } else if (sc->sc_burst == 16) { 603 csr |= L64854_BURST_16; 604 } else { 605 csr |= L64854_BURST_0; 606 } 607 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 608 #if 0 609 /* This bit is read-only in PP csr register */ 610 if (datain) 611 csr |= P_WRITE; 612 else 613 csr &= ~P_WRITE; 614 #endif 615 L64854_SCSR(sc, csr); 616 617 return (0); 618 } 619 /* 620 * Parallel port DMA interrupt. 621 */ 622 int 623 lsi64854_pp_intr(arg) 624 void *arg; 625 { 626 struct lsi64854_softc *sc = arg; 627 char bits[64]; 628 int ret, trans, resid = 0; 629 u_int32_t csr; 630 631 csr = L64854_GCSR(sc); 632 633 DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname, 634 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 635 bitmask_snprintf(csr, PDMACSR_BITS, bits, sizeof(bits)))); 636 637 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 638 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 639 L64854_REG_CNT); 640 printf("%s: pp error: resid %d csr=%s\n", sc->sc_dev.dv_xname, 641 resid, 642 bitmask_snprintf(csr, PDMACSR_BITS, bits,sizeof(bits))); 643 csr &= ~P_EN_DMA; /* Stop DMA */ 644 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 645 csr |= P_INVALIDATE|P_SLAVE_ERR; 646 L64854_SCSR(sc, csr); 647 return (1); 648 } 649 650 ret = (csr & P_INT_PEND) != 0; 651 652 if (sc->sc_active != 0) { 653 DMA_DRAIN(sc, 0); 654 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 655 L64854_REG_CNT); 656 } 657 658 /* DMA has stopped */ 659 csr &= ~D_EN_DMA; 660 L64854_SCSR(sc, csr); 661 sc->sc_active = 0; 662 663 trans = sc->sc_dmasize - resid; 664 if (trans < 0) { /* transferred < 0 ? */ 665 trans = sc->sc_dmasize; 666 } 667 *sc->sc_dmalen -= trans; 668 *sc->sc_dmaaddr += trans; 669 670 if (sc->sc_dmamap->dm_nsegs > 0) { 671 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 672 (csr & D_WRITE) != 0 673 ? BUS_DMASYNC_POSTREAD 674 : BUS_DMASYNC_POSTWRITE); 675 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 676 } 677 678 return (ret != 0); 679 } 680
Indexes created Wed Sep 24 05:09:52 GMT 2025